Data Processing Method, Apparatus, Electronic Device and Computer-Readable Storage Medium

Abstract

The present application discloses a data processing method, apparatus, electronic device and computer-readable storage medium, relating to the technical field of data processing. The method includes: a processor obtains a read command; the read command includes a starting logical block address and a number of logical blocks; based on the starting logical block address, the read command is successively determined for continuity with commands in a plurality of preset data read command streams in different orders; and when it is determined that the read command is continuous with the commands in the target-order data read command stream, the matching compliance count of the target-order data read command stream is incremented by one; if the cumulative value of the matching compliance count of the target-order data read command stream is greater than a first threshold, based on the starting logical block address and the number of logical blocks, pre-read data in the flash memory unit and store the pre-read data in the cache unit, so that when the next read command is obtained, the data corresponding to the next read command can be found from the cache unit.

Description

Technical Field

[0001] This application relates to the technical field of data processing, and in particular, to a data processing method, apparatus, electronic device, and computer-readable storage medium. Background Art

[0002] Due to its delicate size, excellent data throughput and random performance, and low power consumption, solid-state drives based on flash memory technology, such as NAND flash memory technology, are widely used. However, when reading data from a solid-state drive based on flash memory technology, there is a preparation time of dozens of microseconds in the flash memory cells, which occupies most of the latency of the read command. Currently, by classifying the read commands in the read command queue and determining whether the first n read commands have been read for each type of read command, the prefetching of the data corresponding to the (n + 1)-th read command and subsequent read commands can be triggered sequentially to reduce the latency of reading data from a solid-state drive for multiple different types of sequential data read command streams. However, in this method, if a solid-state drive based on flash memory technology processes read commands through multiple processors, the order of each type of read command received by each processor will be distorted, resulting in the inability to trigger the data prefetching operation, leading to the latency of obtaining data for the read command and reducing the user experience. Summary of the Invention

[0003] In view of this, embodiments of this application provide a data processing method, apparatus, electronic device, and computer-readable storage medium.

[0004] According to a first aspect of this application, embodiments of this application provide a data processing method, which is applied to a solid-state drive. The solid-state drive includes flash memory cells, multiple processors, and a cache unit. The method includes:

[0005] A processor obtains a read command; the read command includes a starting logical block address and a logical block count;

[0006] Based on the starting logical block address, the read command is sequentially determined for continuity with the commands in a preset plurality of different sequential data read command streams; and when it is determined that the read command is continuous with the command in the target sequential data read command stream, the matching count of the target sequential data read command stream is incremented by one;

[0007] If the cumulative value of the matching count of the target sequential data read command stream is greater than a first threshold, based on the starting logical block address and the logical block count, prefetch the data in the flash memory cells and store the prefetch data in the cache unit, so that when the next read command is obtained, the data corresponding to the next read command can be found in the cache unit.

[0008] Optionally, determining that the read command is continuous with the command in the target sequential data read command stream includes:

[0009] If the ratio of the difference between the starting logical block address of the read command and the command in the target sequential data read command stream to the number of logical blocks corresponding to the command in the target sequential data read command stream is less than the second threshold, it is determined that the read command is consecutive with the command in the target sequential data read command stream.

[0010] Optionally, based on the starting logical block address and the number of logical blocks, pre-read the data in the flash memory cells, including:

[0011] Based on the starting logical block address and the number of logical blocks, determine the starting logical block address of the pre-read data and the amount of the pre-read data;

[0012] Based on the starting logical block address of the pre-read data and the amount of the pre-read data, pre-read the data in the flash memory cells.

[0013] Optionally, based on the starting logical block address and the number of logical blocks, determining the starting logical block address of the pre-read data and the amount of the pre-read data includes:

[0014] Perform a first weighting process on the starting logical block address based on the number of logical blocks and the first coefficient to obtain the starting logical block address of the pre-read data;

[0015] Perform a second weighting process on the number of logical blocks based on the second coefficient to obtain the amount of the pre-read data.

[0016] Optionally, the data processing method further includes:

[0017] Save the starting logical block address, the amount, and the physical address in the cache unit of the pre-read data;

[0018] Based on the starting logical block address of the pre-read data, update the maximum logical block address corresponding to the cache unit.

[0019] Optionally, the data processing method further includes:

[0020] If it is determined that the target data corresponding to the read command is stored in the cache unit based on the starting logical block address and the number of logical blocks, and the starting logical block address and the amount of the pre-read data stored in the cache unit, determine the physical address of the target data corresponding to the read command in the cache unit;

[0021] Based on the physical address of the target data in the cache unit, read the target data from the cache unit and send it out.

[0022] Optionally, determining that the target data corresponding to the read command is stored in the cache unit based on the starting logical block address and the number of logical blocks, and the starting logical block address and the amount of the pre-read data stored in the cache unit, includes:

[0023] If the number of pre-read data stored in the cache unit is greater than the third threshold, and the maximum logical block address corresponding to the cache unit is greater than the starting logical block address, based on the starting logical block address, the number of logical blocks, and the starting logical block address and the number of the pre-read data stored in the cache unit, determine that the target data corresponding to the read command is stored in the cache unit.

[0024] Optionally, determining that the target data corresponding to the read command is stored in the cache unit based on the starting logical block address, the number of logical blocks, and the starting logical block address and the number of the pre-read data stored in the cache unit includes:

[0025] Based on the starting logical block address and the number of logical blocks, determine the first logical block address range corresponding to the read command;

[0026] Based on the starting logical block address and the number of the pre-read data stored in the cache unit, determine the second logical block address range corresponding to the pre-read data stored in the cache unit;

[0027] If the second logical block address range is greater than or equal to the first logical block address range, determine that the target data corresponding to the read command is stored in the cache unit.

[0028] According to the second aspect of the present application, an embodiment of the present application provides a data processing device, which is applied to a solid-state drive. The solid-state drive includes flash memory cells, multiple processors, and a cache unit. The device includes:

[0029] An acquisition module, configured to acquire a read command; the read command includes a starting logical block address and the number of logical blocks;

[0030] A determination module, configured to sequentially determine the continuity of the read command with the commands in a preset plurality of different-order data read command streams based on the starting logical block address; and when it is determined that the read command is continuous with the commands in the target-order data read command stream, increment the matching compliance count of the target-order data read command stream by one;

[0031] A pre-reading module, configured to, if the cumulative value of the matching compliance count of the target-order data read command stream is greater than the first threshold, pre-read the data in the flash memory cells based on the starting logical block address and the number of logical blocks, and store the pre-read data in the cache unit, so that when the next read command is acquired, the data corresponding to the next read command can be found in the cache unit.

[0032] Optionally, the determination module is configured to determine that a read command is consecutive with a command in the target sequential data read command stream if the ratio of the difference between the starting logical block address of the read command and the command in the target sequential data read command stream to the number of logical blocks corresponding to the command in the target sequential data read command stream is less than a second threshold.

[0033] Optionally, the prefetch module is configured to determine the starting logical block address and the quantity of the prefetch data based on the starting logical block address and the number of logical blocks;

[0034] Prefetch the data in the flash memory cells based on the starting logical block address and the quantity of the prefetch data.

[0035] Optionally, the prefetch module is configured to perform a first weighting process on the starting logical block address based on the number of logical blocks and a first coefficient to obtain the starting logical block address of the prefetch data;

[0036] Perform a second weighting process on the number of logical blocks based on a second coefficient to obtain the quantity of the prefetch data.

[0037] Optionally, the data processing device further includes:

[0038] An update module, configured to save the starting logical block address, the quantity, and the physical address in the cache unit of the prefetch data;

[0039] Update the maximum logical block address corresponding to the cache unit based on the starting logical block address of the prefetch data.

[0040] Optionally, the data processing device further includes:

[0041] A data read module, configured to determine the physical address of the target data corresponding to the read command in the cache unit if it is determined that the target data corresponding to the read command is stored in the cache unit based on the starting logical block address and the number of logical blocks, and the starting logical block address and the number of logical blocks of the prefetch data stored in the cache unit;

[0042] Read the target data from the cache unit based on the physical address of the target data in the cache unit and send it out.

[0043] Optionally, the data read module is configured to determine that the target data corresponding to the read command is stored in the cache unit based on the starting logical block address and the number of logical blocks, and the starting logical block address and the number of logical blocks of the prefetch data stored in the cache unit if the quantity of the prefetch data stored in the cache unit is greater than a second threshold and the maximum logical block address corresponding to the cache unit is greater than the starting logical block address.

[0044] Optionally, the data reading module is used to determine the first logical block address range corresponding to the read command based on the starting logical block address and the number of logical blocks;

[0045] Based on the starting logical block address and the number of the pre-read data stored in the cache unit, determine the second logical block address range corresponding to the pre-read data stored in the cache unit;

[0046] If the second logical block address range is greater than or equal to the first logical block address range, determine that the target data corresponding to the read command is stored in the cache unit.

[0047] According to the third aspect of the present application, an embodiment of the present application provides a solid-state drive, including:

[0048] A flash memory unit, multiple processors, and a cache unit;

[0049] The processor is used to obtain a read command; the read command includes a starting logical block address and the number of logical blocks; based on the starting logical block address, sequentially determine the continuity of the read command with the commands in a preset plurality of data read command streams in different orders; and when it is determined that the read command is continuous with the commands in the target sequential data read command stream, increment the matching count of the target sequential data read command stream by one; if the cumulative value of the matching count of the target sequential data read command stream is greater than a first threshold, pre-read the data in the flash memory unit based on the starting logical block address and the number of logical blocks, and store the pre-read data in the cache unit, so that when the next read command is obtained, the data corresponding to the next read command can be found in the cache unit.

[0050] According to the fourth aspect of the present application, an embodiment of the present application provides a computer-readable storage medium, and the computer-readable storage medium stores computer instructions, and the computer instructions are used to cause a computer to execute the data processing method as described in the first aspect or any implementation manner of the first aspect.

[0051] According to the fifth aspect of the present application, an embodiment of the present application provides a computer program product, including a computer program or instructions, and when the computer program or instructions are executed by a processor, the data processing method as described in the first aspect or any implementation manner of the first aspect is implemented.

[0052] The data processing method, apparatus, electronic device, and computer-readable storage medium provided by the embodiments of the present application obtain a read command through a processor; the read command includes a starting logical block address and a number of logical blocks; based on the starting logical block address, the read command is successively determined for continuity with the commands in a plurality of preset data read command streams in different orders; and when it is determined that the read command is continuous with the commands in the target-order data read command stream, the matching compliance count of the target-order data read command stream is incremented by one; if the cumulative value of the matching compliance count of the target-order data read command stream is greater than a first threshold, based on the starting logical block address and the number of logical blocks, pre-read the data in the flash memory cells and store the pre-read data in the cache unit so that when the next read command is obtained, the data corresponding to the next read command can be found in the cache unit; thus, when a solid-state drive based on flash memory technology processes read commands through multiple processors, each processor can accurately identify whether the read command is an ordered data read command, and when it is recognized that the read command is an ordered data read command, trigger the start of the data pre-reading operation, thereby enabling the solid-state drive to identify multiple ordered data read command streams and perform data pre-reading through multiple processors, which can reduce the read latency of ordered data in the solid-state drive, improve the read performance of the solid-state drive, and enhance the user experience.

[0053] The above description is only an overview of the technical solution of the present application. In order to be able to understand the technical means of the present application more clearly, it can be implemented in accordance with the content of the specification. And in order to make the above and other purposes, features, and advantages of the present application more obvious and understandable, the following specifically illustrates the specific embodiments of the present application. Brief Description of the Drawings

[0054] Figure 1 It is a flowchart of a data processing method in an embodiment of the present application;

[0055] Figure 2 It is a schematic diagram showing that the multi-processor load imbalance of the solid-state drive in an embodiment of the present application causes the order distortion of different ordered data read command streams reaching the firmware;

[0056] Figure 3 It is a schematic diagram showing that the mutual interference between different read command streams in an embodiment of the present application causes the order distortion of different ordered data stream command streams reaching the firmware;

[0057] Figure 4 It is a schematic diagram of the continuity determination process in an embodiment of the present application;

[0058] Figure 5 It is a flowchart of another data processing method in an embodiment of the present application;

[0059] Figure 6 It is a schematic diagram of the structure of a data processing apparatus in an embodiment of the present application;

[0060] Figure 7 This is a schematic diagram of the hardware structure of a solid - state drive in an embodiment of the present application. Detailed implementation manners

[0061] To make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Apparently, the described embodiments are some but not all of the embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without creative efforts shall fall within the protection scope of the present application.

[0062] An embodiment of the present application provides a data processing method, which is applied to a solid - state drive. The solid - state drive includes flash memory cells, multiple processors, and a cache unit, as Figure 1 shown. The method includes:

[0063] S101, a processor obtains a read command; the read command includes a starting logical block address and a logical block count.

[0064] In this embodiment, the flash memory cells are used to store data. The processor runs firmware to implement functions such as address mapping and data pre - fetching. The cache unit serves as a data cache area of the solid - state drive and is used to store pre - fetched data. Multiple processors share the cache unit.

[0065] In this embodiment, the solid - state drive performs data pre - fetching on the received read command through multiple processors.

[0066] In this embodiment, the host side can generate multiple sequential data read command streams based on tasks and then send multiple sequential data read command streams to the solid - state drive simultaneously. Each sequential data read command stream is composed of multiple read commands, and the reading range of each read command is composed of a starting logical block address ( , LPA) and a logical block count ( ). Since the solid - state drive contains multiple processors, even if the sequential data read command streams sent by the host are strictly continuous, that is , represents the i - th read command. However, when the solid - state drive receives the read command stream, it is not strictly continuous inside. As Figure 2 shown, in the figure, the host issues 3 sequential data read command streams (Job1, Job2, and Job3), which access different lba ranges respectively. When the solid - state drive receives the read commands of Job1, due to the distribution of read commands by multiple processors inside the solid - state drive, the order in which different read command streams reach the processor firmware becomes discontinuous, and the same is true for the read commands of Job2 and Job3. When the queue depth of the sequential data read command stream of the host is larger, this discontinuous phenomenon is more obvious.

[0067] Secondly, the host issues sequential data read command streams at different times. The time overlap and timing gap between different sequential data read command streams cause the commands in multiple sequential data read command streams to be interspersed with each other in the firmware. As shown in the appendix Figure 3 As shown, the read commands of Job1, Job2, and Job3 are interspersed with each other to form the order of read commands actually received by the firmware.

[0068] After the solid-state drive receives a read command, it can first be parsed by the firmware in the processor to obtain information such as the logical address range to be read and the corresponding physical address.

[0069] S102, based on the starting logical block address, sequentially determine the continuity of the read command with the commands in a preset plurality of different sequential data read command streams; and when it is determined that the read command is continuous with the commands in the target sequential data read command stream, increment the matching count of the target sequential data read command stream by one.

[0070] In this embodiment, a pre-read data buffer and a pre-read management structure can be set for the pre-read of each sequential data command stream. The pre-read data buffer is located in the cache unit of the solid-state drive. The pre-read management structure can be stored in the processor memory. Each processor can manage the pre-read management structure. The pre-read management structure can include historical commands in the sequential data command stream or the historical read range corresponding to the commands, the matching count, the non-matching count, the valid data bitmap, the LPA of the pre-read data in the cache unit, the physical address (PBA) of the pre-read data, and the maximum LPA of the pre-read data. The historical commands in the sequential data command stream or the historical read range corresponding to the commands are used for the continuity determination of the read command. The matching count is the trigger condition for pre-read, and the non-matching count is one of the interrupt conditions for pre-read. The starting logical block address, physical address, valid data bitmap (recording whether the data is ready), and the maximum LPA of the pre-read data corresponding to each pre-read data are used for the hit determination of pre-read.

[0071] In this embodiment, when the processor obtains a read command, it can sequentially determine the continuity of the read command with the historical commands in the sequential data command stream in each pre-read management structure.

[0072] In some embodiments, for example, the solid-state drive is a solid-state drive based on NAND technology. The overall process of continuity determination is, for example, as Figure 4As shown. The consecutive count is also the matching count, and the non - consecutive count is also the non - matching count. If it is consecutive with the command in the target sequential data read command stream, for example, consecutive with the historical read command in the pre - read management structure 3, then increment the matching count of the pre - read management structure 3 by one and clear the non - matching count. Then enter the NAND data pre - reading process. If the historical read commands in all pre - read management structures are not consecutive with the current read command, the continuity determination fails, the pre - reading is interrupted, the pre - reading process is exited, and data is read from the NAND flash cell.

[0073] In some embodiments, if the read command is consecutive with the command in the target sequential data read command stream, the read command can be updated to the command in the target sequential data read command stream to update the historical commands of the target sequential data read command stream.

[0074] In some embodiments, if the cumulative value of the non - matching counts of a certain sequential data read command stream is greater than the fourth threshold, it is considered that the data in the pre - read data buffer corresponding to the current pre - read management structure is no longer suitable for the host's sequential data read command stream. Then the corresponding pre - read management structure can be re - initialized. The historical commands or the historical read ranges corresponding to the commands in the sequential data command stream in this pre - read management structure, the LPA of the pre - read data in the cache unit, the physical address (PBA) of the pre - read data, and the maximum LPA of the pre - read data are all set to invalid values; the matching count, the non - matching count, and the valid data bitmap are all set to 0. Thus, this pre - read management structure is the pre - read management structure corresponding to the invalid historical read command.

[0075] In some embodiments, if the historical read commands in all pre - read management structures are not consecutive with the current read command, it can be determined whether there is a pre - read management structure corresponding to an invalid historical read command. If so, the read command is updated to the pre - read management structure corresponding to the invalid historical read command.

[0076] S103. If the cumulative value of the matching counts of the target sequential data read command stream is greater than the first threshold, pre - read the data in the flash cell based on the starting logical block address and the number of logical blocks, and store the pre - read data in the cache unit so that when the next read command is obtained, the data corresponding to the next read command can be found in the cache unit.

[0077] In this embodiment, if the cumulative value of the matching counts of the target sequential data read command stream is greater than the first threshold, it is considered that the current solid - state drive has received a sequential data read command stream request, enter the pre - reading process, pre - read the data in the flash cell based on the starting logical block address and the number of logical blocks, and store the pre - read data in the cache unit.

[0078] The data processing method provided by the embodiment of the present application obtains a read command through a processor; the read command includes a starting logical block address and a logical block quantity; based on the starting logical block address, the read command is sequentially determined for continuity with the commands in a plurality of preset data read command streams in different orders; and when it is determined that the read command is continuous with the commands in the target sequential data read command stream, the matching compliance count of the target sequential data read command stream is incremented by one; if the cumulative value of the matching compliance count of the target sequential data read command stream is greater than a first threshold, based on the starting logical block address and the logical block quantity, pre-read the data in the flash memory unit and store the pre-read data in the cache unit, so that when the next read command is obtained, the data corresponding to the next read command can be found in the cache unit; thus, when a solid-state drive based on flash memory technology processes read commands through multiple processors, each processor can accurately identify whether the read command is a sequential data read command, and when it is recognized that the read command is a sequential data read command, trigger the start of the data pre-reading operation, so that the solid-state drive can identify multiple sequential data read command streams and pre-read data through multiple processors, which can reduce the read latency of sequential data of the solid-state drive, improve the read performance of the solid-state drive, and improve the user experience.

[0079] In an optional embodiment, in step S102, determining that the read command is continuous with the commands in the target sequential data read command stream includes:

[0080] If the ratio of the difference between the starting logical block addresses of the read command and the commands in the target sequential data read command stream to the logical block quantity corresponding to the commands in the target sequential data read command stream is less than a second threshold, it is determined that the read command is continuous with the commands in the target sequential data read command stream.

[0081] Specifically, the following formula can be used to sequentially determine the continuity of the read command with the commands in a plurality of preset data read command streams in different orders:

[0082] ;

[0083] where is the initial logical block address of the read command, is the initial logical block address corresponding to the jth command in the mth sequential data read command stream; is the logical block quantity corresponding to the jth command in the mth sequential data read command stream; is the second threshold.

[0084] In this embodiment, if the reading range of the read command and the commands in a sequential data read command stream satisfies the above formula, the read command passes the continuity determination, and this sequential data read command stream is the target sequential data read command stream.

[0085] In this embodiment, by comparing the ratio of the difference in the starting logical block address between the read command and the commands in the target sequential data read command stream to the number of logical blocks corresponding to the commands in the target sequential data read command stream with a second threshold value, it is possible to quickly determine whether the read command is consecutive with the commands in the target sequential data read command stream.

[0086] In an alternative embodiment, in step S103, pre-reading the data in the flash memory cells based on the starting logical block address and the number of logical blocks includes:

[0087] Determining the starting logical block address of the pre-read data and the amount of pre-read data based on the starting logical block address and the number of logical blocks; pre-reading the data in the flash memory cells based on the starting logical block address of the pre-read data and the amount of pre-read data.

[0088] In this embodiment, there should be a certain interval between the starting logical block address of the pre-read data and the reading range of the current read command, such that when the next read command arrives, the pre-read data is just ready in the buffer. Therefore, based on the starting logical block address and the number of logical blocks, as well as a preset pre-read waiting coefficient and a pre-read multiple coefficient, the starting logical block address of the pre-read data and the amount of pre-read data can be determined.

[0089] In this embodiment, after determining the starting logical block address and range of the pre-read data, the solid-state drive sequentially reads the data from the flash memory cells into the cache unit.

[0090] In some embodiments, it is also possible to save the starting logical block address, the amount, and the physical address in the cache unit of the pre-read data; updating the maximum logical block address corresponding to the cache unit based on the starting logical block address of the pre-read data.

[0091] Specifically in implementation, the starting logical block address, the amount, and the PBA of each pre-read data can be saved in a pre-read management structure, and at the same time, the maximum LPA of the pre-read data stored in the current cache unit is updated for hit determination. After the pre-read data storage is completed, the corresponding valid data position in the pre-read management structure is set to 1.

[0092] In some embodiments, determining the starting logical block address of the pre-read data and the amount of pre-read data based on the starting logical block address and the number of logical blocks includes:

[0093] Performing a first weighting process on the starting logical block address based on the number of logical blocks and a first coefficient to obtain the starting logical block address of the pre-read data; performing a second weighting process on the number of logical blocks based on a second coefficient to obtain the amount of pre-read data.

[0094] In specific implementation, accuracy and coverage are used to measure the performance of the prefetching algorithm. The accuracy of prefetching is defined as the ratio of the correctly prefetched data to all the prefetched data, and the coverage is defined as the ratio of the correctly prefetched data to all the prefetched data. To ensure the accuracy and coverage of the prefetching algorithm, the starting logical block address of the prefetched data can be set to:

[0095] ;

[0096] The number of prefetched data can be set to:

[0097] ;

[0098] where is the waiting coefficient for prefetching, that is, the first coefficient; is the multiple coefficient for prefetching, that is, the second coefficient. The starting logical block address of the prefetched data; is the starting logical block address corresponding to the read command, the number of logical blocks.

[0099] In this embodiment, based on the number of logical blocks and the first coefficient, a first weighting process is performed on the starting logical block address to obtain the starting logical block address of the prefetched data; based on the second coefficient, a second weighting process is performed on the number of logical blocks to obtain the number of prefetched data; the accuracy and coverage of the prefetched data can be improved by adjusting the first coefficient and the second coefficient, and the overall read interference of the solid-state drive can be reduced.

[0100] In an alternative embodiment, as Figure 5 shown, the data processing method further includes:

[0101] S104. If it is determined that the target data corresponding to the read command is stored in the cache unit based on the starting logical block address and the number of logical blocks, and the starting logical block address and the number of the prefetched data stored in the cache unit, determine the physical address of the target data corresponding to the read command in the cache unit;

[0102] S105. Based on the physical address of the target data in the cache unit, read the target data from the cache unit and send it out.

[0103] In some embodiments, in step S104, determining that the target data corresponding to the read command is stored in the cache unit based on the starting logical block address and the number of logical blocks, and the starting logical block address and the number of the prefetched data stored in the cache unit includes:

[0104] If the quantity of pre-read data stored in the cache unit is greater than a third threshold value, and the maximum logical block address corresponding to the cache unit is greater than the starting logical block address, based on the starting logical block address, the quantity of logical blocks, as well as the starting logical block address and quantity corresponding to the pre-read data stored in the cache unit, determine that the target data corresponding to the read command is stored in the cache unit.

[0105] In this embodiment, before determining, based on the starting logical block address, the quantity of logical blocks, as well as the starting logical block address and quantity corresponding to the pre-read data stored in the cache unit, that the target data corresponding to the read command is stored in the cache unit, first, by determining whether the quantity of pre-read data stored in the cache unit is greater than a third threshold value, and determining whether the maximum logical block address corresponding to the cache unit is greater than the starting logical block address, it can be timely determined whether there is sufficient data in the cache unit and whether the target data corresponding to the read command exists in the cache unit, avoiding a useless data search process.

[0106] In some embodiments, in step S104, determining, based on the starting logical block address, the quantity of logical blocks, as well as the starting logical block address and quantity corresponding to the pre-read data stored in the cache unit, that the target data corresponding to the read command is stored in the cache unit includes:

[0107] Based on the starting logical block address and the quantity of logical blocks, determine the first logical block address range corresponding to the read command; based on the starting logical block address and quantity corresponding to the pre-read data stored in the cache unit, determine the second logical block address range corresponding to the pre-read data stored in the cache unit; if the second logical block address range is greater than or equal to the first logical block address range, determine that the target data corresponding to the read command is stored in the cache unit.

[0108] Specifically in implementation, when a read command arrives, if it passes the sequential data read naming stream determination, then enter the pre-read hit determination process.

[0109] 1. Determine whether there is a sufficient quantity of data in the cache unit. Since reading data from the flash memory cells takes a delay of dozens of microseconds, while transmitting data from the cache unit to the host only takes a few microseconds, in order to ensure that pre-reading can continuously hit, the firmware needs to check the quantity of valid data in the cache unit. When the quantity of valid data is greater than a third threshold value, continue with the next step, otherwise exit the pre-read process.

[0110] 2. Determine whether the LPA of the current read command is within the LPAs corresponding to the pre-read data. Compare the LPA of the current read command with the largest LPA of the valid data in the cache. If the LPA of the current read command is greater than or equal to the largest LPA of the valid data in the cache, then the target data of the current read command does not exist in the cache unit, and a pre-read interrupt is triggered. If the LPA of the current read command is less than the largest LPA of the valid data in the cache, then the target data corresponding to the current read command may exist in the cache unit, and proceed to the next step.

[0111] 3. Locate the position of the target data corresponding to the read command in the cache unit. According to the LPAs of each pre-read data saved, use the binary search method to find the position of the current read command LPA in the cache unit, and determine whether all the logical block addresses (LBAs) of the read command are fully hit. If all are hit, then proceed to the next step; otherwise, consider the pre-read to fail and exit the pre-read process.

[0112] 4. Based on the position of the matching LBA in the cache unit and the PBAs of each saved data, determine whether the PBAs at the LBA hit positions all match. If they match, then determine that the pre-read is a hit, notify the host to fetch the corresponding part of the data in the cache unit, and clear the corresponding valid data bits to 0. If they do not match, then determine that the hit fails and exit the pre-read process.

[0113] In this embodiment, if based on the starting logical block address and the number of logical blocks, as well as the starting logical block address and the number of the pre-read data stored in the cache unit, it is determined that the target data corresponding to the read command is stored in the cache unit, determine the physical address of the target data corresponding to the read command in the cache unit; based on the physical address of the target data in the cache unit, read the target data from the cache unit and send it out; in this way, the response to the read command can be quickly implemented, and the target data corresponding to the read command can be sent out, reducing the read latency of the solid-state drive.

[0114] The embodiment of the present application provides a data processing device, which is applied to a solid-state drive. The solid-state drive includes flash memory cells, multiple processors, and a cache unit, as Figure 6 shown. The device includes:

[0115] An acquisition module 61, configured to acquire a read command; the read command includes a starting logical block address and the number of logical blocks.

[0116] A determination module 62, configured to, based on the starting logical block address, sequentially determine the continuity of the read command with the commands in a preset multiple different-order data read command streams; and when it is determined that the read command is continuous with the commands in the target-order data read command stream, increment the matching count of the target-order data read command stream by one.

[0117] A prefetch module 63, configured to, if the cumulative value of the number of matches of the target sequential data read command stream is greater than a first threshold, prefetch data in the flash memory cells based on the starting logical block address and the number of logical blocks, and store the prefetched data in a cache unit, so that when the next read command is obtained, the data corresponding to the next read command can be found in the cache unit.

[0118] In the data processing apparatus provided by the embodiment of the present application, a processor obtains a read command; the read command includes a starting logical block address and the number of logical blocks; based on the starting logical block address, the read command is sequentially determined for continuity with the commands in a plurality of preset different sequential data read command streams; and when it is determined that the read command is continuous with the commands in the target sequential data read command stream, the number of matches of the target sequential data read command stream is incremented by one; if the cumulative value of the number of matches of the target sequential data read command stream is greater than a first threshold, prefetch data in the flash memory cells based on the starting logical block address and the number of logical blocks, and store the prefetched data in a cache unit, so that when the next read command is obtained, the data corresponding to the next read command can be found in the cache unit; thus, when a solid-state drive based on flash memory technology processes read commands through multiple processors, each processor can accurately identify whether the read command is a sequential data read command, and when it is recognized that the read command is a sequential data read command, trigger the start of a data prefetch operation, so that the solid-state drive can identify and prefetch multiple sequential data read command streams through multiple processors, which can reduce the read latency of sequential data in the solid-state drive, improve the read performance of the solid-state drive, and improve the user experience.

[0119] In some embodiments, the determination module is configured to, if the ratio of the difference between the starting logical block addresses between the read command and the commands in the target sequential data read command stream to the number of logical blocks corresponding to the commands in the target sequential data read command stream is less than a second threshold, determine that the read command is continuous with the commands in the target sequential data read command stream.

[0120] In some embodiments, the prefetch module is configured to determine the starting logical block address of the prefetched data and the number of prefetched data based on the starting logical block address and the number of logical blocks; and prefetch the data in the flash memory cells based on the starting logical block address of the prefetched data and the number of prefetched data.

[0121] In some embodiments, the prefetch module is configured to perform a first weighted processing on the starting logical block address based on the number of logical blocks and a first coefficient to obtain the starting logical block address of the prefetched data; and perform a second weighted processing on the number of logical blocks based on a second coefficient to obtain the number of prefetched data.

[0122] In some embodiments, the data processing apparatus further includes:

[0123] An update module, configured to save the starting logical block address, quantity, and physical address in the cache unit of the pre-read data; and update the maximum logical block address corresponding to the cache unit based on the starting logical block address of the pre-read data.

[0124] In some embodiments, the data processing device further includes:

[0125] A data reading module, configured to, if it is determined that the target data corresponding to the read command is stored in the cache unit based on the starting logical block address, logical block quantity, and the starting logical block address and quantity of the pre-read data stored in the cache unit, determine the physical address of the target data corresponding to the read command in the cache unit; and read the target data from the cache unit based on the physical address of the target data in the cache unit and send it out.

[0126] In some embodiments, the data reading module is configured to, if the quantity of the pre-read data stored in the cache unit is greater than a second threshold and the maximum logical block address corresponding to the cache unit is greater than the starting logical block address, determine that the target data corresponding to the read command is stored in the cache unit based on the starting logical block address, logical block quantity, and the starting logical block address and quantity of the pre-read data stored in the cache unit.

[0127] In some embodiments, the data reading module is configured to determine a first logical block address range corresponding to the read command based on the starting logical block address and logical block quantity; determine a second logical block address range corresponding to the pre-read data stored in the cache unit based on the starting logical block address and quantity of the pre-read data stored in the cache unit; and if the second logical block address range is greater than or equal to the first logical block address range, determine that the target data corresponding to the read command is stored in the cache unit.

[0128] According to an embodiment of the present application, the present application further provides a solid-state drive, including flash memory cells, a plurality of processors, and a cache unit. The processor is configured to obtain a read command; the read command includes a starting logical block address and a logical block quantity; based on the starting logical block address, continuously determine the read command with commands in a preset plurality of different-order data read command streams in sequence; and when it is determined that the read command is continuous with the commands in the target-order data read command stream, increment the matching count of the target-order data read command stream by one; if the cumulative value of the matching count of the target-order data read command stream is greater than a first threshold, pre-read the data in the flash memory cells based on the starting logical block address and logical block quantity, and store the pre-read data in the cache unit, so that when the next read command is obtained, the data corresponding to the next read command can be found in the cache unit.

[0129] Figure 7A schematic block diagram of an example solid state drive that can be used to implement an embodiment of the present application is shown.

[0130] As Figure 7 shown, the solid state drive includes a solid state drive controller (SSD controller), flash memory cells 804, and a cache unit 808. The SSD controller includes a plurality of processors 801, which can perform various appropriate actions and processes according to a computer program stored in a static random access memory (SRAM) 802. The processors 801, a DRAM controller 803, and the static random access memory 802 are connected to each other via a bus 805. A host interface 806 and a flash memory interface 807 are also connected to the bus 805. The flash memory cells 804, such as a memory, are connected to the flash memory interface 807. The cache unit 808 can be a double data rate synchronous dynamic random access memory (DDR) and is connected to the DRAM controller 803.

[0131] The host interface 806 can serve as an input / output interface.

[0132] The processor 801 can be various general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the processor 801 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any appropriate processor, controller, microcontroller, etc. The processor 801 executes the various methods and processes described above, such as a data processing method. For example, in some embodiments, the data processing method can be implemented as a computer software program that is tangibly embodied in a machine-readable medium, such as the static random access memory 802. In some embodiments, part or all of the computer program can be loaded and / or installed on the solid state drive. When the computer program is executed by the processor 801, one or more steps of the data processing method described above can be executed. Alternatively, in other embodiments, the processor 801 can be configured to execute the data processing method by any other appropriate means (e.g., by means of firmware).

[0133] The various embodiments of the systems and techniques described above in this document may be implemented in digital electronic circuitry, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on a chip (SOCs), complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include: being implemented in one or more computer programs that may be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a special-purpose or general-purpose programmable processor that receives data and instructions from a storage system, at least one input device, and at least one output device, and transmits the data and instructions to the storage system, the at least one input device, and the at least one output device.

[0134] The program code for implementing the methods of this application may be written in any combination of one or more programming languages. These program codes may be provided to a processor or controller of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when the program codes are executed by the processor or controller, the functions / operations specified in the flowchart and / or block diagram are implemented. The program code may be executed entirely on the machine, partially on the machine, executed partially on the machine as an independent software package and partially on a remote machine, or executed entirely on a remote machine or server.

[0135] The embodiments of this application provide a computer program product or a computer program, which includes computer instructions stored in a computer-readable storage medium. The processor of the computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the computer device executes the data processing method described above in the embodiments of this application.

[0136] The embodiments of this application provide a computer-readable storage medium storing executable instructions, where the executable instructions, when executed by a processor, will cause the processor to execute the data processing method provided in the embodiments of this application.

[0137] In some embodiments, a computer-readable storage medium can be a tangible medium that can contain or store a program for use by or in connection with an instruction execution system, apparatus, or device. The computer-readable storage medium can be a machine-readable signal medium or a machine-readable storage medium. The computer-readable storage medium can include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of the computer-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0138] In some embodiments, the executable instructions can be in the form of a program, software, a software module, a script, or code, written in any form of programming language (including compiled or interpreted languages, or declarative or procedural languages), and can be deployed in any form, including being deployed as a stand-alone program or being deployed as a module, component, subroutine, or other unit suitable for use in a computing environment.

[0139] As an example, the executable instructions may or may not correspond to a file in a file system, may be stored as part of a file that holds other programs or data, for example, in one or more scripts in a hypertext markup language (HTML) document, stored in a single file dedicated to the program being discussed, or, stored in multiple cooperating files (e.g., files that store one or more modules, subroutines, or portions of code).

[0140] As an example, the executable instructions can be deployed to execute on one computing device, or on multiple computing devices located at one site, or, on multiple computing devices distributed at multiple sites and interconnected by a communication network.

[0141] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device for displaying information to the user (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor); and a keyboard and a pointing device (e.g., a mouse or a trackball) by which the user can provide input to the computer. Other kinds of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, speech input, or tactile input).

[0142] The systems and techniques described herein can be implemented in a computing system including backend components (e.g., as a data server), or a computing system including middleware components (e.g., an application server), or a computing system including frontend components (e.g., a user computer having a graphical user interface or a web browser through which the user can interact with an implementation of the systems and techniques described herein), or a computing system including any combination of such backend components, middleware components, or frontend components. The components of the system can be interconnected to each other by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: local area network (LAN), wide area network (WAN), and the Internet.

[0143] A computer system can include a client and a server. The client and the server are generally remote from each other and typically interact through a communication network. The relationship between the client and the server is generated by computer programs running on the respective computers and having a client-server relationship with each other. The server can be a cloud server, can also be a server of a distributed system, or a server incorporating a blockchain.

[0144] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps recited in this application can be executed in parallel, sequentially, or in a different order, as long as the desired results of the technical solutions disclosed in this application can be achieved, and no limitation is made herein.

[0145] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" can explicitly or implicitly include at least one of such features. In the description of this application, "a plurality of" means two or more unless otherwise specifically defined.

[0146] As described above, it is only the specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present application can easily think of changes or substitutions, which should all be covered within the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims described above.

Claims

1. A data processing method is applied to a solid-state drive, the solid-state drive includes flash memory cells, multiple processors, and a cache unit, and is characterized in that, The solid-state drive distributes multiple read commands in a sequential read command stream sent by a host to multiple processors for processing, and the starting logical block addresses of the read commands received by the firmware of each processor are discontinuous. The method includes: The processor obtains a read command; the read command includes a starting logical block address and a number of logical blocks; Based on the starting logical block address, sequentially comparing the starting logical block address of the read command with starting logical block addresses of commands in a plurality of preset different sequential data read command streams for continuity; and when it is determined that the starting logical block address of the read command is continuous with the starting logical block address of any command in the target sequential data read command stream, incrementing a matching count of the target sequential data read command stream by one; If the cumulative value of the number of matches of the target sequential data read command stream is greater than a first threshold, the data in the flash memory unit is pre-read based on the starting logical block address of the read command and the number of logical blocks, and the pre-read data is stored in the cache unit, so that when the next read command is obtained, the data corresponding to the next read command can be found in the cache unit.

2. The data processing method according to claim 1, wherein: Determining that the starting logical block address of the read command is continuous with the starting logical block address of any command in the target sequential data read command stream includes: If the ratio of the starting logical block address difference between the read command and any command in the target sequential data read command stream to the number of logical blocks corresponding to the command in the target sequential data read command stream is less than a second threshold, it is determined that the read command is continuous with any command in the target sequential data read command stream.

3. The data processing method according to claim 1, wherein: Pre-reading data in the flash memory unit based on the starting logical block address of the read command and the number of logical blocks, including: Determining a starting logical block address of pre-read data and the amount of pre-read data based on the starting logical block address of the read command and the number of logical blocks; The data in the flash memory unit is pre-read based on the starting logical block address of the pre-read data and the amount of the pre-read data.

4. The data processing method according to claim 3, wherein Determining a starting logical block address of pre-read data and the amount of pre-read data based on the starting logical block address of the read command and the number of logical blocks includes: performing a first weighted processing on the starting logical block address of the read command based on the number of logical blocks and the first coefficient to obtain the starting logical block address of the pre-read data; Based on the second coefficient, a second weighting process is performed on the number of logic blocks to obtain the number of pre-read data.

5. The data processing method according to claim 3, wherein Also includes: storing the starting logical block address, quantity and physical address of the pre-read data in the cache unit; Based on the starting logical block address of the pre-read data, the maximum logical block address corresponding to the cache unit is updated.

6. The data processing method according to claim 1, wherein Also includes: If it is determined that the target data corresponding to the read command is stored in the cache unit based on the starting logical block address and the number of logical blocks of the read command, and the starting logical block address and the number of the pre-read data stored in the cache unit, determine the physical address of the target data corresponding to the read command in the cache unit; Read the target data from the cache unit based on the physical address of the target data in the cache unit, and send it out.

7. The data processing method according to claim 6, wherein Determining that the target data corresponding to the read command is stored in the cache unit based on the starting logical block address and the number of logical blocks of the read command, and the starting logical block address and the number of the pre-read data stored in the cache unit, includes: If the number of the pre-read data stored in the cache unit is greater than a second threshold, and the maximum logical block address corresponding to the cache unit is greater than the starting logical block address of the read command, determine that the target data corresponding to the read command is stored in the cache unit based on the starting logical block address and the number of logical blocks of the read command, and the starting logical block address and the number of the pre-read data stored in the cache unit.

8. The data processing method according to claim 6, characterized in that Determining that the target data corresponding to the read command is stored in the cache unit based on the starting logical block address and the number of logical blocks of the read command, and the starting logical block address and the number of the pre-read data stored in the cache unit, includes: Determine the first logical block address range corresponding to the read command based on the starting logical block address and the number of logical blocks of the read command; Determine the second logical block address range corresponding to the pre-read data stored in the cache unit based on the starting logical block address and the number of the pre-read data stored in the cache unit; If the second logical block address range is greater than or equal to the first logical block address range, determine that the target data corresponding to the read command is stored in the cache unit.

9. A data processing device, applied to a solid-state hard disk, wherein the solid-state hard disk comprises a flash memory unit, multiple processors, and a cache unit, characterized in that: The solid state drive distributes multiple read commands in the sequential read command stream sent by the host to multiple processors for processing, and the starting logical block addresses between the read commands received by each processor firmware are not continuous. The device includes: An acquisition module, configured to acquire a read command; the read command includes a starting logical block address and the number of logical blocks; A determination module, configured to sequentially determine the continuity of the starting logical block address of the read command with the starting logical block addresses of the commands in a preset multiple different sequential data read command streams based on the starting logical block address; and when it is determined that the starting logical block address of the read command is continuous with any one of the starting logical block addresses of the commands in the target sequential data read command stream, increment the matching count of the target sequential data read command stream by one; A prefetch module, which is configured to, if the cumulative value of the number of matches of the target sequential data read command stream is greater than a first threshold, prefetch the data in the flash memory cells based on the starting logical block address of the read command and the number of logical blocks, and store the prefetched data in the cache unit, so that when the next read command is obtained, the data corresponding to the next read command can be found in the cache unit.

10. The data processing device according to claim 9, characterized in that The determination module is configured to, if the ratio of the difference between the starting logical block addresses between the read command and any command in the target sequential data read command stream to the number of logical blocks corresponding to the command in the target sequential data read command stream is less than a second threshold, determine that the read command is consecutive with any command in the target sequential data read command stream.

11. The data processing device according to claim 9, wherein The prefetch module is configured to determine the starting logical block address and the quantity of the prefetched data based on the starting logical block address of the read command and the number of logical blocks. Based on the starting logical block address and the quantity of the prefetched data, prefetch the data in the flash memory cells.

12. The data processing device according to claim 11, characterized in that The prefetch module is configured to perform a first weighted processing on the starting logical block address of the read command based on the number of logical blocks and a first coefficient to obtain the starting logical block address of the prefetched data. Based on a second coefficient, perform a second weighted processing on the number of logical blocks to obtain the quantity of the prefetched data.

13. The data processing device according to claim 11, characterized in that, It further includes: An update module, which is configured to save the starting logical block address, the quantity, and the physical address in the cache unit of the prefetched data. Based on the starting logical block address of the prefetched data, update the maximum logical block address corresponding to the cache unit.

14. The data processing device according to claim 9, wherein It further includes: A data reading module, which is configured to, if it is determined that the target data corresponding to the read command is stored in the cache unit based on the starting logical block address and the number of logical blocks of the read command, and the starting logical block address and the quantity of the prefetched data stored in the cache unit, determine the physical address of the target data corresponding to the read command in the cache unit. Based on the physical address of the target data in the cache unit, read the target data from the cache unit and send it out.

15. The data processing device according to claim 14, characterized in that The data reading module is configured to, if the quantity of the prefetched data stored in the cache unit is greater than a third threshold, and the maximum logical block address corresponding to the cache unit is greater than the starting logical block address of the read command, determine that the target data corresponding to the read command is stored in the cache unit based on the starting logical block address and the number of logical blocks of the read command, and the starting logical block address and the quantity of the prefetched data stored in the cache unit.

16. The data processing device according to claim 14, wherein The data reading module is configured to determine the first logical block address range corresponding to the read command based on the starting logical block address and the number of logical blocks of the read command. Based on the starting logical block address and the quantity of the prefetched data stored in the cache unit, determine the second logical block address range corresponding to the prefetched data stored in the cache unit. If the second logical block address range is greater than or equal to the first logical block address range, it is determined that the target data corresponding to the read command is stored in the cache unit.

17. A solid-state drive, characterized in that, Including: Flash memory cells, multiple processors, and a cache unit; The solid-state drive distributes multiple read commands in the sequential read command stream sent by the host to the multiple processors for processing, and the starting logical block addresses between the read commands received by each processor firmware are not continuous. The processor is used to obtain the read command; the read command includes a starting logical block address and a logical block count. Based on the starting logical block address, the starting logical block address of the read command is sequentially determined for continuity with the starting logical block addresses of the commands in a preset multiple different sequential data read command streams; and when it is determined that the starting logical block address of the read command is continuous with any one of the starting logical block addresses of the commands in the target sequential data read command stream, the matching count of the target sequential data read command stream is incremented by one; if the cumulative value of the matching count of the target sequential data read command stream is greater than a first threshold, based on the starting logical block address and the logical block count of the read command, pre-read the data in the flash memory cells and store the pre-read data in the cache unit so that when the next read command is obtained, the data corresponding to the next read command can be found in the cache unit.

18. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions for causing a computer to execute the data processing method according to any one of claims 1-8.

19. A computer program product, comprising a computer program or instructions, characterized in that, When the computer program or instruction is executed by a processor, the data processing method according to any one of claims 1 to 8 is implemented.

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