Initiation signal processing circuit and communication system

Abstract

The invention discloses an initial signal processing circuit and a communication system, the circuit comprises a first signal identification circuit, a second signal identification circuit, a chip selection circuit and a signal output circuit, the data input end of the first signal identification circuit is connected with the reverse output end of the chip selection circuit and an SCL signal line, and the data output end of the second signal identification circuit is connected with the reverse output end of the chip selection circuit. The clock input end is connected with an SDA signal line, and the output end is connected with the first input end of the signal output circuit; the data input end of the second signal identification circuit is connected with the positive output end of the chip selection circuit and the SCL signal line, the clock input end is connected with the SDA signal line, and the output end is connected with the second input end of the signal output circuit; the data input end of the chip selection circuit is connected with the SCL signal line, and the clock input end of the chip selection circuit is connected with the SDA signal line; the output end of the signal output circuit is connected with at least one slave device to be communicated. According to the circuit, the problem of communication interruption caused by multiple times of continuous occurrence of initial signals in traditional I2C communication can be solved.

Description

Technical Field

[0001] This application relates to the field of digital integrated circuit technology, and particularly to a start signal processing circuit and a communication system. Background Art

[0002] I2C (Inter-Integrated Circuit) is a common serial communication protocol and also a two-wire communication protocol, which is simple and flexible and is mainly used to connect low-speed peripheral devices such as sensors, EEPROMs, real-time clocks (RTCs), LCD displays, etc.

[0003] In the I2C communication protocol, the start signal (START) is triggered by the SDA signal line jumping from high level to low level during the high level of the SCL clock. However, during the I2C communication process, multiple START signals may continuously appear in the I2C-related communication link due to reasons such as level fluctuations and non-standard communication protocols.

[0004] In a conventional I2C start signal processing circuit, it is usually designed to start I2C communication when the SCL signal line outputs a high level and the SDA signal line outputs a falling edge. However, if a START signal is received again immediately at this time, the circuit may not be able to recognize it, resulting in the circuit being unable to restart I2C communication. Summary of the Invention

[0005] In view of this, the embodiments of this application provide a start signal processing circuit and a communication system, mainly aiming to solve the technical problem that inaccurate recognition of the START signal leads to the inability to start I2C communication.

[0006] According to an aspect of the present application, a start signal processing circuit is provided, which is applied to a digital circuit using the I2C serial communication protocol. The start signal processing circuit includes a first signal recognition circuit, a second signal recognition circuit, a chip selection circuit, and a signal output circuit. Among them, the data input terminal of the first signal recognition circuit is connected to the reverse output terminal of the chip selection circuit and the SCL signal line, the clock input terminal is connected to the SDA signal line, and the output terminal is connected to the first input terminal of the signal output circuit; the data input terminal of the second signal recognition circuit is connected to the forward output terminal of the chip selection circuit and the SCL signal line, the clock input terminal is connected to the SDA signal line, and the output terminal is connected to the second input terminal of the signal output circuit; the data input terminal of the chip selection circuit is connected to the SCL signal line, and the clock input terminal is connected to the SDA signal line; the output terminal of the signal output circuit is connected to at least one slave device to be communicated; among them, when the chip selection circuit outputs a first logic signal and the first signal recognition circuit outputs a second logic signal, or when the chip selection circuit outputs a second logic signal and the second signal recognition circuit outputs a second logic signal, the signal output circuit outputs a start signal to the slave device.

[0007] Optionally, the first signal recognition circuit includes a first signal acquisition module, a first signal synchronization module, and a first signal integration module; the data input terminal of the first signal acquisition module is connected to the reverse output terminal of the chip selection circuit and the SCL signal line, and the clock input terminal is connected to the SDA signal line; the data input terminal of the first signal synchronization module is connected to the output terminal of the first signal acquisition module, and the clock input terminal is connected to the SCL signal line; the first input terminal of the first signal integration module is connected to the output terminal of the first signal acquisition module, the second input terminal is connected to the output terminal of the first signal synchronization module, and the output terminal is connected to the first input terminal of the signal output circuit.

[0008] Optionally, the first signal acquisition module includes a first D flip-flop, which is used to follow the logical AND operation signal of the inverted signal of the chip selection signal output by the chip selection circuit and the signal output by the SCL signal line when the SDA signal line outputs a falling edge, so as to output a first acquisition signal; the first signal synchronization module includes a second D flip-flop, which is used to follow the first acquisition signal when the SCL signal line outputs a rising edge, so as to output a first synchronization signal; the first signal output module includes a first NOT gate unit and a first AND gate unit, which are used to invert the first synchronization signal and perform a logical AND operation on the first acquisition signal and the inverted signal of the first synchronization signal, so as to output a first start signal.

[0009] Optionally, the second signal recognition circuit includes a second signal acquisition module, a second signal synchronization module, and a second signal integration module; the data input terminal of the second signal acquisition module is connected to the positive output terminal of the chip select circuit and the SCL signal line, and the clock input terminal is connected to the SDA signal line; the data input terminal of the second signal synchronization module is connected to the output terminal of the second signal acquisition module, and the clock input terminal is connected to the SCL signal line; the first input terminal of the second signal integration module is connected to the output terminal of the second signal acquisition module, the second input terminal is connected to the output terminal of the second signal synchronization module, and the output terminal is connected to the second input terminal of the signal output circuit.

[0010] Optionally, the second signal acquisition module includes a third D flip-flop, which is used to follow the logical AND operation signal of the chip select signal output by the chip select circuit and the signal output by the SCL signal line when the SDA signal line outputs a falling edge, so as to output a second acquisition signal; the second signal synchronization module includes a fourth D flip-flop, which is used to follow the second acquisition signal when the SCL signal line outputs a rising edge, so as to output a second synchronization signal; the second signal output module includes a second NOT gate unit and a second AND gate unit, which are used to invert the second synchronization signal and perform a logical AND operation on the second acquisition signal and the inverted signal of the second synchronization signal, so as to output a second start signal.

[0011] Optionally, the chip select circuit includes a third signal acquisition module, a positive output module, and a negative output module; the data input terminal of the third signal acquisition module is connected to the SCL signal line, and the clock input terminal is connected to the SDA signal line; the first input terminal of the negative output module is connected to the output terminal of the third signal acquisition module, the second input terminal is connected to the SCL signal line, and the output terminal is connected to the data input terminal of the first signal recognition circuit; the first input terminal of the positive output module is connected to the output terminal of the third signal acquisition module, the second input terminal is connected to the SCL signal line, and the output terminal is connected to the data input terminal of the second signal recognition circuit.

[0012] Optionally, the third signal acquisition module includes a fifth flip-flop, which is used to follow the signal output by the SCL signal line when the SDA signal line outputs a falling edge, so as to output a chip select signal; the negative output module includes a third NOT gate unit and a third AND gate unit, which are used to invert the chip select signal and input the logical AND operation signal of the inverted signal of the chip select signal and the signal output by the SCL signal line into the data input terminal of the first signal recognition circuit; the positive output module includes a fourth AND gate unit, which is used to input the logical AND operation signal of the chip select signal and the signal output by the SCL signal line into the data input terminal of the second signal recognition circuit.

[0013] Optionally, the reverse output module further includes a fourth NOT gate unit and a fifth AND gate unit, configured to invert the chip select signal, and input a logical AND operation signal of the inverted signal of the chip select signal and the first start signal output by the first signal recognition circuit into the first input end of the signal output circuit; the forward output module further includes a sixth AND gate unit, configured to input a logical AND operation signal of the chip select signal and the second start signal output by the second signal recognition circuit into the second input end of the signal output circuit.

[0014] Optionally, the signal output circuit includes an exclusive OR unit, wherein a first input end of the exclusive OR unit is connected to an output end of the first signal recognition circuit, a second input end is connected to an output end of the second signal recognition circuit, and an output end is connected to the slave device; alternatively, the first input end of the exclusive OR unit is connected to the output end of the first signal recognition circuit and the reverse output end of the chip select circuit, the second input end is connected to the output end of the second signal recognition circuit and the forward output end of the chip select circuit, and the output end is connected to the slave device.

[0015] According to another aspect of the present application, a communication system is provided, where the communication system includes a master device, at least one slave device, and the start signal processing circuit as described in any one of the above, wherein the start signal processing circuit is connected between the master device and the at least one slave device.

[0016] By means of the above technical solution, the start signal processing circuit and the communication system provided by the embodiments of the present application can solve the problem of communication interruption caused by the repeated continuous occurrence of START signals (start signals) in traditional I2C communication by setting two signal recognition circuits and using the polling switching mechanism of the chip select circuit. In the present application, the two signal recognition circuits can work independently in two states where the chip select signal is a first logic signal (such as low level) or a second logic signal (such as high level). When a valid START signal is detected, regardless of the current chip select state, the start signal output can be triggered and the I2C communication can be restarted. Based on this, when multiple START signals are continuously generated on the I2C communication link, the dynamic switching mechanism of the chip select circuit enables the two signal recognition circuits to alternately obtain the detection priority. Therefore, each START event can be independently recognized and trigger the communication reset. This circuit design method enables the bus state machine to have self-recovery ability. Even if the previous communication is not completed, the new START signal can still force the bus back to the known initial state and restart the I2C communication, thus ensuring the reliability and robustness of the I2C communication.

[0017] The above description is only an overview of the technical solution of the present application. In order to better understand the technical means of the present application, it can be implemented according to the content of the specification. And in order to make the above and other purposes, features and advantages of the present application more obvious and understandable, the specific embodiments of the present application are specifically given below. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The schematic embodiments and descriptions thereof of the present application are used to explain the present application and do not constitute an improper limitation to the present application. In the drawings: Figure 1 The circuit schematic diagram of a start signal processing circuit provided by the prior art is shown; Figure 2 The waveform diagram of a start signal processing circuit provided by the prior art when encountering two consecutive start signals is shown; Figure 3 The waveform diagram of a start signal processing circuit provided by the prior art when encountering three consecutive start signals is shown; Figure 4 The structural schematic diagram of a start signal processing circuit provided by an embodiment of the present application is shown; Figure 5 The structural schematic diagram of another start signal processing circuit provided by an embodiment of the present application is shown; Figure 6 The circuit schematic diagram of a start signal processing circuit provided by an embodiment of the present application is shown; Figure 7 The waveform diagram of a start signal processing circuit provided by an embodiment of the present application when encountering two consecutive start signals is shown; Figure 8 The waveform diagram of a start signal processing circuit provided by an embodiment of the present application when encountering three consecutive start signals is shown. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0019] The present application will be described in detail below with reference to the drawings and in combination with embodiments. It should be noted that, without conflict, the embodiments in the present application and the features in the embodiments can be combined with each other.

[0020] In the I2C serial communication protocol, the start signal (START signal) needs to meet the condition that the SDA signal jumps from high level to low level during the high level of the SCL. However, the level fluctuations of the SCL and SDA communication links when the MCU is powered on and the consecutive START / STOP signals may all cause the state machine to fail due to timing conflicts or incorrect reset, thus making it impossible to restart the I2C communication.

[0021] For example, a traditional START signal recognition circuit is as follows Figure 1 shown. In this circuit, the falling edge of SDA is used as the sampling clock. When the SCL signal is high during sampling, the start_1 signal is set to 1; otherwise, the start_1 signal is set to 0. Then, the rising edge of SCL is used as the synchronization clock to synchronize the start_1 signal by one beat, generating the start_1_dl0 signal. In this scenario, when the start_1 signal is high and the start_1_dl0 signal is low (the start_1 signal has not been synchronized), the start_bit signal is set to high to initiate an I2C communication. At this time, the slave device can detect the start signal on the bus, start listening for the slave address sent on the bus, and prepare to interact with the master device for data transfer.

[0022] However, during the I2C communication process, multiple START signals may appear continuously. For example, when the I2C slave device is already powered on normally and the MCU connected to the peripheral device is powered on, the I2C-related communication link may generate voltage fluctuations, thus generating a special waveform similar to the START signal. Or, the I2C master device may also send a START signal again without sending an end signal (STOP signal) and start a new data transfer. In this scenario, two or three START signals may be continuously generated on the I2C communication link. At this time, the waveform diagram of this circuit is as shown in Figure 2 and Figure 3 shown. As shown in the waveform in the figure, in the traditional I2C circuit design, an I2C communication can be initiated when SCL is high and SDA is at the falling edge. However, if a START signal is received again at this time, the circuit cannot effectively recognize it, thus unable to restart the I2C communication, resulting in the failure of the I2C communication.

[0023] To address the above problems, in one embodiment, as shown in Figure 4As shown in the figure, a start signal processing circuit is provided. The above circuit can be applied to a digital circuit using the I2C serial communication protocol. The circuit includes a first signal recognition circuit 10, a second signal recognition circuit 20, a chip selection circuit 30, and a signal output circuit 40. Among them, the data input terminal of the first signal recognition circuit 10 is connected to the reverse output terminal of the chip selection circuit 30 and the SCL signal line, the clock input terminal is connected to the SDA signal line, and the output terminal is connected to the first input terminal of the signal output circuit 40; the data input terminal of the second signal recognition circuit 20 is connected to the forward output terminal of the chip selection circuit 30 and the SCL signal line, the clock input terminal is connected to the SDA signal line, and the output terminal is connected to the second input terminal of the signal output circuit 40; the data input terminal of the chip selection circuit 30 is connected to the SCL signal line, and the clock input terminal is connected to the SDA signal line; the output terminal of the signal output circuit 40 is connected to at least one slave device to be communicated. Among them, when the chip selection circuit 30 outputs a first logic signal and the first signal recognition circuit 10 outputs a second logic signal, or when the chip selection circuit 30 outputs a second logic signal and the second signal recognition circuit 20 outputs a second logic signal, the signal output circuit outputs a start signal to the slave device.

[0024] In this embodiment, the chip selection circuit 30 can generate a chip selection signal (SEL) according to the timing relationship between the SCL signal and the SDA signal. Specifically, when the chip selection signal is a first logic signal (such as a low level), the first signal recognition circuit 10 is activated. At this time, the first signal recognition circuit 10 can use the falling edge of the SDA as a clock trigger to detect whether the SCL signal is high at the falling edge moment, so as to judge whether the signal on the I2C communication link is a valid START signal; conversely, when the chip selection signal switches to a second logic signal (such as a high level), the second signal recognition circuit 20 is activated and performs the same detection logic. Based on this, the two signal recognition circuits can work alternately through the chip selection signal, so as to ensure that the START signal can be independently recognized under different chip selection states. Further, when the chip selection circuit 30 outputs a first logic signal and the first recognition circuit 10 detects a valid START signal, or when the chip selection circuit 30 outputs a second logic signal and the second recognition circuit 20 detects a valid START signal, the signal output circuit 40 can output a start signal to the slave device. In this embodiment, this time-division multiplexing mechanism enables the circuit to continuously recognize the START signal multiple times, and after each recognition, the state machine can be reset by switching the chip selection circuit, so as to avoid the state machine entering an unknown state due to multiple consecutive START signals.

[0025] In a traditional start signal processing circuit, when START signals continuously appear multiple times in an I2C communication link, the state machine may enter a deadlock state due to timing conflicts or signal omissions, resulting in subsequent communication failures. The start signal processing circuit proposed in this embodiment can solve this problem through a triple mechanism: First, the above circuit uses two identification circuits to work in parallel, which can cover two states of the chip select signal, thus eliminating the detection blind spot; Second, taking the falling edge of SDA as the detection clock and synchronously sampling the SCL level can ensure that the detection process complies with the physical layer specifications of the I2C protocol; Finally, through the forced restart mechanism, the I2C communication can be immediately triggered after detecting a valid START signal, thereby blocking the accumulation of error states. In this embodiment, the two signal identification circuits can work independently under two logic signals of the chip select signal. When a valid START signal is detected, regardless of the current chip select state, the start signal output can be triggered to restart the I2C communication. Since each identification of the START signal is accompanied by a chip select switch and a reset of the state machine, even if the START signal is triggered multiple times continuously, the system can ensure that the state machine starts from a known initial state each time after START by alternately using the two identification channels, thus avoiding communication blockage. Therefore, the above circuit design can achieve continuous identification and communication recovery of any number of START signals through time-division multiplexing and forced reset mechanisms, thereby improving the reliability and robustness of I2C communication.

[0026] In this embodiment, by setting two signal identification circuits and using the polling switching mechanism of the chip select circuit, the problem of communication interruption caused by multiple consecutive START signals (start signals) in traditional I2C communication can be solved. In this application, the two signal identification circuits can work independently under two states where the chip select signal is the first logic signal (such as low level) or the second logic signal (such as high level). When a valid START signal is detected, regardless of the current chip select state, the start signal output can be triggered and the I2C communication can be restarted. Based on this, when multiple START signals are continuously generated in the I2C communication link, the dynamic switching mechanism of the chip select circuit enables the two signal identification circuits to alternately obtain the detection priority. Therefore, each START event can be independently identified and trigger a communication reset. This circuit design method enables the bus state machine to have self-recovery ability. Even if the previous communication is not completed, the new START signal can still force the bus back to the known initial state and restart the I2C communication, thereby ensuring the reliability and robustness of I2C communication.

[0027] In one embodiment, the first signal recognition circuit includes a first signal acquisition module, a first signal synchronization module, and a first signal integration module. Among them, the data input terminal of the first signal acquisition module is connected to the inverted output terminal of the chip select circuit and the SCL signal line, and the clock input terminal is connected to the SDA signal line; the data input terminal of the first signal synchronization module is connected to the output terminal of the first signal acquisition module, and the clock input terminal is connected to the SCL signal line; the first input terminal of the first signal integration module is connected to the output terminal of the first signal acquisition module, the second input terminal is connected to the output terminal of the first signal synchronization module, and the output terminal is connected to the first input terminal of the signal output circuit.

[0028] Specifically, the first signal recognition circuit can accurately recognize the START signal through the first signal acquisition module, the first signal synchronization module, and the first signal integration module. Among them, the first signal acquisition module can perform a logical AND operation on the inverted signal of the chip select signal output by the chip select circuit and the SCL signal, and only allow the SCL signal to pass when the chip select circuit outputs the first logic signal (such as a low-level signal), and use the falling edge of SDA as the trigger condition to capture the falling edge of SDA during the high level of SCL (i.e., the feature of the START signal). Further, the first signal synchronization module can synchronize the acquired signal using the rising edge of SCL to eliminate timing deviation. Finally, the first signal integration module can judge whether the falling edge of SDA meets the condition of "SCL is high level" by comparing the acquired signal and the synchronized signal, and then output a valid first start signal.

[0029] The first signal recognition circuit proposed in this embodiment can improve the reliability of START signal recognition. Even under the interference of continuous START / STOP signals, it can ensure that each detection starts from a known timing starting point through chip select switching and state reset, thereby preventing the I2C state machine from entering an unknown state due to timing errors.

[0030] In one embodiment, as Figure 6As shown in the figure, the first signal acquisition module includes a first D flip-flop D1 triggered by a falling edge. The first D flip-flop D1 can be used to follow the logical AND operation signal of the inverted signal of the chip select signal Sel output by the chip select circuit 30 and the signal output by the SCL signal line when a falling edge appears on the SDA signal line, so as to output a first acquisition signal Start_1; the first signal synchronization module includes a second D flip-flop D2 triggered by a rising edge. The second D flip-flop D2 can be used to follow the first acquisition signal Start_1 when a rising edge appears on the SCL signal line, so as to output a first synchronization signal Start_1_d10; the first signal output module includes a first NOT gate unit N1 and a first AND gate unit A1. The first NOT gate unit N1 can be used to invert the first synchronization signal Start_1_d10, and the first AND gate unit A1 can be used to perform a logical AND operation on the first acquisition signal Start_1 and the inverted signal of the first synchronization signal Start_1_d10, so as to output a first start signal.

[0031] Specifically, the first signal acquisition module can use a D flip-flop D1 triggered by a falling edge. When a falling edge appears on the SDA, D1 can latch the logical AND result of the inverted signal of the chip select signal and the SCL, and generate a first acquisition signal Start_1; the first signal synchronization module can use a D flip-flop D2 triggered by a rising edge to sample Start_1 when a rising edge appears on the SCL and output a synchronization signal Start_1_d10, so as to ensure timing alignment; the first signal integration module can invert Start_1_d10 through a first NOT gate N1 and then perform a logical AND operation with Start_1. In this scenario, only when Start_1 is high (indicating that the SDA falling edge is valid) and Start_1_d10 is low (indicating that the synchronization signal has not been triggered), a first start signal is output. This logical combination verifies the condition that "the SDA falling edge occurs during the SCL high level", so that the output START signal conforms to the legal start signal defined by the I2C protocol.

[0032] During the I2C communication process, there may be situations where multiple START signals appear continuously. All situations can be divided into two cases: continuously even START signals and continuously odd START signals. The following analyzes the above two cases separately with two examples.

[0033] Example 1, as Figure 7As shown, when the MCU connected to the peripheral device is powered on, there are voltage fluctuations on the SCL / SDA lines, generating a START signal. At this time, SCL outputs a high level, SDA is pulled down, the chip select signal Sel is at a low level, START_bit is pulled high, and a start signal is output. After that, SCL is normally pulled high. After the signals are synchronized, START_bit is pulled low, and the signal returns to the initial state. Then, I2C communicates normally. SCL outputs a high level, SDA is pulled down, and a START signal is generated again. At this time, the chip select signal Sel is at a high level, START_bit is pulled high again, and a start signal is output. After that, SCL is pulled high, the signals are synchronized, and START_bit is pulled low, returning to the initial state again. It can be seen that although an error generates a START signal before normal I2C communication, the subsequent I2C communication is still normal.

[0034] Example 2, as Figure 8 As shown, when the MCU connected to the peripheral device is powered on, there are voltage fluctuations on the SCL / SDA lines, generating two START signals. At this time, SCL outputs a high level, SDA is pulled down, generating the first START signal. The chip select signal Sel is at a low level, START_bit is pulled high, and a start signal is output. After that, SCL is pulled up. After the signals are synchronized, START_bit is pulled low, returning to the initial state. Then, SCL outputs a high level, SDA is pulled down, generating the second START signal. The chip select signal Sel is at a high level, START_bit is pulled high again, and a start signal is output. After that, SCL is pulled up. After the signals are synchronized, START_bit is pulled low, returning to the initial state again. Then, I2C starts to communicate normally. SCL outputs a high level, SDA is pulled down, generating the third START signal. At this time, the chip select signal Sel is at a low level, START_bit is pulled high again, and a start signal is output. After that, I2C continues to communicate normally. SCL is pulled up. After the signals are synchronized, START_bit is pulled low, returning to the initial state. It can be seen that although an error generates two START signals before normal I2C communication, the subsequent I2C communication is still normal.

[0035] By analogy, it can be deduced that: after any number of START signals are generated, the subsequent I2C communication can still communicate normally. It should be noted that for the convenience of waveform description, Figure 7 and Figure 8 The waveforms shown are not consistent with Figure 6 the waveforms actually generated by the circuit. In Figure 6 the actually generated waveforms, in the first cycle of the initial power-on stage, the chip select signal Sel should be at a high level. Therefore, Figure 7 and Figure 8The waveform shown is the result after delaying the waveform output by the chip select circuit by one cycle. It can be understood that this waveform description method does not conflict with the actual working principle of the circuit, and the actual working principle remains the same.

[0036] Through precise trigger edge control and logical operations, the above embodiments can achieve hardware-level low-delay detection of the START signal. In addition, through the switching of the chip select signal, the above circuit can support independent detection of the START signal multiple times in a row. After each detection, the state can be reset to avoid state machine blocking, thus solving the problem of communication interruption caused by multiple START / STOP signals in traditional I2C communication.

[0037] In one embodiment, the second signal recognition circuit includes a second signal acquisition module, a second signal synchronization module, and a second signal integration module. Among them, the data input terminal of the second signal acquisition module is connected to the positive output terminal of the chip select circuit and the SCL signal line, and the clock input terminal is connected to the SDA signal line; the data input terminal of the second signal synchronization module is connected to the output terminal of the second signal acquisition module, and the clock input terminal is connected to the SCL signal line; the first input terminal of the second signal integration module is connected to the output terminal of the second signal acquisition module, the second input terminal is connected to the output terminal of the second signal synchronization module, and the output terminal is connected to the second input terminal of the signal output circuit.

[0038] Specifically, the second signal recognition circuit can independently detect the START signal when the chip select circuit outputs the chip select signal through the second signal acquisition module, the second signal synchronization module, and the second signal integration module. Among them, the second signal acquisition module can perform a logical AND operation on the chip select signal and the SCL signal, and only when the chip select signal is valid, use the falling edge of the SDA as the trigger condition to capture the falling edge of the SDA when the SCL is at a high level; the second signal synchronization module can synchronize the signal output by the second signal acquisition module using the rising edge of the SCL; the second signal integration module can verify the timing consistency of the SDA falling edge and the SCL high level by comparing the original acquisition signal and the synchronized signal, and finally output the second start signal.

[0039] By setting the second signal recognition circuit that complements the first signal recognition circuit, the above embodiments can achieve dual-channel alternating detection of the START signal. This detection mechanism combining dual channels with chip select switching enables the circuit to continuously detect the START signal multiple times. That is, when the first channel enters an unknown state due to continuous signals, the chip select circuit can switch to the second channel and restart communication through the detection path of the second channel, thus solving the blocking problem of the traditional I2C state machine caused by multiple START / STOP signals.

[0040] In one embodiment, asFigure 6 As shown in Figure 6 , the second signal acquisition module includes a third D flip-flop D3. The third D flip-flop D3 can be used to follow the logical AND operation signal of the chip select signal Sel output by the chip select circuit 30 and the SCL signal when the falling edge appears on the SDA signal line, so as to output the second acquisition signal Start_2. The second signal synchronization module includes a fourth D flip-flop D4. The fourth D flip-flop D4 can be used to follow the second acquisition signal Start_2 when the rising edge appears on the SCL signal line, so as to output the second synchronization signal Start_2_d10. The second signal output module includes a second NOT gate unit N2 and a second AND gate unit A2. The second NOT gate unit N2 can be used to invert the second synchronization signal Start_2_d10. The second AND gate unit A2 can be used to perform a logical AND operation on the second acquisition signal Start_2 and the inverted signal of the second synchronization signal Start_2_d10, so as to output the second start signal.

[0041] Specifically, the second signal acquisition module can adopt the third D flip-flop D3. When a falling edge appears on SDA, D3 can latch the logical AND result of the chip select signal SEL and the SCL signal, and generate the second acquisition signal Start_2. The second signal synchronization module can be implemented by the fourth D flip-flop D4, sampling the rising edge of Start_2 during the high level of SCL, and outputting the synchronization signal Start_2_d10. The second signal integration module can use the second NOT gate N2 to invert Start_2_d10, and then perform a logical AND operation on Start_2 and the inverted signal of Start_2_d10 through the second AND gate A2. In this scenario, only when Start_2 is high (the falling edge of SDA is valid) and Start_2_d10 is low (the synchronization signal has not been triggered), the circuit can output the second start signal. This logical combination can accurately reproduce the START signal condition of "SDA falls during the high level of SCL" in the I2C protocol. It can be understood that the working principle of the above circuit can be viewed in the examples in the related embodiments of the first signal recognition circuit, which will not be elaborated here.

[0042] In this embodiment, through precise trigger edge control and logical operations, the symmetry and complementarity between the second signal recognition circuit and the first circuit can be ensured. Moreover, through the switching of the chip select signal, the above circuit can form a redundant detection path with the first signal recognition circuit. After each START signal is triggered, the state machine can be reset by switching the channel, thus avoiding the timing accumulation error caused by continuous communication, supporting any number of START signals, and not affecting the reliability of subsequent communication.

[0043] In one embodiment, the chip select circuit includes a third signal acquisition module, a forward output module, and a reverse output module. The data input terminal of the third signal acquisition module is connected to the SCL signal line, and the clock input terminal is connected to the SDA signal line; the first input terminal of the reverse output module is connected to the output terminal of the third signal acquisition module, the second input terminal is connected to the SCL signal line, and the output terminal is connected to the data input terminal of the first signal recognition circuit; the first input terminal of the forward output module is connected to the output terminal of the third signal acquisition module, the second input terminal is connected to the SCL signal line, and the output terminal is connected to the data input terminal of the second signal recognition circuit.

[0044] Specifically, the chip select circuit may be composed of a third signal acquisition module, a forward output module, and a reverse output module. This circuit can control the first signal recognition circuit and the second signal recognition circuit to work alternately by generating a chip select signal. Among them, the third signal acquisition module uses the falling edge of SDA as the clock trigger condition, and follows the SCL signal to generate a chip select signal (Sel), which can reflect the current bus state. The forward output module can perform a logical AND operation on Sel and SCL, and output a forward chip select signal to the second signal recognition circuit; the reverse output module can perform a logical AND operation on the inverted signal of Sel and SCL, and output a reverse chip select signal to the first signal recognition circuit. Through the positive and negative switching of the chip select signal, the above circuit enables the two signal recognition circuits to work independently under different chip select states and realizes time division multiplexing.

[0045] In the above embodiment, by dynamically switching the chip select signal, a mutually exclusive detection window can be provided for the two recognition circuits. This mutual exclusion mechanism can ensure that the two channels do not detect the START signal at the same time, thus avoiding the problem of timing conflicts. At the same time, the logical AND operation of the chip select signal and SCL can ensure that the output takes effect only when SCL is valid (high level), preventing false triggering caused by the low level of SCL. In this embodiment, by alternately enabling the two channels, the START signal can be continuously detected multiple times, and the state machine is reset each time a switch is made, so as to solve the communication blockage problem caused by multiple START / STOP signals in traditional I2C.

[0046] In one embodiment, as Figure 6As shown, the third signal acquisition module includes a fifth flip-flop D5. The fifth flip-flop D5 can be used to follow the signal output on the SCL signal line when a falling edge signal is output on the SDA signal line, so as to output a chip select signal Sel. The reverse output module includes a third NOT gate unit N3 and a third AND gate unit A3. The third NOT gate unit N3 can be used to invert the chip select signal Sel, and input the logical AND operation signal of the inverted signal of the chip select signal Sel and the signal output on the SCL signal line into the data input terminal of the first signal recognition circuit 10. The forward output module includes a fourth AND gate unit A4. The fourth AND gate unit A4 can be used to input the logical AND operation signal of the chip select signal Sel and the signal output on the SCL signal line into the data input terminal of the second signal recognition circuit 20.

[0047] Specifically, the third signal acquisition module can use a fifth flip-flop D5. When a falling edge is output on SDA, D5 can latch the SCL signal and output it as the chip select signal Sel. For example, if the falling edge of SDA triggers D5, the Sel output by D5 will follow the current level of SCL. In addition, the reverse output module can invert Sel through the third NOT gate N3, and then perform a logical AND operation with SCL to generate a reverse chip select signal and input it into the first signal recognition circuit; the forward output module can perform a logical AND operation on Sel and SCL through the fourth AND gate A4, and generate a forward chip select signal and input it into the second signal recognition circuit.

[0048] Through the combination of flip-flops and gate circuits in the above embodiments, it can be ensured that the generation and switching of the chip select signal completely depend on the timing relationship of the bus signals (SCL and SDA). In addition, through hardware-level timing control in this embodiment, low-delay and highly reliable generation of the chip select signal can be achieved, thereby providing stable switching conditions for dual-channel detection, so as to ensure the continuity and anti-interference ability of START signal detection.

[0049] In one embodiment, as Figure 5 and Figure 6 shown, the reverse output module further includes a fourth NOT gate unit N4 and a fifth AND gate unit A5. The fourth NOT gate unit N4 is used to invert the chip select signal Sel, and input the logical AND operation signal of the inverted signal of the chip select signal Sel and the first start signal output by the first signal recognition circuit 10 into the first input terminal of the signal output circuit 40. The forward output module further includes a sixth AND gate unit A6. The sixth AND gate unit A6 is used to input the logical AND operation signal of the chip select signal Sel and the second start signal output by the second signal recognition circuit 20 into the second input terminal of the signal output circuit 40.

[0050] Specifically, in the reverse output module, a fourth NOT gate unit N4 can be added to invert the chip select signal Sel, and after performing a logical AND operation with the first start signal output by the first signal recognition circuit, it is input into the first input terminal of the signal output circuit; in the forward output module, a sixth AND gate unit A6 can be added to perform a logical AND operation on the chip select signal Sel and the second start signal output by the second signal recognition circuit and then input it into the second input terminal of the signal output circuit. In this embodiment, by adding the fourth NOT gate unit N4, the fifth AND gate unit A5, and the sixth AND gate unit A6, the chip select signal can be combined with the detection results of the corresponding recognition circuit, and only when the chip select signal is valid and the START signal is detected, the signal output circuit is triggered to output the start signal, thereby further improving the reliability of I2C communication.

[0051] Through the double logical AND operation in the above embodiment, a double verification mechanism for chip select state matching and START signal detection can be realized. This design ensures that the signal output circuit is triggered only when the chip select state is consistent with the detection result, thereby eliminating incorrect outputs caused by reasons such as chip select switching delay or misjudgment of the recognition circuit.

[0052] In one embodiment, as Figure 5 and Figure 6 shown, the signal output circuit includes an exclusive OR unit X1. Among them, the first input terminal of the exclusive OR unit X1 is connected to the output terminal of the first signal recognition circuit 10, the second input terminal is connected to the output terminal of the second signal recognition circuit 20, and the output terminal is connected to the slave device to be communicated; alternatively, the first input terminal of the exclusive OR unit X1 is connected to the output terminal of the first signal recognition circuit 10 and the reverse output terminal of the chip select circuit 30, the second input terminal is connected to the output terminal of the second signal recognition circuit 20 and the forward output terminal of the chip select circuit 30, and the output terminal is connected to the slave device to be communicated.

[0053] Specifically, the above signal output circuit can be implemented by the exclusive OR unit X1. Among them, the exclusive OR unit X1 can be used to compare the output signals of the first signal recognition circuit and the second signal recognition circuit. When and only when one of the recognition circuits detects a valid START signal (output is high level) while the other does not detect it (output is low level), the exclusive OR unit X1 can output a high level, thereby triggering the start signal to the slave device. For example, if the first signal recognition circuit detects the START signal while the second circuit does not detect the START signal, the exclusive OR result is 1, and vice versa. The above connection method can implement a mutually exclusive valid judgment mechanism through exclusive OR logic, so as to ensure that the start signal is triggered only when a single recognition circuit detects the START signal, thereby avoiding the problem of simultaneous mis-triggering of the dual channels.

[0054] Further, the signal output circuit can also combine the chip select signal and the output of the recognition circuit through the exclusive-OR unit X1, so as to achieve double verification of the chip select state and the detection result. Specifically, the first input terminal of the signal output circuit can perform an AND operation on the output signal of the first signal recognition circuit and the inverted output of the chip select circuit. Only when the chip select signal is in the inverted state and the first signal recognition circuit detects the START signal, a high level is output on this path; the second input terminal of the signal output circuit can perform an AND operation on the output of the second signal recognition circuit and the positive output (SEL) of the chip select circuit. Only when the chip select is in the positive state and the second signal recognition circuit detects the START signal, a high level is output on this path. Subsequently, the exclusive-OR unit X1 can perform an exclusive-OR operation on the logical AND results of the two input terminals and finally output a high-level start signal.

[0055] By binding the chip select signal and the detection result in the above embodiments, potential missed detection or misdetection problems can be solved. The above connection method can ensure that only the detection results of the currently activated recognition circuit can be incorporated into the final judgment. Therefore, even if the two recognition circuits output high levels simultaneously due to timing deviation, only the channel that matches the current chip select state will be adopted, thus avoiding the problem of logical conflict.

[0056] In one embodiment, a communication system is provided, which includes a master device, at least one slave device, and the start signal processing circuit as described in any of the above embodiments. Among them, the start signal processing circuit can be connected between the master device and at least one slave device.

[0057] Specifically, the above communication system can be composed of a master device (such as a microcontroller, etc.), at least one slave device (such as a memory, a temperature sensor, an expander, etc.), and the start signal processing circuit as described in any of the above embodiments. Among them, the start signal processing circuit can be arranged on the SCL and SDA signal lines between the master device and the slave device, and its core modules (chip select circuit, dual signal recognition circuit, signal output circuit) can manage the I2C communication process through a time-division multiplexing mechanism, so as to achieve continuous recognition of any number of START signals and communication recovery, thereby improving the reliability of I2C communication in the communication system.

[0058] By setting the start signal processing circuit with a hardware-level timing management and time-division multiplexing mechanism, the above communication system can accurately control the START signal of the I2C protocol, thereby solving the communication blockage and anti-interference problems in traditional circuits, and making the above communication system applicable to high-reliability scenarios such as industrial control and embedded sensing.

[0059] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0060] The above-described embodiments merely represent several implementation manners of the present application. The description thereof is relatively specific and detailed, but it should not be construed as a limitation to the patent scope of the present application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several variations and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the appended claims.

Claims

1. A start signal processing circuit, applied to a digital circuit using an I2C serial communication protocol, characterized in that: The start signal processing circuit includes a first signal recognition circuit, a second signal recognition circuit, a chip selection circuit and a signal output circuit, wherein: The data input terminal of the first signal recognition circuit is connected to the inverting output terminal of the chip selection circuit and the SCL signal line, the clock input terminal is connected to the SDA signal line, and the output terminal is connected to the first input terminal of the signal output circuit; The data input terminal of the second signal identification circuit is connected to the positive output terminal of the chip selection circuit and the SCL signal line, the clock input terminal is connected to the SDA signal line, and the output terminal is connected to the second input terminal of the signal output circuit; The data input end of the chip select circuit is connected to the SCL signal line, and the clock input end is connected to the SDA signal line; the output end of the signal output circuit is connected to at least one slave device to be communicated; When the chip select circuit outputs a first logic signal and the first signal identification circuit outputs a second logic signal, or when the chip select circuit outputs a second logic signal and the second signal identification circuit outputs a second logic signal, the signal output circuit outputs a start signal to the slave device.

2. The start signal processing circuit according to claim 1, characterized in that: The first signal identification circuit includes a first signal acquisition module, a first signal synchronization module and a first signal integration module; The data input end of the first signal acquisition module is connected to the reverse output end of the chip selection circuit and the SCL signal line, and the clock input end is connected to the SDA signal line; The data input terminal of the first signal synchronization module is connected to the output terminal of the first signal acquisition module, and the clock input terminal is connected to the SCL signal line; The first input end of the first signal integration module is connected to the output end of the first signal acquisition module, the second input end is connected to the output end of the first signal synchronization module, and the output end is connected to the first input end of the signal output circuit.

3. The start signal processing circuit according to claim 2, characterized in that: The first signal acquisition module includes a first D flip-flop, which is used to follow the logic AND operation signal of the inverse signal of the chip select signal output by the chip select circuit and the signal output by the SCL signal line when the SDA signal line outputs a falling edge, so as to output a first acquisition signal; The first signal synchronization module includes a second D flip-flop, which is used to follow the first acquisition signal when the SCL signal line outputs a rising edge to output a first synchronization signal; The first signal output module includes a first NOT gate unit and a first AND gate unit, which are used to invert the first synchronization signal and perform a logic AND operation on the first acquisition signal and an inverse signal of the first synchronization signal to output a first start signal.

4. The start signal processing circuit according to claim 1, characterized in that: The second signal identification circuit includes a second signal acquisition module, a second signal synchronization module and a second signal integration module; The data input terminal of the second signal acquisition module is connected to the positive output terminal of the chip selection circuit and the SCL signal line, and the clock input terminal is connected to the SDA signal line; The data input terminal of the second signal synchronization module is connected to the output terminal of the second signal acquisition module, and the clock input terminal is connected to the SCL signal line; The first input end of the second signal integration module is connected to the output end of the second signal acquisition module, the second input end is connected to the output end of the second signal synchronization module, and the output end is connected to the second input end of the signal output circuit.

5. The start signal processing circuit according to claim 4, characterized in that: The second signal acquisition module includes a third D flip-flop, which is used to follow the logic AND operation signal of the chip selection signal output by the chip selection circuit and the signal output by the SCL signal line when the SDA signal line outputs a falling edge, so as to output a second acquisition signal; The second signal synchronization module includes a fourth D flip-flop, which is used to follow the second acquisition signal when the SCL signal line outputs a rising edge to output a second synchronization signal; The second signal output module includes a second NOT gate unit and a second AND gate unit, which are used to invert the second synchronization signal and perform a logic AND operation on the second acquisition signal and an inverted signal of the second synchronization signal to output a second start signal.

6. The start signal processing circuit according to claim 1, characterized in that: The chip selection circuit includes a third signal acquisition module, a forward output module and a reverse output module; The data input terminal of the third signal acquisition module is connected to the SCL signal line, and the clock input terminal is connected to the SDA signal line; The first input end of the reverse output module is connected to the output end of the third signal acquisition module, the second input end is connected to the SCL signal line, and the output end is connected to the data input end of the first signal recognition circuit; The first input end of the forward output module is connected to the output end of the third signal acquisition module, the second input end is connected to the SCL signal line, and the output end is connected to the data input end of the second signal recognition circuit.

7. The start signal processing circuit according to claim 6, characterized in that: The third signal acquisition module includes a fifth trigger, which is used to follow the signal output by the SCL signal line when the SDA signal line outputs a falling edge, so as to output a chip selection signal; The reverse output module includes a third NOT gate unit and a third AND gate unit, which are used to invert the chip select signal, and input the logic AND operation signal of the reverse signal of the chip select signal and the signal output by the SCL signal line into the data input terminal of the first signal recognition circuit; The forward output module includes a fourth AND gate unit, which is used to input a logic AND operation signal of the chip selection signal and a signal output by the SCL signal line into a data input terminal of the second signal recognition circuit.

8. The start signal processing circuit according to claim 7, characterized in that: The reverse output module further includes a fourth NOT gate unit and a fifth AND gate unit, which are used to invert the chip select signal, and input the logic AND operation signal of the reverse signal of the chip select signal and the first start signal output by the first signal recognition circuit into the first input terminal of the signal output circuit; The forward output module further includes a sixth AND gate unit, which is used to input a logic AND operation signal of the chip selection signal and a second start signal output by the second signal recognition circuit into the second input terminal of the signal output circuit.

9. The start signal processing circuit according to claim 1, characterized in that: The signal output circuit includes an XOR unit, wherein: The first input terminal of the XOR unit is connected to the output terminal of the first signal identification circuit, the second input terminal is connected to the output terminal of the second signal identification circuit, and the output terminal is connected to the slave device; or, The first input end of the XOR unit is connected to the output end of the first signal identification circuit and the reverse output end of the chip select circuit, the second input end is connected to the output end of the second signal identification circuit and the forward output end of the chip select circuit, and the output end is connected to the slave device.

10. A communication system, characterized in that: The communication system comprises a master device, at least one slave device, and a start signal processing circuit according to any one of claims 1 to 9, wherein the start signal processing circuit is connected between the master device and the at least one slave device.

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