High-speed optical fiber interface data transmission system based on FPGA

Abstract

The invention discloses a high-speed optical fiber interface data transmission system based on an FPGA (Field Programmable Gate Array), belongs to the technical field of integrated circuits, and aims to solve the technical problem of how to improve the data transmission efficiency, reduce CPU (Central Processing Unit) intervention and reduce the overall load by utilizing the FPGA and an optical fiber transmission technology. According to the technical scheme, the system takes a QSFP28 interface optical fiber interface and a PCIe 3.0 bus data interface as high data transmission interfaces, and supports a DDR4SRAM (Double Data Rate 4Static Random Access Memory); the system comprises an optical port communication module, a data caching module and a PCIe communication module, wherein the optical port communication module is used for converting photoelectric signals and reducing loss and interference in a signal transmission process by adopting encoding and decoding modes; the data caching module is used for caching data transmitted between the optical port communication module and the PCIe bus; the PCIe communication module is used for realizing a PCIe communication protocol, reading data from the DDR4 memory and transmitting the read data to the PCIe XDMA IP core through an AXI-Stream bus, and the PCIe XDMA IP core is used for processing DMA transmission of streaming data and analyzing a PCIe bus protocol.

Description

Technical Field

[0001] The invention relates to the technical field of integrated circuits, in particular to a high-speed optical fiber interface data transmission system based on FPGA. Background Art

[0002] In the field of electronic design, real-time acquisition, processing and transmission of multi-channel broadband signals is a key task. Traditional signal acquisition and transmission systems rely on application-specific integrated circuits (ASICs) to control peripheral devices such as analog-to-digital converters (A / D converters). However, these ASICs are unable to meet the modern needs of high-speed broadband signal acquisition and processing due to their low clock frequency, insufficient flexibility, poor real-time performance, slow transmission speed and poor versatility.

[0003] In contrast, the Field Programmable Gate Array (FPGA) has the characteristics of high clock frequency, fast speed, flexible control, etc. Through its powerful parallel processing capability, it can receive and process high-bandwidth data in real time, making it an ideal choice for high-speed digital signal processing. In addition, designers can customize IP cores with different functions according to their actual needs, verify the correctness through simulation, and write the local logic control by themselves, which has great flexibility, saves costs, greatly reduces the area of ​​the board, and is more convenient to use.

[0004] In the field of high-speed data transmission, optical fiber transmission exhibits significant advantages over electrical transmission, including high bandwidth, large communication capacity, low transmission loss, strong anti-electromagnetic interference capability, excellent anti-radiation performance, good confidentiality and light weight. Therefore, it is widely used as the main transmission medium in high-speed data transmission systems.

[0005] Therefore, how to use FPGA and fiber optic transmission technology to improve data transmission efficiency, reduce CPU intervention, and reduce the overall load is a technical problem that needs to be solved urgently. Summary of the invention

[0006] The technical task of the present invention is to provide a high-speed fiber optic interface data transmission system based on FPGA to solve the problem of how to use FPGA and fiber optic transmission technology to improve data transmission efficiency, reduce CPU intervention, and reduce overall load.

[0007] The technical task of the present invention is achieved in the following way: a high-speed optical fiber interface data transmission system based on FPGA, which uses QSFP28 interface optical fiber interface and PCIe 3.0 bus data interface as high-number data transmission interface and supports DDR4 SRAM memory; the system includes an optical port communication module, a data cache module and a PCIe communication module:

[0008] Among them, the optical port communication module is used to convert optical and electrical signals, and adopts encoding and decoding methods to reduce signal loss and interference during signal transmission, and improve the reliability of data transmission;

[0009] The data cache module is used to cache the data transmitted between the optical port communication module and the PCIe bus, and solve the problems of large data volume and mismatched transmission rates between the optical fiber interface and PCIe transmission;

[0010] The PCIe communication module is used to implement the PCIe communication protocol, read data from the DDR4 memory, and transmit the read data to the PCIe XDMA IP core through the AXI-Stream bus. The PCIe XDMA IP core is used to process the DMA (Direct Memory Access) transmission of streaming data and parse the PCIe bus protocol to ensure that the data can be transmitted efficiently and accurately.

[0011] Preferably, the optical port communication module includes an optical port encoding and scrambling sub-module, an optical port decoding and descrambling sub-module, an optical port word alignment sub-module, and a GTY top-level sub-module;

[0012] Among them, the optical port encoding and scrambling sub-module is used to perform 64B / 66B encoding and scrambling processing on the data;

[0013] The optical port decoding and descrambling sub-module is used to perform 64B / 66B decoding and descrambling processing on the received data;

[0014] The optical port word alignment sub-module is used to perform word alignment processing on the data to ensure data synchronization in multi-channel transmission, and adjust the data stream in each channel by identifying the synchronization header and channel binding block, so that the data can be received simultaneously on all channels;

[0015] The GTY top-level sub-module is used to connect the user data interface with the GTY physical layer interface to realize data sending and receiving;

[0016] More preferably, the 64B / 66B encoding and scrambling processing of the optical port encoding and scrambling sub-module is specifically as follows:

[0017] 64B / 66B encoding is to convert 64-bit data into 66 bits, adding 2-bit synchronization headers to indicate the data type and achieve data alignment;

[0018] 64B / 66B scrambling processing is to scramble the data through a self-synchronizing scrambler to ensure the zero-one balance of the data, avoid DC offset and difficult clock recovery.

[0019] More preferably, the 64B / 66B decoding and descrambling processing of the optical port decoding and descrambling sub-module is specifically as follows:

[0020] 64B / 66B decoding is to restore the 66-bit block code to 64-bit data and remove the synchronization header;

[0021] 64B / 66B descrambling is to restore the original data through a self-synchronizing descrambler.

[0022] More preferably, the GTY top-level sub-module is based on the GTY high-speed transceiver (the configuration and use of the GTY high-speed transceiver are usually through the IP provided by Xilinx. In this embodiment, the IP core is used for top-level encapsulation, so it is not appropriate to call it the GTY IP module and it is changed to the GTY top-level module). The Aurora64B / 68B protocol is used as the serial protocol of the GTY high-speed transceiver. The Aurora protocol is a high-bandwidth, high-transmission-rate, full-duplex and single-channel mode-supporting, scalable lightweight link protocol that provides a transparent interface for the physical layer and enables easier use of the GTY high-speed transceiver on this basis; the implementation of 64B / 66B encoding relies on scrambling and descrambling; specifically as follows:

[0023] Encode 64B data or control data into 66B data. The encoding process is to add 2-bit data in front of the 64B data or control information;

[0024] Scramble the original data at the sending end;

[0025] Send it out through the GTY high-speed transceiver;

[0026] At the receiving end, descramble the data received by the GTY high-speed transceiver at the PHY layer to restore the original data, thereby reducing the inter-symbol interference and jitter of the serial data stream and improving the reliability of communication.

[0027] Preferably, the data cache module uses DDR4 SDRAM to cache the received high-speed data, which can improve performance and ensure the reliability of data transmission; and receives FIFO (First In, First Out) and transmit FIFO to solve the problems of different data interface types, different data bit widths, and different clock domains between the optical port communication module and the PCIe communication module, ensuring that there is no packet loss and no error in data reception and transmission.

[0028] Preferably, the PCIe XDMA IP core includes a read module and a write module;

[0029] Among them, the read module is used to write the streaming data received through the H2C (Host to Card) channel into the FIFO for subsequent processing;

[0030] The writing module is used to send the data read by the DDR4 read control module to the PCIe XDMA IP core through the C2H (Card to Host) channel, so as to realize the data transmission from the memory to the PC side. Among them, the DDR4 read control module is used to receive the read request from the memory controller and generate corresponding control signals according to the read request to read data from the DDR4 memory.

[0031] Preferably, the working process of the system is specifically as follows:

[0032] S1. The PC-side host computer sends data to the PCIe XDMA IP core through the PCIe bus through the XDMA driver, and sends the streaming data on the H2C channel of the PCIe XDMA IP core to the user-side AXI-Stream bus interface through the read module of the XDMA IP core, and writes the data into the FIFO.

[0033] S2. The read module of the PCIe XDMA IP core writes the data into the FIFO. The optical communication module reads the data from the FIFO and performs 64B / 66B encoding through the optical port encoding and scrambling sub-module, and performs scrambling processing on the encoded data through the scrambler. The scrambler is x^58 + x^39 + 1.

[0034] S3. The data after scrambling processing passes through the GTY top-level sub-module, is converted from an optical signal to an electrical signal, and enters the data loopback through the fiber optic interface QSFP28. The data after loopback passes through the optical port word alignment sub-module and the optical port descrambling and decoding sub-module to align the data word and descramble and process it into the original data.

[0035] S4. Send the descrambled data to the data cache module, write the data into the FIFO according to the DDR4 write control logic, and control the data cache into the off-chip DDR4 chip through the MIG IP core.

[0036] S5. After the data writing is completed, according to the DDR4 read and write control logic, the data is read through the FIFO and sent to the write module of the PCIe XDMA IP core. The data read from the DDR4 read control module is sent to the PCIe XDMA IP core through the C2H channel, and finally sent to the host computer to complete the data transmission process.

[0037] The high-speed fiber optic interface data transmission system based on FPGA of the present invention has the following advantages:

[0038] (1) In the Linux system, the high-speed communication between the FPGA and the host is usually achieved through the PCI Express (PCIe) interface; as a high-speed serial bus standard, PCIe performs excellently in scenarios dealing with large amounts of data due to its excellent compatibility, high reliability, and outstanding transmission performance; the PCIe bus adopts a differential serial transmission method, realizing a point-to-point interconnection technology, significantly enhancing the hot-plugging ability and data transmission efficiency; in addition, by using a PCIe device driver that supports the direct memory access (DMA) function, the present invention greatly improves the data transmission efficiency, reduces the intervention of the CPU, thereby reducing the overall load of the system, achieving a high-speed and reliable data transmission, and enabling high-speed data transmission between the FPGA and the PC end through the optical fiber interface and the PCIe bus;

[0039] (2) The optical fiber communication interface of the present invention has the advantages of high bandwidth, low bit error rate, simple connection method, etc., and is particularly suitable for modern digital signal processing systems; as the control core, the FPGA can realize high-speed optical fiber communication data transmission. By utilizing the high clock frequency and parallel processing ability of the FPGA, the speed of processing and transmitting high-bandwidth data is improved, solving the deficiencies of traditional ASICs in terms of clock frequency, flexibility, real-time performance, and transmission speed. The present invention adopts 64B / 66B coding and scrambling technologies, reducing signal loss and interference during signal transmission and improving the reliability of data transmission; in high-speed data transmission, since ordinary RAM cannot meet the large amount of data and high transmission rate, and DDR4 has the advantages of large capacity, high bandwidth, and low price, the present invention uses DDR4 SDRAM to cache the received high-speed data, which can also improve performance and ensure the reliability of data transmission; in addition, by using a PCIe device driver that supports the DMA function, the CPU intervention is reduced, the system load is lowered, and the data transmission efficiency is improved;

[0040] (3) The electromagnetic interference resistance and radiation resistance performance of optical fiber communication enable the product to work stably in more harsh environments, broadening the application scenarios. The present invention provides higher flexibility, faster time to market, lower cost, and stronger data processing ability through the design of high-speed optical fiber interface data transmission based on the FPGA; in addition, by adopting the latest FPGA technology and high-speed optical fiber communication technology, the reliability of data transmission is improved, data loss and interference are reduced, the stability and reliability of the product are enhanced, the market competitiveness can be improved, and more customers and projects can be attracted. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] The present invention will be further described below with reference to the drawings.

[0042] APPENDIX Figure 1 It is a schematic structural diagram of a high-speed optical fiber interface data transmission system based on the FPGA. Detailed implementation manners

[0043] The high-speed fiber optic interface data transmission system based on FPGA of the present invention will be described in detail below with reference to the accompanying drawings of the specification and specific embodiments.

[0044] Embodiment:

[0045] As shown in the Figure 1 accompanying drawings, this embodiment provides a high-speed fiber optic interface data transmission system based on FPGA. This system uses a QSFP28 interface fiber optic interface and a PCIe 3.0 bus data interface as high-speed data transmission interfaces, and supports a DDR4 SRAM memory; this system includes an optical port communication module, a data cache module, and a PCIe communication module:

[0046] Among them, the optical port communication module is used to convert optical and electrical signals, and uses encoding and decoding methods to reduce the loss and interference during signal transmission, and improve the reliability of data transmission;

[0047] The data cache module is used to cache the data transmitted between the optical port communication module and the PCIe bus, and solve the problems of large data volume and mismatched transmission rates between the fiber optic interface and PCIe;

[0048] The PCIe communication module is used to implement the PCIe communication protocol, read data from the DDR4 memory, and transmit the read data to the PCIe XDMA IP core through the AXI-Stream bus. The PCIe XDMA IP core is used to process the DMA (direct memory access) transmission of streaming data and parse the PCIe bus protocol to ensure that the data can be transmitted efficiently and accurately.

[0049] The optical port communication module in this embodiment includes an optical port encoding and scrambling sub-module, an optical port decoding and descrambling sub-module, an optical port word alignment sub-module, and a GTY top-level sub-module;

[0050] Among them, the optical port encoding and scrambling sub-module is used to perform 64B / 66B encoding and scrambling processing on the data;

[0051] The optical port decoding and descrambling sub-module is used to perform 64B / 66B decoding and descrambling processing on the received data;

[0052] The optical port word alignment sub-module is used to perform word alignment processing on the data, ensure the synchronization of the data in multi-channel transmission, and adjust the data stream in each channel by identifying the synchronization header and channel binding block, so that the data can be received simultaneously on all channels;

[0053] The GTY top-level sub-module is used to connect the user data interface with the GTY physical layer interface to realize the sending and receiving of data;

[0054] The 64B / 66B encoding and scrambling processing of the optical port encoding and scrambling sub-module in this embodiment are as follows:

[0055] 64B / 66B encoding converts 64-bit data into 66 bits, adding 2-bit synchronization headers to indicate the data type and achieve data alignment;

[0056] 64B / 66B scrambling processing scrambles the data through a self-synchronizing scrambler to ensure the zero-one balance of the data, avoiding DC offset and difficulties in clock recovery.

[0057] The 64B / 66B decoding and descrambling processing of the optical port decoding and descrambling sub-module in this embodiment are as follows:

[0058] 64B / 66B decoding restores 66-bit block codes to 64-bit data, removing the synchronization headers;

[0059] 64B / 66B descrambling restores the original data through a self-synchronizing descrambler.

[0060] The GTY top-level sub-module in this embodiment is based on the GTY high-speed transceiver (the configuration and use of the GTY high-speed transceiver are usually through the IP provided by Xilinx. In this embodiment, the IP core is used for top-level encapsulation, so it is not appropriate to call it the GTY IP module and is changed to the GTY top-level module). It uses the Aurora64B / 68B protocol as the serial protocol of the GTY high-speed transceiver. The Aurora protocol is a high-bandwidth, high-transmission-rate, full-duplex and single-channel mode supported, scalable lightweight link protocol that provides a transparent interface for the physical layer and enables easier use of the GTY high-speed transceiver on this basis; the implementation of 64B / 66B encoding relies on scrambling and descrambling; specifically as follows:

[0061] ① Encode 64B data or control data into 66B data. The encoding process adds 2-bit data in front of the 64B data or control information;

[0062] ② Scramble the original data at the sending end;

[0063] ③ Send it out through the GTY high-speed transceiver;

[0064] ④ At the receiving end, descramble the data received by the GTY high-speed transceiver at the PHY layer to restore the original data, thereby reducing the inter-symbol interference and jitter of the serial data stream and improving the reliability of communication.

[0065] In a high-speed data transmission system, since ordinary RAM cannot meet the requirements of a large amount of data and high transmission rate, while DDR4 has the advantages of large capacity, high bandwidth, and low price. In addition, considering the waiting time of the PCIe transmitter during the DMA transmission process due to other related operations, and the waiting time when the computer PCIe bus is occupied by other devices, the data cache module in this embodiment uses DDR4 SDRAM to cache the received high-speed data, which can improve performance and ensure the reliability of data transmission; and receives FIFO (First In, First Out) and transmits FIFO to solve the problems of different data interface types, different data bit widths, and different clock domains between the optical port communication module and the PCIe communication module, ensuring no packet loss and no error code in data reception and transmission.

[0066] The PCIe XDMA IP core in this embodiment includes a read module and a write module;

[0067] Among them, the read module is used to write the streaming data received through the H2C (Host to Card) channel into the FIFO for subsequent processing;

[0068] The write module is used to send the data read by the DDR4 read control module to the PCIe XDMA IP core through the C2H (Card to Host) channel, thereby realizing the transmission of data from the memory to the PC side; among them, the DDR4 read control module is used to receive the read request from the memory controller and generate corresponding control signals according to the read request to read data from the DDR4 memory.

[0069] The working process of this system is as follows:

[0070] S1. The PC-side host computer sends data to the PCIe XDMA IP core through the PCIe bus through the XDMA driver, and the read module of the XDMA IP core sends the streaming data on the H2C channel of the PCIe XDMA IP core to the user-side AXI-Stream bus interface and writes the data into the FIFO;

[0071] S2. The read module of the PCIe XDMA IP core writes the data into the FIFO, the optical port communication module reads the data from the FIFO and performs 64B / 66B encoding through the optical port encoding scrambler module, and the scrambled data is scrambled by the scrambler, and the scrambler is x^58 + x^39 + 1;

[0072] S3. The data after scrambling is passed through the GTY top-level sub-module, converted from optical signals to electrical signals, and enters the fiber optic interface QSFP28 for data loopback. The looped-back data is word-aligned and descrambled into the original data through the optical port word alignment sub-module and the optical port descrambling and decoding sub-module;

[0073] S4. The descrambled data is sent to the data cache module, written into the FIFO according to the DDR4 write control logic, and the data is cached into the off-chip DDR4 chip through the MIG IP core;

[0074] S5. After the data writing is completed, according to the DDR4 read-write control logic, the data is read through the FIFO and sent to the write module of the PCIe XDMA IP core. The data read from the DDR4 read control module is sent to the PCIe XDMA IP core through the C2H channel and finally sent to the host computer to complete the data transmission process.

[0075] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some or all of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A high-speed optical fiber interface data transmission system based on FPGA, characterized in that: The system uses QSFP28 optical fiber interface and PCIe 3.0 bus data interface as high-data data transmission interface and supports DDR4 SRAM memory; the system includes optical port communication module, data cache module and PCIe communication module: Among them, the optical port communication module is used to convert optical and electrical signals, and adopts encoding and decoding methods to reduce the loss and interference during signal transmission; The data cache module is used to cache the data transmitted between the optical port communication module and the PCIe bus; The PCIe communication module is used to implement the PCIe communication protocol, read data from the DDR4 memory, and transfer the read data to the PCIe XDMA IP core through the AXI-Stream bus. The PCIe XDMA IP core is used to process the DMA transmission of streaming data and parse the PCIe bus protocol.

2. The FPGA-based high-speed optical fiber interface data transmission system according to claim 1, characterized in that: The optical port communication module includes an optical port coding and scrambling submodule, an optical port decoding and descrambling submodule, an optical port word alignment submodule and a GTY top-level submodule; Among them, the optical port encoding and scrambling submodule is used to perform 64B / 66B encoding and scrambling processing on the data; The optical port decoding and descrambling submodule is used to perform 64B / 66B decoding and descrambling processing on the received data; The optical port word alignment submodule is used to perform word alignment processing on the data to ensure the synchronization of data in multi-channel transmission, and adjust the data flow in each channel by identifying the synchronization header and channel binding block so that the data can be received simultaneously on all channels; The GTY top-level submodule is used to connect the user data interface with the GTY physical layer interface to realize data transmission and reception.

3. The FPGA-based high-speed optical fiber interface data transmission system according to claim 2, characterized in that: The 64B / 66B encoding and scrambling processing of the optical port encoding and scrambling submodule is as follows: 64B / 66B encoding converts 64-bit data into 66-bit data and adds a 2-bit synchronization header to indicate the data type and achieve data alignment; The 64B / 66B scrambling process scrambles the data through a self-synchronizing scrambler to ensure zero-one balance of the data.

4. The FPGA-based high-speed optical fiber interface data transmission system according to claim 2, characterized in that: The 64B / 66B decoding and descrambling processing of the optical port decoding and descrambling submodule is as follows: 64B / 66B decoding is to restore the 66-bit block code to 64-bit data and remove the synchronization header; 64B / 66B descrambling is done by a self-synchronizing descrambler to restore the original data.

5. The FPGA-based high-speed optical fiber interface data transmission system according to claim 2, characterized in that: The GTY top-level submodule is based on the GTY high-speed transceiver, and adopts the Aurora64B / 68B protocol as the serial protocol of the GTY high-speed transceiver. The implementation of 64B / 66B encoding relies on scrambling and descrambling; the details are as follows: Encode 64B of data or control data into 66B of data. The encoding process is to add 2 bits of data in front of the 64B of data or control information. Scramble the original data at the sending end; Send it out through GTY high-speed transceiver; At the receiving end, the data received by the GTY high-speed transceiver is descrambled at the PHY layer to restore the original data, thereby reducing the inter-symbol interference and jitter of the serial data stream.

6. The FPGA-based high-speed optical fiber interface data transmission system according to claim 1, characterized in that: The data cache module uses DDR4 SDRAM to cache the received high-speed data; and the receiving FIFO and the sending FIFO are used to solve the problems of different data interface types, different data bit widths and different clock domains between the optical port communication module and the PCIe communication module.

7. The FPGA-based high-speed optical fiber interface data transmission system according to claim 1, characterized in that: The PCIeXDMA IP core includes a read module and a write module; Among them, the read module is used to write the streaming data received through the H2C channel into the FIFO; The write module is used to send the data read by the DDR4 read control module to the PCIe XDMA IP core through the C2H channel, thereby realizing the transmission of data from the memory to the PC end; wherein, the DDR4 read control module is used to receive a read request from the memory controller and generate a corresponding control signal according to the read request to read data from the DDR4 memory.

8. The FPGA-based high-speed optical fiber interface data transmission system according to claim 1, characterized in that: The working process of the system is as follows: S1. The PC host computer sends data to the PCIe XDMA IP core through the PCIe bus through the XDMA driver, and sends the streaming data on the H2C channel of the PCIe XDMA IP core to the AXI-Stream bus interface on the user side through the read module of the XDMA IP core, and writes the data into the FIFO; S2, PCIe XDMA IP core read module writes data into FIFO, optical port communication module reads data from FIFO and performs 64B / 66B encoding through optical port encoding and scrambling submodule, and scrambles the encoded data through scrambler, which is x 58 +x 39 +1; S3, the scrambled data is converted from optical signals to electrical signals through the GTY top-level submodule, and enters the optical fiber interface QSFP28 for data loopback. The looped data is word aligned and descrambled into original data through the optical port word alignment submodule and the optical port descrambling decoding submodule; S4, sending the descrambled data to the data cache module, writing the data into the FIFO according to the DDR4 write control logic, and caching the data into the off-chip DDR4 chip through the MIG IP core control; S5. After the data is written, according to the DDR4 read and write control logic, the data is read through the FIFO and sent to the write module of the PCIeXDMA IP core. The data read from the DDR4 read control module is sent to the PCIe XDMA IP core through the C2H channel, and finally sent to the host computer to complete the data transmission process.

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