Data storage method, electronic device, storage medium and product

Abstract

The present application discloses a data storage method, an electronic device, a storage medium and a product, which relate to the technical field of data storage. The method includes: in response to a storage request for a physical address, obtaining a target logical address and parameter information of a pre-created B+ tree structure, and determining a target leaf node for storing the physical address mapped to the target logical address in the B+ tree structure according to the target logical address and the parameter information. Traverse the pre-created B+ tree structure according to the target logical address to determine whether the target leaf node exists. If it exists, store the physical address mapped to the target logical address on the target leaf node. The present application determines the corresponding node only when there is an actual data storage request, without occupying too much storage space in advance, and only stores the physical address mapped to the logical address after determining the target leaf node, reducing the storage space occupied by the logical address and improving the utilization rate of the storage space of the leaf node.

Description

Technical Field

[0001] This application relates to the technical field of data storage, and in particular, to a data storage method, an electronic device, a storage medium, and a product. Background Art

[0002] In the field of data storage, efficiently and accurately mapping logical addresses to physical addresses is a key task. Due to its efficient data organization method and excellent performance, the B+ tree structure has been widely used in the storage field.

[0003] In the related art, corresponding leaf nodes are pre-allocated for each logical address in the B+ tree structure, and both the logical address and the physical address mapped to the logical address are stored in the corresponding leaf nodes at the same time, resulting in insufficient utilization of the leaf nodes. Summary of the Invention

[0004] This application provides a data storage method, an electronic device, a storage medium, and a product, so as to at least solve the problem of insufficient utilization of leaf nodes in the B+ tree structure in the related art.

[0005] This application provides a data storage method, including:

[0006] In response to a physical address storage request, obtain the target logical address requested to be used in the physical address storage request;

[0007] Obtain the parameter information of the pre-created B+ tree structure, where the parameter information includes the order and height of the B+ tree structure;

[0008] According to the target logical address, the order, and the height, determine the target leaf node in the B+ tree structure that stores the physical address mapped to the target logical address;

[0009] Traverse the pre-created B+ tree structure according to the target logical address to determine whether the target leaf node exists;

[0010] If it exists, store the physical address mapped to the target logical address on the target leaf node.

[0011] This application also provides an electronic device, including: a memory for storing a computer program; a processor for implementing the steps of any of the above data storage methods when executing the computer program.

[0012] This application also provides a computer-readable storage medium, in which a computer program is stored, and when the computer program is executed by a processor, the steps of any of the above data storage methods are implemented.

[0013] The present application also provides a computer program product, including a computer program, which when executed by a processor implements the steps of any of the above data storage methods.

[0014] Through the present application, in response to a storage request for a physical address, a target logical address and parameter information of a pre-created B+ tree structure are obtained, and a target leaf node for storing the physical address mapped to the target logical address in the B+ tree structure is determined according to the target logical address and the parameter information. The pre-created B+ tree structure is traversed according to the target logical address to determine whether the target leaf node exists. If it exists, the physical address mapped to the target logical address is stored on the target leaf node. In the method of the present application, the leaf node corresponding to the logical address in the B+ tree structure is not preset in advance, but the target leaf node is determined by the target logical address and the parameter information, so that the corresponding node is determined only when there is an actual data storage request, thus not occupying too much storage space in advance. And after the target leaf node is determined, only the physical address mapped to the logical address is stored, rather than storing both the physical address and the logical address in the related art, thereby reducing the storage space occupied by the logical address in the leaf node, and further improving the utilization rate of the storage space of the leaf node. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application, and those of ordinary skill in the art can obtain other drawings based on these drawings without creative efforts.

[0016] Figure 1 It is a hardware architecture diagram for implementing a data storage method provided by an embodiment of the present application;

[0017] Figure 2 It is a schematic flowchart of a data storage method provided by an embodiment of the present application;

[0018] Figure 3 It is a schematic flowchart of a method for creating a B+ tree structure provided by an embodiment of the present application;

[0019] Figure 4 It is a schematic flowchart of a method for determining a target leaf node provided by an embodiment of the present application;

[0020] Figure 5 It is a schematic flowchart of a method for performing a merging process on leaf nodes provided by an embodiment of the present application;

[0021] Figure 6 It is a schematic diagram of a leaf node merging process provided by an embodiment of the present application;

[0022] Figure 7 The structural schematic diagram of a data storage device provided by an embodiment of the present application;

[0023] Figure 8 The structural schematic diagram of an electronic device provided by an embodiment of the present application. Detailed implementation manners

[0024] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the protection scope of the present application.

[0025] It should be noted that in the description of the present application, the terms "include", "comprise" or any other variant thereof are intended to cover a non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. The terms "first", "second", etc. in the present application are used to distinguish similar objects, rather than to describe a specific order or sequence.

[0026] First, the technical terms involved in the present application are explained:

[0027] The logical address refers to the virtual address from the perspective of the electronic device and is used to identify the location of data in the storage system;

[0028] The physical address refers to the actual location of data on a storage medium such as a NAND (Not AND) flash memory. When the electronic device requests a logical address, the storage system allocates a physical address for the logical address and records the mapping between the logical address and the physical address in the B+ tree;

[0029] The B+ tree is a balanced multi-way search tree widely used in databases and file systems for efficiently managing a large amount of ordered data. It is a variant of the B tree and has higher query efficiency and characteristics more suitable for disk storage.

[0030] In a storage system, taking an all-flash storage system as an example, it has been widely used in modern data centers and storage fields due to its high-speed read and write performance, low latency, and high reliability. All-flash storage uses NAND flash memory as the storage medium. Its inherent write-erase limitation requires the storage system to adopt wear leveling technology to extend the service life of the flash memory module. To achieve wear leveling, all-flash storage uses the append write method, writing data into free blocks instead of directly overwriting the original data. This writing method causes the mapping relationship between the logical block address (LBA) and the physical block address (PBA) to change continuously. As a commonly used self-balancing tree data structure, the B+ tree can maintain the order of data and support efficient insertion, deletion, and search operations. Therefore, it can be applied in an all-flash storage system, enabling the mapping table based on the B+ tree to dynamically manage the mapping between the logical address and the physical address.

[0031] In the related art, during the initialization phase, the storage system will pre-allocate corresponding tree node resources for the entire logical address in the constructed B+ tree structure, and store or insert the corresponding physical address and logical address on the corresponding target leaf node.

[0032] However, pre-allocating tree node resources in the above manner may cause some nodes to be idle for a long time, and storing both the logical address and the physical address on the leaf node makes the utilization of the node storage space insufficient, resulting in space waste.

[0033] Therefore, in view of the above problems in the related art, it is found in the research process that if the corresponding nodes are determined only when there is an actual data storage request instead of pre-allocating tree node resources, excessive storage space will not be occupied in advance, and only storing the physical address in the leaf node instead of both the physical address and the logical address can also reduce the storage space occupied by the logical address in the leaf node, thereby improving the utilization of the storage space in the B+ tree structure. Specifically, in response to a storage request for a physical address, obtain the target logical address and the parameter information of the pre-created B+ tree structure. The parameter information includes, but is not limited to, the order and height of the B+ tree structure, etc., and determine the target leaf node for storing the physical address mapped to the target logical address in the B+ tree structure according to the target logical address and the parameter information. Traverse the pre-created B+ tree structure according to the target logical address to determine whether the target leaf node exists. If it exists, store the physical address mapped to the target logical address on the target leaf node. Therefore, this application proposes a data storage method, an electronic device, a storage medium, and a product.

[0034] To enable those skilled in the art of this technical field to better understand the solution of this application, the following further detailed description of this application will be given in conjunction with the accompanying drawings and specific embodiments.

[0035] In combination with the specific application environment architecture or specific hardware architecture on which the execution of the data storage method depends, the specific application environment architecture or specific hardware architecture will be described herein. Refer to Figure 1 , Figure 1 FIG. is a hardware architecture diagram for implementing the data storage method provided by an embodiment of this application, which includes a client 01, a storage controller 02, a storage system 03, and a NADA flash storage array 04. The storage system 03 may further include a logical address resolution module 031, a B+ tree parameter storage module 032, a calculation module 033, a search module 034, and a physical address storage module 035.

[0036] Among them, the client 01 is used to send a physical address storage request to the storage controller 02. The storage controller 02 determines the target logical address according to this request and sends the target logical address to the logical address resolution module 031 in the storage system 03. The logical address resolution module 031 sends the target logical address to the calculation module 033. The storage controller 02 also obtains the parameter information of the B+ tree structure and sends the parameter information to the B+ tree parameter storage module 032 in the storage system 03. The B+ tree parameter storage module 032 sends the parameter information to the calculation module 033, and the calculation module 033 determines the target leaf node according to the target logical address and the parameter information.

[0037] The storage controller 02 can also control the search module 034 in the storage system 03 to traverse in the pre-created B+ tree structure to determine whether the target leaf node exists. If it exists, the physical address mapped to the target logical address is stored in the physical address storage module 035. The physical address storage module 035 sends the stored physical address to the NADA flash storage array 04 to store the actual data corresponding to the physical address in the NADA flash storage array 04.

[0038] It can be understood that the various modules included in the above architecture diagram are only for illustrative purposes and do not limit this application. They can be determined according to actual application situations, etc.

[0039] Please refer to Figure 2 , Figure 2A flowchart of a data storage method provided by an embodiment of the present application. The execution subject of this method can be a data storage device, which can be implemented through a computer program; it can also be implemented through a medium storing relevant computer programs, such as a USB flash drive and / or an optical disc, etc. Or, it can also be implemented through an entity device integrated or installed with relevant computer programs, such as an electronic device. The electronic device can be a server, a server cluster, a smart terminal, etc. As Figure 2 shown, the method may include the following steps:

[0040] S201: In response to a physical address storage request, obtain the target logical address requested to be used in the physical address storage request.

[0041] In response to the issued input / output (Input / Output Request, IO) request, which can be a physical address storage request, obtain the target logical address requested to be used in the physical address storage request.

[0042] S202: Obtain the parameter information of the pre-created B+ tree structure. The parameter information includes the order and height of the B+ tree structure.

[0043] In this embodiment, the parameter information includes but is not limited to: the order and height of the B+ tree structure, etc.

[0044] In the B+ tree structure, there are root nodes, intermediate layer nodes, and leaf layer nodes. Root nodes and intermediate layer nodes are also called internal nodes. The root node is the starting point of the B+ tree and is located at the topmost layer of the tree. It can be a leaf node or an internal node. Intermediate layer nodes are located between the root node and the leaf layer nodes. Leaf layer nodes are located at the bottommost layer of the tree and are the places where actual data is stored. In this application, they are used to store the physical addresses mapped to the logical addresses.

[0045] Among them, the order represents the maximum number of child nodes that each node in the B+ tree can have. For example, if the order of the B+ tree is m, then the node can have at most m child nodes.

[0046] The height refers to the number of nodes on the longest path from the root node to the leaf node. The height of the root node is 0, the height of the child nodes of the root node is 1, and so on. It can be understood as the number of layers of the B+ tree. Starting from the root node layer, the number of layers to the bottommost leaf node layer is the height of the tree.

[0047] S203: According to the target logical address, the order, and the height, determine the target leaf node in the B+ tree structure that stores the physical address mapped to the target logical address.

[0048] Starting from the root node, determine the child nodes corresponding to the intermediate layer nodes layer by layer according to the target logical address, order number, and height, until the target leaf node is determined in the leaf layer, and store the physical address mapped to the target logical address on the target leaf node.

[0049] S204: Traverse the pre-created B+ tree structure according to the target logical address to determine whether the target leaf node exists.

[0050] After determining the storage location of the physical address mapped to the target logical address in the leaf node layer, that is, the target leaf node, it is necessary to check the determined node.

[0051] Starting from the root node, traverse the nodes in each layer of the pre-created B+ tree structure according to the target logical address until the target leaf node is traversed. If the target leaf node is traversed, it means that the target leaf node already exists. If the target leaf node cannot be traversed, it means that there are missing nodes in the intermediate layer, resulting in the non-existence of the target leaf node. By performing the check, data consistency can be improved and duplicate insertions can be avoided.

[0052] S205: If it exists, store the physical address mapped to the target logical address on the target leaf node.

[0053] If the target leaf node exists, store the physical address mapped to the target logical address on the target leaf node.

[0054] In the above embodiment of the present application, in response to the storage request of the physical address, obtain the target logical address and the parameter information of the pre-created B+ tree structure, and determine the target leaf node for storing the physical address mapped to the target logical address in the B+ tree structure according to the target logical address and the parameter information. Traverse the pre-created B+ tree structure according to the target logical address to determine whether the target leaf node exists. If it exists, store the physical address mapped to the target logical address on the target leaf node. The method of this embodiment does not preset the leaf node corresponding to the logical address in the B+ tree structure in advance, but determines the target leaf node through the target logical address and the parameter information, so that the corresponding node is determined only when there is an actual data storage request, thus not occupying too much storage space in advance. And after determining the target leaf node, only store the physical address mapped to the logical address, rather than storing both the physical address and the logical address in the related art, thereby reducing the storage space occupied by the logical address in the leaf node, and further improving the utilization rate of the storage space of the leaf node.

[0055] Further, on the basis of the above embodiment, through Figure 3 For the creation process of the B+ tree structure, please refer to Figure 3 , Figure 3It is a schematic flowchart of a method for creating a B+ tree structure provided by an embodiment of this application. The method may include the following steps:

[0056] S301: Obtain the creation information of the B+ tree structure.

[0057] In this embodiment, the B+ tree structure adopts a static preset level, that is, according to the logical address scale, the complete B+ tree structure is pre-calculated and constructed, but only the basic framework of the tree is allocated initially, and all node resources are not actually occupied.

[0058] Obtain the creation information of the B+ tree structure. The creation information includes but is not limited to: the total number of logical addresses, the preset node capacity in the B+ tree structure, and the node capacity occupied by the logical addresses.

[0059] S302: Determine the order, height, and number of nodes of the B+ tree structure according to the creation information.

[0060] Determine the order m of the B+ tree structure according to the preset node capacity and the node capacity occupied by the logical addresses.

[0061] Optionally, determine the order of the B+ tree structure through the following formula (1):

[0062]

[0063] where the symbol " " represents the floor function, also known as the Floor function.

[0064] Determine the height k of the B+ tree structure according to the total number of logical addresses and the order.

[0065] Optionally, determine the height of the B+ tree structure through the following formula (2):

[0066]

[0067] where represents the total number of logical addresses; the symbol " " represents the ceiling function, also known as the Ceiling function.

[0068] Determine the number of nodes of the B+ tree structure according to the total number of logical addresses, the order, and the height.

[0069] Optionally, determine the number of nodes of the B+ tree structure through the following formula (3):

[0070]

[0071] where represents the number of nodes on the i-th layer of the path from the next layer of the root node (the 0th layer) to the leaf node.

[0072] S303: Create a B+ tree structure according to the order, height, and number of nodes.

[0073] Furthermore, based on the order, height, and number of nodes calculated according to the above formula, create a B+ tree structure based on a preset construction algorithm.

[0074] In the above embodiments of the present application, by obtaining the creation information of the B+ tree structure, and according to the creation information, determining the order, height, and number of nodes of the B+ tree structure, and then creating a B+ tree structure according to the order, height, and number of nodes, the created B+ tree structure is more accurate and flexible.

[0075] Further, on the basis of the above embodiments, the process of determining the target leaf node in the B+ tree structure that stores the physical address mapped to the target logical address according to the target logical address, order, and height is described through the following embodiments.

[0076] Please refer to Figure 4 , Figure 4 , which is a schematic flowchart of a method for determining a target leaf node provided by an embodiment of the present application. The method may include the following steps:

[0077] S401: Determine the serial number of the target logical address based on the address information of the target logical address and a preset conversion rule.

[0078] Based on a preset conversion rule, such as a preset specific sorting rule of the B+ tree, perform serial number conversion on the address information of the target logical address, and convert it into a consecutive integer serial number, so that the serial number can reflect the position of the node of the target logical address in the B+ tree.

[0079] Optionally, determine the serial number s of the target logical address through the following formula (4):

[0080]

[0081] Exemplarily, assuming that the block capacity size is 4KB and the address information of the target logical address is 0x8000, then s is 8 after calculation through the above formula (4).

[0082] S402: Determine the target leaf node in the B+ tree structure that stores the physical address mapped to the target logical address according to the serial number, order, and height.

[0083] Determine the target nodes corresponding to each intermediate layer in the B+ tree structure according to the serial number, order, and height, where the target nodes can also be referred to as child nodes.

[0084] Optionally, the target nodes corresponding to each intermediate layer in the B+ tree structure corresponding to the sequence number s of the target logical address are determined by the following formula (5):

[0085]

[0086] Based on the sequence number and the order, the target leaf node storing the physical address mapped to the target logical address in the B+ tree structure is determined.

[0087] Optionally, the target leaf node is determined by the following formula (6):

[0088]

[0089] Among them, the leaf node corresponding to the slot offset in the leaf node layer is the target leaf node.

[0090] In the above embodiments of the present application, based on the address information of the target logical address, the sequence number of the target logical address is determined based on a preset conversion rule, and based on the sequence number, order, and height, the target leaf node storing the physical address mapped to the target logical address in the B+ tree structure is determined, making the traversal process more accurate and fast, and improving the user experience.

[0091] When traversing the pre-created B+ tree structure according to the target logical address to determine whether the target leaf node exists, a possible implementation is:

[0092] According to the target logical address, traverse each intermediate layer in the pre-created B+ tree structure to determine whether there is a missing target node in the intermediate layer. If there is a missing target node, it is determined that the target leaf node does not exist. If there is no missing target node, traverse the leaf node layer in the pre-created B+ tree structure to determine whether the target leaf node can be traversed. If it is determined that the target leaf node can be traversed, it is determined that the target leaf node exists.

[0093] After determining the target leaf node through the above embodiments, check the leaf nodes in the B+ tree structure. Starting from the root node, calculate the node that should be searched in the current layer according to the target logical address. If the current layer is in the intermediate layer, check the node corresponding to the current layer to determine whether it is a valid value. In this embodiment, the value range of the nodes corresponding to each layer is preset in advance. Therefore, if it is determined that the value of the corresponding node searched in the current layer is within the preset range, it is valid. Then continue to traverse from the current layer to the next layer until the target leaf node can be traversed.

[0094] If it is determined that the value of the corresponding node found in the current layer is not within the preset range, it is invalid, indicating that the target node corresponding to the current layer does not exist, which means there are missing target nodes. Then, obtain the node information of the missing target nodes, allocate a new node from the preset memory pool, and perform initialization settings on the new node to obtain the initialized node. Furthermore, according to the node information of the missing target nodes, mount the new node to the parent node of the missing target nodes, and continue traversing from the new node until the target leaf node is traversed.

[0095] Optionally, during the traversal process, if it is found that there are missing target nodes in the current layer, trigger the dynamic application process, which will allocate a new node from the pre-allocated memory pool and initialize the metadata of the new node. Then, according to the node information of the missing target nodes, mount the new node to the corresponding parent node of the upper layer and update the physical address array in the parent node to show the inclusion of the new node. After completion, continue traversing to the next layer until the target leaf node is traversed.

[0096] For a certain physical address that already exists in a certain leaf node of the B+ tree, if you want to update this physical address, you can determine the target leaf node through the logical address mapped to this physical address, and then update the original physical address with the new physical address on the target leaf node, thereby reducing the creation of unnecessary nodes and data movement and improving the efficiency of the update.

[0097] In the above embodiments of the present application, traverse the pre-created B+ tree structure according to the target logical address to determine whether the target leaf node exists. If it is determined that the target leaf node can be traversed, it is determined that the target leaf node exists. If there are missing target nodes, insert a new node as the missing target node. This in-situ direct insertion method saves computing resources, simplifies the insertion process, and improves the insertion efficiency.

[0098] In the present application, the actual node allocation of the physical address is carried out on demand. Only when data is written to a certain logical address, that is, when a logical address storage request is issued, will the corresponding physical address storage space, that is, the target leaf node, be allocated for it. Although this on-demand allocation strategy reduces the initial resource occupation, in actual operation, random writing and over-allocation of the address space often lead to a low data filling rate of some leaf nodes, thereby causing waste of leaf node storage space. Therefore, in the present application, the leaf nodes can also be merged.

[0099] Please refer to Figure 5 , Figure 5 which is a schematic flowchart of a method for merging leaf nodes provided by an embodiment of the present application. The method may include the following steps:

[0100] S501: Obtain the currently used storage space of the target leaf node and the currently used storage space of the adjacent leaf nodes.

[0101] Obtain the currently used storage space of each leaf node. If the leaf node is the target leaf node, the currently used storage space of the leaf nodes adjacent to the target leaf node can thus be obtained.

[0102] S502: If the currently used storage space of the target leaf node is less than the preset storage space threshold and the currently used storage space of the adjacent leaf nodes is less than the preset storage space threshold, then perform a merging process on the target leaf node and the adjacent leaf nodes to obtain a merged leaf node.

[0103] If the currently used storage spaces of the target leaf node and the leaf nodes adjacent to the target leaf node are both less than the preset storage space threshold, then merge the target leaf node and the adjacent leaf nodes. During the merging process, the physical addresses that already exist in the two leaf nodes will be rearranged compactly in one node, and at the same time, the mapping relationship will be updated to keep the B+ tree structure stable.

[0104] Although the structure between the node and its parent node is not damaged after merging into a new node, the internal structure of the leaf node is damaged. Before merging, it is chosen not to save the logical address in the leaf node, but to deduce the physical address corresponding to the logical address through the calculation formula in the above embodiments to obtain the target leaf node. However, when the leaf nodes are merged, this mapping relationship is disrupted, and it is impossible to directly rely on the original formula to determine the correspondence between the logical address and the mapped physical address.

[0105] Therefore, this application also proposes a self-describing structure to rearrange the internal structure of the merged leaf node. A possible implementation method is:

[0106] Obtain the stored data and the logical address validity bitmap of the target leaf node, where the stored data includes valid data and invalid data, and the valid data is the stored physical address. Obtain the stored data and the logical address validity bitmap of the adjacent leaf nodes, perform a merging process on the stored data of the target leaf node and the stored data of the adjacent leaf nodes to obtain the merged stored data, perform a merging process on the logical address validity bitmap of the target leaf node and the logical address validity bitmap of the adjacent leaf nodes to obtain the merged logical address validity bitmap, and according to the merged logical address validity bitmap, remove the invalid data in the merged stored data to obtain the merged leaf node.

[0107] Optionally, the merged logical address validity bitmap consists of a first preset identifier, such as "0", and a second preset identifier, such as "1".

[0108] When removing invalid data in the merged stored data according to the merged logical address validity bitmap, the position information of the bit corresponding to the first preset identifier can be determined from the merged logical address validity bitmap, and according to the position information, the invalid data corresponding to the position information in the merged stored data is removed to obtain the merged leaf node.

[0109] S503: Mount the merged leaf node to the parent node of the target leaf node according to the node information of the target leaf node.

[0110] After merging, mount the merged leaf node to the parent node of the target leaf node, and add a merge flag bit Reorder_Flag to the pointer corresponding to the merged leaf node to indicate that the leaf node is a merged node.

[0111] Exemplarily, please refer to Figure 6 , Figure 6 FIG. is a schematic diagram of a leaf node merging process provided by an embodiment of the present application. Assume that node B, node C, and node D are leaf nodes, and node A is the parent node of the above three nodes. Assume that the physical address mapped by the logical address [100~199) is currently stored in node C, and the physical address mapped by the logical address [200~299) is currently stored in node D. If the currently used storage spaces of node C and node D are both less than the preset storage space threshold, for example, 50%, then node C and node D are merged into node E. The logical address covered by node E is [100~299), and node E is mounted to the parent node A.

[0112] In the above embodiment of the present application, although node merging occurs, the logical B+ tree structure remains unchanged. By updating the mapping table, the data that originally pointed to nodes C and D now uniformly points to the new node E. In this way, when querying the logical address, the preset B+ tree calculation still points to the leaf node where the logical address is located, that is, node E. This method not only improves the space utilization rate at the physical address level but also ensures the structural consistency between the leaf nodes at the logical address level.

[0113] Further, based on the above embodiment, combined with the specific example of this embodiment, the application of the self-describing structure is described, that is, the process of determining the physical address mapped to the target logical address from the merged leaf nodes according to the target logical address.

[0114] In this application, the self-describing structure consists of a description information area and a leaf node data area. The description information area is used to deduce the position of data in the logical space, including key fields such as the starting logical address Start_LBA, the logical address validity bitmap Address_Bitmap, and the logical address step size Slot_Step. The leaf node data area is specifically used to store physical addresses. It does not save logical addresses, and it is assumed that each physical address value occupies a fixed length.

[0115] Exemplarily, taking the illustration in Figure 6 as an example, assume that both leaf node C and leaf node D store 10 physical addresses. The stored data in the data area of leaf node C is [PBA1,0,PBA2,0,0,PBA3,0,0,PBA4,0], and the stored data in the data area of leaf node D is [0,PBA5,PBA6,0,0,PBA7,0,PBA8,0]. Then, the starting logical address Start_LBA covered by the merged leaf node E is 100, the logical address step size Slot_Step is 10, and the logical address validity bitmap Address_Bitmap of the merged leaf node E is the set of the logical address validity bitmaps corresponding to leaf node C and leaf node D, which is [1,0,1,0,0,1,0,0,1,0,0,1,0,1,0,0,1,0,1,0]. Here, "0" represents invalid data, and "1" represents valid data, that is, the stored physical address. After merging and removing the invalid data, the data area will be compactly arranged as [PBA1,PBA2,PBA3,PBA4,PBA5,PBA6,PBA7,PBA8].

[0116] The process of determining the physical address mapped to the target logical address from the merged leaf nodes can be as follows:

[0117] Obtain the starting logical address, logical address step size, merged logical address validity bitmap, and the stored data with invalid data removed, covered by the merged leaf nodes.

[0118] Taking the above example, the starting logical address covered by the merged leaf nodes is 100, the logical address step size is 10, the merged logical address validity bitmap is [1,0,1,0,0,1,0,0,1,0,0,1,0,1,0,0,1,0,1,0], and the stored data with invalid data removed is [PBA1,PBA2,PBA3,PBA4,PBA5,PBA6,PBA7,PBA8].

[0119] Determine the index value according to the target logical address, starting logical address, and logical address step size.

[0120] Optionally, the index value, i.e., the slot index index, is determined by the following formula (7):

[0121]

[0122] Check whether there is a bit equal to "1" in [1,0,1,0,0,1,0,0,1,0,0,1,0,1,0,0,1,0,1,0] in the merged logical address validity bitmap. If there is a bit equal to "1", it is determined that the data exists. Calculate the position of the physical address mapped to the target logical address in the data area, and the empty slots, i.e., the invalid data, have been removed from the data area.

[0123] According to the index value and the merged logical address validity bitmap, determine the valid index value index_valid = the number of "1"s in Address_Bitmap[0~index] minus 1.

[0124] According to the valid index value and the stored data with invalid data removed, determine the physical address mapped to the target logical address from the merged leaf nodes.

[0125] Optionally, return the index_valid-th physical address in the data area as the target logical address corresponding to the target logical address.

[0126] In the above embodiments of the present application, this self-describing leaf node design can reduce the waste of leaf node storage space, maintain the integrity of the saved logical addresses, and support fast query. Each physical address can be quickly located with the help of a small amount of metadata. At the same time, it maintains the logic of the B+ tree structure. In the case of changes in physical addresses, the logical address mapping can still be kept clear, efficient, and accurate.

[0127] Through the description of the above embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be implemented by means of software plus a necessary general hardware platform. Of course, it can also be implemented by hardware, but in many cases, the former is a better implementation method.

[0128] Figure 7 It is a schematic structural diagram of a data storage device provided by an embodiment of the present application. As Figure 7 shown, it includes:

[0129] An acquisition module 701, configured to acquire the target logical address requested to be used in the physical address storage request in response to the physical address storage request.

[0130] The acquisition module 701 is further configured to acquire the parameter information of the pre-created B+ tree structure, where the parameter information includes the order and height of the B+ tree structure.

[0131] A determination module 702, configured to determine a target leaf node in a B+ tree structure that stores a physical address mapped to a target logical address according to the target logical address, the order, and the height.

[0132] A processing module 703, configured to traverse a pre-created B+ tree structure according to the target logical address to determine whether the target leaf node exists.

[0133] The processing module 703 is further configured to, if it exists, store the physical address mapped to the target logical address on the target leaf node.

[0134] In a possible implementation, the determination module 702 is specifically configured to:

[0135] Determine the serial number of the target logical address based on a preset conversion rule according to the address information of the target logical address.

[0136] Determine the target leaf node in the B+ tree structure that stores the physical address mapped to the target logical address according to the serial number, the order, and the height.

[0137] In a possible implementation, the determination module 702 is further configured to:

[0138] Determine the target nodes corresponding to each intermediate layer in the B+ tree structure according to the serial number, the order, and the height.

[0139] In a possible implementation, the processing module 703 is specifically configured to:

[0140] Traverse each intermediate layer in the pre-created B+ tree structure according to the target logical address to determine whether there is a missing target node in the intermediate layer.

[0141] If there is a missing target node, determine that the target leaf node does not exist.

[0142] If there is no missing target node, traverse the leaf node layer in the pre-created B+ tree structure to determine whether the target leaf node can be traversed out.

[0143] If it is determined that the target leaf node can be traversed out, determine that the target leaf node exists.

[0144] In a possible implementation, the processing module 703 is further configured to:

[0145] If there is a missing target node, obtain the node information of the missing target node.

[0146] Allocate a new node from a preset memory pool.

[0147] Perform initialization settings on the new node to obtain the node after initialization settings.

[0148] Mount a new node to the parent node of the missing target node according to the node information of the missing target node.

[0149] Continue traversing from the new node until the target leaf node is traversed.

[0150] A possible implementation is that the processing module 703 is further configured to:

[0151] Obtain the currently used storage space of the target leaf node and the currently used storage space of the adjacent leaf node.

[0152] If the currently used storage space of the target leaf node is less than the preset storage space threshold and the currently used storage space of the adjacent leaf node is less than the preset storage space threshold, then perform a merging process on the target leaf node and the adjacent leaf node to obtain a merged leaf node.

[0153] Mount the merged leaf node to the parent node of the target leaf node according to the node information of the target leaf node.

[0154] A possible implementation is that the processing module 703 is further specifically configured to:

[0155] Obtain the stored data of the target leaf node and the logical address validity bitmap. The stored data includes valid data and invalid data, and the valid data is the stored physical address.

[0156] Obtain the stored data of the adjacent leaf node and the logical address validity bitmap.

[0157] Perform a merging process on the stored data of the target leaf node and the stored data of the adjacent leaf node to obtain merged stored data.

[0158] Perform a merging process on the logical address validity bitmap of the target leaf node and the logical address validity bitmap of the adjacent leaf node to obtain a merged logical address validity bitmap.

[0159] Remove the invalid data in the merged stored data according to the merged logical address validity bitmap to obtain a merged leaf node.

[0160] A possible implementation is that the processing module 703 is further specifically configured to:

[0161] Determine the position information of the bit corresponding to the first preset identifier from the merged logical address validity bitmap.

[0162] Remove the invalid data corresponding to the position information in the merged stored data according to the position information to obtain a merged leaf node.

[0163] One possible implementation is that the processing module 703 is further configured to:

[0164] Determine a physical address mapped to the target logical address from the merged leaf nodes according to the target logical address.

[0165] One possible implementation is that the processing module 703 is specifically configured to:

[0166] Obtain the starting logical address covered by the merged leaf nodes, the logical address step size, the merged logical address validity bitmap, and the stored data with invalid data removed.

[0167] Determine an index value according to the target logical address, the starting logical address, and the logical address step size.

[0168] Determine a valid index value according to the index value and the merged logical address validity bitmap.

[0169] Determine a physical address mapped to the target logical address from the merged leaf nodes according to the valid index value and the stored data with invalid data removed.

[0170] One possible implementation is that the processing module 703 is further configured to:

[0171] Obtain the creation information of the B+ tree structure.

[0172] Determine the order, height, and number of nodes of the B+ tree structure according to the creation information.

[0173] Create a B+ tree structure according to the order, height, and number of nodes.

[0174] One possible implementation is that the processing module 703 is specifically configured to:

[0175] Determine the order, height, and number of nodes of the B+ tree structure according to the creation information, including:

[0176] Determine the order of the B+ tree structure according to the preset node capacity and the node capacity occupied by the logical address.

[0177] Determine the height of the B+ tree structure according to the total number of logical addresses and the order.

[0178] Determine the number of nodes of the B+ tree structure according to the total number of logical addresses, the order, and the height.

[0179] For the description of the features in the corresponding embodiments of the data storage device, reference can be made to the relevant descriptions in the corresponding embodiments of the data storage device method, which will not be elaborated here one by one.

[0180] Figure 8A schematic structural diagram of an electronic device provided by an embodiment of the present application. As Figure 8 shown, the electronic device provided in this embodiment includes: at least one processor 801 and a memory 802. Optionally, a communication component 803 is further included. Among them, the processor 801, the memory 802, and the communication component 803 are connected through a bus 804.

[0181] In a specific implementation process, at least one processor 801 executes computer-executable instructions stored in the memory 802, so that at least one processor 801 executes the above data storage method embodiment.

[0182] For the specific implementation process of the processor 801, reference may be made to the above method embodiment, and its implementation principle and technical effects are similar, which will not be elaborated here in this embodiment.

[0183] In the above embodiment, it should be understood that the processor may be a central processing unit (Central Processing Unit, abbreviated as: CPU), or other general-purpose processors, digital signal processors (Digital Signal Processor, abbreviated as: DSP), application specific integrated circuits (Application Specific Integrated Circuit, abbreviated as: ASIC), etc. The general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc. The steps of the method disclosed in combination with the application can be directly embodied as being executed by a hardware processor, or executed by a combination of hardware and software modules in the processor.

[0184] The memory may include a high-speed memory (Random Access Memory, RAM), and may also include a non-volatile memory (Non-volatile Memory, NVM), such as at least one disk memory.

[0185] The bus may be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc. For the convenience of representation, the bus in the drawings of the present application is not limited to only one bus or one type of bus.

[0186] Embodiments of the present application also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the above-described embodiments of the data storage method when running.

[0187] In an exemplary embodiment, the above computer-readable storage medium may include, but is not limited to: various media such as USB flash drives, read-only memories (ROMs), random access memories (RAMs), external hard drives, magnetic disks, or optical discs that can store computer programs.

[0188] Embodiments of the present application also provide a computer program product, the computer program product including a computer program, and the steps in any of the above-described embodiments of the data storage method are implemented when the computer program is executed by a processor.

[0189] Embodiments of the present application also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program, and the steps in any of the above-described embodiments of the data storage method are implemented when the computer program is executed by a processor.

[0190] Those skilled in the art can further realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of the two. To clearly illustrate the interchangeability of hardware and software, the components and steps of each example have been generally described according to their functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Skilled artisans can use different methods for each specific application to implement the described functions, but such implementation should not be considered to exceed the scope of the present application.

[0191] The above has introduced in detail a data storage method, an electronic device, a storage medium, and a product provided by the present application. Specific examples are used herein to illustrate the principles and implementation manners of the present application. The description of the above embodiments is only used to help understand the method and its core idea of the present application. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the protection scope of the claims of the present application.

Claims

1. A data storage method, characterized in that, Including: In response to a physical address storage request, obtain the target logical address requested to be used in the physical address storage request; Obtain parameter information of a pre-created B+ tree structure, where the parameter information includes the order and height of the B+ tree structure; Based on the address information of the target logical address, determine the sequence number of the target logical address according to a preset conversion rule; According to the sequence number, the order, and the height, determine the target leaf node in the B+ tree structure that stores the physical address mapped to the target logical address; Traverse the pre-created B+ tree structure according to the target logical address to determine whether the target leaf node exists; If it exists, store the physical address mapped to the target logical address on the target leaf node.

2. The method according to claim 1, characterized in that, Also including: According to the sequence number, the order, and the height, determine the target nodes corresponding to each intermediate layer in the B+ tree structure.

3. The method according to claim 2, wherein The step of traversing the pre-created B+ tree structure according to the target logical address to determine whether the target leaf node exists includes: According to the target logical address, traverse each intermediate layer in the pre-created B+ tree structure to determine whether there is a missing target node in the intermediate layer; If there is the missing target node, determine that the target leaf node does not exist; If there is no missing target node, traverse the leaf node layer in the pre-created B+ tree structure to determine whether the target leaf node can be traversed; If it is determined that the target leaf node can be traversed, determine that the target leaf node exists.

4. The method according to claim 3, characterized in that Also including: If there is a missing target node, obtain the node information of the missing target node; Allocate a new node from a preset memory pool; Perform initialization settings on the new node to obtain the initialized node; According to the node information of the missing target node, mount the new node to the parent node of the missing target node; Continue to traverse starting from the new node until the target leaf node is traversed.

5. The method according to claim 1, wherein Also including: Obtain the currently used storage space of the target leaf node and the currently used storage space of the adjacent leaf node; If the currently used storage space of the target leaf node is less than a preset storage space threshold and the currently used storage space of the adjacent leaf node is less than the preset storage space threshold, perform a merging process on the target leaf node and the adjacent leaf node to obtain a merged leaf node; According to the node information of the target leaf node, mount the merged leaf node to the parent node of the target leaf node.

6. The method according to claim 5, characterized in that, The step of performing a merging process on the target leaf node and the adjacent leaf node to obtain a merged leaf node includes: Obtain the stored data and the logical address validity bitmap of the target leaf node, where the stored data includes valid data and invalid data, and the valid data is the stored physical address; Obtain the stored data and the logical address validity bitmap of the adjacent leaf node; Merge the stored data of the target leaf node and the stored data of the adjacent leaf node to obtain the merged stored data; Merge the logical address validity bitmaps of the target leaf node and the adjacent leaf node to obtain the merged logical address validity bitmap; According to the merged logical address validity bitmap, remove the invalid data in the merged stored data to obtain the merged leaf node.

7. The method according to claim 6, wherein The merged logical address validity bitmap consists of a first preset identifier and a second preset identifier; The step of removing the invalid data in the merged stored data according to the merged logical address validity bitmap to obtain the merged leaf node includes: Determine the position information of the bits corresponding to the first preset identifier from the merged logical address validity bitmap; According to the position information, remove the invalid data corresponding to the position information in the merged stored data to obtain the merged leaf node.

8. The method according to claim 7, characterized in that, Further included: According to the target logical address, determine the physical address mapped to the target logical address from the merged leaf node.

9. The method according to claim 8, wherein The step of determining the physical address mapped to the target logical address from the merged leaf node according to the target logical address includes: Obtain the starting logical address covered by the merged leaf node, the logical address step size, the merged logical address validity bitmap, and the stored data with invalid data removed; Determine an index value according to the target logical address, the starting logical address, and the logical address step size; Determine a valid index value according to the index value and the merged logical address validity bitmap; According to the valid index value and the stored data with invalid data removed, determine the physical address mapped to the target logical address from the merged leaf node.

10. The method according to claim 1, wherein The creation process of the B+ tree structure includes: Obtain the creation information of the B+ tree structure; According to the creation information, determine the order, height, and number of nodes of the B+ tree structure; Create the B+ tree structure according to the order, height, and number of nodes.

11. The method according to claim 10, characterized in that, The creation information includes: the total number of logical addresses, the preset node capacity in the B+ tree structure, and the node capacity occupied by the logical address; The step of determining the order, height, and number of nodes of the B+ tree structure according to the creation information includes: Determine the order of the B+ tree structure according to the preset node capacity and the node capacity occupied by the logical address; Determine the height of the B+ tree structure according to the total number of logical addresses and the order; Determine the number of nodes of the B+ tree structure according to the total number of logical addresses, the order, and the height.

12. An electronic device, characterized in that, Included: A memory for storing a computer program; A processor for implementing the steps of the data storage method according to any one of claims 1 to 11 when executing the computer program.

13. A computer-readable storage medium, characterized in that, A computer program is stored in the computer-readable storage medium, wherein when the computer program is executed by a processor, the steps of the data storage method according to any one of claims 1 to 11 are implemented.

14. A computer program product comprising a computer program, characterized in that, When the computer program is executed by a processor, the steps of the data storage method according to any one of claims 1 to 11 are implemented.

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