Chip verification method based on multi-core constraint solving, electronic device and medium

Abstract

The present application relates to the technical field of computer, especially to a chip verification method based on multi-core constraint solving, electronic equipment and medium, comprising: S1, the main thread acquires the candidate solver core set of the target constraint problem; S2, the main thread acquires M sub-threads; S3, the main thread copies M copies of the target constraint problem, and sends each W m , Each W m performs the target constraint problem in parallel; S4, the main thread returns the optimal C m solution result, and generates the target solver core set; S5, when the target constraint problem is acquired again, the target constraint problem is solved by selecting D1 first; S6, the coverage rate improvement speed is monitored, if the coverage rate improvement speed meets the preset coverage rate improvement speed reduction condition, then S7 is executed; step S7 selects a target D i , switches to the target D i to solve the target constraint problem, and returns to step S6. The present application improves the convergence speed of chip function coverage rate.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and in particular to a chip verification method, electronic device, and medium based on multi-core constraint solving. Background Technology

[0002] Constraint problem solving techniques have wide applications in hardware verification, software automated testing, and a range of common programming problems. Many problems can be transformed into constraint problems and solved using constraint solvers. There are various types of solver cores used for constraint problem solving, and a single constraint solver can contain different types of solver cores. Different types of constraint solver cores typically excel at solving very different types of problems, and different types of solver cores will exhibit completely different random distributions of solutions for the same constraint problem. Functional coverage is a crucial metric in the chip verification process. Verification engineers need to write functional coverage reports to statistically analyze the coverage of data, addresses, and control signals to verify whether the stimuli are achieving their intended purpose, thus quantifying the completeness of the entire verification process. Therefore, the convergence of the functional coverage metric plays a vital role in the convergence of the entire verification process.

[0003] In a typical hardware verification project, a sufficient number of test iterations need to be run on the same random test cases. Therefore, the same constraint problem is solved repeatedly. The quality of the random value distribution often determines the speed of functional coverage improvement and plays a crucial role in the convergence of the entire verification process. Using only one solver core can lead to distribution bias problems. Therefore, how to combine solver cores with different distribution characteristics to generate richer stimulus distributions, cover more of the stimulus solution space, make the random variable distribution more uniform, and improve the convergence speed of chip functional coverage has become an urgent technical problem to be solved. Summary of the Invention

[0004] The purpose of this invention is to provide a chip verification method, electronic device, and medium based on multi-core constraint solving, which improves the convergence speed of chip functional coverage.

[0005] According to a first aspect of the present invention, a chip verification method based on multi-core constraint solving is provided, comprising:

[0006] Step S1: The main thread obtains the core set of candidate solvers for the objective constraint problem {C1, C2, ..., C...}. m ,...,C M}, C m Let m be the m-th candidate solver core of the constraint problem to be solved, where m ranges from 1 to M, and M is the total number of candidate solver cores of the target constraint problem, where M≥2.

[0007] Step S2: The main thread obtains M child threads {W1, W2, ..., W...} from the thread pool. m ,...,W M}, and establish a one-to-one correspondence between each sub-thread and the candidate solver core, W m For the m-th child thread, W m With C m Correspondingly;

[0008] Step S3: The main thread copies the target constraint problem M times and sends them to each W. m Each W m Parallel execution of objective constraints;

[0009] Step S4: The main thread returns the optimal C. m The solution results are obtained, and the core set of the objective solver {D1,D2,...,D} is generated. i ,...,D I}, D i For the i-th objective solver core, where i ranges from 1 to I, D i For the solver core that solves the objective constraint problem with a runtime less than or equal to a preset waiting time threshold for the objective constraint problem, {D1,D2,...,D i ,...,D I} is {C1,C2,...,C m ,...,C M A subset of}, where D1 is the optimal C. m ;

[0010] Step S5: When the target constraint problem is obtained again, the main thread first selects D1 to solve the target constraint problem;

[0011] Step S6: Monitor the coverage improvement rate. If the coverage improvement rate meets the preset condition for reducing the coverage improvement rate, then proceed to step S7.

[0012] Step S7: From {D1,D2,...,D... i ,...,D I Select a target D from} i Switch to target D i Solve the objective constraint problem and return to step S6.

[0013] According to a second aspect of the present invention, an electronic device is provided, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being configured to perform the method described in the first aspect of the present invention.

[0014] According to a third aspect of the present invention, a computer-readable storage medium is provided, storing computer-executable instructions for performing the method described in the first aspect of the present invention.

[0015] Compared with existing technologies, this invention has significant advantages and beneficial effects. Through the above technical solution, the chip verification method, electronic device, and medium based on multi-core constraint solving provided by this invention achieve considerable technological advancement and practicality, and have broad industrial application value. It possesses at least the following beneficial effects:

[0016] This invention can combine solver cores with different distribution characteristics to generate richer excitation distributions, cover more excitation solution space, make the random variable distribution more uniform, and improve the convergence speed of the new chip's functional coverage. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 The flowchart illustrates the chip verification method based on multi-core constraint solving provided in this embodiment of the invention. Detailed Implementation

[0019] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0020] This invention provides a chip verification method based on multi-core constraint solving, such as... Figure 1 As shown, it includes:

[0021] Step S1: The main thread obtains the core set of candidate solvers for the objective constraint problem {C1, C2, ..., C...}. m ,...,C M}, C m Let m be the m-th candidate solver core of the constraint problem to be solved, where m ranges from 1 to M, and M is the total number of candidate solver cores of the target constraint problem, where M≥2.

[0022] Among them, different C mThe solver core types may be the same or different. The solver core types include SAT (Booleansatisfiability problem) solver, SMT (Satisfiability modulo theories) solver, CSP (Constraint satisfaction problem) solver, and BDD (Binary decision diagram) solver.

[0023] Step S2: The main thread obtains M child threads {W1, W2, ..., W...} from the thread pool. m ,...,W M}, and establish a one-to-one correspondence between each sub-thread and the candidate solver core, W m For the m-th child thread, W m With C m Correspondingly.

[0024] Step S3: The main thread copies the target constraint problem M times and sends them to each W. m Each W m Parallel execution of target constraints problem.

[0025] Step S4: The main thread returns the optimal C. m The solution results are obtained, and the core set of the objective solver {D1,D2,...,D} is generated. i ,...,D I}, D i This is the i-th objective solver core, where i ranges from 1 to I, and I is the total number of objective solver cores. D i For the solver core that solves the objective constraint problem with a runtime less than or equal to a preset waiting time threshold for the objective constraint problem, {D1,D2,...,D i ,...,D I} is {C1,C2,...,C m ,...,C M A subset of}, where D1 is the optimal C. m .

[0026] Step S5: When the target constraint problem is obtained again, the main thread first selects D1 to solve the target constraint problem.

[0027] Step S6: Monitor the coverage improvement rate. If the coverage improvement rate meets the preset condition for reducing the coverage improvement rate, then proceed to step S7.

[0028] The preset condition for reducing the coverage rate improvement speed can be set to the coverage rate improvement speed being less than a preset speed threshold, or it can be that the coverage rate improvement speed begins to decrease, or it can be that the coverage rate improvement speed continues to decrease within a preset time period. The specific settings can be flexibly configured according to the application requirements.

[0029] Step S7: From {D1,D2,...,D... i ,...,D I Select a target D from} i Switch to target D i Solve the objective constraint problem and return to step S6.

[0030] It should be noted that, through steps S5-S6, when the same objective constraint problem is randomized again, the main thread defaults to prioritizing the optimal C. m The solution is performed, and the main thread continuously monitors the rate of improvement in functional coverage. When the preset condition for a decrease in the rate of improvement in coverage is met, it enters adaptive scheduling mode, starting from {D1,D2,...,D...}. i ,...,D I Randomly select another D that is different from D1 in} i The call to solve the problem will be performed, and if the improvement in functional coverage is detected to be effective, D will continue to be used. i Otherwise, continue switching. When the preset conditions for increasing coverage and decreasing speed are met, continue switching between different solver cores for use until the chip verification is completed.

[0031] By combining solvers with different distribution characteristics and superimposing them to generate the final random value distribution, the stimulus distribution generated by the constraint solver can be enriched, the random variable distribution can be more uniform, and a wider range of random solutions can be covered, avoiding the distribution bias problem caused by using only one solver. Furthermore, it can generate richer test scenarios, helping to achieve faster convergence of functional coverage.

[0032] As one embodiment, step S1 includes:

[0033] Step S11: The main thread extracts feature information from the target constraint problem; the feature information includes the number of variables, the number of variable bits, the number of expressions, and the expression type.

[0034] The objective constraint problem consists of variables, constants, and expressions. Variables are signed or unsigned bit vectors with a fixed bit width. Expressions consist of operands and operators. Operands can be constants or variables, and operators can be categorized into six types: logical operators, bitwise operators, arithmetic operators, relational operators, if-then-else operators, and set relational operators. Logical operators include &&, ||, and !. Bitwise operators include &, |, ^, ~, etc. Arithmetic operators include +, -, *, / , and %. Relational operators include >, <, >=, <=, ==, !, and =. Set relational operators include inside and dist.

[0035] Step S12: Determine the solver cores that can match the feature information corresponding to the target constraint problem and are not marked with the target constraint problem disable flag as candidate solver cores, and generate a set of candidate solver cores.

[0036] It should be noted that solver cores marked with the "disabled for target constraint problems" label refer to solver cores that are not applicable to target constraint problems. Specifically, they can be solver cores whose target constraint problem solution time exceeds a preset waiting time threshold.

[0037] As one embodiment, step S4 includes:

[0038] Step S41: The main thread will first obtain the solution result C. m Determined as the current optimal C m Return the current optimal C m The solution results are as follows.

[0039] Step S42: Divide the current optimal C m C other than m The corresponding W m Continue running in the background, and optimize C. m And except for the current optimal C m In addition to returning the solution result within the preset waiting time threshold, C m All of them are determined to be the core of the objective solver, generating {D1,D2,...,D...} i ,...,D I}

[0040] As one embodiment, step S41 includes:

[0041] Step S411, each W m For the objective-constrained problem, a targeted approach is taken for C. m Preprocessing modeling adaptation to generate C mThe corresponding intermediate state constraint problem P m .

[0042] Preprocessing modeling adaptation is a process of adjusting and optimizing the original constraint model based on the characteristics of the specific problem, its environment, and specific requirements before formally applying the solution algorithm to find solutions that satisfy the constraints. Intermediate constraint problems are transitional problem forms after preprocessing modeling adaptation during the process of solving the original constraint problem. Step S411 can be directly implemented based on the existing preprocessing modeling adaptation process and will not be elaborated further here.

[0043] Step S412, Start each C m Combined with the shared inference constraint library, the corresponding P m The solution is performed, and the shared inference constraint library is initially empty.

[0044] Step S413, if C m Generate inference constraints, then C m The corresponding inference constraints are returned to the main thread, and the main thread will then return C. m The corresponding inference constraints are stored in the shared inference constraint library.

[0045] Among them, inference constraints refer to additional constraint information derived through inference mechanisms based on existing constraints of the target problem, relevant knowledge of the problem domain, and logical rules. This information helps to further limit the solution space of the problem and helps to find feasible solutions that satisfy all constraints more efficiently and accurately. By setting up a shared inference constraint library, each C m Interact with the shared inference constraint library to collaboratively solve the corresponding P m This can accelerate the solution process.

[0046] Step S414: The earliest C to obtain the solution result m Determined as the current optimal C m .

[0047] As one embodiment, the step S42 is followed by:

[0048] Step S43: If the solution result is not returned after the preset waiting time threshold is exceeded, then... m The target constraint issue is marked as disabled.

[0049] It should be noted that by marking the target constraint problem with a disabled flag in step S43, the speed and accuracy of obtaining the candidate solver core set can be improved when step S1 is executed again.

[0050] Suppose a random integer variable x is defined in a target constraint problem, and a defined function coverage is associated with x. The solution space of x is [a:b], [c:d], [e:f]. Calling different solver cores produces different random value distributions for x. C1 cannot produce solutions in the range [e:f] or has a very low probability, C2 cannot produce solutions in the range [a:b] or has a very low probability, and C3 produces solutions that mainly fall in the interval [c:d]. Using the method described in this embodiment of the invention, multiple distributions can be superimposed, so that x can be more uniform and cover more solution values, generating richer test scenarios and improving the relevant coverage.

[0051] Here is an example of a goal-constrained problem:

[0052]

[0053] For SAT-type solver cores, the distribution of the generated random solutions on x is such that the highest bit is always 0, and the probability of 0 or 1 is equal for each of the 7 bits from low to high. For CSP-type solver cores, x uniformly takes values ​​within the range of [1:99]. In this case, BDD-type solver cores also uniformly take values ​​within the range of [1:99]. However, as the number of variables increases, BDD-type solver cores will follow a strictly uniform joint probability distribution. The distribution of other types of solver cores becomes more complex and unpredictable. Using only one type of solver core can lead to distribution bias problems. This invention combines solver cores with different distribution characteristics to superimpose the final random value distribution, making the excitation distribution generated by the constraint solver core richer, the random variable distribution more uniform, and covering a wider random solution space.

[0054] As one embodiment, in step S7, the values ​​can be directly derived from {D1,D2,...,D...} i ,...,D I Randomly select a target D from} i Alternatively, a strategy adjustment module can be set up, which can be used to adjust the strategy from {D1,D2,...,D...} i ,...,D I Select target D in} i The inputs to the strategy adjustment module can specifically include the relationship between random constraint variables and coverage variables, the statistical distribution data of the current random constraint variables, and the current coverage trend, etc. The outputs of the strategy adjustment module can specifically include the target D. iThe key parameters of the solver core, along with the corresponding adjustments, are then defined. The strategy adjustment module can be implemented using algorithms such as AI (Artificial Intelligence). It should be noted that the above is merely an example; other examples can be derived from {D1, D2, ..., D...}. i ,...,D I Select target D in} i The algorithm also applies here.

[0055] It should be noted that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although the flowcharts describe the steps as sequential processes, many of these steps can be performed in parallel, concurrently, or simultaneously. Furthermore, the order of the steps can be rearranged. A process can be terminated when its operation is complete, but it may also have additional steps not included in the figures. A process can correspond to a method, function, procedure, subroutine, subroutine, etc.

[0056] This invention also provides an electronic device, including: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being configured to perform the method described in this invention.

[0057] This invention also provides a computer-readable storage medium storing computer-executable instructions for performing the methods described in this invention.

[0058] The embodiments of the present invention can combine solver cores with different distribution characteristics to generate richer excitation distributions, cover more excitation solution space, make the random variable distribution more uniform, and improve the convergence speed of the new chip's functional coverage.

[0059] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the scope of the present invention.

Claims

1. A chip verification method based on multi-core constraint solving, characterized in that, include: Step S1: The main thread obtains the core set of candidate solvers for the objective constraint problem {C1, C2, ..., C...}. m ,...,C M }, C m Let m be the m-th candidate solver core of the constraint problem to be solved, where m ranges from 1 to M, and M is the total number of candidate solver cores of the target constraint problem, where M≥2. Step S2: The main thread obtains M child threads {W1, W2, ..., W...} from the thread pool. m ,...,W M }, and establish a one-to-one correspondence between each sub-thread and the candidate solver core, W m For the m-th child thread, W m With C m Correspondingly; Step S3: The main thread copies the target constraint problem M times and sends them to each W. m Each W m Parallel execution of target constraints; Step S4: The main thread returns the optimal C. m The solution results are obtained, and the target solver core set {D1,D2,...,D} is generated. i ,...,D I }, D i For the i-th objective solver core, where i ranges from 1 to I, D i For the solver core that solves the objective constraint problem with a runtime less than or equal to a preset waiting time threshold for the objective constraint problem, {D1,D2,...,D i ,...,D I } is {C1,C2,...,C m ,...,C M A subset of}, where D1 is the optimal C. m ; Step S5: When the target constraint problem is obtained again, the main thread first selects D1 to solve the target constraint problem; Step S6: Monitor the coverage improvement rate. If the coverage improvement rate meets the preset condition for reducing the coverage improvement rate, then proceed to step S7. The preset conditions for reducing the coverage rate increase rate are set as follows: the coverage rate increase rate is less than the preset rate threshold, the coverage rate increase rate starts to decrease, or the coverage rate increase rate continues to decrease within a preset time period. Step S7: From {D1,D2,...,D... i ,...,D I Select a target D from} i Switch to target D i Solve the objective constraint problem and return to step S6.

2. The method according to claim 1, characterized in that, Step S1 includes: Step S11: The main thread extracts feature information from the target constraint problem; Step S12: Determine the solver cores that can match the feature information corresponding to the target constraint problem and are not marked with the target constraint problem disable flag as candidate solver cores, and generate a set of candidate solver cores.

3. The method according to claim 2, characterized in that, The feature information includes the number of variables, the number of variable bits, the number of expressions, and the expression type.

4. The method according to claim 1, characterized in that, Step S4 includes: Step S41: The main thread will first obtain the solution result C. m Determined as the current optimal C m Return the current optimal C m The solution results; Step S42: Divide the current optimal C... m C other than m The corresponding W m Continue running in the background, and optimize C. m And except for the current optimal C m In addition to returning the solution result within the preset waiting time threshold, C m All of them are determined to be the core of the objective solver, generating {D1,D2,...,D...} i ,...,D I } 5. The method according to claim 4, characterized in that, Step S41 includes: Step S411, each W m For the objective-constrained problem, a targeted approach is taken for C. m Preprocessing modeling adaptation to generate C m The corresponding intermediate state constraint problem P m ; Step S412, Start each C m Combined with the shared inference constraint library, for the corresponding P m The solution is performed when the shared inference constraint library is initially empty. Step S413, if C m Generate inference constraints, then C m The corresponding inference constraints are returned to the main thread, and the main thread will then return C. m The corresponding inference constraints are stored in the shared inference constraint library; Step S414: The earliest C to obtain the solution result m Determined as the current optimal C m .

6. The method according to claim 4, characterized in that, Following step S42, the following is also included: Step S43: If the solution result is not returned after the preset waiting time threshold is exceeded, then... m The above label indicates a disabled target constraint issue.

7. The method according to claim 1, characterized in that, Different C m The solver core types may be the same or different, and the solver core types include SAT solver, SMT solver, CSP solver and BDD solver.

8. An electronic device, characterized in that, include: At least one processor; And, a memory communicatively connected to the at least one processor; The memory stores instructions that are executed by the at least one processor, the instructions being configured to perform the method of any one of claims 1-7.

9. A computer-readable storage medium, characterized in that, The device stores computer-executable instructions for performing the method of any one of claims 1-7.

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