Zero-knowledge-proof-oriented CPU-GPU data processing and transmission optimization system and method

Abstract

Disclosed in the present invention is a zero-knowledge-proof-oriented CPU-GPU data processing and transmission optimization system, which is used for executing multi-scalar multiplication operations on the basis of elliptic curve cryptography, so as to generate zero-knowledge proofs. The system comprises a CPU and a GPU, wherein a data transmission channel is provided between the CPU and the GPU; the CPU is used for acquiring and storing point sets and scalar sets that are involved in multi-scalar multiplication operations, and using a set parallelized data transmission mechanism to communicate with the GPU; and the GPU executes multi-scalar multiplication computation on the basis of the point sets and the scalar sets, and returns a computation result to the CPU. By means of the coordinated effect of a plurality of technical features, the present invention significantly improves the speed and efficiency of zero-knowledge proof generation and optimizes resource utilization efficiency.

Description

CPU-GPU data processing and transmission optimization system and method for zero-knowledge proof TECHNICAL FIELD

[0001] The present application relates to the technical field of computers, and more particularly to a CPU-GPU data processing and transmission optimization system and method for zero-knowledge proof. BACKGROUND

[0002] Zero-Knowledge Proof (ZKP) is a cryptographic protocol based on mutual recognition between two or more parties, which aims to enable the prover to convince the verifier of the authenticity of a statement without revealing any useful information to the verifier. The key to this protocol is to ensure the trust of the verifier while protecting the privacy of the prover. The core value of zero-knowledge proof lies in the ability to prove the authenticity of a statement without revealing any specific information. However, the implementation of this technology faces enormous computational challenges, mainly due to the computationally intensive nature of its algorithms. Traditional Central Processing Unit (CPU) architecture is not capable of handling such high-concurrency and high-computational-density tasks, especially when dealing with large-scale data sets and complex operations. Limited by its single-thread performance and memory access delay, CPU often fails to achieve satisfactory efficiency.

[0003] To overcome this limitation, heterogeneous computing architectures, particularly field-programmable gate arrays (FPGA), application-specific integrated circuits (ASIC), and graphics processing units (GPU), have emerged as key enablers for efficient computation of zero-knowledge proofs. FPGAs can significantly speed up complex mathematical operations in ZKPs through parallel processing and pipeline optimization, thereby reducing the time for proof generation and verification, which is particularly important for applications with high real-time requirements. Additionally, the programmability and flexibility of FPGAs allow for customized designs tailored to specific ZKP algorithms, enabling more efficient computation paths, reducing unnecessary data movement and storage, and ultimately improving overall performance, making large-scale deployment possible. ASICs are integrated circuits designed specifically for a particular application. For zero-knowledge proofs, ASICs can be designed to perform specific mathematical operations such as modular multiplication and elliptic curve point addition, providing higher performance, lower power consumption, smaller physical size, and long-term economic benefits. In stable and large-scale applications, the fixed circuit design of ASICs ensures the security of computation efficiency and data processing. For example, PipeZK uses an ASIC chip to implement a pipelined architecture that accelerates the two computationally intensive stages of fast Fourier transform and multi-scalar multiplication by setting up dedicated circuits, achieving efficient zero-knowledge proof generation. GPUs have a large number of simple computing units dedicated to parallel computing, capable of performing a large number of similar computing tasks simultaneously, which is very effective for matrix operations, vector operations, and parallelized large number operations commonly found in zero-knowledge proofs. GPUs have a good programming environment, providing developers with friendly development tools and libraries, allowing developers to program in a high-level language similar to C++, which significantly reduces the learning curve for developing zero-knowledge proof algorithms, enabling more developers with diverse backgrounds to participate. Moreover, the GPU market is relatively mature, with rich driver support and development tools.

[0004] However, existing heterogeneous computing architectures for generating zero-knowledge proofs have the following limitations:

[0005] 1) FPGA design and implementation usually require deep knowledge of hardware description languages (such as Verilog or VHDL) and a deep understanding of hardware logic design principles. This results in a high technical threshold and learning cost, and for developers with a software background, it often takes a long time and effort to master FPGA development skills. In addition, circuit design on FPGA is usually highly customized, optimized for specific algorithms or applications. This specificity means that it is difficult to port designs between different application scenarios, requiring re-evaluation and adjustment of hardware configurations, increasing the development cycle and cost of projects.

[0006] 2) ASIC chips can be applied to the generation and verification of zero-knowledge proofs, which can significantly improve the efficiency of specific algorithms and reduce energy consumption, but also have some limitations. For example, poor flexibility: once the ASIC chip is designed, its circuit layout and function are fixed, which means it cannot easily adapt to new ZKP algorithms or parameter changes; high development cost: designing and manufacturing ASIC chips requires high upfront investment, including design costs, mask costs, and testing and production costs, which is not economical for smaller-scale applications or experimental ZKP schemes; long update cycle: the design and manufacturing cycle of ASIC is longer, if there is a major breakthrough or algorithm improvement in the ZKP field, ASIC cannot keep up with the times, leading to obsolescence.

[0007] 3) Although GPU has high-bandwidth video memory, ZKP computation may involve a large amount of data transfer, especially when data needs to be frequently exchanged between CPU and GPU, which will increase additional delay and overhead. Data transfer between host (CPU) and device (GPU) needs to go through PCIe bus, which is a bottleneck. For ZKP computation, if the algorithm requires a large amount of data exchange, this communication delay will significantly affect performance. Especially when ZKP involves complex interactive protocols, frequent data transfer will exacerbate the problem. In addition, not only is there a delay in the communication between GPU and the outside, but also in the data sharing and synchronization between different threads within the GPU. If the ZKP algorithm is poorly designed, resulting in unnecessary memory access patterns or excessive synchronization operations, it will also increase the computation delay.

[0008] In existing zero-knowledge proof generation libraries, such as the Bellman algorithm library, the architecture is often limited by the data transfer between CPU and GPU, causing performance bottlenecks. As shown in Figure 1, in the process of multiple scalar multiplication computation, it usually involves a large amount of point set and scalar set transfer between heterogeneous architectures. However, since GPU needs to wait for CPU to complete data transfer before starting computation, it leads to GPU being idle during the waiting period for data transfer to complete, thus affecting the overall computation efficiency.

[0009] In summary, the popularization and application of zero-knowledge proof technology still face high computing requirements, long generation cycle and high operating costs, which greatly hinder its wide application in blockchain architecture. Especially in the financial market and other environments with strict requirements for instant response, the generation and verification delay of zero-knowledge proof will directly threaten the privacy and robustness of transactions, and thus cause a series of negative effects, such as transaction delay, decreased trust and potential economic losses. It is worth noting that the frequent data exchange between the host and the graphics processing unit (GPU) often causes idle of computing resources, forming a bottleneck for performance improvement. Therefore, optimizing the communication mechanism between CPU and GPU and improving the memory access strategy have become the key strategies to improve the performance of zero-knowledge proof, aiming to greatly reduce the proof construction time.

[0010] SUMMARY

[0011] The purpose of the present application is to overcome the above-mentioned defects of the prior art and provide a CPU-GPU data processing and transmission optimization system and method for zero-knowledge proof.

[0012] According to a first aspect of the present application, a CPU-GPU data processing and transmission optimization system for zero-knowledge proof is provided for performing multi-scalar multiplication operation based on elliptic curve cryptography to realize the generation of zero-knowledge proof, the system comprising a CPU and a GPU, wherein a data transmission channel is provided between the CPU and the GPU, the CPU is configured to acquire and store a point set and a scalar set involved in the multi-scalar multiplication operation, and communicate with the GPU using a set parallel data transmission mechanism, the GPU performs multi-scalar multiplication calculation based on the point set and the scalar set, and returns the calculation result to the CPU.

[0013] According to a second aspect of the present application, a CPU-GPU data processing and transmission optimization method for zero-knowledge proof is provided. The method comprises the following steps:

[0014] The point set and the scalar set involved in the multi-scalar multiplication operation are stored in the CPU, the multi-scalar multiplication operation is a multi-scalar multiplication operation based on elliptic curve cryptography, and is used to realize the generation of zero-knowledge proof;

[0015] Data is transmitted between the CPU and the GPU using a set parallel data transmission mechanism to control the GPU to perform multi-scalar multiplication calculation based on the point set and the scalar set, and return the calculation result to the CPU.

[0016] Compared with the prior art, the application has the advantages that for the CPU-GPU heterogeneous architecture, an innovative parallel data transmission mechanism is proposed, the core of the parallel mechanism is to redesign the data flow, allowing the CPU to prepare data while the GPU immediately processes the transmitted part of the data, without waiting for all the data to be transmitted in one complete transmission. This design improves the throughput of zero-knowledge proof generation, reduces the idle period of the GPU, and through more efficient task scheduling, shortens the generation time of the proof, thereby realizing the effective improvement of the system performance and the reduction of the computing cost without increasing the hardware overhead. The application solves the problems of communication delay between CPU and GPU, data sharing and synchronization delay and the like.

[0017] Other features and advantages of the present application will become apparent from the following detailed description of illustrative embodiments thereof, which proceeds with reference to the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0018] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the application and, together with the description, serve to explain the principles of the application.

[0019] Fig. 1 is a Bellman execution graph of the prior art;

[0020] Fig. 2 is a CPU-GPU heterogeneous architecture diagram for zero-knowledge proof according to an embodiment of the application;

[0021] Fig. 3 is a shared pre-computed table update process diagram according to an embodiment of the application;

[0022] Fig. 4 is a calculation diagram of an elliptic curve according to an embodiment of the application;

[0023] Fig. 5 is a CPU-GPU transmission performance comparison diagram for zero-knowledge proof according to an embodiment of the application;

[0024] Fig. 6 is a zero-copy technology diagram according to an embodiment of the application. DETAILED DESCRIPTION

[0025] Various exemplary embodiments of the present application will now be described in detail with reference to the accompanying drawings. It should be noted that the relative arrangement of the components and steps set forth in these embodiments, numerical expressions, and numerical values are not limiting to the scope of the present application unless otherwise specifically stated.

[0026] The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way limiting to the scope of the application or its applications or uses.

[0027] Techniques, methods, and apparatus known to those of ordinary skill in the relevant art(s) can not be discussed in detail herein. However, where appropriate, the techniques, methods, and apparatus should be considered as being part of the description of the application.

[0028] In all of the compositions and methods shown and discussed herein, any particular value is to be construed merely as an example and not a limitation. Other examples of the exemplary embodiments can therefore have different values.

[0029] It should be noted that like reference numerals and letters refer to like items throughout the attached drawings, and once an item is defined in one drawing, it is not necessary that it be further discussed in subsequent drawings.

[0030] In the calculation process of zero-knowledge proof, efficient data transmission between CPU and GPU is crucial. Improving the efficiency of data transmission can greatly shorten the delay of data exchange between CPU and GPU, reduce the waiting time in the transmission process, thereby speeding up the generation and verification speed of zero-knowledge proof, and can provide users with a more smooth and efficient service experience under the premise of ensuring high security and privacy, meet the growing demand for big data processing and complex computing.

[0031] The CPU-GPU data processing and transmission optimization system for zero-knowledge proof provided by the application is a CPU-GPU heterogeneous architecture, as shown in FIG. 2. CPU (Central Processing Unit) is the main computing unit of the computer, for example, including controller, ALU (Arithmetic Logic Unit), cache, memory, etc. CPU is responsible for controlling and coordinating the operation of the system, including but not limited to running the operating system, managing memory and I / O devices. In the context of ZKP, CPU is usually responsible for processing non-parallel logical processes, such as initialization, data preparation, result aggregation, etc., as well as necessary data preprocessing and post-processing work before and after GPU (Graphics Processing Unit) calculation. GPU was originally designed for graphics rendering, but due to its powerful parallel computing capability, it has been widely used in scientific computing, machine learning and cryptography fields. GPU is composed of multiple stream processors (SM), each of which adopts single instruction multiple thread parallel processing mode, supporting thousands of synchronous threads co-resident in GPU main memory. This makes GPU have high parallelism, especially suitable for processing large-scale operation tasks without data dependency, such as the operation operations required in zero-knowledge proof. In the context of zero-knowledge proof, GPU is mainly used to perform a large number of parallel mathematical operations, such as matrix multiplication, modular operation, polynomial operation, etc., which are the most time-consuming part of the generation and verification process of zero-knowledge proof.

[0032] Overall, the system architecture of the present invention focuses on optimizing the communication architecture and memory architecture, which are crucial for improving the efficient data transmission of zero-knowledge proof (ZKP) between CPU and GPU. For the communication structure, a high-speed data transmission channel such as PCIe (Peripheral Component Interconnect Express) is needed between CPU and GPU. The optimized system will use more efficient transmission protocols and hardware to achieve intelligent scheduling and optimization of data flow, ensuring efficient data flow between CPU and GPU, reducing unnecessary data duplication and waiting time, and ensuring that data transmission does not become a bottleneck of the entire system performance. For the memory architecture, the system usually contains two types of memory, CPU memory and GPU memory. To improve efficiency, data needs to be intelligently managed and scheduled between these memory spaces to minimize data duplication and transmission during computation.

[0033] For the performance bottleneck in the generation of zero-knowledge proof, an innovative high-performance computing framework is proposed, which focuses on optimizing data transmission and preprocessing mechanisms. This framework aims to significantly improve the execution efficiency of zero-knowledge proof algorithms, while ensuring reasonable use of resources, enhancing the overall performance and security of the system. In the following, the implementation of the optimized preprocessing mechanism and data transmission mechanism will be introduced.

[0034] First, optimize the preprocessing mechanism

[0035] 1. Shared pre-computation table

[0036] Pre-computation table (Precomputation Table) is a data structure used to pre-compute and store the results of specific functions or operations that are frequently used in subsequent calculations. By creating such a table before the start of the calculation or in the early stages of the computation-intensive task, a portion of the computation-intensive workload can be transferred to the preprocessing phase. This method can significantly reduce the cost of online or real-time computation and improve computational efficiency.

[0037] Shared pre-computation table is an optimization technique used in the context of multiple scalar multiplication (MSM) on elliptic curve cryptography (ECC) to reduce computation time and storage requirements. Shared pre-computation table is an effective method to speed up subsequent multiple scalar multiplication calculations by pre-computing and storing multiples of points on an elliptic curve. This method is particularly useful when dealing with multiple related points, as it allows these points to share the same optimized table, thereby reducing redundant calculations and storage burden.

[0038] The basic idea of shared pre-computation table is: assuming there is a set of points {P1, P2,..., Pn} on an elliptic curve, where n is the number of points. The pre-computation table will store the result of each point multiplied by a certain scalar value, such as 2, 3, 5, etc. nand these points all lie in the same subgroup of the elliptic curve. This means that for any point P i and P j there exists some integer k such that P i = k - P j or P j = k - P i . If a base point G can be found, which is a generator of all points, i.e. all P i = k i - G, then only the multiples of the base point G can be pre-computed and these multiples can be used to speed up the scalar multiplication of any point P i .

[0039] In one embodiment, the step of implementing multi-scalar multiplication using a shared pre-computation table comprises:

[0040] S1, selecting a base point: find a suitable base point G which generates a subgroup containing all P i .

[0041] Typically, G is a generator of a large prime order on the elliptic curve.

[0042] S2, constructing a pre-computation table: pre-compute the sequence of multiples of G.

[0043] For example, pre-compute the sequence of multiples of G as G, 2G, 3G,..., IG, where / is the maximum length of the pre-computation table, typically 2 w where w is the window size of the split window phase in the Pippenger (bucket) algorithm.

[0044] S3, optimizing the scalar multiplication.

[0045] For example, for each point P i = k i - G, the scalar multiplication can be sped up by looking up the appropriate value in the pre-computation table. In particular, if k i can be factored in binary as k i = b0+ bi - 2 w + b2- 2 2w +..., where b j are w-bit binary digits, then the points G, 2 w G, 2 2w G,... in the pre-computation table can be used and P i is obtained by point addition and doubling operations.

[0046] The storage core of the pre-computation table mainly lies in the well-selected multiple sets of the base point G and the storage of the scalar relationship between each point in the point set and G. These multiples constitute the basic components for quickly constructing the result of arbitrary scalar multiplication. By pre-computing a series of multiple points of the base point G and storing them, the subsequent large-scale scalar multiplication operation can be significantly accelerated, because many common multiplications can be decomposed into simple combinations of pre-computed points, reducing the need for real-time calculation. In addition, in order to reduce the storage overhead of the pre-computation table, coordinate compression technology can be adopted, that is, only the x coordinate of the point is stored, and the y coordinate can be calculated according to the elliptic curve equation when needed, realizing the effective utilization of storage space.

[0047] In order to cope with different situations and performance requirements, in an embodiment, the set pre-computation table will also be updated regularly, including but not limited to adding deeper pre-computed points to adapt to the Pippenger algorithm of larger window size, or updating the algorithm to improve efficiency.

[0048] Figure 3 is the updating process of the pre-computation table. At the beginning of the calculation, a certain amount of storage space is reserved in the pre-computation table for storing the pre-computed point sets. These point sets are usually carefully selected according to the expected calculation requirements, so as to cover as many cases as possible in the subsequent calculation process. When the point set to be solved is encountered during the calculation process, it is first tried to find out whether there is a corresponding calculated result in the pre-computation table. If there is, the result can be directly obtained from the table without the need for complex calculation again, thereby saving a lot of calculation time and resources; if there is not, the point set is recalculated and the calculation result is returned to the GPU. As the calculation progresses, the contents in the pre-computation table will also change. When new calculation results are generated, it needs to be decided whether to add them to the pre-computation table. If there is still enough space left in the pre-computation table, the newly generated point set result will be directly inserted into the table for subsequent query and use. Through this design, the future calculation burden can be further reduced and the calculation efficiency can be improved. However, when the space of the pre-computation table is insufficient, an effective strategy is adopted to manage the contents in the table. Considering that the calculation of the point set has obvious temporal locality, i.e. the point set that has been accessed recently is likely to be accessed again in the future, in an embodiment, the Least Recently Used (LRU) strategy is used to update the contents of the pre-computation table. The LRU algorithm is a replacement algorithm, whose basic idea is to preferentially eliminate those items that have not been used for the longest time, so as to keep the contents stored in the table are the most representative and most frequently used point sets. In this way, the value of the pre-computation table can be maximized, so that it is always in the optimal state to meet the current calculation requirements.

[0049] Meanwhile, with the update of the pre-computation table, the point set relational database designed by the pre-computation table will also be checked and updated synchronously to ensure that all points dependent on the pre-computation table can be correctly mapped to the latest point set to maintain the accuracy and efficiency of the calculation. Finally, in the selection of data structures, in order to efficiently manage the points and their scalar relationships in the pre-computation table, for example, a hash table is used to store the scalar values of the base points, ensuring an average search time of O(1), i.e. the time required to search for the scalar value of a point is constant regardless of the size of the data set. Through this strategy, the pre-computation table not only significantly improves the computational efficiency of the multi-scalar multiplication in elliptic curve cryptography, but also effectively manages storage resources to ensure the security and reliability of the system.

[0050] 2. Signed window method

[0051] In combination with FIG. 4, in elliptic curve cryptography, the negative operation of a point exhibits a significant computational efficiency advantage compared to point addition or point doubling, which is mainly due to the simplified mathematical operation requirement. Specifically, in elliptic curve cryptography, the negative point -P of a point P usually refers to the point on the elliptic curve that is symmetric with P about the x-axis. In the mathematical representation of most elliptic curves, calculating the negative point of a point is a very simple operation because it only involves changing the sign of the y-coordinate. Without the need to perform complex modulo operations, multiplicative inverse calculations or square root solutions, etc. Therefore, in an embodiment, the computational amount of multi-scalar multiplication is reduced according to the easy way of taking the sign of the elliptic curve, and the generation efficiency of zero-knowledge proof is improved.

[0052] In contrast, point addition or point doubling not only involves polynomial calculation, but often needs to solve the multiplicative inverse, which is a relatively time-consuming task in a finite field. Therefore, the present application introduces it into the multi-scalar multiplication and point multiplication calculation, and in view of the high efficiency of the negative operation, it can significantly reduce the consumption of computing resources and improve the overall operation speed, providing an important performance optimization approach for the application of elliptic curve cryptography. In the traditional Pippenger unsigned window method, the window value range is [0, 2 c-1 ], which may require up to 2 c different values to be processed for each window. After introducing the signed window, the range of window values becomes [-2 c-1 , 2 c-1 -1]. This not only narrows the absolute range of window values, but also allows the use of the negative representation of points, i.e. the negation of points, to replace part of the point multiplication operation, thereby reducing the number of window values that need to be handled separately.

[0053] In an embodiment, the step of converting the scalar k into a signed sliding window code includes:

[0054] Step S21, determining the window size

[0055] For example, a window size c is chosen. The window size determines how many bits are in each window.

[0056] Step S2, express the scalar k in binary form to obtain a binary string.

[0057] For example, if k = 23, its binary form is 10111.

[0058] Step S3, divide the binary string into windows.

[0059] The binary string is divided into windows of length c bits. For example, for c = 3, 10111 is divided into 010 and 111. It should be understood that in order to form a complete window, 0s are added in front of the highest bit in some cases.

[0060] Step S4, convert the window values into decimal numbers.

[0061] For example, 010 is converted to 2, and 111 is converted to 7.

[0062] Step S5, signed conversion

[0063] For each window value v, if v > 2 c-1 - 1, subtract 2 c from v to make it a signed number. For example, if c = 3, the range of window values should be [-4, 3]. If the window value is 5 or greater, it is converted to the equivalent negative number. For example, 5 is converted to -3 because 5 - 8 = -3.

[0064] Step S6, adjust the subsequent window

[0065] If the value of the current window changes from positive to negative (i.e. 2 c is subtracted from it), the value of the next window needs to be increased by 1 to maintain the equivalence of scalar multiplication.

[0066] In elliptic curve arithmetic, point addition and point doubling are the most basic and most expensive operations. The signed window method reduces the absolute size of the window value by allowing the use of negative points, thereby more frequently utilizing the negated form of points in the multi-scalar multiplication (MSM) process, improving computational efficiency. By taking advantage of this efficient feature, the number of complex point operations is significantly reduced, the consumption of computing resources is reduced, the computational efficiency is improved, and the efficiency and correctness of the calculation are ensured even when a smaller window size is used.

[0067] Second, optimize the data transmission mechanism

[0068] 1. Asynchronous data transmission mechanism

[0069] The core value of asynchronous data transmission lies in breaking the inherent boundary between data transmission and computing tasks, making it possible for both to proceed in parallel. Specifically, when data is being copied from the CPU to the GPU, the GPU does not stall, but instead can continue processing existing data sets and performing computing tasks. This mechanism not only significantly shortens the idle period of the GPU, but also greatly improves the utilization of hardware resources through the overlap of data transmission and computation.

[0070] To achieve this optimization in the data transmission part of zero-knowledge proof generation, in one embodiment, a point set-based batch transmission strategy is proposed. The key to this strategy lies in fine performance evaluation and data management. First, a large data set is divided into several small batches, and the size of each batch is evaluated based on the performance of the GPU to ensure that the GPU has enough workload after receiving the data, while avoiding waiting time during data transmission. The purpose of this strategy is to keep the GPU active at all times, fully utilizing its computing power and avoiding performance waste due to data transmission.

[0071] In addition, in the process of data processing, after each batch of data is calculated, the GPU immediately returns the results to the CPU, rather than waiting for all data processing to be completed before summarizing. This immediate feedback mechanism allows the CPU to timely reduce and integrate sub-tasks, preparing for the next step of computation, further accelerating the entire computing process. Furthermore, to address the storage needs of large-scale data sets while reducing storage costs, the strategy also emphasizes effective memory management. Once a data set or part of its elements is no longer involved in computation, the occupied memory space is immediately released, ensuring efficient use of resources.

[0072] In summary, by implementing an asynchronous data transmission strategy, combined with point set-based batch processing and immediate feedback mechanisms, as well as dynamic memory management strategies, the efficiency of CPU and GPU working together can be significantly improved. This overlapping computation and data transmission method not only reduces the waiting time of the GPU, but also optimizes memory usage, providing strong technical support for processing large-scale data sets, especially in computationally intensive tasks such as the generation and verification of zero-knowledge proofs (ZKP), showing great potential and advantages. Compared to the original zero-knowledge generation system, as shown in Figure 1, Figure 5 shows that the CPU has improved by 4 time blocks, and the GPU has also improved by two time blocks, and as the data volume increases, the optimization method proposed in this invention will also have more obvious advantages in improving the efficiency of CPU and GPU.

[0073] 2. Zero-copy technology

[0074] Zero-copy technology refers to a series of methods and strategies designed to minimize or completely eliminate data replication operations when data is transferred between different software layers or hardware components. By reducing the number of data copies, zero-copy technology can significantly improve system performance, reduce latency, and reduce CPU and memory bandwidth consumption, thereby improving the overall efficiency of the system. In the process of zero-knowledge proof computing multiple scalar multiplications, efficient data transmission between CPU and GPU is a key factor in improving overall system performance. Traditionally, data needs to be explicitly copied from CPU memory to GPU device memory, which not only increases the burden on the CPU, but also causes significant delay and bandwidth consumption on large-scale data sets. To solve these problems, the present invention introduces zero-copy technology on the premise of implementing a multi-batch asynchronous transmission mechanism.

[0075] Zero-copy technology is an asynchronous memory mapping method that directly maps fixed (non-pageable) host memory to GPU memory and implicitly transfers it to the GPU. This technology allows GPU threads to directly access host memory. When a GPU thread reads a variable mapped to the host, it will submit a PCIe read transaction, and the host will return the data through the PCIe bus. The core principle of zero-copy technology is to reduce or eliminate the number of data copies between different memory regions, especially during data transmission between CPU and GPU. In traditional data transmission processes, data usually needs to be copied from host memory to kernel buffer, and then from kernel buffer to GPU device memory. This series of copy operations consumes a large number of CPU cycles and memory bandwidth. In contrast, zero-copy technology allows data to be directly transmitted from host memory to GPU device memory without the need for intermediate copy steps, thereby significantly reducing CPU intervention and data transmission latency.

[0076] In traditional CUDA programming, data must be explicitly copied from host memory to GPU device memory using APIs such as cudaMemcpy. This process not only increases additional latency, but also occupies CPU resources. In contrast, as shown in Figure 6, the present invention will implement the CUDA Unified Virtual Addressing (UVA) function in the CUDA environment to achieve a similar zero-copy effect. After implementing the UVA function, CPU and GPU share a unified virtual address space. This means that both CPU and GPU can use the same virtual address to access data without knowing which physical memory region (CPU memory or GPU memory) the data is actually stored in. UVA allows GPU to directly access host memory without the need to explicitly copy data to GPU device memory. This simplifies data management and speeds up data transmission.

[0077] In summary, the present application significantly improves the speed and efficiency of ZKP generation through the synergistic effect of multiple technical points, while optimizing resource usage, providing strong support for zero-knowledge proof technology in high-performance computing environments. Compared with the prior art, the advantages of the present application mainly lie in the following aspects:

[0078] 1) The present application introduces an innovative preprocessing mechanism, which builds an efficient computing framework by utilizing CPU to perform key computing tasks in advance, significantly shortening the time of ZKP generation, especially in processing large-scale data sets. For example, through the design of shared pre-computation table, effective use of computing resources is achieved, and through caching intermediate data of complex operations, repeated calculations are avoided, reducing the calculation time and energy consumption when processing large-scale data sets or high-complexity algorithms, especially in multi-scalar multiplication calculations. For example, in view of the low cost of elliptic curve negation, a signed window technology is designed for multi-scalar multiplication operation, which reduces the number of point multiplication in actual operation by extending the operand, reducing the complexity of large number multiplication in elliptic curve cryptography. This signed sliding window technology reduces the number of point multiplications required for large number multiplication in elliptic curve cryptography by extending the operand and optimizing the operand processing, directly accelerating the generation process of zero-knowledge proof.

[0079] 2) The present application provides an optimization scheme for the generation speed of zero-knowledge proof systems, without the need to reconstruct the original proof generation logic, but focusing on optimizing the communication efficiency between heterogeneous computing platforms, by improving the data transmission mechanism between CPU and GPU, effectively reducing the generation delay and greatly improving the system performance. For example, the transmission mode between the improved system is changed, and through the zero-copy transmission technology, the data exchange process is realized when processing and transmitting data, which can realize faster and resource-saving data exchange process. This zero-copy transmission technology realizes the optimization in the data processing and transmission process, not only greatly reduces the processing burden of CPU and reduces the consumption of memory bandwidth, but also greatly shortens the data transmission delay, so as to realize the acceleration of data processing and the significant improvement of overall system performance. For another example, by improving the transmission mode of data between heterogeneous architectures, implementing batch transmission strategy, realizing the progressive delivery of point set and scalar set to GPU, avoiding the idle waiting period of GPU, ensuring the continuous use of GPU resources, so as to significantly improve the resource utilization and overall efficiency in the process of zero-knowledge proof generation. This design not only significantly improves the utilization rate of GPU, but also greatly optimizes the overall computing efficiency, especially when processing large-scale data sets, this progressive delivery mechanism greatly reduces the waiting time and promotes the continuous and maximum utilization of resources, so as to realize the leap of system performance. This decoupled data delivery strategy makes CPU and GPU work cooperatively rather than alternately, so as to ensure the continuous use of GPU resources.

[0080] 3) The present application has been tested many times, and the experiment proves that it can meet the expected design indicators. For example, by using the parallel computing capability of CPU, a series of key computing tasks are preformed, and a pre-computation table is constructed, which makes it possible to directly reference these pre-computed results when generating zero-knowledge proof, avoiding repeated calculation and greatly compressing the time required for generating proof.

[0081] The present application can be a system, a method, and / or a computer program product. The computer program product can include a computer readable storage medium having computer readable program instructions loaded thereon for causing a processor to implement various aspects of the present application.

[0082] Computer readable storage media can be tangible storage media which can retain and store instructions for use by an instruction execution device. Computer readable storage media can be, for example, but is not limited to, electronic storage media, magnetic storage media, optical storage media, electromagnetic storage media, semiconductor storage media, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of computer readable storage media include the following: a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanically encoded device such as punch-cards or raised structures in a groove having instructions recorded thereon, and any suitable combination of the foregoing. A computer readable storage medium, as used herein, is not to be construed as being transitory signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission media (e.g., light pulses passing through a fiber-optic cable), or electrical signals transmitted through a wire.

[0083] Computer readable program instructions described herein can be downloaded to respective computing / processing devices from a computer readable storage medium or to an external computer or external storage device via a network, for example, the Internet, a local area network, a wide area network and / or a wireless network. The network can comprise copper transmission cables, optical transmission fibers, wireless transmission, routers, firewalls, switches, gateway computers and / or edge servers. A network adapter card or network interface in each computing / processing device receives computer readable program instructions from the network and forwards the computer readable program instructions for storage in a computer readable storage medium within the respective computing / processing device.

[0084] Computer readable program instructions for carrying out operations of the present application can be assembler instructions, instruction-set-architecture (ISA) instructions, machine instructions, machine dependent instructions, microcode, firmware instructions, state-setting data, or either source code or object code written in any combination of one or more programming languages, including an object oriented programming language such as Smalltalk, C++ or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The computer readable program instructions can execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer can be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection can be made to an external computer (for example, through the Internet using an Internet Service Provider). In some embodiments, electronic circuitry including, for example, programmable logic circuitry, field-programmable gate array (FPGA), or programmable logic array (PLA) can execute the computer readable program instructions by utilizing state information of the computer readable program instructions to personalize the electronic circuitry, in order to perform aspects of the present application.

[0085] The computer readable program instructions can also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus or other device to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide processes for implementing the functions / acts specified in the flowchart and / or block diagram block or blocks.

[0086] The computer readable program instructions can also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus or other device to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide processes for implementing the functions / acts specified in the flowchart and / or block diagram block or blocks.

[0087] The computer readable program instructions can also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable data processing apparatus or other device to produce a computer implemented process such that the instructions which execute on the computer, other programmable data processing apparatus, or other device implement the functions / acts specified in the flowchart and / or block diagram block or blocks.

[0088] The flow diagrams and the block diagrams in the drawings are presented to illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present application. In this regard, each block in the flow diagrams and the block diagrams can represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logic functions. In some alternative implementations, the functions noted in the blocks can occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks can sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and / or flow diagrams, and combinations thereof, can be implemented by special purpose hardware-based systems that perform the specified functions or acts, or combinations of special purpose hardware and

[0089] Embodiments of the application have been described above, and the description is intended to be illustrative of the embodiments of the application and not exhaustive. Numerous modifications and adaptations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The scope of the application is defined by the appended claims.

Claims

1. A CPU-GPU data processing and transmission optimization system for zero-knowledge proof, configured to perform multi-scalar multiplication operation based on elliptic curve cryptography to realize generation of zero-knowledge proof, the system comprising a CPU and a GPU, wherein a data transmission channel is provided between the CPU and the GPU, the CPU is configured to acquire and store a point set and a scalar set involved in the multi-scalar multiplication operation, and communicate with the GPU by using a set parallelized data transmission mechanism, the GPU is configured to perform calculation of multi-scalar multiplication based on the point set and the scalar set, and return the calculation result to the CPU.

2. The system of claim 1, wherein, The GPU performs the multi-scalar multiplication operation by using a shared pre-computed table, the shared pre-computed table is configured to store a series of multiple points of a base point G, and store scalar relationships between points in each point set and the base point G, the base point G is a generator of all points in the point set.

3. The system of claim 1, wherein, The GPU realizes the multi-scalar multiplication operation based on a bucket algorithm, in the bucket algorithm, the scalar k is converted into a signed sliding window by the following way: determining a window size c, the window size c is configured to limit how many bits in each window; expressing the scalar k in binary form to form a binary string; dividing the binary string into multiple windows according to the length of c bits to obtain multiple window values; converting the window values into decimal numbers to obtain the window values in decimal form; For each decimal window value v, if v > 2 c-1 - 1, subtract 2 from v c making it a signed number; if the value of the current window changes from positive to negative, then add 1 to the value of the next window to maintain the equivalence of the scalar multiplication.

4. The system of claim 2, wherein, The shared pre-computed table is configured to be updated periodically according to the following steps: at the beginning of the calculation, reserving a set number of storage spaces in the shared pre-computed table for storing the pre-computed point set; during the calculation, for a point set to be solved, searching the shared pre-computed table to check whether there is a corresponding calculated result, if there is, obtaining the result from the table, if there is not, recalculating the point set and returning the calculation result to the GPU; when a new point set result is generated, if the shared pre-computed table still has enough remaining space, inserting the newly generated point set result into the table, when the shared pre-computed table is insufficient, using a set update strategy to update the storage content in the table.

5. The system of claim 4, wherein, The update strategy adopts a least recently used strategy to preferentially eliminate the item that has not been used for the longest time.

6. The system of claim 1, wherein, The parallelized data transmission mechanism is based on a batch transmission strategy of the point set, comprising: for the point set stored in the CPU, dividing the point set into several batches according to the performance of the GPU, and transmitting the point set to the GPU in batches; after the GPU obtains the calculation result of each batch, immediately returning the calculation result of the batch to the CPU, and releasing the memory space occupied by the elements that no longer participate in the calculation.

7. The system of claim 1, wherein, During the execution of the multi-scalar multiplication operation, the CPU and the GPU share a unified virtual address space to realize the transmission of data between the CPU and the GPU by using zero-copy technology.

8. The system of claim 1, wherein, In the shared pre-computed table, a hash table is used to store the scalar value of the base point G, and for the points in the point set, only the x coordinate of the point is stored. 9.A CPU-GPU data processing and transmission optimization method for zero-knowledge proof, comprising the following steps: The point set and the scalar set involved in a multi-scalar multiplication operation based on elliptic curve cryptography are stored in a CPU, and the multi-scalar multiplication operation is used to implement generation of zero-knowledge proof; Data is transmitted between the CPU and the GPU by using a set parallelization data transmission mechanism to control the GPU to perform multi-scalar multiplication calculation based on the point set and the scalar set, and the calculation result is transmitted back to the CPU.

10. A computer readable storage medium having stored thereon a computer program, wherein, The computer program is executed by a processor to implement the steps of the method according to claim 9.

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