Gate drive circuit, display panel and display device

Abstract

The invention relates to the technical field of display, and discloses a gate drive circuit, a display panel and a display device.The gate drive circuit comprises a shifting register unit and a level control unit, and the shifting register unit comprises a scanning shifting register and a virtual shifting register; the level control unit is electrically connected with a first scanning input signal line and a second scanning input signal line of the scanning shift register and the virtual shift register, and is configured to input different signals to the first scanning input signal line and the second scanning input signal line under the driving of different control signals. In this way, after transistors used for frame reset in the scanning shift register and the virtual shift register are removed, frame reset processing is performed on the scanning shift register and the virtual shift register in combination with different conduction conditions of the level control unit, so that the number of tubes in the gate drive circuit is reduced, the cost is saved, and the reliability of the gate drive circuit is improved. And the panel yield is improved.

Description

Technical Field

[0001] The present application relates to the field of display technologies, and provides a gate driving circuit, a display panel, and a display device. Background Art

[0002] In the field of display technologies, a gate driving circuit is often used to replace a gate management chip IC to provide a scanning signal for a display panel, thereby reducing the cost of the circuit. Moreover, in order to solve the display inversion problem during the display process of the display panel, the above-mentioned gate driving circuit often adopts a bidirectional scanning method. The above-mentioned gate driving circuit usually includes three shift registers, namely, a dummy Gate driver On Array (dummy GOA1), a Normal Gate driver On Array (Normal GOA), and a dummy Gate driver On Array (dummy GOA2). For the specific circuit, refer to Figure 1 、 Figure 2 and Figure 3 As shown, the shift register structure in the gate driving circuit is relatively complex, which further leads to a high cost of the display panel and a poor panel yield. Summary of the Invention

[0003] Embodiments of the present application provide a gate driving circuit, a display panel, and a display device, which are used to perform frame reset processing on a scanning shift register and a dummy shift register in combination with different conduction conditions of a level control unit, thereby reducing the number of transistors in the gate driving circuit, saving costs, and improving the panel yield.

[0004] The specific technical solutions provided by the present application are as follows:

[0005] In a first aspect, an embodiment of the present application provides a gate driving circuit, including: a shift register unit and a level control unit;

[0006] The shift register unit includes a scanning shift register and a dummy shift register. The scanning shift register is electrically connected to a gate line and is configured to input a scanning driving signal to the gate line according to signals of a first scanning input signal line and a second scanning input signal line. The dummy shift register is electrically connected to the scanning shift register and is configured to input a cascading driving signal to the scanning shift register according to signals of the first scanning input signal line and the second scanning input signal line;

[0007] A level control unit is electrically connected to the first scan input signal lines and the second scan input signal lines of the scan shift register and the virtual shift register respectively, and is configured to, in response to a first control signal, write a first scan control signal to the first scan input signal lines of the scan shift register and the virtual shift register, write a second scan control signal to the second scan input signal lines of the scan shift register and the virtual shift register, in response to a second control signal, write the second scan control signal to the first scan input signal lines and the second scan input signal lines of the scan shift register and the virtual shift register, and, in response to a third control signal, write the first scan control signal to the first scan input signal lines and the second scan input signal lines of the scan shift register and the virtual shift register.

[0008] Optionally, the level control unit includes: a first control subunit, a second control subunit, and a third control subunit;

[0009] The control terminal of the first control subunit is electrically connected to the first control signal line, the first end of the first control subunit is electrically connected to the first transmission line, and the second end of the first control subunit is electrically connected to the second transmission line;

[0010] The first control subunit is configured to conduct the first transmission line and the second transmission line in response to a valid level signal of the first control signal line;

[0011] The control terminal of the second control subunit is electrically connected to the second control signal line, the first end of the second control subunit is electrically connected to the first transmission line, and the second end of the first control subunit is electrically connected to the first scan control signal;

[0012] The second control subunit is configured to write the first scan control to the first transmission line in response to a valid level signal of the second control signal line;

[0013] The control terminal of the third control subunit is electrically connected to the third control signal line, the first end of the third control subunit is electrically connected to the second transmission line, and the second end of the third control subunit is electrically connected to the second scan control signal;

[0014] The third control subunit is configured to write the second scan control to the second transmission line in response to a valid level signal of the third control signal line.

[0015] Optionally, the first scan input signal lines of the scan shift register and the virtual shift register are electrically connected to the first transmission line, and the second scan input signal lines of the scan shift register and the virtual shift register are electrically connected to the second transmission line;

[0016] The first control signal causes the first control signal line to provide an invalid level signal, the second control signal line to provide a valid level signal, and the third control signal line to provide a valid level signal;

[0017] The second control signal causes the first control signal line to provide an active-level signal, the second control signal line to provide an inactive-level signal, and the third control signal line to provide an active-level signal;

[0018] The third control signal causes the first control signal line to provide an active-level signal, the second control signal line to provide an active-level signal, and the third control signal line to provide an inactive-level signal.

[0019] Optionally, the first control subunit includes: a first transistor, the control terminal of the first transistor is electrically connected to the first control signal line, the first terminal of the first transistor is electrically connected to the first transmission line, and the second terminal of the first transistor is electrically connected to the second transmission line.

[0020] Optionally, the second control subunit includes: a second transistor, the control terminal of the second transistor is electrically connected to the second control signal line, the first terminal of the second transistor is electrically connected to the first scan control signal, and the second terminal of the second transistor is electrically connected to the first transmission line.

[0021] Optionally, the third control subunit includes: a third transistor, the control terminal of the third transistor is electrically connected to the third control signal line, the first terminal of the third transistor is electrically connected to the second transmission line, and the second terminal of the third transistor is electrically connected to the second scan control signal.

[0022] Optionally, the shift register unit includes a plurality of scan shift registers, and the plurality of scan shift registers are cascaded;

[0023] The virtual shift register includes a first virtual shift register. The first input signal line of the first virtual shift register is electrically connected to the frame start signal line. The second input signal line of the first virtual shift register is electrically connected to the cascade signal output terminal of the first scan shift register among the plurality of scan shift registers. The cascade output signal line of the first virtual shift register is electrically connected to the first input signal line of the first scan shift register.

[0024] Optionally, the shift register unit includes a plurality of scan shift registers, and the plurality of scan shift registers are cascaded;

[0025] The virtual shift register includes a second virtual shift register. The first input signal line of the second virtual shift register is electrically connected to the cascade signal output terminal of the last scan shift register among the plurality of scan shift registers. The second input signal line of the second virtual shift register is electrically connected to the frame start signal line. The cascade output signal line of the second virtual shift register is electrically connected to the second input signal line of the last scan shift register.

[0026] Optionally, the scan shift register includes:

[0027] A first input module, configured to provide the signal of a first scan input signal line to a pull-up node in response to the signal of a first input signal line;

[0028] A second input module, configured to provide the signal of a second scan input signal line to the pull-up node in response to the signal of a second input signal line;

[0029] A first node control module, configured to control the signals of the pull-up node and the pull-down node;

[0030] A first cascaded output module, configured to provide the signal of a cascaded clock signal line to a cascaded signal output terminal in response to the signal of the pull-up node; or, provide the signal of a first reference signal line to the cascaded signal output terminal in response to the signal of the pull-down node;

[0031] A first drive output module, configured to provide the signal of a clock signal line to a drive output terminal in response to the signal of the pull-up node; or, provide the signal of a second reference signal line to the drive output terminal in response to the signal of the pull-down node.

[0032] Optionally, the first input module includes: a fourth transistor;

[0033] The control end of the fourth transistor is electrically connected to the first input signal line, the first end of the fourth transistor is electrically connected to the first scan input signal line, and the second end of the fourth transistor is electrically connected to the pull-up node.

[0034] Optionally, the second input module includes: a fifth transistor;

[0035] The control end of the fifth transistor is electrically connected to the second input signal line, the first end of the fifth transistor is electrically connected to the pull-up node, and the second end of the fifth transistor is electrically connected to the second scan input signal line.

[0036] Optionally, further includes: a frame reset module, and the frame reset module is electrically connected to the pull-up node;

[0037] The frame reset module is configured to provide the signal of the first reference signal line to the pull-up node in response to the signal of a frame start signal line.

[0038] Optionally, the frame reset module includes: a sixth transistor;

[0039] The control end of the sixth transistor is electrically connected to the frame start signal line, the first end of the sixth transistor is electrically connected to the pull-up node, and the second end of the sixth transistor is electrically connected to the first reference signal line.

[0040] Optionally, the virtual shift register includes:

[0041] A third input module, configured to provide the signal of the first scan input signal line to the pull-up node in response to the signal of the first input signal line;

[0042] A fourth input module, configured to provide the signal of the second scan input signal line to the pull-up node in response to the signal of the second input signal line;

[0043] A second node control module, configured to control the signals of the pull-up node and the pull-down node;

[0044] A second cascaded output module, configured to provide the signal of the cascaded clock signal line to the cascaded output signal line in response to the signal of the pull-up node; or, provide the signal of the first reference signal line to the cascaded output signal line in response to the signal of the pull-down node;

[0045] A second drive output module, configured to provide the signal of the clock signal line to the drive output terminal in response to the signal of the pull-up node; or, provide the signal of the second reference signal line to the drive output terminal in response to the signal of the pull-down node.

[0046] Optionally, the third input module includes: a seventh transistor;

[0047] The control terminal of the seventh transistor is electrically connected to the first input signal line, the first terminal of the seventh transistor is electrically connected to the first scan input signal line, and the second terminal of the seventh transistor is electrically connected to the pull-up node.

[0048] Optionally, the fourth input module includes: an eighth transistor;

[0049] The control terminal of the eighth transistor is electrically connected to the second input signal line, the first terminal of the eighth transistor is electrically connected to the pull-up node, and the second terminal of the eighth transistor is electrically connected to the second scan input signal line.

[0050] Optionally, a compensation module is further included, and the compensation module is electrically connected to the pull-up node;

[0051] The compensation module is configured to provide a high-level compensation signal to the pull-up node in response to the signal of the compensation signal line.

[0052] Optionally, the compensation module includes a twenty-seventh transistor, a twenty-eighth transistor, a twenty-ninth transistor, and a fourth capacitor;

[0053] The control terminal of the twenty-seventh transistor is electrically connected to the compensation signal line, the first terminal of the twenty-seventh transistor is electrically connected to the cascaded signal output terminal, and the second terminal of the twenty-seventh transistor is electrically connected to the control terminal of the twenty-eighth transistor;

[0054] The first terminal of the twenty-eighth transistor is electrically connected to the compensation clock signal line, and the second terminal of the twenty-eighth transistor is electrically connected to the first terminal of the twenty-ninth transistor;

[0055] The control terminal of the twenty-ninth transistor is electrically connected to the compensation clock signal line, and the second terminal of the twenty-ninth transistor is electrically connected to the pull-up node;

[0056] The first terminal of the fourth capacitor is electrically connected to the control terminal of the twenty-eighth transistor, and the second terminal of the fourth capacitor is electrically connected to the first reference signal line.

[0057] Optionally, it further includes an auxiliary compensation module, and the auxiliary compensation module includes a thirtieth transistor and a thirty-first transistor;

[0058] The control terminal of the thirtieth transistor is electrically connected to the compensation clock signal line, the first terminal of the thirtieth transistor is electrically connected to the pull-down node, and the second terminal of the thirtieth transistor is electrically connected to the first terminal of the thirty-first transistor;

[0059] The control terminal of the thirty-first transistor is electrically connected to the control terminal of the twenty-eighth transistor, and the second terminal of the thirty-first transistor is electrically connected to the first reference signal line.

[0060] In a second aspect, an embodiment of the present application further provides a display panel, including: a plurality of gate lines and the above-mentioned gate driving circuit;

[0061] The driving output terminal of a scan shift register in the gate driving circuit is electrically connected to one of the plurality of gate lines.

[0062] In a third aspect, an embodiment of the present application further provides a display device, including the above-mentioned display panel.

[0063] In a fourth aspect, an embodiment of the present application further provides a driving method for the above-mentioned gate driving circuit, including:

[0064] Scanning stage: The level control unit responds to the first control signal, conducts the first scan input signal line and the first scan control signal, conducts the second scan input signal line and the second scan control signal, the scan shift register responds to the signals of the first scan input signal line and the second scan input signal line to input a scan driving signal to the gate line, and the virtual shift register responds to the signals of the first scan input signal line and the second scan input signal line to input a cascade driving signal to the scan shift register;

[0065] Frame reset stage: The scan shift register resets its pull-up node in response to the frame start signal line, and the virtual shift register resets its pull-up node in response to the signal of the frame start signal line through the signals of the first scan input signal line and / or the second scan input signal line; wherein, the level control unit writes the second scan control signal to the first scan input signal line and the second scan input signal line of the scan shift register and the virtual shift register in response to the second control signal, or writes the first scan control signal to the first scan input signal line and the second scan input signal line of the scan shift register and the virtual shift register in response to the third control signal.

[0066] The beneficial effects of this application are as follows:

[0067] In summary, embodiments of this application provide a gate driving circuit, a display panel, and a display device. The gate driving circuit includes: a shift register unit and a level control unit. The shift register unit includes a scan shift register and a virtual shift register. The scan shift register is electrically connected to the gate line and is configured to input a scan driving signal to the gate line according to the signals of the first scan input signal line and the second scan input signal line. The virtual shift register is electrically connected to the scan shift register and is configured to input a cascade driving signal to the scan shift register according to the signals of the first scan input signal line and the second scan input signal line. The level control unit is electrically connected to the first scan input signal line and the second scan input signal line of the scan shift register and the virtual shift register respectively, and is configured to write the signal provided by the first scan control signal line to the first scan input signal line of the scan shift register and the virtual shift register and write the signal provided by the second scan control signal line to the second scan input signal line of the scan shift register and the virtual shift register in response to the first control signal, write the signal provided by the second scan control signal line to the first scan input signal line and the second scan input signal line of the scan shift register and the virtual shift register in response to the second control signal, and write the signal provided by the first scan control signal line to the first scan input signal line and the second scan input signal line of the scan shift register and the virtual shift register in response to the third control signal. After removing the transistors for frame reset in the scan shift register and the virtual shift register, the frame reset process of the scan shift register and the virtual shift register is performed by combining different conduction situations of the level control unit, thereby reducing the number of transistors in the gate driving circuit, saving costs, and improving the panel yield.

[0068] Other features and advantages of this application will be described in the subsequent specification, and part of them will become obvious from the specification, or will be understood by implementing this application. The objectives and other advantages of this application can be achieved and obtained by the structures specifically pointed out in the written specification, claims, and drawings. Description of the Drawings

[0069] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The schematic embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation of the present application. In the drawings:

[0070] Figure 1 is a schematic diagram of a dummy GOA1 in the related art;

[0071] Figure 2 is a schematic diagram of a Normal GOA in the related art;

[0072] Figure 3 is a schematic diagram of a dummy GOA2 in the related art;

[0073] Figure 4 is a schematic diagram of the electrical connection of a gate driving circuit in an embodiment of the present application;

[0074] Figure 5 is a schematic diagram of the electrical connection of a gate driving circuit in an embodiment of the present application;

[0075] Figure 6 is a schematic diagram of the electrical connection of a scan shift register in an embodiment of the present application;

[0076] Figure 7 is a schematic diagram of the electrical connection of a scan shift register in an embodiment of the present application;

[0077] Figure 8 is a schematic diagram of the electrical connection of a virtual shift register in an embodiment of the present application;

[0078] Figure 9 is a schematic diagram of the electrical connection of a first virtual shift register in an embodiment of the present application;

[0079] Figure 10 is a schematic diagram of the electrical connection of a second virtual shift register in an embodiment of the present application;

[0080] Figure 11 is a simulation waveform diagram of a gate driving circuit in an embodiment of the present application;

[0081] Figure 12 is a schematic diagram of the electrical connection of another scan shift register unit in an embodiment of the present application;

[0082] Figure 13 is a schematic diagram of the electrical connection of another first virtual shift register in the related art;

[0083] Figure 14 is a schematic diagram of the electrical connection of another second virtual shift register in an embodiment of the present application;

[0084] Figure 15 This is a flowchart of a driving method for a gate driving circuit in an embodiment of the present application. Detailed implementation manners

[0085] To make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the technical solutions of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Apparently, the described embodiments are some but not all of the embodiments of the technical solutions of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments recorded in this application document without creative efforts belong to the scope protected by the technical solutions of the present application.

[0086] Terms such as "first" and "second" in the description and claims of the present invention and the above accompanying drawings are used to distinguish similar objects and do not necessarily need to describe a specific order or sequence. It should be understood that such used data can be interchanged under appropriate circumstances so that the embodiments of the present invention described here can be implemented in an order other than those illustrated or described here.

[0087] The preferred embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0088] Refer to Figure 4 As shown, a gate driving circuit proposed in an embodiment of the present application includes: a level control unit 10 and a shift register unit 20.

[0089] Refer to Figure 5 As shown, the level control unit 10 is electrically connected to the first scan input signal line CN and the second scan input signal line CNB of the scan shift register and the virtual shift register respectively, and is configured to, in response to the first control signal, write the first scan control signal CN1 to the first scan input signal line CN of the scan shift register and the virtual shift register, write the second scan control signal CNB1 to the second scan input signal line CNB of the scan shift register and the virtual shift register, in response to the second control signal, write the second scan control signal CNB1 to the first scan input signal line CN and the second scan input signal line CNB of the scan shift register and the virtual shift register, and, in response to the third control signal, write the first scan control signal CN1 to the first scan input signal line CN and the second scan input signal line CNB of the scan shift register and the virtual shift register.

[0090] It should be noted that during the above forward scan, the first scan control signal CN1 is at a high level and the second scan control signal CNB1 is at a low level; during the reverse scan, the first scan control signal CN1 is at a low level and the second scan control signal CNB1 is at a high level.

[0091] When the gate driving circuit performs a forward scan, during the scan of the current frame of the picture, the level control unit 10 responds to the first control signal, conducts the first scan input signal line CN of the scan shift register and the virtual shift register with the first scan control signal CN1, and conducts the second scan input signal line CNB of the scan shift register and the virtual shift register with the second scan control signal CNB1, that is, the level control unit 10 provides a high-level signal for the first scan control signal CN1 and a low-level signal for the second scan control signal CNB1. It should be noted that the above first control signal makes the first control signal line A1 provide an invalid level signal, that is, the first transistor T1 is turned off, the second control signal line A2 provides a valid level signal, that is, the second transistor T2 is turned on, and the third control signal line A3 provides a valid level signal, that is, the third transistor T3 is turned on.

[0092] After the scan of the current frame of the picture and before the scan of the next frame of the picture, the level control unit 10 responds to the second control signal, conducts the first scan input signal line CN and the second scan input signal line CNB of the scan shift register and the virtual shift register with the second scan control signal CNB1, that is, during the frame reset process, the second scan control signal CNB1 provides a low-level signal for the first scan control signal CN1 and the second scan control signal CNB1. It should be noted that the above second control signal makes the first control signal line A1 provide a valid level signal, that is, the first transistor T1 is turned on, the second control signal line A2 provides an invalid level signal, that is, the second transistor T2 is turned off, and the third control signal line A3 provides a valid level signal, that is, the third transistor T3 is turned on.

[0093] When the gate driving circuit performs a reverse scan, during the scan of the current frame of the picture, the level control unit 10 responds to the first control signal, conducts the first scan input signal line CN of the scan shift register and the virtual shift register with the first scan control signal CN1, and conducts the second scan input signal line CNB of the scan shift register and the virtual shift register with the second scan control signal CNB1, that is, the level control unit 10 provides a low-level signal for the first scan control signal line CN1 and a high-level signal for the second scan control signal line CNB1.

[0094] After scanning the current frame image and before scanning the next frame image, in response to the third control signal, the level control unit 10 conducts the first scan input signal lines CN and CNB of the scan shift register and the virtual shift register with the first scan control signal CN1, that is, during the frame reset process, the first scan control signal CN1 provides a low-level signal for the first scan control signal CN1 and the second scan control signal CNB1. It should be added that the above third control signal enables the first control signal line A1 to provide an effective level signal, that is, the first transistor T1 is turned on, the second control signal line A2 provides an effective level signal, that is, the second transistor T2 is turned on, and the third control signal line A3 provides an ineffective level signal, that is, the third transistor T3 is turned off.

[0095] The following specifically introduces the level control unit 10. The level control unit 10 includes: a first control subunit 110, a second control subunit 120, and a third control subunit 130.

[0096] The control end of the first control subunit 110 is electrically connected to the first control signal line A1, the first end of the first control subunit 110 is electrically connected to the first transmission line, and the second end of the first control subunit 110 is electrically connected to the second transmission line.

[0097] The first control subunit 110 is configured to conduct the first transmission line and the second transmission line in response to the effective level signal of the first control signal line A1.

[0098] In the embodiment of the present application, the first control subunit 110 mainly functions as a switch. When the first control signal line A1 provides an effective level signal, the first control subunit 110 conducts the first transmission line and the second transmission line. Obviously, in this case, the signals in the first transmission line and the second transmission line are the same signal.

[0099] It should be added that the first scan input signal line CN of the scan shift register and the virtual shift register is electrically connected to the first transmission line, and the second scan input signal line CNB of the scan shift register and the virtual shift register is electrically connected to the second transmission line.

[0100] In the embodiment of the present application, the signal of the first scan input signal line CN of the scan shift register and the virtual shift register is provided by the first transmission line, and the second scan input signal line CNB of the scan shift register and the virtual shift register is provided by the second transmission line.

[0101] Exemplarily, refer to Figure 5As shown, the first control subunit 110 includes: a first transistor T1, a control terminal of the first transistor T1 is electrically connected to a first control signal line A1, a first terminal of the first transistor T1 is electrically connected to a first transmission line, and a second terminal of the first transistor T1 is electrically connected to a second transmission line.

[0102] During implementation, when the first control signal line A1 provides a valid level signal, the first transistor T1 is turned on, and the first transmission line is connected to the second transmission line, that is, the same signal is transmitted in the first transmission line and the second transmission line.

[0103] A control terminal of the second control subunit 120 is electrically connected to a second control signal line A2, a first terminal of the second control subunit 120 is electrically connected to the first transmission line, and a second terminal of the first control subunit 110 is electrically connected to a first scan control signal CN1.

[0104] The second control subunit 120 is configured to write the first scan control signal CN1 into the first transmission line in response to a valid level signal of the second control signal line A2.

[0105] In an embodiment of the present application, the second control subunit 120 mainly functions to transmit the first scan control signal CN1 to the first transmission line. When the second control signal line A2 provides a valid level signal, the first scan control signal CN1 is transmitted to the first transmission line via the second control subunit 120.

[0106] Exemplarily, refer to Figure 5 As shown, the second control subunit 120 includes: a second transistor T2, a control terminal of the second transistor T2 is electrically connected to the second control signal line A2, a first terminal of the second transistor T2 is electrically connected to the first scan control signal CN1, and a second terminal of the second transistor T2 is electrically connected to the first transmission line.

[0107] During implementation, when the second control signal line A2 provides a valid level signal, the second transistor T2 is turned on, and the first scan control signal CN1 is transmitted to the first transmission line via the turned-on second transistor T2.

[0108] A control terminal of the third control subunit 130 is electrically connected to a third control signal line A3, a first terminal of the third control subunit 130 is electrically connected to the second transmission line, and a second terminal of the third control subunit 130 is electrically connected to a second scan control signal CNB1.

[0109] The third control subunit 130 is configured to write the second scan control signal CNB1 into the second transmission line in response to a valid level signal of the third control signal line A3.

[0110] In the embodiment of the present application, the third control subunit 130 mainly serves to transmit the signal provided by the second scan control signal line CNB1 to the second transmission line. When the third control signal line A3 provides a valid level signal, the signal provided by the second scan control signal line CNB1 is transmitted to the second transmission line via the third control subunit 130.

[0111] Exemplarily, referring to Figure 5 As shown, the third control subunit 130 includes: a third transistor T3. The control terminal of the third transistor T3 is electrically connected to the third control signal line A3. The first terminal of the third transistor T3 is electrically connected to the second transmission line. The second terminal of the third transistor T3 is electrically connected to the second scan control signal CNB1.

[0112] During the implementation process, when the third control signal line A3 provides a valid level signal, the above-mentioned third transistor T3 is turned on, and the second scan control signal CNB1 is transmitted to the second transmission line via the turned-on third transistor T3.

[0113] In addition, it should be noted that the first control signal causes the first control signal line A1 to provide an invalid level signal, the second control signal line A2 to provide a valid level signal, and the third control signal line A3 to provide a valid level signal.

[0114] That is, during the forward scan process, when the gate driving circuit inputs a scan driving signal to the gate line, the second control signal line A2 provides a valid level signal, the second transistor T2 is turned on, and the first scan control signal CN1 provides a high level signal for the first scan input signal line CN of the scan shift register and the virtual shift register; the third control signal line A3 provides a valid level signal, the third transistor T3 is turned on, and the second scan control signal CNB1 provides a low level signal for the second scan input signal line CNB of the scan shift register and the virtual shift register.

[0115] During the reverse scan process, when the gate driving circuit inputs a scan driving signal to the gate line, the second control signal line A2 provides a valid level signal, the second transistor T2 is turned on, and the first scan control signal CN1 provides a low level signal for the first scan input signal line CN of the scan shift register and the virtual shift register; the third control signal line A3 provides a valid level signal, the third transistor T3 is turned on, and the second scan control signal CNB1 provides a high level signal for the second scan input signal line CNB of the scan shift register and the virtual shift register.

[0116] The second control signal causes the first control signal line A1 to provide a valid level signal, the second control signal line A2 to provide an invalid level signal, and the third control signal line A3 to provide a valid level signal.

[0117] That is, during the forward scan, after scanning the current frame image and during the frame reset process before scanning the next frame image, the third control signal line A3 provides an active level signal, the third transistor T3 is turned on, the second scan control signal CNB1 provides a low level signal to the second scan input signal line CNB of the scan shift register and the virtual shift register, the first control signal line A1 provides an active level signal, the first transistor T1 is turned on, the first transmission line and the second transmission line are turned on, the low level signal is provided to the first transmission line through the second transmission line, and then provided to the first scan input signal line CN of the scan shift register and the virtual shift register, that is, the signal accessed by the first scan input signal line CN is a low level signal.

[0118] The third control signal causes the first control signal line A1 to provide an active level signal, the second control signal line A2 to provide an active level signal, and the third control signal line A3 to provide an inactive level signal.

[0119] That is, during the reverse scan, after scanning the current frame image and during the frame reset process before scanning the next frame image, the second control signal line A2 provides an active level signal, the second transistor T2 is turned on, the first scan control signal CN1 provides a low level signal to the first scan input signal line CN of the scan shift register and the virtual shift register, the first control signal line A1 provides an active level signal, the first transistor T1 is turned on, the first transmission line and the second transmission line are turned on, the low level signal is provided to the second transmission line through the first transmission line, and then provided to the second scan input signal line CNB of the scan shift register and the virtual shift register, that is, the signal in the second scan input signal line CNB is a low level signal.

[0120] In the embodiment of the present application, the shift register unit 20 includes a scan shift register and a virtual shift register. The scan shift register is electrically connected to the gate line and is configured to input a scan driving signal to the gate line according to the signals of the first scan input signal line CN and the second scan input signal line CNB. The virtual shift register is electrically connected to the scan shift register and is configured to input a cascade driving signal to the scan shift register according to the signals of the first scan input signal line CN and the second scan input signal line CNB.

[0121] During the implementation process, the scan shift register is electrically connected to a corresponding gate line. During the forward scan and reverse scan of the display panel, the scan shift register can input a scan driving signal to the gate line according to the signals provided by the first scan input signal line CN and the second scan input signal line CNB.

[0122] To ensure the normal operation of the above scanning shift register, a virtual shift register is also provided in the embodiment of the present application. During the implementation process, the virtual shift register inputs a cascaded driving signal to the scanning shift register according to the signals provided by the first scanning input signal line CN and the second scanning input signal line CNB.

[0123] Generally, the number of virtual shift registers is at least two. One of the virtual shift registers is arranged in the row before the first-row scanning shift register, and this virtual shift register inputs a cascaded driving signal to the scanning shift register in the first row. The above cascaded driving signal serves as the input signal of the scanning shift register in the first row, so that the scanning shift register in the first row can start working as soon as possible; another one of the virtual shift registers is arranged in the row after the last-row scanning shift register, and this virtual shift register inputs a cascaded driving signal to the scanning shift register in the last row. The above cascaded driving signal serves as the reset signal of the scanning shift register in the last row, so that the scanning shift register in the last row can clear the data after the data in this row is displayed.

[0124] In the embodiment of the present application, the transistors for frame reset originally provided in the scanning shift register and the virtual shift register are omitted, thus saving costs and improving the panel yield. However, in order to clear the data in the scanning shift register and the virtual shift register after the display of the data in this frame, a level control unit 10 is provided, that is, the level control unit 10 cooperates with the scanning shift register and the virtual shift register after removing the transistors for frame reset to complete the work of inputting the scanning driving signal to the gate line, which includes resetting the gate driving circuit before the start of scanning the next frame of the picture.

[0125] The following introduces the shift register unit 20:

[0126] (1) The shift register unit 20 in the embodiment of the present application includes a plurality of scanning shift registers, and the plurality of scanning shift registers are cascaded.

[0127] The above-mentioned cascaded scanning shift registers drive row by row, and respectively provide scanning driving signals for the gate lines corresponding to each row of pixel units. The scanning shift register in the previous row also outputs a cascaded signal to the scanning shift register in the next row. The working process of the plurality of scanning shift registers will not be elaborated here.

[0128] The virtual shift register in the embodiment of the present application includes a first virtual shift register. The first input signal line of the first virtual shift register is electrically connected to the frame start signal line STU, the second input signal line of the first virtual shift register is electrically connected to the cascaded signal output end of the first scanning shift register among the plurality of scanning shift registers, and the cascaded output signal line of the first virtual shift register is electrically connected to the first input signal line of the first scanning shift register.

[0129] That is, in the first case: when at least one virtual shift register (i.e., the first virtual shift register) is further provided before the scan shift register in the first row, the signal of the frame start signal line STU is provided to the first input signal line of the first virtual shift register to prompt the cascade output signal line of the first virtual shift register to output a signal.

[0130] The cascade output signal line of the above-mentioned first virtual shift register is electrically connected to the first input signal line of the first scan shift register. That is, the signal of the cascade output signal line of the first virtual shift register serves as the signal of the first input signal line of the first scan shift register to enable the first scan shift register to start the scan process.

[0131] The reset signal line of the first virtual shift register, i.e., the second input signal line, is electrically connected to the cascade signal output terminal of the first scan shift register among the multiple scan shift registers, and the signal of the cascade signal output terminal of the first scan shift register is used to provide a signal for resetting this row for the first virtual shift register.

[0132] (2) The shift register unit 20 includes multiple scan shift registers, and the multiple scan shift registers are cascaded.

[0133] The above-mentioned cascaded scan shift registers are driven row by row to respectively provide scan drive signals for the gate lines corresponding to each row of pixel units, and the scan shift register of the previous row also outputs a cascade signal to the scan shift register of the next row. The working process of the multiple scan shift registers will not be elaborated here.

[0134] The virtual shift register includes a second virtual shift register. The first input signal line of the second virtual shift register is electrically connected to the cascade signal output terminal of the last scan shift register among the multiple scan shift registers. The second input signal line of the second virtual shift register is electrically connected to the frame start signal line STU. The cascade output signal line of the second virtual shift register is electrically connected to the second input signal line of the last scan shift register.

[0135] That is, in the second case: when at least one virtual shift register (i.e., the second virtual shift register) is further provided after the scan shift register in the last row, the cascade signal output terminal of the last scan shift register among the multiple scan shift registers is used to provide the signal of the first input signal line for the second virtual shift register to enable the second virtual shift register to start working.

[0136] The signal of the cascade output signal line of the above-mentioned second virtual shift register is used to provide a signal for the second input signal line of the last scan shift register to enable the last scan shift register to be used for resetting this row.

[0137] The reset signal line of the second virtual shift register, i.e., the second input signal line, is electrically connected to the frame start signal line STU, and the signal of the frame start signal line STU is used to provide a signal for frame reset to the second virtual shift register.

[0138] Next, the structure of a single scan shift register will be introduced. For simplicity, the working process of the following scan shift register will be described in detail taking the forward scan as an example. Refer to Figure 6 As shown, the scan shift register includes:

[0139] A first input module 101, configured to respond to the first input signal line CR <n-1>The signal is used to supply the signal of the first scan input signal line CN to the pull-up node Q1.

[0140] Exemplarily, refer to Figure 7 As shown, the above-mentioned first input module 101 includes: a fourth transistor T4.

[0141] The control terminal of the fourth transistor T4 is connected to the first input signal line CR <n-1>electrically connected, the first end of the fourth transistor T4 is electrically connected to the first scan input signal line CN, and the second end of the fourth transistor T4 is electrically connected to the pull-up node Q1.

[0142] During the implementation process, when the first input signal line CR <n-1>When the signal of is at a high level, the fourth transistor T4 is turned on, and the signal of the first scan input signal line CN is provided to the pull-up node Q1, that is, the pull-up node Q1 is written with a high-level signal.

[0143] The second input module 102 is configured to provide the signal of the second scan input signal line CNB to the pull-up node Q1 in response to the signal of the second input signal line CR<N+1>.

[0144] Exemplarily, referring to Figure 7 As shown, the above-mentioned second input module 102 includes: a fifth transistor T5.

[0145] The control terminal of the fifth transistor T5 is electrically connected to the second input signal line CR<N+1>, the first terminal of the fifth transistor T5 is electrically connected to the pull-up node Q1, and the second terminal of the fifth transistor T5 is electrically connected to the second scan input signal line CNB.

[0146] During the implementation process, when the second input signal line CR<N+1> provides a high-level signal, the fifth transistor T5 is turned on, the signal in the second scan input signal line CNB is provided to the pull-up node Q1, and the pull-up node Q1 is written with a low-level signal.

[0147] The first node control module 103 is configured to control the signals of the pull-up node Q1 and the pull-down node QB1.

[0148] Exemplarily, referring to Figure 7 As shown, the above-mentioned first node control module 103 includes: a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12, and a thirteenth transistor T13.

[0149] The control terminal of the ninth transistor T9 is electrically connected to the pull-up node Q1, the first terminal of the ninth transistor T9 is electrically connected to the pull-down node QB1, and the second terminal of the ninth transistor T9 is electrically connected to the first reference signal line VGL1.

[0150] During the implementation process, when the pull-up node Q1 is at a high level, the ninth transistor T9 is turned on, and the low level provided by the first reference signal line VGL1 is provided to the pull-down node QB1 through the turned-on ninth transistor T9, and the pull-down node QB1 is written with a low-level signal.

[0151] The control terminal of the tenth transistor T10 is electrically connected to the pull-down node, the first terminal of the tenth transistor T10 is electrically connected to the pull-up node Q1, and the second terminal of the tenth transistor T10 is electrically connected to the first reference signal line VGL1.

[0152] During the implementation process, when the pull-down node QB1 is at a high level, the tenth transistor T10 is turned on, and the low level provided by the first reference signal line VGL1 is supplied to the pull-up node Q1 through the turned-on tenth transistor T10, so that the pull-up node Q1 is written with a low-level signal, thereby realizing reset after the line scan is completed.

[0153] The control terminal of the eleventh transistor T11 is electrically connected to the power supply signal line VDD, the first terminal of the eleventh transistor T11 is electrically connected to the power supply signal line VDD, and the second terminal of the eleventh transistor T11 is electrically connected to the pull-down node.

[0154] During the implementation process, in the stage except when the pull-up node Q1 is at a high level and the pull-down node QB1 is at a low level, the above-mentioned power supply signal line VDD is at a high level, which further turns on the eleventh transistor T11, and the high level provided by the power supply signal line VDD is supplied to the pull-down node QB1, that is, the pull-down node QB1 is written with a high level.

[0155] The control terminal of the twelfth transistor T12 is connected to the first input signal line CR of the scan shift register <n-1>electrically connected, a first end of the twelfth transistor T12 is electrically connected to the pull-down node QB1, and a second end of the twelfth transistor T12 is electrically connected to the second scan input signal line CNB.

[0156] During implementation, a first input signal line CR of the scan shift register <n-1>When a high-level signal is provided, the twelfth transistor T12 is turned on, and the low-level signal provided by the second scan input signal line CNB is supplied to the pull-down node QB1 through the turned-on twelfth transistor T12, so that the pull-down node QB1 is written with a low-level signal.

[0157] The control terminal of the thirteenth transistor T13 is electrically connected to the second input signal line CR<N+1> of the scan shift register. The first terminal of the thirteenth transistor T13 is electrically connected to the pull-down node QB1, and the second terminal of the thirteenth transistor T13 is electrically connected to the first scan input signal line CN.

[0158] During implementation, when the second input signal line CR<N+1> of the scan shift register is at a high level, the thirteenth transistor T13 is turned on, and the high-level signal provided by the first scan input signal line CN is supplied to the pull-down node QB1 through the turned-on thirteenth transistor T13, so that the pull-down node QB1 is written with a high-level signal.

[0159] The first cascaded output module 104 is configured to supply the signal of the cascaded clock signal line CLKD_1 to the cascaded signal output terminal cr in response to the signal of the pull-up node Q1. <n>; or, in response to a signal of the pull-down node QB1, providing a signal of the first reference signal line VGL1 to the cascaded signal output terminal cr <n>。

[0160] Exemplarily, referring to Figure 7 As shown, the above first cascaded output module 104 includes: a fourteenth transistor T14 and a fifteenth transistor T15.

[0161] The control end of the fourteenth transistor T14 is electrically connected to the pull-up node Q1, the first end of the fourteenth transistor T14 is electrically connected to the cascaded clock signal line CLKD_1, and the second end of the fourteenth transistor T14 is connected to the cascaded signal output end cr <n>Electrical connection.

[0162] During implementation, when the pull-up node Q1 is a high-level signal, the fourteenth transistor T14 conducts, and the high-level signal provided by the cascaded clock signal line CLKD_1 is written to the cascaded signal output terminal cr through the conducting fourteenth transistor T14. <n>。

[0163] The control terminal of the fifteenth transistor T15 is electrically connected to the pull-down node QB1, and the first terminal of the fifteenth transistor T15 is connected to the cascade signal output terminal cr <n>Electrically connected, the second end of the fifteenth transistor T15 is electrically connected to the first reference signal line VGL1.

[0164] During the implementation process, when the pull-down node QB1 is at a high-level signal, the fifteenth transistor T15 is turned on, and the low-level signal provided by the first reference signal line VGL1 is written to the cascade signal output terminal cr through the turned-on fifteenth transistor T15. <n>, for the cascaded signal output terminal cr <n>Perform reset.

[0165] The first drive output module 105 is configured to provide the signal provided by the clock signal line CLKE_1 to the drive output terminal OUT1 in response to the signal of the pull-up node Q1. <n>; or, in response to the signal of the dropdown node QB1, providing the signal of the second reference signal line VGL2 to the drive output terminal OUT1 <n>。

[0166] Exemplarily, referring to Figure 7 as shown, the above-mentioned first driving output module 105 includes: a sixteenth transistor T16, a seventeenth transistor T17, and a first capacitor c1.

[0167] The control terminal of the sixteenth transistor T16 is electrically connected to the pull-up node Q1, the first terminal of the sixteenth transistor T16 is electrically connected to the clock signal line CLKE_1, and the second terminal of the sixteenth transistor T16 is connected to the driving output terminal OUT1 <n>Electrical connection.

[0168] During the implementation process, when the pull-up node Q1 is a high-level signal, the sixteenth transistor T16 conducts, and the high-level signal provided by the clock signal line CLKE_1 is written to the drive output terminal OUT1 through the conducting sixteenth transistor T16 <n>。

[0169] The control terminal of the seventeenth transistor T17 is electrically connected to the pull - down node QB1, and the first terminal of the seventeenth transistor T17 is connected to the drive output terminal OUT1 <n>Electrically connected, the second terminal of the seventeenth transistor T17 is electrically connected to the second reference signal line VGL2.

[0170] During implementation, when the signal at the pull-down node QB1 is at a high level, the seventeenth transistor T17 conducts, and the low-level signal provided by the second reference signal line VGL2 is written to the drive output terminal OUT1 through the conducting seventeenth transistor T17. <n>, drive output terminal OUT1 <n>A low-level signal can be provided to the gate line.

[0171] In the embodiment of the present application, the first end of the first capacitor C1 is electrically connected to the pull-up node Q1, and the second end of the first capacitor C1 is connected to the drive output terminal OUT1 <n>Electrical connection. When the fourth transistor T4 is turned on, a high level can be transmitted to the pull-up node Q1, causing the voltage of the pull-up node Q1 to increase. At the same time, the first capacitor C1 can be charged. When the fourth transistor T4 is turned off, the first capacitor C1 can discharge, causing the pull-up node Q1 to maintain a high level, thereby causing the sixteenth transistor T16 to remain in the conducting state.

[0172] In addition, when the sixteenth transistor T16 is turned on and the signal provided by the clock signal line CLKE_1 changes from a high level to a low level, the drive output terminal OUT1 at this time <n>The output is at a low level. At the same time, due to the bootstrap effect of the first capacitor C1, the voltage of the pull-up node Q1 also decreases.

[0173] It should be noted that after scanning a frame of the picture, the gate driving circuit needs to be frame-reset to avoid affecting the display of the next frame. To this end, the above scanning shift register further includes: a frame reset module, and the frame reset module is electrically connected to the pull-up node.

[0174] The frame reset module is configured to provide the signal of the first reference signal line VGL1 to the pull-up node Q1 in response to the signal of the frame start signal line STU.

[0175] Exemplarily, refer to Figure 7 As shown, the frame reset module includes: a sixth transistor T6.

[0176] The control end of the sixth transistor T6 is electrically connected to the frame start signal line STU, the first end of the sixth transistor T6 is electrically connected to the pull-up node Q1, and the second end of the sixth transistor T6 is electrically connected to the first reference signal line VGL1.

[0177] During the implementation process, after scanning a frame of the picture, the frame start signal line STU provides a high-level signal, so that the sixth transistor T6 is turned on, and the low-level signal provided by the first reference signal line VGL1 is written into the pull-up node Q1, thereby resetting the pull-up node Q1 after scanning a frame of the picture.

[0178] Since the above shift register unit 20 provided by the embodiment of the present invention can realize bidirectional scanning. During reverse scanning, the functions of the first input module 101 and the second input module 102 of the scanning shift register are interchanged, that is, during forward scanning, the first input module 101 serves as the input module and the first input signal line serves as the input signal line. The above gate driving circuit, when realizing reverse scanning of the gate lines, interchanges the functions of the first input module 101 and the second input module 102 of each scanning shift register. During reverse scanning, the second input module 102 of each scanning shift register serves as the input module, the second input signal line serves as the input signal line, and the first input module 101 of each scanning shift register serves as the reset module, and the first input signal line serves as the reset signal line. At this time, the electrical connection relationship of the circuit does not change, but only the circuit function changes.

[0179] Then, introduce the composition of a single virtual shift register. And, for the sake of simplicity, the working process of the following virtual shift register is described in detail taking forward scanning as an example. Refer to Figure 8 As shown, the virtual shift register includes:

[0180] The third input module 201 is configured to provide the signal of the first scan input signal line CN to the pull-up node Q2 of the first virtual shift register or the pull-up node Q3 of the second virtual shift register in response to the signal of the first input signal line STU.

[0181] Exemplarily, referring to Figure 9 As shown, the third input module 201 includes: a seventh transistor T7.

[0182] The control end of the seventh transistor T7 is electrically connected to the first input signal line STU, the first end of the seventh transistor T7 is electrically connected to the first scan input signal line CN, and the second end of the seventh transistor T7 is electrically connected to the pull-up node Q2.

[0183] During the implementation process, when the signal provided by the first input signal line is at a high level, the seventh transistor T7 is turned on, and the high-level signal provided by the first scan input signal line CN is written into the pull-up node Q2 through the turned-on seventh transistor T7, making the pull-up node Q2 at a high level. It should be noted that when the virtual shift register is the first virtual shift register, the first input signal line is electrically connected to the frame start signal line STU; when the virtual shift register is the second virtual shift register, the first input signal line is connected to the cascade signal output end CR of the last scan shift register <n-1>Electrical connection, refer to Figure 10 as shown.

[0184] The fourth input module 202 is configured to provide the signal of the second scan input signal line CNB to the pull-up node Q2 in response to the signal of the second input signal line CR<N+1>.

[0185] Exemplarily, refer to Figure 9 as shown, the fourth input module 202 includes: the eighth transistor T8.

[0186] The control terminal of the eighth transistor T8 is electrically connected to the second input signal line CR<N+1>, the first terminal of the eighth transistor T8 is electrically connected to the pull-up node Q2, and the second terminal of the eighth transistor T8 is electrically connected to the second scan input signal line CNB.

[0187] During the implementation process, when the signal of the second input signal line CR<N+1> is at a high level, the eighth transistor T8 is turned on, and the low level provided by the second scan input signal line CNB writes a low level to the pull-up node Q2, thereby realizing the reset of the pull-up node Q2. It should be noted that when the virtual shift register is the first virtual shift register, the second input signal line is electrically connected to the cascaded signal output terminal CR<N+1> of the first scan shift register; when the virtual shift register is the second virtual shift register, the second input signal line is electrically connected to the frame start signal line STU.

[0188] The second node control module 203 is configured to control the signals of the pull-up node and the pull-down node.

[0189] Exemplarily, refer to Figure 9 as shown, the above-mentioned second node control module 203 includes: the eighteenth transistor T18, the nineteenth transistor T19, the twentieth transistor T20, the twenty-first transistor T21, and the twenty-second transistor T22.

[0190] Next, in combination with Figure 9 the electrical connection relationships and conduction conditions of the above-mentioned various transistors will be introduced in detail.

[0191] The control terminal of the eighteenth transistor T18 is electrically connected to the pull-up node of the virtual shift register, the first terminal of the eighteenth transistor T18 is electrically connected to the pull-down node of the virtual shift register, and the second terminal of the eighteenth transistor T18 is electrically connected to the first reference signal line VGL1 of the virtual shift register.

[0192] During the implementation process, when the pull-up node Q2 of the virtual shift register is at a high level, the eighteenth transistor T18 is turned on, and the low level provided by the first reference signal line VGL1 is written to the pull-up node Q2 through the turned-on eighteenth transistor T18, making the pull-down node QB2 of the virtual shift register at a low level.

[0193] The control terminal of the nineteenth transistor T19 is electrically connected to the pull-down node QB2 of the virtual shift register. The first terminal of the nineteenth transistor T19 is electrically connected to the pull-up node Q2 of the virtual shift register. The second terminal of the nineteenth transistor T19 is electrically connected to the first reference signal line VGL1 of the virtual shift register.

[0194] During the implementation process, when the pull-down node QB2 of the virtual shift register is at a high level, the nineteenth transistor T19 is turned on. The low level of the first reference signal line VGL1 of the virtual shift register is provided to the pull-up node Q2 through the turned-on nineteenth transistor T19, making the pull-up node Q2 of the virtual shift register at a low level, so as to achieve reset after the line scan is completed.

[0195] The control terminal of the twentieth transistor T20 is electrically connected to the power supply signal line VDD of the virtual shift register. The first terminal of the twentieth transistor T20 is electrically connected to the power supply signal line VDD of the virtual shift register. The second terminal of the twentieth transistor T20 is electrically connected to the pull-down node QB2 of the virtual shift register.

[0196] During the implementation process, except for the stage when the pull-up node Q2 of the virtual shift register is at a high level and the pull-down node QB2 is at a low level, the above-mentioned power supply signal line VDD is at a high level, which further turns on the twentieth transistor T20. The high level of the power supply signal line VDD makes the pull-down node QB2 of the virtual shift register at a high level.

[0197] See Figure 9 , the control terminal of the twenty-first transistor T21 is connected to the frame start signal line STU of the first virtual shift register. The first terminal of the twenty-first transistor T21 is electrically connected to the pull-down node QB2 of the virtual shift register. The second terminal of the twenty-first transistor T21 is electrically connected to the second scan input signal line CNB.

[0198] During the implementation process, when the first input signal line STU of the first virtual shift register is at a high level, the twenty-first transistor T21 is turned on. The low level signal of the second scan input signal line CNB is provided to the pull-down node QB2 through the turned-on twenty-first transistor T21, making the pull-down node QB2 at a low level.

[0199] See Figure 10 , the control terminal of the twenty-first transistor T21' is connected to the first input signal line CR of the second virtual shift register <n-1>electrically connected, the first end of the twenty-first transistor T21' is electrically connected to the pull-down node QB3 of the virtual shift register, and the second end of the twenty-first transistor T21' is electrically connected to the second scan input signal line terminal CNB.

[0200] During implementation, the first input signal line CR of the second virtual shift register <n-1>When it is at a high level, the twenty-first transistor T21' is turned on, and the low-level signal of the twenty-first scan input signal line CNB is supplied to the pull-down node QB3 through the turned-on twenty-first transistor T21', making the pull-down node QB3 at a low level.

[0201] See Figure 9 , the control terminal of the twenty-second transistor T22 is electrically connected to the second input signal line CR<N + 1> of the first virtual shift register, the first terminal of the twenty-second transistor T22 is electrically connected to the pull-down node QB2 of the first virtual shift register, and the second terminal of the twenty-second transistor T22 is electrically connected to the first scan input signal line CN.

[0202] See Figure 10 , the control terminal of the twenty-second transistor T22' is electrically connected to the frame start signal line STU of the second shift register, the first terminal of the twenty-second transistor T22' is electrically connected to the pull-down node QB3 of the second virtual shift register, and the second terminal of the twenty-second transistor T22' is electrically connected to the first scan input signal line CN.

[0203] During the implementation process, when the second input signal line CR<N + 1> of the first virtual shift register is at a high level, the twenty-second transistor T22 is turned on, and the high-level signal provided by the first scan input signal line CN is written into the pull-down node QB2 through the turned-on twenty-second transistor T22, making the pull-down node QB2 at a high level.

[0204] During the implementation process, when the frame start signal line STU of the second shift register is at a high level, the twenty-second transistor T22' is turned on, and the high-level signal provided by the first scan input signal line CN is written into the pull-down node QB3 through the turned-on twenty-second transistor T22', making the pull-down node QB3 at a high level.

[0205] The second cascade output module 204 is configured to supply the signal of the cascade clock signal line to the cascade output signal line CR in response to the signal of the pull-up node Q3 <n>; or, in response to a signal of a pull-down node QB2 of the first virtual shift register or a pull-down node QB3 of the second virtual shift register, providing a signal of the first reference signal line VGL1 to the cascade output signal line CR <n>。

[0206] Exemplarily, referring to Figure 9 as shown, the above-mentioned second cascaded output module 204 includes: a twenty-third transistor T23 and a twenty-fourth transistor T24.

[0207] For Figure 9 illustration, the control terminal of the twenty-third transistor T23 is electrically connected to the pull-up node Q2 of the first virtual shift register, the first terminal of the twenty-third transistor T23 is electrically connected to the cascaded clock signal line CLKD_2 of the virtual shift register, and the second terminal of the twenty-third transistor T23 is electrically connected to the cascaded output signal line CR <n>Electrical connection.

[0208] During the implementation process, when the pull-up node Q2 of the first virtual shift register is at a high-level signal, the twenty-third transistor T23 conducts, and the high-level signal of the cascaded clock signal line CLKD_2 is written into the cascaded output signal line CR through the conducting twenty-third transistor T23. <n>。

[0209] The control terminal of the twenty-fourth transistor T24 is electrically connected to the pull-down node QB2 of the first virtual shift register, and the first end of the twenty-fourth transistor T24 is connected to the cascade output signal line CR of the first virtual shift register <n>Electrically connected, the second terminal of the twenty-fourth transistor T24 is electrically connected to the first reference signal line VGL1 of the virtual shift register.

[0210] During the implementation process, when the pull-down node QB2 of the first virtual shift register is a high-level signal, the twenty-fourth transistor T24 is turned on, and the low-level signal of the first reference signal line VGL1 is written to the cascaded output signal line CR through the turned-on twenty-fourth transistor T24 <n>, for the cascaded output signal line CR <n>Perform reset.

[0211] The second drive output module 205 is configured to provide the signal of the clock signal line CLKE_2 to the drive output terminal OUT2 in response to the signal of the pull-up node Q2. <n>; or, in response to the signal of the pull-down node QB2, providing the signal of the second reference signal line VGL2 to the drive output terminal OUT2 <n>。

[0212] Exemplarily, referring to Figure 9 as shown, the second drive output module 205 includes: a twenty-fifth transistor T25, a twenty-sixth transistor T26, and a second capacitor c2.

[0213] For Figure 9 illustration, the control terminal of the twenty-fifth transistor T25 is electrically connected to the pull-up node Q2 of the first virtual shift register, the first terminal of the twenty-fifth transistor T25 is electrically connected to the clock signal line CLKE_2 of the first virtual shift register, and the second terminal of the twenty-fifth transistor T25 is electrically connected to the drive output terminal OUT2 of the first virtual shift register <n>Electrical connection.

[0214] During the implementation process, when the pull-up node Q2 of the first virtual shift register is at a high-level signal, the twenty-fifth transistor T25 conducts, and the high-level signal of the clock signal line CLKE_2 of the first virtual shift register is provided to the drive output terminal OUT2 through the conducting twenty-fifth transistor T25. <n>。

[0215] The control terminal of the twenty-sixth transistor T26 is electrically connected to the pull-down node QB2 of the first virtual shift register, and the first terminal of the twenty-sixth transistor T26 is connected to the driving output terminal OUT2 of the first virtual shift register <n>electrically connected, the second terminal of the twenty-sixth transistor T26 is electrically connected to the second reference signal line VGL2.

[0216] During the implementation process, when the signal of the pull-down node QB2 of the first virtual shift register is at a high level, the twenty-sixth transistor T26 is turned on, and the low-level signal of the second reference signal line VGL2 is written to the drive output terminal OUT2 through the turned-on twenty-sixth transistor T26 <n>。

[0217] In the embodiment of the present application, the first end of the second capacitor C2 is electrically connected to the pull-up node Q2, and the second end of the second capacitor C2 is connected to the drive output terminal OUT2 <n>Electrical connection. When the seventh transistor T7 is turned on, a high level can be transmitted to the pull-up node Q2, causing the voltage of the pull-up node Q2 to increase. At the same time, the first capacitor C1 can be charged. When the seventh transistor T7 is turned off, the second capacitor C2 can discharge, causing the pull-up node Q2 to maintain a high level, thereby keeping the twenty-fifth transistor T25 in a conducting state.

[0218] In addition, when the twenty-fifth transistor T25 is turned on and the clock signal line CLKE_2 changes from a high level to a low level, the drive output terminal OUT2 <n>The output is at a low level. At the same time, due to the bootstrap effect of the first capacitor C1, the voltage of the pull-up node Q2 also decreases.

[0219] Similarly, the above-mentioned shift register unit 20 provided by the embodiment of the present invention can achieve bidirectional scanning. During reverse scanning, the functions of the third input module 201 and the fourth input module 202 of the virtual shift register are interchanged. That is, during forward scanning, the third input module 201 serves as the input module, and the third input signal line serves as the input signal line. For the above-mentioned gate driving circuit, when realizing the reverse scanning of the gate line, the functions of the third input module 201 and the fourth input module 202 of each virtual shift register are interchanged. That is, relative to forward scanning, during reverse scanning, the fourth input module 202 of each virtual shift register serves as the input module, the second input signal line serves as the input signal line, the third input module 201 of each virtual register serves as the reset module, and the first input signal line serves as the reset signal line. At this time, the electrical connection relationship of the circuit does not change, but only the circuit function changes.

[0220] Refer to Figure 11 As shown in the figure, the main working process of the gate driving circuit during forward scanning is described below in conjunction with the timing diagram. Assume that the above-mentioned gate driving circuit includes three shift registers: a first virtual shift register, a scanning virtual shift register, and a second virtual shift register. The driving output terminal of the scanning virtual shift register provides a scanning signal for the corresponding gate line.

[0221] During the timing t1 stage: The invalid level signal of the first control signal line A1 in the level control unit 10, that is, the first transistor T1 is cut off, the valid level signal of the second control signal line A2, that is, the second transistor T2 is turned on, and the valid level signal of the third control signal line A3, that is, the third transistor T3 is turned on. The cascaded clock signal line CLKD_1 in the shift register unit 20 is at a low level, the clock signal line CLKE_1 is at a low level, the first reference signal line VGL1 is at a low level, the second reference signal line VGL2 is at a low level, and the frame start signal line STU is at a high level.

[0222] When the second transistor T2 is turned on, the high-level signal in the first scan control signal CN1 is provided to the first scan input signal line CN of the three shift registers, namely the first virtual shift register, the scanning virtual shift register, and the second virtual shift register, through the first transmission line, so that the signal of the first scan input signal line CN is at a high level. When the third transistor T3 is turned on, the low-level signal in the second scan control signal CNB1 is provided to the second scan input signal line CNB of the three shift registers, namely the first virtual shift register, the scanning virtual shift register, and the second virtual shift register, through the second transmission line, so that the signal of the second scan input signal line CNB is at a low level.

[0223] When the frame start signal line STU is at a high level, the seventh transistor T7 is turned on, and the signal of the first scan input signal line CN is at a high level. In this way, a high-level signal is written to the pull-up node Q2 of the first virtual shift register.

[0224] In the first virtual shift register, since the pull-up node Q2 of the first virtual shift register is at a high-level signal, the twenty-third transistor T23 and the twenty-fifth transistor T25 are both turned on at this time. Since the frame start signal line STU provides a high-level signal, the twenty-first transistor T21 is turned on at this time, and the low-level signal provided by the second scan input signal line CNB is written to the pull-down node QB2. At this time, the twenty-fourth transistor T24 and the twenty-sixth transistor T26 are both turned off. Among them, the low-level signal of the cascade clock signal line CLKD_2 of the first virtual shift register is written to the cascade output signal line CR via the turned-on twenty-third transistor T23 <n>, cascaded output signal line CR <n>Output a low-level signal; the low-level signal of the clock signal line CLKE_2 of the first virtual shift register is written to the drive output terminal OUT2 through the turned-on twenty-fifth transistor T25 <n>, the driving output terminal OUT2 of the first virtual shift register <n>Output a low-level signal.

[0225] In the scan shift register, since the cascaded output signal line of the first virtual shift register provides a low-level signal, the fourth transistor T4 and the twelfth transistor T12 are turned off. The frame start signal line STU is a high-level signal. Therefore, the sixth transistor T6 is turned on, and the low-level signal of the first reference signal line VGL1 is written into the pull-up node Q1 of the scan shift register via the turned-on sixth transistor T6. As a result, the fourteenth transistor T14 and the sixteenth transistor T16 are turned off. At this time, the VDD signal in the power supply signal line is written into the pull-down node QB1 via the turned-on eleventh transistor T11, that is, the pull-down node DB1 is written with a high-level signal. At this time, the fifteenth transistor T15 and the seventeenth transistor T17 are turned on. Among them, the low-level signal of the first reference signal line VGL1 is written into the cascaded signal output terminal cr via the fifteenth transistor T15 <n>, cascade signal output terminal cr <n>Output a low-level signal; the low-level signal of the second reference signal line VGL2 is written to the drive output terminal OUT1 via the seventeenth transistor T17 <n>, the driving output terminal OUT1 of the scan shift register <n>Output a low-level signal.

[0226] In the second virtual shift register, due to the cascade signal output terminal cr of the scan shift register <n>A low-level signal is provided, and the seventh transistor T7' and the twenty-first transistor T21' are turned off. Since the frame start signal line STU is at a high level, the eighth transistor T8' and the twenty-second transistor T22' are turned on. At this time, the low-level signal of the second scan input signal line CNB is written into the pull-up node Q3 via the eighth transistor T8', and the high-level signal of the first scan input signal line CN is written into the pull-down node QB3 via the twenty-second transistor T22'. At this time, the twenty-third transistor T23' and the twenty-fifth transistor T25' are turned off, the twenty-fourth transistor T24' and the twenty-sixth transistor T26' are turned on, and the cascaded output signal line CR of the second virtual shift register <n>and the drive output terminal OUT3 <n>All output low-level signals.

[0227] During the timing t2 stage: The invalid level signal of the first control signal line A1 in the level control unit 10, i.e., the first transistor T1 is cut off, and the valid level signal of the second control signal line A2, i.e., the second transistor T2 is turned on, and the valid level signal of the third control signal line A3, i.e., the third transistor T3 is turned on. The cascaded clock signal line CLKD_2 in the first virtual shift register is at a high level, the clock signal line CLKE_2 is at a high level, the first reference signal line VGL1 is at a low level, the second reference signal line VGL2 is at a low level, and the frame start signal line STU is at a low level.

[0228] When the second transistor T2 is turned on, the high-level signal in the first scan control signal CN1 is provided to the first scan input signal line CN of the three shift registers, namely the first virtual shift register, the scan virtual shift register, and the second virtual shift register, via the first transmission line, making the signal on the first scan input signal line CN at a high level. When the third transistor T3 is turned on, the low-level signal in the second scan control signal CNB1 is provided to the second scan input signal line CNB of the three shift registers, namely the first virtual shift register, the scan virtual shift register, and the second virtual shift register, via the second transmission line, making the signal on the second scan input signal line CNB at a low level.

[0229] After the signals in the cascaded clock signal line CLKD_2 and the clock signal line CLKE_2 jump from a low level to a high level, due to the bootstrap effect of the second capacitor c2, the voltage of the pull-up node Q2 of the first virtual shift register is further lifted, the twenty-third transistor T23 and the twenty-fifth transistor T25 are fully turned on, the high level of the pull-up node Q2 of the first virtual shift register controls the eighteenth transistor T18 to turn on, the low level of the first reference signal line VGL1 is written into the pull-down node QB2 of the first virtual shift register via the turned-on eighteenth transistor T18, and the high level of the clock signal line CLKE_2 is written into the drive output terminal OUT2 via the twenty-fifth transistor T25 <n>, that is, the drive output terminal OUT2 <n>Output a high-level signal. The high level of the cascaded clock signal line CLKD_2 is written to the cascaded output signal line CR through the twenty-third transistor T23 <n>, that is, the cascaded output signal line CR <n>Output a high-level signal.

[0230] At the same time, due to the cascaded output signal line CR of the first virtual shift register <n>Output a high-level signal, the cascaded output signal line CR <n>The high-level signal in is provided to the first input signal line CR of the scan shift register <n-1>, thereby turning on the fourth transistor T4 in the scan shift register, and writing the high-level signal of the first scan input signal line CN into the pull-up node Q1 in the scan shift register through the turned-on fourth transistor T4. The fourteenth transistor T14 and the sixteenth transistor T16 are turned on. At the same time, due to the cascaded output signal line CR of the first virtual shift register <n>The high-level signal in turns on the twelfth transistor T12 in the scan shift register. The low-level signal on the second scan input signal line CNB makes the pull-down node QB1 of the scan shift register at a low level, causing the tenth transistor T10, the fifteenth transistor T15, and the seventeenth transistor T17 to be turned off.

[0231] Meanwhile, due to the cascaded output signal line CR of the first virtual shift register <n>Output a high-level signal, the twelfth transistor T12 is turned on, and the low-level signal in the second scan input signal line CNB is written into the pull-down node QB1 in the scan shift register through the turned-on twelfth transistor T12.

[0232] At this time, in the second virtual shift register, due to the cascade signal output terminal cr of the scan shift register <n>Output a low-level signal. At this time, the seventh transistor T7' and the twenty-first transistor T21' in the second virtual shift register are both turned off.

[0233] During the timing t3 stage: The invalid level signal of the first control signal line A1 in the level control unit 10, i.e., the first transistor T1 is turned off, the valid level signal of the second control signal line A2, i.e., the second transistor T2 is turned on, and the valid level signal of the third control signal line A3, i.e., the third transistor T3 is turned on. The cascaded clock signal line CLKD_1 in the scan shift register is at a high level, the clock signal line CLKE_1 is at a high level, the first reference signal line VGL1 is at a low level, the second reference signal line VGL2 is at a low level, and the frame start signal line STU is at a low level.

[0234] When the second transistor T2 is turned on, the high-level signal in the first scan control signal CN1 is provided to the first scan input signal line CN of the three shift registers, namely the first virtual shift register, the scan virtual shift register, and the second virtual shift register, through the first transmission line, making the signal of the first scan input signal line CN at a high level. When the third transistor T3 is turned on, the low-level signal in the second scan control signal CNB1 is provided to the second scan input signal line CNB of the three shift registers, namely the first virtual shift register, the scan virtual shift register, and the second virtual shift register, through the second transmission line, making the signal of the second scan input signal line CNB at a low level.

[0235] At this time, in the first virtual shift register: Since the cascaded clock signal line CLKD_1 and the clock signal line CLKE_1 in the first virtual shift register change from a high level to a low level, the cascaded output terminal CR in the first virtual shift register <n>and the drive output terminal OUT2 <n>Both output low-level signals. In the scan shift register, the cascaded output terminals CR of the fourth transistor T4 and the twelfth transistor T12 in the first virtual shift register <n>Turned off under the control of a low-level signal.

[0236] In the scan shift register, after the clock signal line CLKE_2 in the cascade clock signal line CLKD_2 jumps from a low level to a high level, due to the bootstrap effect of the first capacitor c1, the voltage of the pull-up node Q1 of the scan shift register is further raised, the fourteenth transistor T14 and the sixteenth transistor T16 are fully turned on, the high level of the pull-up node Q1 of the scan shift register controls the ninth transistor T9 to turn on, the low level of the first reference signal line VGL1 is written to the pull-down node QB1 of the scan shift register, and the high level of the clock signal line CLKE_1 is output through the sixteenth transistor T16, that is, the drive output terminal OUT1 <n>Output a high-level signal, that is, the driving output terminal OUT1 of the scan shift register <n>Provide a high-level signal for the gate line. The high level of the cascaded clock signal line CLKD_1 is output through the fourteenth transistor T14, that is, the cascaded output signal line CR <n>Output a high-level signal.

[0237] Meanwhile, since the signal in the cascaded output signal line of the scan shift register is at a high level, this cascaded output signal line CR <n>The high-level signal in is provided to the first input signal line of the second virtual shift register, thereby turning on the seventh transistor T7' in the second virtual shift register. The high-level signal in the first scan input signal line CN is written into the pull-up node Q3 in the second virtual shift register through the turned-on seventh transistor T7', and the twenty-third transistor T23' and the twenty-fifth transistor T25' are turned on.

[0238] At this time, the cascaded output signal line CR of the second virtual shift register <n>and the drive output terminal OUT3 <n>All output low-level signals. Correspondingly, the fifth transistor T5 and the thirteenth transistor T13 in the scan shift register are turned off.

[0239] At the same time, since the signal in the cascaded output signal line of the scan shift register is at a high level, this cascaded output signal line CR <n>The high-level signal in is provided to the second input signal line of the first virtual shift register, thereby turning on the eighth transistor T8 of the first virtual shift register, and the low-level signal of the second scan input signal is written into the pull-up node of the first virtual shift register 。 Since the signal in the cascaded output signal line of the scan shift register is high level, this cascaded output signal line CR <n>The high-level signal in is supplied to the twenty-second transistor T22 of the first virtual shift register, turning on the twenty-second transistor T22. The high-level signal of the first scan input signal is supplied to the pull-down node of the first virtual shift register through the turned-on twenty-second transistor T22, thereby turning on the twenty-fourth transistor T24. The low-level signal of the first reference signal line VGL1 is written into the cascaded signal output terminal of the first virtual shift register through the turned-on twenty-fourth transistor T24, realizing the reset of the cascaded signal output terminal. The high-level signal of the pull-down node is also supplied to the twenty-sixth transistor T26, turning on the twenty-sixth transistor T26. The low-level signal of the second reference signal line VGL2 is written into the drive output terminal of the first virtual shift register through the turned-on twenty-sixth transistor T26, and the drive output terminal outputs a low-level signal. The high-level signal of the pull-down node is also supplied to the nineteenth transistor T19, turning on the nineteenth transistor T19. The low-level signal of the first reference signal line VGL1 is written into the pull-up node of the first virtual shift register through the turned-on nineteenth transistor T19, resetting the pull-up node.

[0240] Meanwhile, since the signal in the cascaded output signal line of the scan shift register is at a high level, this cascaded output signal line CR <n>The high-level signal in is provided to the twenty-first transistor T21' of the second virtual shift register. The twenty-first transistor T21' is turned on, and the low-level signal of the second scan input signal is written to the pull-down node of the second virtual shift register through the turned-on twenty-first transistor T21'.

[0241] Timing t4 stage: The invalid level signal of the first control signal line A1 in the level control unit 10, i.e., the first transistor T1, is turned off, and the valid level signal of the second control signal line A2, i.e., the second transistor T2, is turned on, and the valid level signal of the third control signal line A3, i.e., the third transistor T3, is turned on. The cascaded clock signal line CLKD_3 in the shift register unit 20 is at a high level, the clock signal line CLKE_3 is at a high level, the first reference signal line VGL1 is at a low level, the second reference signal line VGL2 is at a low level, and the frame start signal line STU is at a low level.

[0242] When the second transistor T2 is turned on, the high-level signal in the first scan control signal CN1 is provided to the first scan input signal line CN of the three shift registers, namely the first virtual shift register, the scan virtual shift register, and the second virtual shift register, through the first transmission line, making the signal on the first scan input signal line CN at a high level. When the third transistor T3 is turned on, the low-level signal in the second scan control signal CNB1 is provided to the second scan input signal line CNB of the three shift registers, namely the first virtual shift register, the scan virtual shift register, and the second virtual shift register, through the second transmission line, making the signal on the second scan input signal line CNB at a low level.

[0243] In the scan shift register, since the cascaded clock signal line CLKD_1 and the clock signal line CLKE_1 change from a high level to a low level, at this time, the cascaded output terminal CR in the scan shift register <n>and the drive output terminal OUT1 <n>All output low-level signals.

[0244] In the first virtual shift register, the eighth transistor T8 and the twenty-second transistor T22 are at the cascaded output terminal CR in the scan shift register <n>is turned off under the control of a low-level signal.

[0245] In the second virtual shift register, the seventh transistor T7' and the twenty-first transistor T21' are at the cascaded output terminal CR in the scan shift register <n>Turned off under the control of the low-level signal.

[0246] After the second virtual shift register cascade clock signal line CLKD_3 and the clock signal line CLKE_3 jump from low level to high level, due to the bootstrap effect of the third capacitor c3, the voltage of the pull-up node Q3 of the second virtual shift register is further raised, and the twenty-third transistor T23' and the twenty-fifth transistor T25' are fully turned on. The high level of the pull-up node Q3 of the second virtual shift register controls the eighteenth transistor T18' of the second virtual shift register to turn on. The low level of the first reference signal line VGL1 is written into the pull-down node Q3 of the second virtual shift register, and the high level of the clock signal line CLKE_3 is written into the drive output terminal OUT3 through the twenty-fifth transistor T25' <n>, that is, the drive output terminal OUT3 <n>Output a high-level signal. The high level of the cascaded clock signal line CLKD_3 is written into the cascaded output signal line CR through the twenty-third transistor T23'. <n>, namely the cascaded signal output terminal CR <n>Output a high-level signal.

[0247] Meanwhile, due to the cascaded output signal line CR of the second virtual shift register <n>The signal in is at a high level, and the cascaded output signal line CR <n>The high-level signal in is provided to the second input signal line of the scan shift register, thereby turning on the fifth transistor T5 of the scan shift register, and the low-level signal of the second scan input signal line CNB in the scan shift register is written into the pull-up node Q1 of the scan shift register 。 Due to the cascaded output signal line CR of the second virtual shift register <n>The signal in is at a high level, and the cascaded output signal line CR <n>The high-level signal in is supplied to the thirteenth transistor T13 of the scan shift register, causing the thirteenth transistor T13 to conduct. The high-level signal on the first scan input signal line CN is supplied to the pull-down node QB1 of the scan shift register through the conducting thirteenth transistor T13, and then the fifteenth transistor T15 of the scan shift register is caused to conduct. The low-level signal on the first reference signal line VGL1 is written to the cascade signal output terminal cr of the scan shift register through the conducting fifteenth transistor T15 <n>, to realize the reset of the cascaded signal output terminal.

[0248] Meanwhile, the high-level signal of the pull-down node QB1 of the scan shift register is also provided to the tenth transistor T10 of the scan shift register. The tenth transistor T10 is turned on, and the low-level signal of the first reference signal line VGL1 is written into the pull-up node Q1 of the scan shift register through the turned-on tenth transistor T10.

[0249] Timing t5 stage: The effective level signal of the first control signal line A1 in the level control unit 10, that is, the first transistor T1 is turned on, the ineffective level signal of the second control signal line A2, that is, the second transistor T2 is turned off, and the effective level signal of the third control signal line A3, that is, the third transistor T3 is turned on. The cascaded clock signal line CLKD_2 in the shift register unit 20 is at a low level, the clock signal line CLKE_2 is at a low level, the first reference signal line VGL1 is at a low level, the second reference signal line VGL2 is at a low level, the frame start signal line STU is at a high level, and the cascaded output signal line CR of the first virtual shift register <n>is at a low level, and the cascade signal output terminal OUT1 of the scan shift register is at a low level.

[0250] First of all, it should be supplemented that after a frame of the display panel is displayed, the signal in the frame start signal line STU is reset to a high level again.

[0251] When the third transistor T3 is turned on, the low-level signal in the second scan control signal CNB1 is provided to the second scan input signal line CNB of the three shift registers, namely the first virtual shift register, the scan virtual shift register, and the second virtual shift register, through the second transmission line, making the signal of the second scan input signal line CNB at a low level. When the first transistor T1 is turned on, the first transmission line and the second transmission line are connected, and the low-level signal in the second scan control signal CNB1 is transmitted to the first transmission line through the second transmission line. Then, the first transmission line provides the low-level signal to the first scan input signal line CN of the three shift registers, namely the first virtual shift register, the scan virtual shift register, and the second virtual shift register, through the second transmission line, making the signal of the first scan input signal line CN also at a low level.

[0252] When the signal of the frame start signal line STU is at a high level, the second input signal line of the second virtual shift register is at a high-level signal, and the eighth transistor T8' is turned on. The low-level signal of the second scan input signal line CNB is written into the pull-up node of the second virtual shift register through the turned-on eighth transistor T8'. At the same time, when the signal of the frame start signal line STU is at a high level, the twenty-second transistor T22' of the second virtual shift register is turned on, and the low-level signal of the first scan input signal line CN is written into the pull-down node Q3 of the second virtual shift register through the turned-on twenty-second transistor T22'. However, the high-level signal of the power supply signal line VDD turns on the twenty-fourth transistor T24' and the twenty-sixth transistor T26', and the low-level signal of the first reference signal line VGL1 is written into the cascade signal output terminal of the second virtual shift register through the turned-on twenty-fourth transistor T24', thereby realizing the reset of the cascade signal output terminal of the second virtual shift register. The low-level signal of the second reference signal line VGL2 is provided to the drive output terminal OUT3 of the second virtual shift register through the turned-on twenty-sixth transistor T26' <n>, thereby achieving the driving output terminal OUT3 of the second virtual shift register <n>Reset.

[0253] In addition, after scanning a frame of picture using the three shift registers, namely the first virtual shift register, the scan virtual shift register, and the second virtual shift register, and before scanning the next frame of picture, a frame reset of the gate driving circuit is required.

[0254] During the frame reset process, in the first virtual shift register, the high-level signal of the frame start signal line STU turns on the seventh transistor T7 of the third input module 201 of the first virtual shift register, and the low-level signal of the first scan input signal line CN is provided to the pull-up node Q2 of the first virtual shift register through the turned-on seventh transistor T7, thereby performing a frame reset.

[0255] During the frame reset process, in the scan shift register, the high-level signal of the frame start signal line STU turns on the sixth transistor T6 of the frame reset module of the scan shift register, and the low-level signal of the first reference signal line VGL1 is provided to the pull-up node Q1 of the scan shift register through the turned-on sixth transistor T6, thereby performing a frame reset.

[0256] During the frame reset process, in the second virtual shift register, the high-level signal of the frame start signal line STU turns on the eighth transistor T8' of the fourth input module 202 of the second virtual shift register, and the low-level signal of the second scan input signal line CNB is provided to the pull-up node Q3 of the second virtual shift register through the turned-on eighth transistor T8', thereby performing a frame reset.

[0257] In addition, it should be noted that the above process of using the frame start signal line STU for frame reset can also be applied to Figure 12 , Figure 13 and Figure 14 the circuits shown in, where the frame reset process is similar to the above Figure 7 , 9 and 10, and will not be elaborated one by one.

[0258] In addition, as shown in Figure 12 , due to the influence of the negative bias voltage, the pull-up node Q4 will have leakage. Therefore, the scan shift register in the embodiment of the present application further includes a compensation module, and the compensation module is configured to provide a high-level compensation signal to the pull-up node Q4 in response to the signal of the compensation signal line OE.

[0259] The above compensation module includes the twenty-seventh transistor T27, the twenty-eighth transistor T28, the twenty-ninth transistor T29, and the fourth capacitor c4. The control end of the twenty-seventh transistor T27 is electrically connected to the compensation signal line OE, and the first end of the twenty-seventh transistor T27 is connected to the cascade signal output end cr <n>Electrically connect, the second terminal of the twenty-seventh transistor T27 is electrically connected to the control terminal of the twenty-eighth transistor T28, the first terminal of the twenty-eighth transistor T28 is electrically connected to the compensated clock signal line CLKA, the second terminal of the twenty-eighth transistor T28 is electrically connected to the first terminal of the twenty-ninth transistor T29, the control terminal of the twenty-ninth transistor T29 is electrically connected to the compensated clock signal line CLKA, and the second terminal of the twenty-ninth transistor T29 is electrically connected to the pull-up node Q4. The first terminal of the fourth capacitor c4 is electrically connected to the control terminal of the twenty-eighth transistor T28, and the second terminal of the fourth capacitor c4 is electrically connected to the first reference signal line VGL1.

[0260] During the implementation process, the waveform of the compensation signal line OE and the cascaded signal output terminal cr <n>is consistent with the waveform when the cascaded signal output terminal is cr <n>When outputting a high-level signal, the compensation signal line OE is also a high-level signal, the twenty-seventh transistor T27 is turned on, and the cascaded signal output terminal cr <n>The high-level signal is provided to the control terminal of the twenty-eighth transistor T28 through the conducting twenty-seventh transistor T27. The twenty-eighth transistor T28 conducts, and the high-level signal of the compensation clock signal line CLKA is provided to the control terminal of the twenty-ninth transistor T29. The twenty-ninth transistor T29 conducts, and the high-level signal of the compensation clock signal line CLKA is provided to the pull-up node Q4 through the conducting twenty-eighth transistor T28 and twenty-ninth transistor T29 to compensate the level of the pull-up node Q4. The fourth capacitor C4 is used to maintain the potential of the control terminal of the twenty-eighth transistor T28. During the display stage of a frame of the picture, the control terminal of the twenty-eighth transistor T28 will write a high potential through the twenty-seventh transistor T27. Moreover, the high potential of the control terminal of the twenty-eighth transistor T28 will be maintained until the end of the display of a frame of the picture, that is, the blank area. In the blank area, the pull-up node Q4 writes a high potential through the twenty-eighth transistor T28 and twenty-ninth transistor T29.

[0261] In addition, the scan shift register further includes an auxiliary compensation module. When the pull-up node Q4 is written with a high potential, the auxiliary compensation module can pull down the pull-down node QB4. The auxiliary compensation module includes a thirtieth transistor T30 and a thirty-first transistor T31.

[0262] The control terminal of the thirtieth transistor T30 is electrically connected to the compensation clock signal line CLKA. The first end of the thirtieth transistor T30 is electrically connected to the pull-down node QB4. The second end of the thirtieth transistor T30 is electrically connected to the first end of the thirty-first transistor T31. The control terminal of the thirty-first transistor T31 is electrically connected to the control terminal of the twenty-eighth transistor T28. The second end of the thirty-first transistor T31 is electrically connected to the first reference signal line VGL1.

[0263] During the implementation process, when the compensation clock signal line CLKA is at a high potential, the thirtieth transistor T30 conducts. When the control terminal of the twenty-eighth transistor T28 is at a high potential, the thirty-first transistor T31 conducts. The low potential of the first reference signal line VGL1 is written to the pull-down node QB4 through the conducting thirtieth transistor T30 and thirty-first transistor T31, making the pull-down node QB4 at a low potential.

[0264] Based on the same inventive concept, an embodiment of the present application provides a display panel, including: a plurality of gate lines and the above-mentioned gate driving circuit;

[0265] The driving output terminal of a scan shift register in the gate driving circuit is electrically connected to one of the plurality of gate lines.

[0266] Based on the same inventive concept, an embodiment of the present application provides a display device, including the above-mentioned display panel.

[0267] The above display device provided by the embodiments of the present application may be any product or component with a display function, such as a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, etc. Other essential components of the display device are understood by those of ordinary skill in the art and will not be elaborated here, nor should they be regarded as a limitation to the present application.

[0268] Based on the same inventive concept, the embodiments of the present application provide a driving method for the above-mentioned gate driving circuit. Refer to Figure 15 as shown, including:

[0269] Step 201: Scanning stage: The level control unit 10, in response to the first control signal, writes the first scan control signal CN1 to the first scan input signal line CN, writes the second scan control signal CNB1 to the second scan input signal line CNB. The scan shift register inputs a scan driving signal to the gate line in response to the signals of the first scan input signal line CN and the second scan input signal line CNB, and the virtual shift register inputs a cascade driving signal to the scan shift register in response to the signals of the first scan input signal line CN and the second scan input signal line CNB.

[0270] During the implementation process, the level control unit 10 and the shift register unit 20 are used in cooperation. The above-mentioned level control unit 10 mainly provides different-level first scan control signals and second scan control signals for the shift register unit 20 during forward scanning, reverse scanning, and frame reset processes, so that the shift register unit 20 operates according to the first scan input signal and the second scan input signal during forward scanning, reverse scanning, and the frame reset process after removing the original tubes for frame reset.

[0271] During the forward scanning process, under the action of the first control signal, the level control unit 10 writes the first scan control signal CN1 to the first scan input signal line CN and writes the second scan control signal CNB1 to the second scan input signal line CNB, and then provides a high-level signal to the first scan input signal line CN of the scan shift register and the virtual shift register in the shift register unit 20, and provides a low-level signal to the second scan input signal line CNB of the scan shift register and the virtual shift register in the shift register unit 20. The virtual shift register inputs a cascade driving signal to the scan shift register under the control of the above first scan input signal and second scan input signal. The scan shift register inputs a scan driving signal to the gate line under the control of the above first scan input signal, second scan input signal, and cascade driving signal.

[0272] During the reverse scan process, under the action of the first control signal, the level control unit 10 writes the first scan control signal CN1 to the first scan input signal line CN, and writes the second scan control signal CNB1 to the second scan input signal line CNB, providing a low-level signal to the first scan input signal line CN of the scan shift register and the virtual shift register in the shift register unit 20, and providing a high-level signal to the second scan input signal line CNB of the scan shift register and the virtual shift register in the shift register unit 20. Under the control of the above first scan input signal and second scan input signal, the virtual shift register inputs a cascaded drive signal to the scan shift register. Under the control of the above first scan input signal, second scan input signal, and cascaded drive signal, the scan shift register inputs a scan drive signal to the gate line.

[0273] Step 202: Frame reset stage: The scan shift register responds to the frame start signal line STU to reset its pull-up node, and the virtual shift register responds to the signal of the frame start signal line STU to reset its pull-up node through the signal of the first scan input signal line CN and / or the second scan input signal line CNB; wherein, the level control unit 10 writes the second scan control signal CNB1 to the first scan input signal line CN and the second scan input signal line CNB of the scan shift register and the virtual shift register in response to the second control signal, or writes the first scan control signal CN1 to the first scan input signal line CN and the second scan input signal line CNB of the scan shift register and the virtual shift register in response to the third control signal.

[0274] In the embodiment of the present application, since the transistor originally used for frame reset is removed, therefore, before the next frame of the picture starts after a frame of the picture is displayed, the level control unit 10 and the shift register unit 20 need to cooperate to complete the frame reset work.

[0275] In the specific implementation process, after the forward scan ends, the level control unit 10 responds to the second control signal and writes the second scan control signal CNB1 to the first scan input signal lines CN and the second scan input signal line CNB of the scan shift register and the virtual shift register. That is, after the forward scan ends, low-level signals are input to both the first scan input signal line CN and the second scan input signal line CNB of the above-mentioned scan shift register and virtual shift register. The scan shift register responds to the frame start signal line STU and uses the sixth transistor T6 to reset its pull-up node. The virtual shift register responds to the signal of the frame start signal line STU and resets its pull-up node through the signal of the first scan input signal line CN and / or the second scan input signal line CNB. That is, the first virtual shift register responds to the signal of the frame start signal line STU and uses the seventh transistor T7 to reset its pull-up node through the signal of the first scan input signal line CN; the second virtual shift register responds to the signal of the frame start signal line STU and uses the eighth transistor T8 to reset its pull-up node through the signal of the second scan input signal line CNB.

[0276] In the specific implementation process, after the reverse scan ends, the level control unit 10 responds to the third control signal and writes the first scan control signal CN1 to the first scan input signal lines CN and the second scan input signal line CNB of the scan shift register and the virtual shift register. That is, after the forward scan ends, low-level signals are input to both the first scan input signal line CN and the second scan input signal line CNB of the above-mentioned scan shift register and virtual shift register. The scan shift register responds to the frame start signal line STU and uses the sixth transistor T6 to reset its pull-up node. The virtual shift register responds to the signal of the frame start signal line STU and resets its pull-up node through the signal of the first scan input signal line CN and / or the second scan input signal line CNB. That is, the first virtual shift register responds to the signal of the frame start signal line STU and uses the seventh transistor T7 to reset its pull-up node through the signal of the second scan input signal line CNB; the second virtual shift register responds to the signal of the frame start signal line STU and uses the eighth transistor T8 to reset its pull-up node through the signal of the first scan input signal line CN.

[0277] In summary, a gate driving circuit, a display panel, and a display device provided in an embodiment of the present application. The gate driving circuit includes: a shift register unit and a level control unit. The shift register unit includes a scanning shift register and a virtual shift register. The scanning shift register is electrically connected to a gate line and is configured to input a scanning driving signal to the gate line according to signals of a first scanning input signal line and a second scanning input signal line. The virtual shift register is electrically connected to the scanning shift register and is configured to input a cascading driving signal to the scanning shift register according to signals of the first scanning input signal line and the second scanning input signal line. The level control unit is electrically connected to the first scanning input signal line and the second scanning input signal line of the scanning shift register and the virtual shift register respectively, and is configured to, in response to a first control signal, write a first scanning control signal to the first scanning input signal line of the scanning shift register and the virtual shift register, write a second scanning control signal to the second scanning input signal line of the scanning shift register and the virtual shift register, in response to a second control signal, write the second scanning control signal to the first scanning input signal line and the second scanning input signal line of the scanning shift register and the virtual shift register, and, in response to a third control signal, write the first scanning control signal to the first scanning input signal line and the second scanning input signal line of the scanning shift register and the virtual shift register. After removing transistors for frame reset in the scanning shift register and the virtual shift register, combined with different conduction conditions of the level control unit, frame reset processing is performed on the scanning shift register and the virtual shift register, thereby reducing the number of transistors in the gate driving circuit, saving costs, and improving the panel yield.

[0278] Those skilled in the art should understand that the embodiments of the present application can be provided as a method, a system, or a computer program product system. Therefore, the present application can take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present application can take the form of a computer program product system implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0279] The present application is described with reference to the flowcharts and / or block diagrams of methods, devices (systems), and computer program product systems according to the present application. It should be understood that each flow and / or block in the flowcharts and / or block diagrams, as well as the combination of flows and / or blocks in the flowcharts and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing devices to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing devices generate for implementing in the process Figure 1 one or more processes and / or blocks Figure 1 means for the functions specified in one or more blocks

[0280] These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to work in a particular manner, such that the instructions stored in the computer-readable memory produce a manufacture including an instruction means that implements the processes Figure 1 one or more processes and / or blocks Figure 1 the functions specified in one or more blocks

[0281] These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus, such that a series of operational steps are performed on the computer or other programmable apparatus to produce a computer-implemented process, whereby the instructions executed on the computer or other programmable apparatus provide steps for implementing the functions specified in Figure 1 one or more processes and / or blocks Figure 1 the functions specified in one or more blocks

[0282] Obviously, those skilled in the art can make various changes and modifications to this application without departing from the spirit and scope of this application. Thus, if these modifications and variations of this application fall within the scope of the claims of this application and their equivalent technologies, this application is also intended to include these changes and modifications.< / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n>

Claims

1. A gate driving circuit, characterized in that, it includes: a shift register unit and a level control unit; The shift register unit includes a scan shift register and a dummy shift register. The scan shift register is electrically connected to a gate line and is configured to input a scan driving signal to the gate line according to signals of a first scan input signal line and a second scan input signal line. The dummy shift register is electrically connected to the scan shift register and is configured to input a cascade driving signal to the scan shift register according to signals of the first scan input signal line and the second scan input signal line; The level control unit is electrically connected to the first scan input signal line and the second scan input signal line of the scan shift register and the dummy shift register respectively, and is configured to, in response to a first control signal, write a first scan control signal to the first scan input signal line of the scan shift register and the dummy shift register, write a second scan control signal to the second scan input signal line of the scan shift register and the dummy shift register, in response to a second control signal, write the second scan control signal to the first scan input signal line and the second scan input signal line of the scan shift register and the dummy shift register, and, in response to a third control signal, write the first scan control signal to the first scan input signal line and the second scan input signal line of the scan shift register and the dummy shift register.

2. The circuit according to claim 1, characterized in that, the level control unit includes: a first control sub-unit, a second control sub-unit and a third control sub-unit; The control end of the first control sub-unit is electrically connected to a first control signal line, the first end of the first control sub-unit is electrically connected to a first transmission line, and the second end of the first control sub-unit is electrically connected to a second transmission line; The first control sub-unit is configured to conduct the first transmission line and the second transmission line in response to a valid level signal of the first control signal line; The control end of the second control sub-unit is electrically connected to a second control signal line, the first end of the second control sub-unit is electrically connected to the first transmission line, and the second end of the first control sub-unit is electrically connected to the first scan control signal line; The second control sub-unit is configured to write the first scan control signal to the first transmission line in response to a valid level signal of the second control signal line; The control end of the third control sub-unit is electrically connected to a third control signal line, the first end of the third control sub-unit is electrically connected to the second transmission line, and the second end of the third control sub-unit is electrically connected to the second scan control signal line; The third control sub-unit is configured to write the second scan control signal to the second transmission line in response to a valid level signal of the third control signal line.

3. The circuit according to claim 2, characterized in that, The first scan input signal lines of the scan shift register and the virtual shift register are electrically connected to the first transmission line, and the second scan input signal lines of the scan shift register and the virtual shift register are electrically connected to the second transmission line; The first control signal causes the first control signal line to provide an invalid level signal, the second control signal line to provide a valid level signal, and the third control signal line to provide a valid level signal; The second control signal causes the first control signal line to provide a valid level signal, the second control signal line to provide an invalid level signal, and the third control signal line to provide a valid level signal; The third control signal causes the first control signal line to provide a valid level signal, the second control signal line to provide a valid level signal, and the third control signal line to provide an invalid level signal.

4. The circuit according to claim 2, wherein, The first control sub-unit includes: a first transistor, the control end of the first transistor is electrically connected to the first control signal line, the first end of the first transistor is electrically connected to the first transmission line, and the second end of the first transistor is electrically connected to the second transmission line.

5. The circuit according to claim 2, wherein, The second control sub-unit includes: a second transistor, the control end of the second transistor is electrically connected to the second control signal line, the first end of the second transistor is electrically connected to the first scan control signal line, and the second end of the second transistor is electrically connected to the first transmission line.

6. The circuit according to claim 2, wherein, The third control sub-unit includes: a third transistor, the control end of the third transistor is electrically connected to the third control signal line, the first end of the third transistor is electrically connected to the second transmission line, and the second end of the third transistor is electrically connected to the second scan control signal line.

7. The circuit according to claim 1, wherein, The shift register unit includes a plurality of scan shift registers, and the plurality of scan shift registers are cascaded; The virtual shift register includes a first virtual shift register, the first input signal line of the first virtual shift register is electrically connected to the frame start signal line, the second input signal line of the first virtual shift register is electrically connected to the cascade signal output end of the first scan shift register among the plurality of scan shift registers, and the cascade output signal line of the first virtual shift register is electrically connected to the first input signal line of the first scan shift register.

8. The circuit according to claim 1, wherein, The shift register unit includes a plurality of scan shift registers, and the plurality of scan shift registers are cascaded; The virtual shift register includes a second virtual shift register, the first input signal line of the second virtual shift register is electrically connected to the cascade signal output end of the last scan shift register among the plurality of scan shift registers, the second input signal line of the second virtual shift register is electrically connected to the frame start signal line, and the cascade output signal line of the second virtual shift register is electrically connected to the second input signal line of the last scan shift register.

9. The circuit according to claim 7 or 8, characterized in that, the scan shift register includes: a first input module configured to provide the signal of the first scan input signal line to a pull-up node in response to the signal of the first input signal line; a second input module configured to provide the signal of the second scan input signal line to the pull-up node in response to the signal of the second input signal line; a first node control module configured to control the signals of the pull-up node and the pull-down node; a first cascaded output module configured to provide the signal of the cascaded clock signal line to a cascaded signal output terminal in response to the signal of the pull-up node; or provide the signal of the first reference signal line to the cascaded signal output terminal in response to the signal of the pull-down node; a first drive output module configured to provide the signal of the clock signal line to a drive output terminal in response to the signal of the pull-up node; or provide the signal of the second reference signal line to the drive output terminal in response to the signal of the pull-down node.

10. The circuit according to claim 9, characterized in that, the first input module includes: a fourth transistor; a control terminal of the fourth transistor is electrically connected to the first input signal line, a first end of the fourth transistor is electrically connected to the first scan input signal line, and a second end of the fourth transistor is electrically connected to the pull-up node.

11. The circuit according to claim 9, characterized in that, the second input module includes: a fifth transistor; a control terminal of the fifth transistor is electrically connected to the second input signal line, a first end of the fifth transistor is electrically connected to the pull-up node, and a second end of the fifth transistor is electrically connected to the second scan input signal line.

12. The circuit according to claim 9, characterized in that, it further includes: a frame reset module, the frame reset module is electrically connected to the pull-up node; the frame reset module is configured to provide the signal of the first reference signal line to the pull-up node in response to the signal of the frame start signal line.

13. The circuit according to claim 12, characterized in that, the frame reset module includes: a sixth transistor; a control terminal of the sixth transistor is electrically connected to the frame start signal line, a first end of the sixth transistor is electrically connected to the pull-up node, and a second end of the sixth transistor is electrically connected to the first reference signal line.

14. The circuit according to claim 7 or 8, characterized in that, the virtual shift register includes: a third input module configured to provide the signal of the first scan input signal line to a pull-up node in response to the signal of the first input signal line; a fourth input module configured to provide the signal of the second scan input signal line to the pull-up node in response to the signal of the second input signal line; a second node control module configured to control the signals of the pull-up node and the pull-down node; a second cascaded output module configured to provide the signal of the cascaded clock signal line to a cascaded output signal line in response to the signal of the pull-up node; or provide the signal of the first reference signal line to the cascaded output signal line in response to the signal of the pull-down node; The second driving output module is configured to supply the signal of the clock signal line to the driving output terminal in response to the signal of the pull-up node; or supply the signal of the second reference signal line to the driving output terminal in response to the signal of the pull-down node.

15. The circuit according to claim 14, wherein, the third input module includes: a seventh transistor; the control terminal of the seventh transistor is electrically connected to the first input signal line, the first terminal of the seventh transistor is electrically connected to the first scan input signal line, and the second terminal of the seventh transistor is electrically connected to the pull-up node.

16. The circuit according to claim 15, wherein, the fourth input module includes: an eighth transistor; the control terminal of the eighth transistor is electrically connected to the second input signal line, the first terminal of the eighth transistor is electrically connected to the pull-up node, and the second terminal of the eighth transistor is electrically connected to the second scan input signal line.

17. The circuit according to claim 13, wherein, it further includes a compensation module, and the compensation module is electrically connected to the pull-up node; the compensation module is configured to supply a high-level compensation signal to the pull-up node in response to the signal of the compensation signal line.

18. The circuit according to claim 17, wherein, the compensation module includes a twenty-seventh transistor, a twenty-eighth transistor, a twenty-ninth transistor, and a fourth capacitor; the control terminal of the twenty-seventh transistor is electrically connected to the compensation signal line, the first terminal of the twenty-seventh transistor is electrically connected to the cascaded signal output terminal, and the second terminal of the twenty-seventh transistor is electrically connected to the control terminal of the twenty-eighth transistor; the first terminal of the twenty-eighth transistor is electrically connected to the compensation clock signal line, and the second terminal of the twenty-eighth transistor is electrically connected to the first terminal of the twenty-ninth transistor; the control terminal of the twenty-ninth transistor is electrically connected to the compensation clock signal line, and the second terminal of the twenty-ninth transistor is electrically connected to the pull-up node; the first terminal of the fourth capacitor is electrically connected to the control terminal of the twenty-eighth transistor, and the second terminal of the fourth capacitor is electrically connected to the first reference signal line.

19. The circuit according to claim 18, wherein, it further includes an auxiliary compensation module, and the auxiliary compensation module includes a thirtieth transistor and a thirty-first transistor; the control terminal of the thirtieth transistor is electrically connected to the compensation clock signal line, the first terminal of the thirtieth transistor is electrically connected to the pull-down node, and the second terminal of the thirtieth transistor is electrically connected to the first terminal of the thirty-first transistor; the control terminal of the thirty-first transistor is electrically connected to the control terminal of the twenty-eighth transistor, and the second terminal of the thirty-first transistor is electrically connected to the first reference signal line.

20. A display panel, wherein, it includes: a plurality of gate lines and the gate driving circuit according to any one of claims 1 to 19; the driving output terminal of a scan shift register in the gate driving circuit is electrically connected to one of the plurality of gate lines.

21. A display device, wherein, it includes: the display panel according to claim 20.

22. A driving method for a gate driving circuit according to any one of claims 1 to 19, characterized in that, it includes: Scanning stage: The level control unit responds to the first control signal, writes the first scan control signal to the first scan input signal line, writes the second scan control signal to the second scan input signal line, the scan shift register responds to the signals of the first scan input signal line and the second scan input signal line to input a scan driving signal to the gate line, and the virtual shift register responds to the signals of the first scan input signal line and the second scan input signal line to input a cascading driving signal to the scan shift register; Frame reset stage: The scan shift register responds to the frame start signal line to reset its pull-up node, and the virtual shift register responds to the signal of the frame start signal line to reset its pull-up node through the signals of the first scan input signal line and / or the second scan input signal line; wherein, the level control unit responds to the second control signal and writes the second scan control signal to the first scan input signal line and the second scan input signal line of the scan shift register and the virtual shift register, or responds to the third control signal and writes the first scan control signal to the first scan input signal line and the second scan input signal line of the scan shift register and the virtual shift register.

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