8K liquid crystal screen TCON board and high-speed differential signal output method

Abstract

The invention provides an 8K liquid crystal screen TCON board and a high-speed differential signal output method thereof, the TCON board scales the vertical resolution of an input image to 1 / N of the vertical resolution of a liquid crystal screen, so that the line number of effective image data output in an image frame is 1 / N of the vertical resolution of the liquid crystal screen, and the value range of N is 2-4. According to the invention, the data transmission rate of the high-speed differential signal of the TCON board is reduced, and the high-speed differential signal is prevented from being output by using a high-speed transceiver, so that the cost of a main control chip of the 8K liquid crystal screen TCON board is greatly reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of TCON boards, in particular to an 8K liquid crystal display (LCD) TCON board, a high-speed differential signal output method thereof, and a TCON board. Background Art

[0002] With the development of technology, the resolution of liquid crystal displays is getting higher and higher. The data bandwidth required for a TCON board to drive a high-resolution liquid crystal display is very high. Taking an 8K liquid crystal display with a common resolution of 7680*4320, a refresh rate of 60 Hz, and 24 source driver chips as an example, the image data transmission bandwidth between the TCON board and the liquid crystal display is as high as about 65 Gbps. Each source driver chip on the liquid crystal display usually transmits image data by a pair of high-speed differential signals, and the data transmission rate of each pair of high-speed differential signals is as high as about 65 Gbps / 24 = 2.7 Gbps. Therefore, the TCON main control chip must integrate up to 24 high-speed data transmitters to normally drive the 8K liquid crystal display.

[0003] FPGA (Field Programmable Gate Array) is an integrated circuit with programmable characteristics pre-designed and implemented on a silicon wafer. The advantage of using an FPGA chip as the TCON main control chip is fast development speed, and both function customization and modification are very flexible. However, as described above, the FPGA chip must integrate 24 high-speed transceivers to meet the basic data transmission bandwidth requirements of the 8K liquid crystal display, and the price of an FPGA chip supporting 24 high-speed transceivers is very expensive, and the market is difficult to accept such a high cost. If the data transmission speed of the high-speed differential signals between the TCON board and the liquid crystal display can be reduced to less than 1.5 Gbps, then the ordinary differential ports of the FPGA can meet the data transmission bandwidth requirements, thereby greatly reducing the cost of the main control chip of the TCON board. Summary of the Invention

[0004] In order to overcome the deficiencies of the prior art, the present invention provides an 8K liquid crystal display TCON board and a high-speed differential signal output method thereof, which reduce the data transmission rate of the high-speed differential signals of the TCON board and avoid using high-speed transceivers to output high-speed differential signals, thereby greatly reducing the cost of the main control chip.

[0005] The technical solution adopted by the present invention to solve its technical problems is: a high-speed differential signal output method for an 8K liquid crystal display TCON board, characterized in that the TCON board scales the vertical resolution of the input image to 1 / N of the vertical resolution of the liquid crystal display, and the number of effective image data rows output within one image frame is 1 / N of the vertical resolution of the liquid crystal display, where N ranges from 2 to 4.

[0006] As a further preferred embodiment, after the high-speed differential signal outputs the image data of the Kth row, the liquid crystal screen starts to sequentially scan the pixels of the [(K - 1)*N + 1]th to K*Nth rows, where the value range of K is 1 to 4320 / N; the pixels of the [(K - 1)*N + 1]th to K*Nth rows of the liquid crystal screen jointly display the valid image data of the Kth row output by the TCON board.

[0007] The present invention also provides a TCON board, which is used to implement the above high-speed differential signal output method, and includes a main control chip, a GOA driving chip, a power supply circuit, an input interface and an output interface. The main control chip is connected to the output interface through 24 pairs or 48 pairs of high-speed differential signals, and the data transmission rate of each pair of high-speed differential signals is:

[0008]

[0009] As a further preferred embodiment, the main control chip is an FPGA or a chip integrating FPGA functions.

[0010] As a further preferred embodiment, the main control chip is composed of a signal decoding module, a GOA timing control module, and a resolution conversion and encoding module;

[0011] The signal decoding module is used to receive LVDS or V-by-One signals from the input interface, and after decoding the LVDS or V-by-One signals, it obtains the line and field synchronization signals and parallel image data;

[0012] The GOA timing control module is used to receive the line and field synchronization signals and generate GOA control signals;

[0013] The resolution conversion and encoding module is used to receive the parallel image data, and the image data after resolution conversion and encoding is transmitted to the output interface through high-speed differential signals.

[0014] As a further preferred embodiment, the horizontal resolution of the liquid crystal screen is 7680, and the vertical resolution is 4320.

[0015] As a further preferred embodiment, the data transmission efficiency is 0.6 to 0.9.

[0016] As a further preferred embodiment, the color bit number is 24 bits or 30 bits; the refresh rate is 60Hz or 120Hz.

[0017] The present invention also provides an electronic device, characterized by comprising: an FPGA or a chip integrating FPGA functions; and a memory for storing a configuration program of the FPGA or the chip integrating FPGA functions; wherein, the FPGA or the chip integrating FPGA functions is configured by the configuration program to execute the method for high-speed differential signal output of the 8K LCD panel TCON board.

[0018] Positive effects of the present invention:

[0019] 1. Significantly reduce the data transmission rate of high-speed differential signals

[0020] For the high-speed differential signal output method provided by the present invention, it adopts a grouped scanning mechanism, that is, when the TCON board drives the LCD panel to scan the pixels of the [(K - 1)*N + 1]th to K*Nth rows, the source driver chip of the LCD panel outputs the pixel voltages corresponding to the valid image data of the Kth row under the drive of the high-speed differential signal of the TCON board, and the pixels of the [(K - 1)*N + 1]th to K*Nth rows of the LCD panel jointly display the valid image data of the Kth row output by the TCON, so that the number of rows of valid image data output by the TCON board in one image frame is reduced to 1 / N of the vertical resolution of the LCD panel, and the data transmission rate of the high-speed differential signal of the TCON board is also correspondingly reduced to 1 / N of the existing transmission rate.

[0021] 2. Significantly reduce the cost of the main control chip

[0022] The present invention can reduce the data transmission speed of the high-speed differential signal between the TCON board and the LCD panel to below 1.5 Gbps. Therefore, the present invention can use an FPGA or a chip integrating FPGA functions as the main control chip of the TCON board, and only use the ordinary differential port of the FPGA to output high-speed differential signals, avoiding the use of high-speed transceivers to output high-speed differential signals, thereby greatly reducing the cost of the main control chip.

[0023] 3. Improve system compatibility and stability

[0024] Low-speed signals reduce electromagnetic interference and signal attenuation problems, enhancing system reliability; at the same time, the ordinary differential port design can simplify the PCB wiring difficulty and reduce the production complexity.

[0025] 4. Flexibly adapt to different resolution requirements

[0026] By adjusting the N value (2 - 4), the transmission rate and display effect can be dynamically balanced to adapt to high refresh rate (such as 120 Hz) or higher color depth (such as 30 bits) scenarios.

[0027] 5. Maintain display quality

[0028] The grouped scanning mechanism ensures that N rows of pixels are synchronously driven by each row of image data, avoiding screen tearing or latency and maintaining the display effect of 8K resolution.

[0029] 6. Extended application scenarios

[0030] The low-cost solution is applicable to consumer-grade 8K display devices (such as TVs and monitors), facilitating the popularization of high-resolution technologies. Brief description of the drawings

[0031] Figure 1 It is a schematic diagram of the overall frame structure of the TCON board described in the present invention;

[0032] Figure 2 It is a schematic diagram of the functional structure of the main control chip described in the present invention;

[0033] Figure 3 It is a schematic diagram of the output of the high-speed differential signal described in the present invention. Detailed implementation manners

[0034] The preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0035] Refer to Figure 3 , the preferred embodiment of the present invention first provides a method for transmitting high-speed differential signals of an 8K liquid crystal display TCON board, wherein the TCON board scales the vertical resolution of the input image to 1 / N of the vertical resolution of the liquid crystal display, and the number of effective image data rows output within one image frame is 1 / N of the vertical resolution of the liquid crystal display, and the value range of N is 2 to 4.

[0036] Specifically, taking an 8K LCD screen with a resolution of 7680*4320 as an example, the TCON board scales the vertical resolution of the input image to 1 / N of the vertical resolution of the LCD screen (i.e., 4320 / N). After the first row of image data of the high-speed differential signal of the TCON board is output, the LCD screen starts to sequentially scan the first to N rows of pixels. After the second row of image data of the high-speed differential signal is output, the LCD screen starts to sequentially scan the (N + 1)th to 2Nth rows of pixels. After the third row of image data of the high-speed differential signal is output, the LCD screen starts to sequentially scan the (2N + 1)th to 3Nth rows of pixels, and so on. After the 4320 / Nth row of image data of the high-speed differential signal is output, the LCD screen starts to sequentially scan the (4320 - N + 1)th to 4320th rows of pixels. That is, after the Kth row of image data of the high-speed differential signal is output, the LCD screen starts to sequentially scan the [(K - 1)*N + 1]th to K*Nth rows of pixels, where the value range of K is 1 to 4320 / N. With the present invention, when the LCD screen scans the [(K - 1)*N + 1]th to K*Nth rows of pixels, the source driver chip of the LCD screen outputs the pixel voltages corresponding to the Kth row of valid image data under the drive of the high-speed differential signal of the TCON board, and the [(K - 1)*N + 1]th to K*Nth rows of pixels of the LCD screen jointly display the Kth row of valid image data output by the TCON, thereby reducing the number of rows of valid image data output by the TCON board in one image frame to 4320 / N, and correspondingly reducing the data transmission rate of the high-speed differential signal of the TCON board to 1 / N of the existing transmission rate.

[0037] Among them, Figure 3 is a schematic diagram of the output of the high-speed differential signal of the TCON board of the present invention. In one frame time, the high-speed differential signal sequentially outputs the first row of image data, the second row of image data, the third row of image data, until the "4320 / N"th row of image data. There is a line idle interval between adjacent rows of image data, and a frame idle interval between adjacent frames. During the line idle and frame idle periods, the high-speed differential signal outputs clock training data, configuration data, etc. required by the encoding protocol. One frame time is determined by the refresh rate and is 1 / 60 second or 1 / 120 second.

[0038] That is, the present invention adopts a grouped scanning mechanism (as Figure 3 shown), divides the vertical resolution of the LCD screen (4320 rows) into 4320 / N groups (N = 2 to 4), and each group contains N rows of pixels; every time the TCON board outputs one row of valid image data, the LCD screen synchronously scans N rows of pixels. Through this mechanism, the number of rows of valid data output by the TCON board per frame is reduced to 4320 / N, and the data transmission rate is correspondingly reduced to 1 / N of the original rate.

[0039] Such as Figure 1 and Figure 2As shown in the figure, a preferred embodiment of the present invention further provides a TCON board, which is used to implement the above-mentioned high-speed differential signal output method. It includes a main control chip, a GOA driving chip, a power supply circuit, an input interface and an output interface. The main control chip is connected to the output interface through 24 pairs or 48 pairs of high-speed differential signals. The data transmission rate of each pair of high-speed differential signals is:

[0040]

[0041] Among them, the input interface of the TCON board is used to input LVDS or V-by-One signals to the TCON board and the power supply of the TCON board.

[0042] The GOA driving chip is driven by the GOA control signal generated by the main control chip of the TCON board to generate the GOA driving signal for the liquid crystal screen. The GOA driving signal for the liquid crystal screen is connected to the output interface of the TCON board.

[0043] The main control chip is composed of a signal decoding module, a GOA timing control module, and a resolution conversion and encoding module;

[0044] The signal decoding module is used to receive LVDS or V-by-One signals from the input interface. After decoding the LVDS or V-by-One signals, the line-field synchronization signal and parallel image data are obtained;

[0045] The GOA timing control module is used to receive the line-field synchronization signal and generate the GOA control signal;

[0046] The resolution conversion and encoding module is used to receive parallel image data. The image data after resolution conversion and encoding is transmitted to the output interface through high-speed differential signals. Among them, the main control chip of the TCON board uses the general differential port of the FPGA to output high-speed differential signals. The main control chip of the TCON board is connected to the output interface of the TCON board through 24 pairs or 48 pairs of high-speed differential signals. The data transmission rate of each pair of high-speed differential signals is (taking an 8K liquid crystal screen with a resolution of 7680*4320 as an example):

[0047]

[0048] The power supply circuit is used to generate the working voltage of the main control chip of the TCON board and the working voltage of the liquid crystal screen. The working voltage of the main control chip is connected to the main control chip to provide power for the main control chip. The working voltage of the liquid crystal screen is connected to the output interface of the TCON board to provide power for the liquid crystal screen.

[0049] The output interface of the TCON board outputs the GOA driving signal for the liquid crystal screen, high-speed differential signals and the working voltage of the liquid crystal screen to the externally connected liquid crystal screen.

[0050] Among them, the main control chip is an FPGA or a chip integrating FPGA functions. The ordinary differential ports of the FPGA are used to output high-speed differential signals, avoiding the use of high-speed transceivers to output high-speed differential signals, thus greatly reducing the cost of the main control chip.

[0051] In addition, the definition of the data transmission efficiency is the total number of bits of valid image data sent by the TCON board through high-speed differential signals within one frame / the total number of bits of transmitted data. The total number of bits of transmitted data includes not only valid image data but also clock training data, configuration data, etc. The value range of the data transmission efficiency is 0.6 to 0.9.

[0052] In addition, the number of color bits is 24 bits or 30 bits; the refresh rate is 60 Hz or 120 Hz.

[0053] Taking the common resolution of 7680*4320, N = 2, refresh rate 60 Hz, color 24 bits, data transmission efficiency 0.8, and the number of pairs of high-speed differential signals being 24 pairs as an example:

[0054] The data transmission rate of each pair of high-speed differential signals is 2.7 / 2 = 1.35 Gbps of the traditional scheme. The rate is lower than 1.5 Gbps, which can meet the performance of ordinary FPGA differential ports, that is, the ordinary FPGA differential ports of the present invention can meet the bandwidth requirements of data transmission, thus greatly reducing the cost of the main control chip of the TCON board.

[0055] In addition, the preferred embodiment of the present invention also provides an electronic device, which is characterized by including: an FPGA or a chip integrating FPGA functions; and a memory for storing the configuration program of the FPGA or the chip integrating FPGA functions; among them, the FPGA or the chip integrating FPGA functions is configured by the configuration program to execute the method for outputting high-speed differential signals of the 8K LCD screen TCON board.

[0056] The above are only the preferred embodiments of the present invention. It should be understood that the description of the above embodiments is only used to help understand the method and its core idea of the present invention, and is not used to limit the protection scope of the present invention. Any modifications, equivalent replacements, etc. made within the thought and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A high-speed differential signal output method for an 8K LCD screen TCON board, characterized in that: The TCON board scales the vertical resolution of the input image to 1 / N of the vertical resolution of the LCD screen, and the number of valid image data rows it outputs in one image frame is 1 / N of the vertical resolution of the LCD screen, with N ranging from 2 to 4.

2. According to claim 1, a high-speed differential signal output method for an 8K LCD screen TCON board is characterized in that: After the Kth row of image data of the high-speed differential signal is output, the LCD screen starts to scan the pixels of [(K-1)*N+1] to K*N rows in sequence, and the value range of K is 1 to 4320 / N; the pixels of [(K-1)*N+1] to K*N rows of the LCD screen jointly display the Kth row of valid image data output by the TCON board.

3. A TCON board, characterized in that: The TCON board is used to implement the high-speed differential signal output method described in claim 1 or 2, and includes a main control chip, a GOA driver chip, a power supply circuit, an input interface and an output interface. The main control chip and the output interface are connected through 24 pairs or 48 pairs of high-speed differential signals, and the data transmission rate of each pair of high-speed differential signals is:

4. A TCON board according to claim 3, characterized in that: The main control chip is FPGA or a chip integrating FPGA function.

5. A TCON board according to claim 4, characterized in that: The main control chip is composed of a signal decoding module, a GOA timing control module, and a resolution conversion and encoding module; The signal decoding module is used to receive the LVDS or V-by-One signal from the input interface, and obtain the line field synchronization signal and the parallel image data after decoding the LVDS or V-by-One signal; The GOA timing control module is used to receive the horizontal and vertical synchronization signals and generate the GOA control signals; The resolution conversion and encoding module is used to receive parallel image data, and the image data after resolution conversion and encoding is transmitted to the output interface through a high-speed differential signal.

6. A TCON board according to claim 3, characterized in that: The horizontal resolution of the LCD screen is 7680 and the vertical resolution is 4320.

7. A TCON board according to claim 3, characterized in that: The data transmission efficiency is 0.6-0.

9.

8. A TCON board according to claim 3, characterized in that: The color bit number is 24 bits or 30 bits.

9. A TCON board according to claim 3, characterized in that: The refresh rate is 60 Hz or 120 Hz.

10. An electronic device, characterized in that: include: FPGA or chip with integrated FPGA function; And a memory for storing a configuration program of the FPGA or a chip with integrated FPGA function; wherein the FPGA or the chip with integrated FPGA function is configured by the configuration program to execute the 8K LCD screen TCON board high-speed differential signal output method according to claim 1 or 2.

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