Memory device and method of operating the same

Abstract

The present technology relates to a memory device and a method of operating the same. The memory device includes: a plurality of memory blocks each including a plurality of memory cells; a peripheral circuit configured to perform a background operation and a rewrite operation on a selected memory block among the plurality of memory blocks; and a control logic configured to control the peripheral circuit to perform a background operation and a rewrite operation, and control the peripheral circuit to perform the rewrite operation based on an amount of valid data stored in the selected memory block, the rewrite operation includes increasing a threshold voltage of a plurality of memory cells of the selected memory block to at least a predetermined threshold voltage value.

Description

Technical Field

[0001] The present disclosure relates to an electronic device, and more particularly, to a memory device and a method of operating the memory device. Background Art

[0002] Non-volatile memory devices have relatively slow write and read speeds, but can retain stored data even when power is off. Thus, non-volatile memory devices are generally used to store data that needs to be retained whether power is supplied or not. Examples of non-volatile memory devices include read-only memory (ROM), mask ROM (MROM), programmable ROM (PROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, phase change random access memory (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), ferroelectric RAM (FRAM), etc. Flash memory is classified as NOR type or NAND type.

[0003] Flash memory has the advantages of RAM in freely programming and erasing data and of ROM in retaining stored data even when power is off. Flash memory is widely used as a storage medium for portable electronic devices such as digital cameras, personal digital assistants (PDAs), and MP3 players. Summary of the Invention

[0004] According to an embodiment of the present disclosure, a memory device includes: a plurality of memory blocks, each including a plurality of memory cells; a peripheral circuit configured to perform a background operation and a rewrite operation on a selected one of the plurality of memory blocks; and control logic configured to control the peripheral circuit to perform the background operation and the rewrite operation, and the control logic controls the peripheral circuit to perform the rewrite operation based on an amount of valid data stored in the selected memory block, the rewrite operation including increasing threshold voltages of the plurality of memory cells of the selected memory block to at least a predetermined threshold voltage value.

[0005] According to an embodiment of the present disclosure, a method of operating a memory device includes: determining an amount of valid data stored in a selected memory block; when the amount of valid data is less than a predetermined value, performing a write-back operation on the selected memory block; and performing a rewrite operation on selected memory cells corresponding to an erased state or an erased state and at least one programmed state among the memory cells included in the selected memory block.

[0006] According to one embodiment of the present disclosure, a method of operating a memory device includes: determining an amount of valid data stored in a selected memory block on which a background operation is performed; identifying the selected memory block as a rewrite operation target memory block based on the amount of valid data; performing a write-back operation that includes storing the valid data stored in the selected memory block in a target memory block; and performing a rewrite operation after the write-back operation, the rewrite operation including increasing threshold voltages of selected memory cells corresponding to an erased state or an erased state and at least one programmed state among the memory cells included in the selected memory block to at least a predetermined threshold voltage value.

[0007] According to one embodiment of the present disclosure, a method includes: determining an amount of valid data stored in a first memory block among a plurality of memory blocks; when the amount of valid data is less than a predetermined value, performing a write-back operation that includes storing the valid data stored in the first memory block in a second memory block among the plurality of memory blocks; and performing a rewrite operation based on the amount of valid data stored in the first memory block, the rewrite operation including increasing threshold voltages of a plurality of memory cells of the first memory block to at least a predetermined threshold voltage value. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a diagram illustrating a memory system according to an embodiment of the present disclosure.

[0009] Figure 2 is a diagram illustrating a memory device according to an embodiment of the present disclosure.

[0010] Figure 3 is a diagram illustrating a rewrite manager according to an embodiment of the present disclosure.

[0011] Figure 4 is a diagram illustrating a memory block according to an embodiment of the present disclosure.

[0012] Figure 5 is a diagram illustrating an embodiment of a memory block in a three-dimensional configuration.

[0013] Figure 6A , Figure 6B , Figure 6C , Figure 6D and Figure 6E is a diagram illustrating a phenomenon in which threshold voltages of memory cells are reduced due to holes present in regions between memory cells.

[0014] Figure 7 is a diagram illustrating a threshold voltage distribution in which threshold voltages of programmed memory cells are reduced according to retention characteristics.

[0015] Figure 8is a flowchart showing a method of operating a memory device according to an embodiment of the present disclosure.

[0016] Figure 9A is a diagram showing the threshold voltage distribution of memory cells during a rewrite operation of a memory device according to an embodiment of the present disclosure.

[0017] Figure 9B is a diagram showing the threshold voltage distribution of memory cells during a rewrite operation of a memory device according to another embodiment of the present disclosure.

[0018] Figure 10 is a diagram showing another embodiment of a memory system including a memory device.

[0019] Figure 11 is a diagram showing another embodiment of a memory system including a memory device.

[0020] Figure 12 is a diagram showing another embodiment of a memory system including a memory device.

[0021] Figure 13 is a diagram showing another embodiment of a memory system including a memory device. Detailed Embodiments

[0022] A specific structural description or functional description of an embodiment according to the concept disclosed in this specification or this application is an example of describing an embodiment according to the concept of the present disclosure. Embodiments according to the concept of the present disclosure can be implemented in various forms and should not be construed as limited to the embodiments described in this specification or this application.

[0023] Various embodiments of the present disclosure are described with reference to the accompanying drawings in sufficient detail to allow a person of ordinary skill in the art to easily implement the technical aspects of the present disclosure.

[0024] Embodiments of the present disclosure provide a memory device and a method of operating the memory device that can improve the retention characteristic of the memory device. According to the present disclosure, the retention characteristic of memory cells can be improved by performing a rewrite operation on a storage block when the amount of valid data is less than a predetermined value.

[0025] Figure 1 is a diagram showing a memory system according to an embodiment of the present disclosure.

[0026] Referring Figure 1 , under the control of the host 2000, the memory system 1000 includes a memory device 1100 in which data is stored and a memory controller 1200 that controls the memory device 1100.

[0027] The host 2000 communicates with the memory system 1000 using an interface protocol, such as Peripheral Component Interconnect-Express (PCIE), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), or Serial Attached SCSI (SAS). Additionally, the interface protocol between the host 2000 and the memory system 1000 is not limited to the above examples and can be one of various other interface protocols such as Universal Serial Bus (USB), Multimedia Card (MMC), Enhanced Small Disk Interface (ESDI), and Integrated Drive Electronics (IDE).

[0028] The memory controller 1200 controls the overall operation of the memory system 1000 and controls the data exchange between the host 2000 and the memory device 1100. For example, the memory controller 1200 programs or reads data by controlling the memory device 1100 according to a request received from the host 2000. For example, the memory device 1100 may include Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), Low Power Double Data Rate 4 (LPDDR4) SDRAM, Graphics Double Data Rate (GDDR) SDRAM, Low Power DDR (LPDDR), Rambus Dynamic Random Access Memory (RDRAM), or flash memory. The memory controller 1200 may control the memory device 1100 to perform background operations autonomously, independent of a request from the host 2000. For example, the memory controller 1200 may control the memory device 1100 to perform read scavenging, garbage collection, or read refresh operations.

[0029] The memory device 1100 performs programming operations, read operations, erase operations, and background operations under the control of the memory controller 1200.

[0030] When the amount of valid data in the programmed data in the selected storage block is less than a predetermined value, or when no valid data is stored in the selected storage block, the memory device 1100 performs a rewrite operation on the selected storage block. For example, when the amount of valid data in the programmed data in the selected storage block is less than a predetermined value, the memory device 1100 performs a rewrite operation on the selected storage block after performing a copyback operation, which includes reading the programmed valid data from the selected storage block and programming the programmed valid data into another storage block. When no valid data is stored in the programmed or stored data in the selected storage block, the memory device 1100 performs a rewrite operation on the selected storage block without performing a copyback operation. The rewrite operation includes, for example, operations that include increasing the threshold voltages of the memory cells corresponding to the erased state or the erased state and at least one programmed state among the memory cells included in the selected storage block to at least a predetermined threshold voltage value or a value greater than or equal to the predetermined threshold voltage value. The at least one programmed state may be a programmed state with a relatively low threshold voltage distribution among the plurality of programmed states. The predetermined value includes a value that can be determined in advance or can be determined when used in a process or algorithm. The value can be determined at the start of the process or algorithm, or can be determined during the execution of the process or algorithm.

[0031] Figure 2 is a diagram showing, for example Figure 1 the memory device shown in

[0032] Referring to Figure 2 , the memory device 1100 includes a memory cell array 100 in which data is stored. The memory device 1100 includes a peripheral circuit 200 configured to perform a programming operation for storing data in the memory cell array 100, a read operation for outputting the stored data, and an erase operation for erasing the stored data.

[0033] The memory device 1100 includes a control logic 300 that controls the peripheral circuit 200 under the control of a memory controller 1200 in Figure 1 .

[0034] The memory cell array 100 includes a plurality of memory blocks MB1 to MBk (where k is a positive integer). Local lines LL and bit lines BL1 to BLm (where m is a positive integer) are connected to each of the memory blocks MB1 to MBk. For example, the local lines LL include a first select line, a second select line, and a plurality of word lines arranged between the first select line and the second select line. The local lines LL may include dummy lines arranged between the first select line and the word lines and between the second select line and the word lines. For example, the first select line may be a source select line, and the second select line may be a drain select line. For example, the local lines LL include word lines, drain select lines, source select lines, and source lines SL. For example, the local line L1 may include pipeline lines. According to an embodiment of the present disclosure, the word lines may be divided into a plurality of groups.

[0035] The local lines LL are connected to the memory blocks MB1 to MBk, and the bit lines BL1 to BLm are commonly connected to the memory blocks MB1 to MBk. The memory blocks MB1 to MBk may be implemented as a two-dimensional structure or a three-dimensional structure. For example, in the memory blocks of the two-dimensional structure, pages may be arranged in a direction parallel to or horizontal with respect to the substrate. For example, in the memory blocks of the three-dimensional structure, pages may be arranged in a direction perpendicular to the substrate.

[0036] The peripheral circuit 200 is configured to perform a programming operation, a read operation, and an erase operation on a selected memory block under the control of the control logic 300. In addition, the peripheral circuit 200 is configured to perform a write-back operation and a rewrite operation. The write-back operation includes moving and storing valid data stored in a selected memory block among the plurality of memory blocks MB1 to MBk included in the memory cell array 100 to another memory block, and the rewrite operation includes increasing the threshold voltage of the memory cells included in the selected memory block to at least a predetermined threshold voltage value. For example, the predetermined threshold voltage value may be greater than 0V.

[0037] For example, under the control of the control logic 300, the peripheral circuit 200 provides a verification voltage and a pass voltage to the first select line, the second select line, and the word lines, selectively discharges the first select line, the second select line, and the word lines, and verifies the memory cells connected to the selected word line among the word lines. For example, the peripheral circuit 200 may include a voltage generation circuit 210, a row decoder 220, a page buffer bank 230, a column decoder 240, an input / output circuit 250, and a sensing circuit 260.

[0038] The voltage generation circuit 210 generates various operation voltages Vop used in programming operations, read operations, and erase operations in response to the operation signal OP-CMD. The voltage generation circuit 210 selectively discharges the local line LL in response to the operation signal OP-CMD. For example, the voltage generation circuit 210 generates a programming voltage, a verification voltage, a pass voltage, a turn-on voltage, a read voltage, a first erase voltage, a source line voltage, etc. under the control of the control logic 300.

[0039] The row decoder 220 transfers or applies the operation voltage Vop to the local line LL connected to the selected memory block in response to receiving the row address RADD.

[0040] The page buffer group 230 includes a plurality of page buffers PB1 to PBm respectively connected to bit lines BL1 to BLm. The page buffers PB1 to PBm operate in response to receiving the page buffer control signals PBSIGNALS. For example, the page buffers PB1 to PBm temporarily store data received through the bit lines BL1 to BLm or sense the voltage or current of the bit lines BL1 to BLm during a read operation or a verification operation.

[0041] The column decoder 240 transfers data between the input / output circuit 250 and the page buffer group 230 in response to receiving the column address CADD. For example, the column decoder 240 exchanges data with the page buffers PB1 to PBm through the data lines DL, or exchanges data with the input / output circuit 250 through the column lines CL.

[0042] The input / output circuit 250 transfers the command CMD and the address ADD received from Figure 1 the memory controller 1200 to the control logic 300, and exchanges data DATA with the column decoder 240.

[0043] During a read operation or a verification operation, the sense circuit 260 generates a reference current in response to receiving the enable bit VRY-BIT<#>, compares the sense voltage VPB received from the page buffer group 230 with the reference voltage generated by the reference current, and outputs a pass signal PASS or a fail signal FAIL as the result of the comparison.

[0044] The control logic 300 outputs the operation signal OP-CMD, the row address RADD, the page buffer control signals PBSIGNALS, and the enable bit VRY-BIT<#> in response to receiving the command CMD and the address ADD to control the peripheral circuit 200. In addition, the control logic 300 determines whether the verification operation passes or fails in response to receiving the pass signal PASS or the fail signal FAIL.

[0045] The control logic 300 may control the peripheral circuit 200 to perform a programming operation or an erasing operation on a selected memory block among a plurality of memory blocks MB1 to MBk included in the memory cell array 100.

[0046] The control logic 300 controls the peripheral circuit 200 to perform a write-back operation including programming valid data stored in the selected memory block into another memory block (referred to as a target memory block), and controls the peripheral circuit 200 to perform a rewrite operation including programming memory cells included in the selected memory block to a threshold voltage greater than a predetermined value after performing the write-back operation.

[0047] The control logic 300 includes a rewrite manager 310 which controls the write-back operation and the rewrite operation on the selected memory block. The rewrite manager 310 determines the amount of valid data in the data stored in the selected memory block, and when the amount of the checked valid data is less than a predetermined value, controls the peripheral circuit 200 to perform the write-back operation and the rewrite operation on the selected memory block.

[0048] Figure 3 is a diagram showing, for example Figure 2 the rewrite manager as shown in

[0049] Referring to Figure 3 , the rewrite manager 310 includes a memory block status determiner 311, a write-back operation controller 312, a rewrite operation controller 313, and a control signal generator 314.

[0050] In one embodiment, the memory block status determiner 311 determines whether the selected memory block is eligible as a rewrite operation target memory block based on the amount of valid data in the data stored in the selected memory block. For example, when the amount of valid data in the data stored in the selected memory block is less than a predetermined value, the memory block status determiner 311 determines or identifies the selected memory block as a rewrite operation target memory block. When the amount of valid data in the data stored in the selected memory block is equal to or greater than the predetermined value, the memory block status determiner 311 determines or identifies the selected memory block as a memory block other than the rewrite operation target memory block.

[0051] In another embodiment, the memory block status determiner 311 determines or identifies the selected memory block as a rewrite operation target memory block based on the ratio of valid data in all the data stored in the selected memory block. For example, when the ratio of valid data in all the data stored in the selected memory block is less than a predetermined ratio value, the memory block status determiner 311 determines or identifies the selected memory block as a rewrite operation target memory block. When the ratio of valid data in all the data stored in the selected memory block is equal to or greater than the predetermined ratio value, the memory block status determiner 311 determines or identifies the selected memory block as a memory block other than the rewrite operation target memory block.

[0052] For example, the storage block status determiner 311 may calculate the amount or ratio of valid data of the selected storage block by counting the amount of pages storing valid data among the multiple pages included in the selected storage block.

[0053] When the selected storage block is determined or identified as the storage block for rewrite operation and at least one valid data exists in or is stored in the selected storage block, the storage block status determiner 311 generates and outputs a write-back activation signal ACT-CB and a rewrite activation signal ACT-OW.

[0054] When the selected storage block is determined or identified as the storage block for rewrite operation and no valid data is stored in the selected storage block, the storage block status determiner 311 deactivates the write-back activation signal ACT-CB and only generates and outputs the rewrite activation signal ACT-OW. Therefore, no write-back operation is performed on the selected storage block.

[0055] In response to receiving the write-back activation signal ACT-CB, the write-back operation controller 312 generates and outputs a write-back control signal CB-CTR, which corresponds to a read operation of the valid data stored in the selected storage block and a valid data programming operation including storing the read valid data in a storage block other than the selected storage block.

[0056] The rewrite operation controller 313 generates and outputs a rewrite control signal OW-CTR in response to the rewrite activation signal ACT-OW, which corresponds to a rewrite operation of increasing the threshold voltage value of the memory cells included in the selected storage block to at least a predetermined threshold voltage value.

[0057] In response to the write-back control signal, the control signal generator 314 generates an operation signal OP-CMD, a row address RADD, and a page buffer control signal PBSIGNALS, and outputs the operation signal OP-CMD, the row address RADD, and the page buffer control signal PBSIGNALS to Figure 2 the peripheral circuit 200 to perform a read operation of the valid data stored in the selected storage block and a valid data programming operation including storing the read valid data in a storage block other than the selected storage block.

[0058] In response to the rewrite control signal OW-CTR, the control signal generator 314 generates an operation signal OP-CMD, a row address RADD, and a page buffer control signal PBSIGNALS, and outputs the operation signal OP-CMD, the row address RADD, and the page buffer control signal PBSIGNALS to Figure 2 the peripheral circuit 200 to perform a rewrite operation including increasing the threshold voltage value of the memory cells included in the selected storage block to at least a predetermined threshold voltage value.

[0059] Figure 4 is a diagram showing, for example, Figure 2 the memory block shown.

[0060] Referring to Figure 4 , a plurality of word lines arranged parallel to each other between a first select line and a second select line are connected to the memory block. In this example, the first select line is a source select line SSL, and the second select line is a drain select line DSL. The memory block includes a plurality of memory strings ST connected between bit lines BL1 to BLm and a source line SL. Each of the bit lines BL1 to BLm is connected to a different one of the memory strings ST in the memory string ST, and the source line SL is commonly connected to the memory strings ST. Since each of the memory strings ST is similarly configured, one memory string ST connected to the first bit line BL1 will be described as an example.

[0061] The memory string ST includes a source select transistor SST connected in series between the source line SL and the first bit line BL1, a plurality of memory cells MC1 to MC16, and a drain select transistor DST. One memory string ST may include at least one source select transistor SST and at least one drain select transistor DST, and may include more memory cells than the memory cells MC1 to MC16 shown in the figure.

[0062] The source of the source select transistor SST is connected to the source line SL, and the drain of the drain select transistor DST is connected to the first bit line BL1. The memory cells MC1 to MC16 are connected in series between the source select transistor SST and the drain select transistor DST. The gates of the source select transistors SST included in different memory strings ST are connected to the source select line SSL, the gates of the drain select transistors DST included in different memory strings ST are connected to the drain select line DSL, and the gates of the memory cells MC1 to MC16 are connected to different ones of the plurality of word lines WL1 to WL16. A set of memory cells connected to the same word line among the memory cells included in different memory strings ST may be referred to as a page PG. In this example, the memory block includes the same number of pages PG as the number of word lines WL1 to WL16.

[0063] Each of the memory cells MC1 to MC16 may be configured as a single-level cell (SLC) storing one data bit, a multi-level cell (MLC) storing two data bits, a triple-level cell (TLC) storing three data bits, or a quad-level cell (QLC) capable of storing four data bits.

[0064] Figure 5 is a diagram showing an embodiment of a memory block configured as a three-dimensional (3D) structure.

[0065] Referring to Figure 5, the memory cell array 100 may include a plurality of memory blocks MB1 to MBk. For the sake of simplicity of description and the drawings, the internal configuration of the first memory block MB1 is shown, while the internal configurations of the remaining memory blocks MB2 to MBk are omitted. It is beneficial that the second memory block MB2 to the kth memory block MBk are configured similarly to the first memory block MB1. Figure 5 For the sake of simplicity of description and the drawings, the internal configuration of the first memory block MB1 is shown, while the internal configurations of the remaining memory blocks MB2 to MBk are omitted. It is beneficial that the second memory block MB2 to the kth memory block MBk are configured similarly to the first memory block MB1.

[0066] The first memory block MB1 includes a plurality of memory strings ST11 to ST1m and ST21 to ST2m. Each of the plurality of memory strings ST11 to ST1m and ST21 to ST2m extends along a vertical direction (e.g., the Z direction) with respect to the Figure 5 orientation. In the first memory block MB1, m memory strings are arranged in the row direction (e.g., the X direction). In Figure 5 , although for ease of description, two memory strings are arranged in the column direction (e.g., the Y direction), three or more memory strings may be arranged in the column direction (the Y direction).

[0067] Each of the plurality of memory strings ST11 to ST1m and ST21 to ST2m includes at least one source selection transistor SST, first memory cells MC1 to nth memory cells MCn, and at least one drain selection transistor DST.

[0068] The source selection transistor SST of each memory string is connected between the source line SL and the memory cells MC1 to MCn. The source selection transistors of the memory strings arranged in the same row are connected to the same source selection line. For example, the source selection transistors of the memory strings ST11 to ST1m arranged in the first row are connected to the first source selection line SSL1. The source selection transistors of the memory strings ST21 to ST2m arranged in the second row are connected to the second source selection line SSL2. As another embodiment, the source selection transistors of the memory strings ST11 to ST1m and ST21 to ST2m are commonly connected to one source selection line.

[0069] The first memory cells MC1 to nth memory cells MCn of each memory string are connected in series with each other between the source selection transistor SST and the drain selection transistor DST. The gates of the first memory cells MC1 to nth memory cells MCn are respectively connected to the first word line WL1 to the nth word line WLn.

[0070] In one embodiment, at least one of the memory cells MC1 to MCn serves as a dummy memory cell. When a dummy memory cell is provided, the voltage or current of the corresponding memory string is stably controlled. Therefore, the reliability of the data stored in the memory block MB1 can be improved.

[0071] The drain select transistor DST of each memory string is connected between the bit line and the memory cells MC1 to MCn. The drain select transistors DST of the memory strings arranged in the row direction are connected to the drain select lines extending in the row direction. For example, the drain select transistors DST of the memory strings ST11 to ST1m in the first row are connected to the first drain select line DSL1. In another example, the drain select transistors DST of the memory strings ST21 to ST2m in the second row are connected to the second drain select line DSL2.

[0072] Figure 6A , Figure 6B , Figure 6C , Figure 6D and Figure 6E are diagrams showing the phenomenon of the threshold voltage reduction of the memory cells due to the holes present in the region between the memory cells.

[0073] Referring Figure 6A , among the memory cells including the channel CH, the tunneling insulating layer Tox, the charge storage layer CTN, the blocking insulating layer Box, and the gate GA, when the memory cell corresponding to the second word line WL2 is in the erased state or a programming state with a relatively low threshold voltage distribution, a plurality of holes + are included in the charge storage layer CTN.

[0074] Referring Figure 6B , when a certain number of holes + are included in the charge storage layer CTN of the memory cell programmed to the erased state or a programming state with a relatively low threshold voltage distribution, the certain number of holes + diffuse in the direction of adjacent memory cells or word lines over time. Therefore, some holes + become located inside the charge storage layer CTN between the memory cells.

[0075] Referring Figure 6C , when programming the memory cell corresponding to the second word line WL2 to a relatively high programming state among the multiple programming states, due to tunneling along the tunneling insulating layer Tox, electrons - in the channel CH become trapped in the charge storage layer CTN of the memory cell corresponding to the second word line WL2.

[0076] Referring Figure 6D , a certain number of electrons - included in the charge storage layer CTN of the memory cell corresponding to the second word line WL2 diffuse to the charge storage layer CTN between the memory cells towards the holes + existing inside the charge storage layer CTN between the memory cells, and the electrons - and holes + diffusing in the charge storage layer CTN between the memory cells combine, as shown by the arrows.

[0077] Referring Figure 6E, as electrons diffuse through the charge storage layer CTN between memory cells, the number of electrons trapped in the charge storage layer CTN of the memory cells corresponding to the second word line WL2 decreases. As a result, the threshold voltage of the memory cells corresponding to the second word line WL2 decreases.

[0078] Figure 7 is a diagram showing the threshold voltage distribution reduced according to the retention characteristics of the programmed memory cells.

[0079] In one embodiment of the present disclosure, the threshold voltage distribution of memory cells programmed by the MLC method is described.

[0080] Refer to Figure 7 , the memory cells included in the selected memory block are programmed to the erase state E and multiple programming states P1, P2, and P3. For example, the threshold voltage of the memory cells in the erase state E is lower than 0V, and the threshold voltage of the memory cells programmed to the first programming state P1 is higher than the first read voltage R1 and lower than the second read voltage R2. The threshold voltage of the memory cells programmed to the second programming state P2 is higher than the second read voltage R2 and lower than the third read voltage R3, and the threshold voltage of the memory cells programmed to the third programming state P3 is higher than the third read voltage R3.

[0081] In the memory cells programmed to at least one programming state with a relatively high threshold voltage distribution (e.g., the second programming state P2 and the third programming state P3), as described above Figure 6A , Figure 6B , Figure 6C , Figure 6D and Figure 6E shown, the trapped electrons diffuse in the direction of adjacent memory cells. As a result, the threshold voltage distribution decreases. According to this example, the threshold voltage distribution of some of the memory cells programmed to the second programming state P2 is lower than the second read voltage R2, and the threshold voltage distribution of some of the memory cells programmed to the third programming state P3 is lower than the third read voltage R3. As a result, the reliability of the data stored in the programmed memory block decreases.

[0082] Figure 8 is a flowchart showing a method of operating a memory device according to an embodiment of the present disclosure.

[0083] Refer to Figures 2 to 8 , a method of operating a memory device according to an embodiment of the present disclosure is described as follows.

[0084] The memory device 1100 counts the amount of valid data in the selected memory block S810.

[0085] Memory device 1100 may perform a background operation on a selected memory block (e.g., MB1). For example, the background operation may be a read reclaim, garbage collection, or read refresh operation.

[0086] After performing any background operation on the selected memory block MB1, memory device 1100 counts the amount of valid data among the data stored in the selected memory block MB1.

[0087] The memory block status determiner 311 of the rewrite manager 310 counts the amount of valid data among the data stored in the selected memory block MB1. Based on the counted amount of valid data of the selected memory block MB1, the memory block status determiner 311 determines whether the selected memory block MB1 is eligible as a rewrite operation target memory block. For example, when the amount of valid data of the selected memory block MB1 is less than a predetermined value, the memory block status determiner 311 determines or identifies the selected memory block MB1 as a rewrite operation target memory block. When the amount of valid data among the data stored in the selected memory block MB1 is equal to or greater than the predetermined value, the memory block status determiner 311 determines or identifies the selected memory block MB1 as a memory block other than the rewrite operation target memory block.

[0088] In another embodiment, the memory block status determiner 311 determines or identifies whether the selected memory block MB1 is eligible as a rewrite operation target memory block based on the ratio of valid data among all the data stored in the selected memory block MB1. For example, when the ratio of valid data among all the data stored in the selected memory block MB1 is less than a predetermined ratio value, the memory block status determiner 311 determines or identifies the selected memory block MB1 as a rewrite operation target memory block. When the ratio of valid data among all the data stored in the selected memory block MB1 is equal to or greater than the predetermined ratio value, the memory block status determiner 311 determines or identifies the selected memory block as a memory block other than the rewrite operation target memory block.

[0089] When the selected memory block is determined or identified as a rewrite operation target memory block and at least one valid data is stored in the selected memory block, the memory block status determiner 311 generates and outputs a write-back activation signal ACT-CB and a rewrite activation signal ACT-OW.

[0090] When the selected memory block MB1 is determined or identified as a rewrite operation target memory block and no valid data is stored in the selected memory block, or only invalid data is stored in the selected memory block, the memory block status determiner 311 generates and outputs only the rewrite activation signal ACT-OW without generating the write-back activation signal ACT-CB. The write-back activation signal ACT-CB can be deactivated by not generating the write-back activation signal ACT-CB, preventing the generation of the write-back activation signal ACT-CB, or preventing the generated write-back activation signal ACT-CB from being received.

[0091] Memory device 1100 programs S820 the valid data of the selected memory block MB1 into a target memory block (e.g., MB2). The target memory block can be any memory block of the memory device 1100 other than the selected memory block MB1, for example.

[0092] When the memory block status determiner 311 identifies the selected memory block MB1 as a memory block to be rewritten, the peripheral circuit 200 performs a write-back operation including reading the valid data stored in the selected memory block MB1 and programming the read valid data into the target memory block MB2.

[0093] For example, the write-back operation controller 312 of the rewrite manager 310 generates and outputs a write-back control signal CB-CTR in response to a write-back activation signal ACT-CB, which corresponds to a read operation of the valid data stored in the selected memory block MB1 and a valid data programming operation including storing the read valid data in the target memory block MB2. The target memory block may not be the selected memory block MB1. In response to the write-back control signal CB-CTR, the control signal generator 314 generates an operation signal OP-CMD, a row address RADD, and a page buffer control signal PBSIGNALS to perform a read operation of the valid data stored in the selected memory block MB1. The peripheral circuit 200 reads the valid data stored in the selected memory block MB1 in response to the operation signal OP-CMD, the row address RADD, and the page buffer control signal PBSIGNALS.

[0094] In response to the write-back control signal CB-CTR, the control signal generator 314 generates an operation signal OP-CMD, a row address RADD, and a page buffer control signal PBSIGNALS to perform a programming operation including storing the read valid data in the target memory block MB2. The peripheral circuit 200 programs the read valid data into the target memory block MB2 in response to the operation signal OP-CMD, the row address RADD, and the page buffer control signal PBSIGNALS.

[0095] When the memory block status determiner 311 determines or identifies the selected memory block MB1 as a memory block to be rewritten but no valid data is stored in the selected memory block MB1, no write-back operation is performed on the selected memory block MB1.

[0096] Memory device 1100 performs an S830 rewrite operation on the selected memory block MB1.

[0097] During the rewrite operation, the memory cells of the selected memory block MB1 on which background operations and write-back operations have been performed are programmed to an erase state E and multiple programming states P1, P2, and P3.

[0098] The rewrite operation controller 313 of the rewrite manager 310 generates and outputs a rewrite control signal OW-CTR corresponding to the rewrite operation of the selected memory block MB1 in response to a rewrite activation signal ACT-OW.

[0099] In response to the rewrite control signal OW-CTR, the control signal generator 314 outputs an operation signal OP-CMD, a row address RADD, and a page buffer control signal PBSIGNALS to the peripheral circuit 200 to perform a rewrite operation including increasing the threshold voltage value of the memory cells included in the selected memory block MB1 to at least a predetermined threshold voltage value.

[0100] For example, in response to the operation signal OP-CMD, the voltage generation circuit 210 generates and outputs a programming voltage, and the row decoder 220 transfers or transmits the programming voltage to the word lines of the selected memory block MB1 based on the row address RADD. In addition, the page buffer group 230 applies a programming enable voltage (e.g., a ground voltage) to the bit lines BL1 to BLm in response to the page buffer control signal PBSIGNALS.

[0101] The rewrite operation can be performed by an SLC programming method, an MLC programming method, a TLC programming method, or a QLC programming method.

[0102] The rewrite operation is a programming operation including increasing the threshold voltage of the memory cells in the erased state E among the memory cells included in the selected memory block MB1 to at least a predetermined threshold voltage value.

[0103] During the rewrite operation, the voltage generation circuit 210 generates a rewrite programming voltage that selectively increases only the threshold voltage of the memory cells in the erased state E. The voltage generation circuit 210 generates the rewrite programming voltage a predetermined number of times, and the row decoder 220 applies the rewrite programming voltage to the selected word lines or all word lines a predetermined number of times. In another embodiment, the voltage generation circuit 210 generates the rewrite programming voltage during a predetermined time period, and the row decoder 220 applies the rewrite programming voltage to the selected word lines or all word lines during a predetermined application time period.

[0104] In another embodiment, the rewrite operation is a programming operation including increasing the threshold voltage of the memory cells in the erased state E and at least one programmed state among the memory cells included in the selected memory block MB1 to at least a predetermined threshold voltage value. The at least one programmed state can be the first programmed state P1 with the lowest threshold voltage distribution among multiple programmed states (e.g., P1, P2, and P3).

[0105] During a rewrite operation, after applying a rewrite programming voltage to the selected word line or all word lines of a selected memory block MB1, it is not necessary to perform a verification operation on the selected memory block MB1 that includes determining whether the threshold voltage value of the memory cells included in the selected memory block MB1 is equal to or greater than a predetermined threshold voltage value.

[0106] The above operations S810, S820, and S830 of the memory device 1100 may be performed immediately after a background operation of the selected memory block, and in another embodiment, the above operations S810, S820, and S830 of the memory device 1100 may be performed when the memory device 1100 is in an idle state.

[0107] Figure 9A is a diagram showing the threshold voltage distribution of memory cells during a rewrite operation of a memory device according to an embodiment of the present disclosure.

[0108] Refer to Figure 9A , among the plurality of memory cells included in the selected memory block, the memory cells in the erased state E are selectively programmed to the rewrite state OWP.

[0109] The plurality of memory cells have threshold voltage values corresponding to the erased state E and the plurality of programming states P1, P2, and P3. For example, the threshold voltage of the memory cells in the erased state E is lower than 0V, and the threshold voltage of the memory cells programmed to the first programming state P1 is higher than the first read voltage R1 and lower than the second read voltage R2. In addition, the threshold voltage of the memory cells programmed to the second programming state P2 is higher than the second read voltage R2 and lower than the third read voltage R3, and the threshold voltage of the memory cells programmed to the third programming state P3 is higher than the third read voltage R3.

[0110] During the rewrite operation, the memory cells corresponding to the erased state E among the plurality of memory cells are selectively programmed to increase the threshold voltage. Therefore, the threshold voltage of the memory cells corresponding to the erased state E increases to the rewrite state OWP. The rewrite state OWP has a threshold voltage distribution greater than the rewrite reference voltage ROW. The rewrite reference voltage ROW may be greater than 0V.

[0111] The memory cells in the erased state E in which holes exist in the charge storage layer among the memory cells included in the selected memory block are programmed to the rewrite state OWP by the rewrite operation. Therefore, the phenomenon of hole diffusion to the region between the memory cells as Figure 6B shown is prevented. Therefore, the problem of a decrease in the threshold voltage distribution during subsequent programming operations of the selected memory block can be reduced.

[0112] Figure 9Bis a diagram showing the threshold voltage distribution of memory cells during a rewrite operation of a memory device according to another embodiment of the present disclosure.

[0113] Referring Figure 9B , among the plurality of memory cells included in the selected memory block, the memory cells in the erased state E and at least one programmed state (e.g., P1) are selectively programmed to the rewrite state OWP.

[0114] The plurality of memory cells have threshold voltage values corresponding to the erased state E and the plurality of programmed states P1, P2, and P3. For example, the threshold voltage of the memory cells in the erased state E is lower than 0V, and the threshold voltage of the memory cells programmed to the first programmed state P1 is higher than the first read voltage R1 and lower than the second read voltage R2. In addition, the threshold voltage of the memory cells programmed to the second programmed state P2 is higher than the second read voltage R2 and lower than the third read voltage R3, and the threshold voltage of the memory cells programmed to the third programmed state P3 is higher than the third read voltage R3.

[0115] During the rewrite operation, the memory cells corresponding to the erased state E and the first programmed state P1 with a relatively low threshold voltage distribution are selectively programmed to increase the threshold voltage. Thus, the threshold voltage of the memory cells corresponding to the erased state E and the first programmed state P1 increases to the rewrite state OWP. The rewrite state OWP has a threshold voltage distribution greater than the rewrite reference voltage R-OW. The rewrite reference voltage R-OW can be greater than 0V.

[0116] Among the memory cells included in the selected memory block, the memory cells in the erased state E and the first programmed state P1 in which holes exist in the charge storage layer are programmed to the rewrite state OWP by the rewrite operation. Thus, the phenomenon of hole diffusion into the region between the memory cells as Figure 6B shown is prevented. Thus, the problem of a decrease in the threshold voltage distribution during subsequent programming operations of the selected memory block can be reduced.

[0117] Figure 10 is a diagram showing another embodiment of a memory system including a memory device such as Figure 2 shown.

[0118] Referring Figure 10, the memory system 3000 can be a cellular phone, a smart phone, a tablet PC, a personal digital assistant (PDA), a wireless communication device, etc. The memory system 3000 includes a memory device 1100 and a memory controller 1200 capable of controlling the operations of the memory device 1100. The memory controller 1200 controls the data access operations (e.g., programming operations, erasing operations, and reading operations) of the memory device 1100 under the control of a processor 3100. The memory device 1100 and the memory controller 1200 together perform the above-mentioned write-back operation and rewrite operation.

[0119] Under the control of the memory controller 1200, the data programmed in the memory device 1100 can be output through a display 3200.

[0120] A radio transceiver 3300 transmits and receives radio signals through an antenna ANT. For example, the radio transceiver 3300 converts the radio signals received through the antenna ANT into signals processed by the processor 3100. The processor 3100 processes the signals from the radio transceiver 3300 and transmits the processed signals to, for example, the memory controller 1200 or the display 3200. The memory controller 1200 can provide the signals processed by the processor 3100 to the memory device 1100. The radio transceiver 3300 converts the signals output from the processor 3100 into radio signals and transmits the converted radio signals to an external device through the antenna ANT. An input device 3400 is a device that inputs control signals for controlling the operations of the processor 3100 or data to be processed by the processor 3100. The input device 3400 can be a pointing device such as a touchpad or a computer mouse, a keypad, a keyboard, etc. The processor 3100 controls the operations of the display 3200 such that the data output from the memory controller 1200, the data output from the radio transceiver 3300, and the data output from the input device 3400 are output through the display 3200.

[0121] According to one embodiment, the memory controller 1200 capable of controlling the operations of the memory device 1100 can be a part of the processor 3100 or an integrated circuit chip separate from the processor 3100.

[0122] Figure 11 is a diagram showing another embodiment of a memory system including a memory device such as Figure 2 shown.

[0123] Refer to Figure 11 , the memory system 4000 can be a personal computer (PC), a tablet PC, a netbook, an e-reader, a personal digital assistant (PDA), a portable multimedia player (PMP), an MP3 player, an MP4 player, etc.

[0124] The memory system 4000 includes a memory device 1100 and a memory controller 1200 capable of controlling data processing operations of the memory device 1100. The memory device 1100 performs data access operations (e.g., programming operations, erasing operations, and reading operations) under the control of the memory controller 1200. The memory device 1100 and the memory controller 1200 perform the above-mentioned write-back operation and rewrite operation together.

[0125] The processor 4100 outputs the data stored in the memory device 1100 via the display 4300 according to the data input through the input device 4200. For example, the input device 4200 may be a pointing device such as a touchpad or a computer mouse, a keypad, a keyboard, etc.

[0126] The processor 4100 controls the overall operation of the memory system 4000 and controls the operation of the memory controller 1200. The memory controller 1200 capable of controlling the operation of the memory device 1100 may be a part of the processor 4100 or an integrated circuit chip separate from the processor 4100.

[0127] Figure 12 is a diagram showing another embodiment of a memory system including, for example, Figure 2 the memory device shown.

[0128] Referring to Figure 12 , the memory system 5000 may be an image processing device, such as a digital camera, a portable phone including a digital camera, a smart phone including a digital camera, a tablet PC including a digital camera, etc.

[0129] The memory system 5000 includes a memory device 1100 and a memory controller 1200 capable of controlling data processing operations (e.g., programming operations, erasing operations, and reading operations) of the memory device 1100. The memory device 1100 and the memory controller 1200 perform the above-mentioned write-back operation and rewrite operation together.

[0130] The image sensor 5200 of the memory system 5000 converts an optical image into a digital signal. The converted digital signal is transmitted or sent to the processor 5100 or the memory controller 1200. Under the control of the processor 5100, the digital signal may be output via the display 5300 or stored in the memory device 1100 through the memory controller 1200. The data stored in the memory device 1100 may be output via the display 5300 under the control of the processor 5100 or the memory controller 1200.

[0131] According to one embodiment, the memory controller 1200 that can control the operation of the memory device 1100 can be a part of the processor 5100 or can be an integrated circuit chip separate from the processor 5100.

[0132] Figure 13 is a diagram showing another embodiment of a memory system including a memory device such as Figure 2 shown.

[0133] Referring to Figure 13 , the memory system 7000 can be a memory card or a smart card. The memory system 7000 includes a memory device 1100, a memory controller 1200, and a card interface 7100.

[0134] The memory device 1100 performs data access operations (e.g., programming operations, erasing operations, and reading operations) under the control of the memory controller 1200. The memory device 1100 performs the above-described write-back operation and rewrite operation together with the memory controller 1200.

[0135] The memory controller 1200 controls the data exchange between the memory device 1100 and the card interface 7100. The card interface 7100 can be, but is not limited to, a Secure Digital (SD) card interface or a Multimedia Card (MMC) interface.

[0136] The card interface 7100 provides an interface for data exchange between the host 6000 and the memory controller 1200 according to the protocol of the host 6000. The card interface 7100 can support a Universal Serial Bus (USB) protocol, an Inter-Chip (IC) USB protocol, etc. In this example, the card interface can refer to the hardware that can support the protocol used by the host 6000, the software installed in the hardware, and / or the signal transmission method.

[0137] When the memory system 7000 is connected to the host interface 6200 of the host 6000 (e.g., a PC, a tablet PC, a digital camera, a digital audio player, a mobile phone or a cellular phone, a console video game hardware, a digital set-top box, etc.), the host interface 6200 performs data communication with the memory device 1100 through the card interface 7100 and the memory controller 1200 under the control of the microprocessor 6100.

[0138] Although specific embodiments are described in the detailed description, various changes can be made without departing from the scope and spirit of the present disclosure. Therefore, the scope of the present disclosure should not be limited to the above embodiments. All changes within the meaning and equivalents of the claims should be included within the scope of the claims.

[0139] Cross-reference to related applications

[0140] This application claims the priority of Korean Patent Application No. 10-2023-0167993, filed with the Korean Intellectual Property Office on November 28, 2023, the entire disclosure of which is incorporated herein by reference.

Claims

1. A memory device, comprising: a plurality of memory blocks, each of the plurality of memory blocks comprising a plurality of memory cells; a peripheral circuit that performs background operations and rewrite operations on a selected memory block among the plurality of memory blocks; as well as control logic, the control logic controlling the peripheral circuit to perform the background operation and the rewrite operation, The control logic controls the peripheral circuit to perform the rewrite operation based on the amount of valid data stored in the selected storage block, and the rewrite operation includes increasing the threshold voltage of the memory cell of the selected storage block to at least a predetermined threshold voltage value.

2. The memory device according to claim 1, wherein: The control logic also includes a rewrite manager that determines the amount of the valid data stored in the selected storage block, and when the determined amount of the valid data is less than a predetermined value, controls the peripheral circuit to perform a write-back operation and the rewrite operation on the selected storage block.

3. The memory device according to claim 2, wherein: The rewrite manager includes: a storage block state determiner, the storage block state determiner counting the amount of the valid data stored in the selected storage block, determining whether the selected storage block is qualified as a rewrite operation object storage block based on the counted amount of the valid data, generating a write-back activation signal and a rewrite activation signal, and outputting the write-back activation signal and the rewrite activation signal; a write-back operation controller, the write-back operation controller generating and outputting a write-back control signal in response to the write-back activation signal, the write-back control signal corresponding to a write-back operation, the write-back operation including a read operation of the valid data stored in the selected storage block and a valid data programming operation, the valid data programming operation including storing the read valid data in a target storage block other than the selected storage block among the plurality of storage blocks; a rewrite operation controller that generates and outputs a rewrite control signal corresponding to the rewrite operation on the selected memory block in response to the rewrite activation signal; and A control signal generator generates a control signal for controlling the peripheral circuit in response to at least one of the write-back control signal and the rewrite control signal.

4. The memory device according to claim 1, further comprising a memory block status determiner, the memory block status determiner counting the amount of the valid data stored in the selected memory block, wherein When the amount of valid data stored in the selected storage block is less than a predetermined value, the storage block status determiner identifies the selected storage block as a rewrite operation object storage block, and when no valid data is stored in the selected storage block, the storage block status determiner deactivates a write-back activation signal corresponding to a write-back operation.

5. The memory device according to claim 3, wherein: The memory block state determiner counts the amount of the valid data by counting the amount of pages storing the valid data among a plurality of pages included in the selected memory block.

6. The memory device according to claim 1, wherein: During the rewrite operation, the peripheral circuit applies a rewrite program voltage to a selected word line or all word lines of the selected memory block.

7. The memory device according to claim 1, wherein: During the rewrite operation, the peripheral circuit increases a threshold voltage of a memory cell corresponding to an erase state among the plurality of memory cells included in the selected memory block to at least the predetermined threshold voltage value.

8. The memory device according to claim 1, wherein: During the rewrite operation, the peripheral circuit increases a threshold voltage of a memory cell corresponding to an erase state and at least one program state among the plurality of memory cells included in the selected memory block to at least the predetermined threshold voltage value.

9. The memory device according to claim 8, wherein: The at least one programming state is a programming state having a relatively low threshold voltage distribution among the plurality of programming states.

10. The memory device according to claim 1, wherein: The predetermined threshold voltage value is greater than 0V.

11. A method of operating a memory device, the method comprising the steps of: determining an amount of valid data stored in the selected memory block; When the amount of the valid data is less than a predetermined value, performing a write-back operation on the selected storage block; as well as A rewrite operation is performed on selected memory cells corresponding to an erase state or the erase state and at least one program state among memory cells included in the selected memory block.

12. The method according to claim 11, wherein: During the write-back operation, the valid data of the selected memory block is read, and the read valid data is programmed into a target memory block other than the selected memory block.

13. The method according to claim 11, further comprising the steps of: When the valid data is stored in the selected memory block, the write-back operation is performed in response to a write-back control signal.

14. The method according to claim 11, wherein: The rewrite operation increases the threshold voltage value of the selected memory cell to at least a predetermined threshold voltage value by applying a rewrite program voltage to the selected word line or all word lines of the selected memory block.

15. The method according to claim 14, wherein: The predetermined threshold voltage value is greater than 0V.

16. The method according to claim 14, wherein: The at least one programming state is a programming state having a relatively low threshold voltage distribution among the plurality of programming states.

17. A method of operating a memory device, the method comprising the steps of: determining an amount of valid data stored in a selected memory block on which a background operation is performed; identifying the selected storage block as a rewrite operation target storage block based on the amount of the valid data; Performing a write-back operation, the write-back operation comprising storing the valid data stored in the selected storage block in a target storage block; as well as A rewrite operation is performed after the write-back operation, the rewrite operation including increasing a threshold voltage of selected memory cells corresponding to an erase state or the erase state and at least one program state among memory cells included in the selected memory block to at least a predetermined threshold voltage value.

18. The method according to claim 17, wherein: The step of identifying the selected memory block as the rewrite operation target memory block includes determining whether the amount of the valid data stored in the selected memory block is less than a predetermined value.

19. The method according to claim 17, wherein: The rewrite operation increases the threshold voltage value of the selected memory cell to at least a predetermined threshold voltage value by applying a rewrite program voltage to the selected word line or all word lines of the selected memory block.

20. The method according to claim 17, wherein: The at least one programming state is a programming state having a relatively low threshold voltage distribution among the plurality of programming states.

21. A method of operating a memory device, the method comprising the steps of: determining an amount of valid data stored in a first storage block of the plurality of storage blocks; When the amount of the valid data is less than a predetermined value, performing a write-back operation, the write-back operation comprising storing the valid data stored in the first storage block in a second storage block among the plurality of storage blocks; as well as A rewrite operation is performed based on the amount of the valid data stored in the first memory block, the rewrite operation including increasing a threshold voltage of a plurality of memory cells of the first memory block to at least a predetermined threshold voltage value.

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