Memory particle multi-dimensional test method and system

Abstract

The invention discloses a memory particle multi-dimensional test method and system, and relates to the technical field of memory particle testing, and the method comprises the steps: installing a plurality of memory particles to be tested to form a multi-Rank combination, and simulating a high-load environment in actual use by setting a staggered mapping mode; performing a non-contact light wave signal integrity test by using a photonic crystal sensor, and outputting light wave signal integrity data; on the basis of the mechanical performance data and the light wave signal integrity data of the multi-Rank combination, a fault prediction model is used for predicting potential faults; based on a fault prediction result of the fault prediction model, positioning a fault memory particle unit by combining conversion of a linear address and a physical address; according to the method, the mechanical performance data and the light wave signal integrity data are combined, intelligent analysis and early warning of potential faults are achieved through the fault prediction model, and the stability and reliability of memory particles are improved.

Description

Technical Field

[0001] The present invention relates to the technical field of memory chip testing, and particularly to a multi-dimensional testing method and system for memory chips. Background Art

[0002] With the rapid development of computer technology, memory, as a key storage component in a computer system, its performance and reliability play a crucial role in the operating efficiency and stability of the entire system. In recent years, DDR (Double DataRate) memory technology has evolved from DDR3 to DDR4 and DDR5. These new-generation memory chips have not only achieved significant improvements in storage density and access speed but also realized more efficient data transmission and parallel processing capabilities through a multi-Rank combined architecture design.

[0003] However, this complex architecture has also brought challenges to the reliability testing and fault diagnosis of memory chips. Most traditional memory testing methods rely on the integrity testing of electrical signals and simple read-write verification of logical addresses, making it difficult to comprehensively evaluate the dynamic performance of memory chips under high load and complex environments. Summary of the Invention

[0004] In view of the above existing problems, the present invention is proposed.

[0005] Therefore, the present invention provides a multi-dimensional testing method for memory chips to solve the problem of comprehensively evaluating the dynamic performance of memory chips under high load and complex environments.

[0006] To solve the above technical problems, the present invention provides the following technical solutions:

[0007] In a first aspect, the present invention provides a multi-dimensional testing method for memory chips, which includes

[0008] installing multiple memory chips to be tested to form a multi-Rank combination, and simulating a high-load environment in actual use by setting an interleaved mapping mode;

[0009] performing high-frequency vibration and stress testing using a SAW sensor, real-time monitoring the vibration and strain of the multi-Rank combination, and outputting mechanical property data;

[0010] performing non-contact optical wave signal integrity testing using a photonic crystal sensor, and outputting optical wave signal integrity data;

[0011] predicting potential faults using a fault prediction model based on the mechanical property data and optical wave signal integrity data of the multi-Rank combination;

[0012] locating the faulty memory chip unit based on the fault prediction result of the fault prediction model in combination with the conversion between linear addresses and physical addresses.

[0013] As a preferred solution of the multi-dimensional testing method for memory particles of the present invention, wherein: install multiple memory particles to be tested to form a multi-Rank combination, and simulate a high-load environment in actual use by setting an interleaved mapping mode. The specific steps are as follows:

[0014] According to the size and pin distribution of the memory particles to be tested, construct a multi-Rank layout of the test board. Each Rank corresponds to a group of memory particles, and different Ranks are arranged on both sides of the test board;

[0015] Integrate an interface connected to the test device on the test board;

[0016] Use an automatic chip mounter to install the memory particles onto the pads of the test board;

[0017] Connect the test board to the automated test device;

[0018] Start the self-check program of the automated test device to check whether the hardware on the test board is working properly;

[0019] Set the interleaved mapping mode to simulate a high-load environment in actual use;

[0020] According to the specifications of the memory particles to be tested, configure the timing parameters, voltage parameters, and frequency parameters of the memory controller.

[0021] As a preferred solution of the multi-dimensional testing method for memory particles of the present invention, wherein: use SAW sensors to perform high-frequency vibration and stress testing, and monitor the vibration and strain of the multi-Rank combination in real time, and output mechanical performance data. The specific steps are as follows:

[0022] Use SAW sensors based on piezoelectric materials, and evenly arrange multiple SAW sensors on the pads and signal channels of the test board;

[0023] Fix the SAW sensors with conductive adhesive;

[0024] Under no-load conditions, record the initial response characteristics of the SAW sensors as a reference benchmark for subsequent testing;

[0025] Apply mechanical stress and vibration, record the response changes of the SAW sensors, and adjust the sensitivity and linearity of the sensors by comparing the actual values of strain and vibration frequency with the measured values of the SAW sensors;

[0026] Set the vibration frequency range according to the application scenario of the memory particles;

[0027] Set the stress intensity according to the specifications and application scenarios of the memory particles;

[0028] Apply vibration and stress to the test board according to the settings of vibration frequency and stress intensity;

[0029] While applying vibration and stress to the test board, use the SAW sensor to output the propagation speed and phase change of the acoustic wave through the reflection and propagation of the acoustic wave on the surface of each memory particle;

[0030] Calculate the vibration frequency of the memory particle by measuring the propagation time difference of the acoustic wave on the surface of the memory particle;

[0031] Calculate the strain of the memory particle by analyzing the phase change of the acoustic wave and combining with the elastic mechanics formula;

[0032] Output the vibration frequency and strain of the memory particle as mechanical property data.

[0033] As a preferred solution of the multi-dimensional test method for memory particles of the present invention, wherein: the non-contact optical wave signal integrity test is performed using a photonic crystal sensor, and optical wave signal integrity data is output. The specific steps are as follows.

[0034] Install photonic crystal sensors on the signal pins of each memory particle and form a surrounding array;

[0035] Calibrate the photonic crystal sensors under no-load conditions and under the condition of applying optical wave signals respectively;

[0036] Set the frequency range of optical wave signal transmission according to the operating frequency and application scenario of the memory particle;

[0037] Set the intensity range of signal transmission according to the voltage parameters and application scenario of the memory particle;

[0038] Based on the pin distribution and signal routing design of the memory particle, use the differential signal transmission method;

[0039] Control the signal generator through an automated test device to send optical wave signals with a set frequency and intensity range to the memory particle;

[0040] Monitor the propagation speed, amplitude and phase change of the optical wave signal through the photonic crystal sensor;

[0041] Calculate the optical wave signal attenuation value based on the amplitude change of the optically monitored wave signal;

[0042] Calculate the optical wave signal reflection coefficient based on the propagation speed of the optical wave signal;

[0043] Calculate the phase difference between the input optical wave signal and the output optical wave signal through the phase change of the monitored optical wave signal;

[0044] Output the optical wave signal attenuation value, reflection coefficient, and phase difference as the optical wave signal integrity data.

[0045] As a preferred embodiment of the multi-dimensional testing method for memory particles of the present invention, wherein: based on the mechanical property data and optical wave signal integrity data of the multi-Rank combination, use a fault prediction model to predict potential faults, and the specific steps are as follows.

[0046] Collect the historical data of the mechanical properties and optical wave signal integrity of the memory particles in the multi-Rank combination under normal working conditions and fault conditions, and process them.

[0047] Shuffle the processed training samples and divide them into a training set, a validation set, and a test set.

[0048] Based on a convolutional neural network, construct a fault prediction model, input the training set into the fault prediction model, judge whether a fault occurs according to the fault risk score output by the fault prediction model, and output the predicted binary label.

[0049] Based on the predicted binary label and the actual binary label, use the binary cross-entropy loss function to calculate the loss value of the fault prediction model.

[0050] Calculate the gradient of the loss with respect to the parameters of the fault prediction model through the gradient descent algorithm, and update the parameters of the fault prediction model.

[0051] Based on the Adam optimization algorithm, dynamically adjust the parameters of the fault prediction model to minimize the loss function.

[0052] After each training, evaluate the performance of the fault prediction model on the validation set and record it.

[0053] When all the training samples in the training set have participated in the training of the fault prediction model, it means that the training is completed, and use the training samples in the test set to test the performance of the trained fault prediction model.

[0054] Integrate the trained fault prediction model into an automated testing device.

[0055] Input the mechanical property data and optical wave signal integrity data of the multi-Rank combination obtained by real-time monitoring into the fault prediction model, and output the binary label representing fault and normal.

[0056] As a preferred embodiment of the multi-dimensional testing method for memory particles of the present invention, wherein: the step of collecting the historical data of the mechanical properties and optical wave signal integrity of the memory particles in the multi-Rank combination under normal working conditions and fault conditions, and processing them is as follows.

[0057] Add a unified timestamp according to the collection time of each piece of historical data;

[0058] Integrate the mechanical property data and optical wave signal integrity data in the historical data into training samples, and add binary labels indicating normal and faulty to each training sample;

[0059] Use a filtering algorithm to remove high-frequency noise and use statistical methods to remove outliers;

[0060] Adopt the Min-Max normalization method to map the historical data to a specific range.

[0061] As a preferred solution of the multi-dimensional test method for memory particles described in the present invention, wherein: based on the fault prediction result of the fault prediction model, combined with the conversion of linear address and physical address, locate the faulty memory particle unit, and the specific steps are as follows.

[0062] When the prediction result of the fault prediction model represents a normal binary label, it means that the memory particles in the multi-Rank combination are all operating normally;

[0063] When the prediction result of the fault prediction model represents a faulty binary label, it means that the memory particles in the multi-Rank combination are faulty, and record the fault occurrence time;

[0064] Establish a mapping relationship between the linear address and the physical address according to the linear address range and the physical address range of the memory particle on the test board;

[0065] Extract the corresponding linear address range from the input data according to the fault time detected by the fault prediction model;

[0066] Use the mapping relationship between the linear address and the physical address to convert the linear address into a physical address;

[0067] Determine the Rank number and the memory particle number by comparing the faulty physical address with the physical address intervals of each Rank. The expression is as follows: ; ;

[0068] Wherein, is the Rank number at the time of fault occurrence, is the physical address, and respectively represent the starting physical address and the ending physical address of the th Rank, is the memory particle number at the time of fault occurrence, is the physical address span of a single memory particle, is the number The starting physical address allocated by the Rank in the physical memory address space;

[0069] Using an automated test equipment (ATE), perform unit tests on the memory particles with fault location to verify the read / write performance and data integrity.

[0070] In a second aspect, the present invention provides a multi-dimensional test system for memory particles, including a multi-Rank combination module, a mechanical property data module, an integrity data module, a fault prediction module, and a fault location module.

[0071] The multi-Rank combination module is used to install multiple memory particles to be tested to form a multi-Rank combination, and simulate a high-load environment in actual use by setting an interleaved mapping mode.

[0072] The mechanical property data module is used to perform high-frequency vibration and stress tests using SAW sensors, monitor the vibration and strain of the multi-Rank combination in real time, and output mechanical property data.

[0073] The integrity data module is used to perform non-contact optical wave signal integrity tests using photonic crystal sensors and output optical wave signal integrity data.

[0074] The fault prediction module is used to predict potential faults based on the mechanical property data and optical wave signal integrity data of the multi-Rank combination using a fault prediction model.

[0075] The fault location module is used to locate the faulty memory particle unit based on the fault prediction result of the fault prediction model in combination with the conversion between the linear address and the physical address.

[0076] In a third aspect, the present invention provides a computer device, including a memory and a processor, where the memory stores a computer program, and: when the computer program is executed by the processor, any step of the multi-dimensional test method for memory particles as described in the first aspect of the present invention is implemented.

[0077] In a fourth aspect, the present invention provides a computer-readable storage medium, on which a computer program is stored, and: when the computer program is executed by the processor, any step of the multi-dimensional test method for memory particles as described in the first aspect of the present invention is implemented.

[0078] The beneficial effects of the present invention are as follows: By installing multiple Rank combinations and setting an interleaved mapping mode, the present invention simulates an actual high-load environment, making the test closer to the real application scenario, exposing potential problems in advance. Using SAW sensors for high-frequency vibration and stress testing, mechanical performance data is collected in real time to evaluate the reliability of particles in a dynamic stress environment. Through the non-contact optical wave signal integrity testing of photonic crystal sensors, anomalies in high-speed signal transmission are accurately captured to ensure the stability of signal transmission. Combining mechanical performance data and optical wave signal integrity data, intelligent analysis and early warning of potential faults are achieved through a fault prediction model, improving the stability and reliability of memory particles. Based on the mapping between linear addresses and physical addresses, the faulty particle unit is accurately located, providing support for the rapid maintenance of faults. BRIEF DESCRIPTION OF THE DRAWINGS

[0079] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for description in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0080] Figure 1 It is a flowchart of the multi-dimensional testing method for memory particles in Embodiment 1.

[0081] Figure 2 It is a module diagram of the multi-dimensional testing system for memory particles in Embodiment 1. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0082] To make the above objects, features, and advantages of the present invention more obvious and understandable, the following detailed description of the specific embodiments of the present invention will be made in conjunction with the accompanying drawings of the specification.

[0083] Many specific details are set forth in the following description in order to fully understand the present invention. However, the present invention can also be implemented in other ways different from those described herein. Those skilled in the art can make similar extensions without departing from the connotation of the present invention. Therefore, the present invention is not limited by the specific embodiments disclosed below.

[0084] Secondly, the so-called "one embodiment" or "embodiment" herein refers to a specific feature, structure, or characteristic that can be included in at least one implementation of the present invention. The phrase "in one embodiment" appearing in different places in this specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment that excludes other embodiments.

[0085] Embodiment 1, refer to Figure 1 and Figure 2, which is the first embodiment of the present invention. This embodiment provides a multi-dimensional testing method for memory particles, including the following steps:

[0086] S1. Install multiple memory particles to be tested to form a multi-Rank combination, and simulate a high-load environment in actual use by setting an interleaved mapping mode.

[0087] Adopt PCB materials with good electrical performance and mechanical stability, such as FR-4 or Rogers RO4350B. These materials have a low dielectric constant and loss tangent, which can reduce losses and interference during signal transmission;

[0088] According to the size and pin distribution of the memory particles to be tested, construct a multi-Rank layout of the test board. Each Rank corresponds to a group of memory particles, and different Ranks are arranged on both sides of the test board to increase the test density. For example, 4 Ranks can be arranged on one side of the test board and 4 Ranks on the other side, for a total of 8 Ranks;

[0089] Integrate interfaces connected to the test equipment, such as JTAG, SPI, I2C, etc., on the test board to facilitate subsequent automated testing;

[0090] Use an automatic chip mounter to install the memory particles on the pads of the test board. During the installation process, the temperature and pressure should be strictly controlled to avoid damaging the memory particles. For memory particles with BGA packaging, it is recommended to use an X-ray detection device to check the solder joint quality to ensure that each pin is in good contact with the pad;

[0091] Connect the test board to an automated test equipment (ATE) to ensure that all interfaces (such as JTAG, SPI, I2C, etc.) are correctly connected;

[0092] Start the self-check program of the automated test equipment to check whether the hardware on the test board is working properly;

[0093] Including, initialize each memory particle through the BIOS or firmware to ensure that it is in a normal working state, verify whether the address mapping register group of the memory controller is correctly configured to ensure that the interleaved mapping mode can be enabled normally, and detect whether there are short circuits or open circuits in the power and signal traces of each Rank to ensure the integrity of signal transmission;

[0094] Setting the interleaved mapping mode to simulate a high-load environment in actual use means that the memory controller distributes consecutive memory addresses to different Ranks, enabling the CPU to open multiple Ranks simultaneously during memory access, thus forming a dynamic "heavy-load mode";

[0095] Configure the timing parameters (tRCD, tRP, tRFC, etc.), voltage parameters (VDD, VDDQ, etc.), and frequency parameters (operating frequency of DDR4 / DDR5) of the memory controller according to the specifications of the memory die under test.

[0096] S2. Use SAW sensors to perform high-frequency vibration and stress tests, monitor the vibration and strain of the multi-Rank combination in real time, and output mechanical property data.

[0097] Use SAW sensors based on piezoelectric materials, such as ZnO or AlN, and evenly arrange multiple SAW sensors on the test board pads and signal channels to ensure full coverage of all possible stress concentration areas. For example, install one SAW sensor at each of the four corners of each memory die to form a four-point array for more accurate monitoring of the memory die.

[0098] Fix the SAW sensors using conductive adhesive. During the fixing process, ensure that the sensors are in close contact with the surface of the memory die to avoid measurement errors caused by poor contact. For BGA-packaged memory dies, it is recommended to use flexible connectors to connect the SAW sensors to the pads of the test board to reduce mechanical interference to the memory die.

[0099] Under no-load conditions, record the initial response characteristics of the SAW sensors, such as the acoustic wave propagation speed, amplitude, and phase, as a reference benchmark for subsequent tests.

[0100] Apply mechanical stress and vibration, record the response changes of the SAW sensors, and adjust the sensitivity and linearity of the sensors by comparing the actual values of strain and vibration frequency with the measured values of the SAW sensors.

[0101] Set the vibration frequency range according to the application scenario of the memory die.

[0102] For example, for server applications, simulate the mechanical vibration during high-speed data transmission by setting high-frequency vibration (such as 100 kHz to 1 MHz). For mobile device applications, simulate the mechanical shock during daily use by setting low-frequency vibration (such as 10 Hz to 100 Hz).

[0103] Set the stress intensity according to the specifications and application scenario of the memory die.

[0104] For example, for BGA-packaged memory dies, apply a certain bending stress (such as a bending deformation of 100 μm to 500 μm) to simulate the mechanical stress during the plugging or thermal cycling of the memory die. For TSOP-packaged memory dies, apply a certain shear stress (such as a shear force of 10 N to 50 N) to simulate the mechanical stress during the soldering or desoldering of the memory die.

[0105] Apply vibration and stress to the test board according to the set vibration frequency and stress intensity;

[0106] While applying vibration and stress to the test board, use the SAW sensor to output the propagation speed and phase change of the acoustic wave through the reflection and propagation of the acoustic wave on the surface of each memory particle;

[0107] Calculate the vibration frequency of the memory particle by measuring the propagation time difference of the acoustic wave on the surface of the memory particle. The expression is as follows: ; Where, is the vibration frequency of the memory particle, is the propagation speed of the acoustic wave, is the wavelength of the acoustic wave, is the propagation time difference of the acoustic wave, is the round-trip distance from the acoustic wave emission point to the surface of the memory particle;

[0108] Calculate the strain of the memory particle by analyzing the phase change of the acoustic wave and combining with the elasticity formula. The expression is as follows: ; Where, is the strain of the memory particle, is the acoustic wave phase difference;

[0109] Output the vibration frequency and strain of the memory particle as mechanical property data.

[0110] S3. Use the photonic crystal sensor to perform non-contact optical wave signal integrity testing and output optical wave signal integrity data.

[0111] Install photonic crystal sensors on the signal pins of each memory particle and form a surrounding array to more accurately monitor the optical wave signal integrity;

[0112] Calibrate the photonic crystal sensor under no-load conditions and under the condition of applying an optical wave signal respectively;

[0113] Among them, under no-load conditions, record the initial response characteristics of the photonic crystal sensor, such as the propagation speed, amplitude and phase of the optical wave. These data will be used as a reference benchmark for subsequent tests;

[0114] By comparing the actual value of the known signal with the measured value of the sensor, adjust the sensitivity and linearity of the sensor to ensure that it can accurately measure the signal integrity of the memory particle under different load conditions;

[0115] Set the frequency range of optical wave signal transmission according to the operating frequency and application scenario of the memory particle;

[0116] For DDR4 / DDR5 memory chips, it is recommended to set high-frequency signals (such as 2 GHz to 5 GHz) to simulate signal integrity during high-speed data transmission. For low-speed applications, it is recommended to set lower signal frequencies (such as 100 MHz to 500 MHz) to simulate signal transmission in daily use;

[0117] Set the intensity range of signal transmission according to the voltage parameters and application scenarios of the memory chips;

[0118] For server applications, it is recommended to apply a relatively high intensity of optical wave signals (such as 1.2 V to 1.8 V) to simulate voltage fluctuations during high-speed data transmission. For mobile device applications, it is recommended to apply a relatively low intensity of optical wave signals (such as 0.9 V to 1.2 V) to simulate signal transmission in low-power mode;

[0119] Based on the pin distribution and signal trace design of the memory chips, use differential signal transmission methods (such as differential pairs) to reduce electromagnetic interference and signal reflection;

[0120] Control the signal generator through an automated test equipment (ATE) to send optical wave signals with set frequencies and intensity ranges to the memory chips;

[0121] Monitor the propagation speed, amplitude, and phase changes of the optical wave signals in real time through a photonic crystal sensor;

[0122] Based on the amplitude changes of the optical wave signals monitored in real time, calculate the optical wave signal attenuation value, which reflects the energy loss of the signal during transmission. The expression is as follows: ; where is the optical wave signal attenuation value, is the amplitude of the input optical wave signal, is the amplitude of the output optical wave signal;

[0123] Based on the propagation speed of the optical wave signal, calculate the optical wave signal reflection coefficient, which reflects the reflection phenomenon that occurs during signal transmission. The expression is as follows: ; ; where is the optical wave signal reflection coefficient, is the load impedance, is the characteristic impedance of the transmission line, is the propagation speed of the optical wave signal in the transmission line, is the propagation speed of the optical wave signal in a vacuum;

[0124] Calculate the phase difference between the input optical wave signal and the output optical wave signal by monitoring the phase change of the optical wave signal;

[0125] Output the optical wave signal attenuation value, reflection coefficient, and phase difference as optical wave signal integrity data.

[0126] S4. Based on the mechanical property data and optical wave signal integrity data of the multi-Rank combination, use the fault prediction model to predict potential faults.

[0127] Collect historical data on the mechanical properties and optical wave signal integrity of memory particles in the multi-Rank combination under normal operating conditions and fault conditions, and process them;

[0128] Add a unified timestamp according to the acquisition time of each piece of historical data;

[0129] Integrate the mechanical property data and optical wave signal integrity data in the historical data into training samples, and add binary labels indicating normal and fault (0 indicates normal, 1 indicates fault) to each training sample;

[0130] Use filtering algorithms (such as low-pass filtering, high-pass filtering, or band-pass filtering) to remove high-frequency noise, and use statistical methods (such as mean filtering, median filtering) to remove outliers;

[0131] Generate more types of fault data by introducing artificial faults (such as randomly adding noise, changing signal strength, etc.);

[0132] Adopt the Min-Max normalization method to map the historical data to a specific range.

[0133] Shuffle the processed training samples and divide them into a training set, a validation set, and a test set;

[0134] Based on a convolutional neural network, construct a fault prediction model, input the training set into the fault prediction model, judge whether a fault occurs according to the fault risk score output by the fault prediction model, and output binary labels indicating normal and fault for the prediction;

[0135] Specifically, at the input layer, a multi-dimensional feature tensor after time windowing is input. At the convolutional layer, a one-dimensional convolutional kernel is used to extract time series features. The multi-dimensional feature tensor is convolved through the first and second convolutional layers, and a max pooling layer is added. The pooling window size is 2 and the stride is 2 to reduce the feature dimension while retaining key features. The outputs of the convolutional layer and the pooling layer are flattened and input into the fully connected layer. The ReLU activation function is used to further extract non-linear features. Finally, at the output layer, the fault risk score is output through the Sigmoid activation function, and based on the fault risk score, it is determined whether there is a fault in the operation of the memory particle, and a binary label indicating fault and normal is output. The expression is as follows: ; Among them, is the fault risk score. When , it indicates that the predicted operation result of the memory particle is faulty, and the fault prediction model outputs 1. When , it indicates that the predicted operation result of the memory particle is normal, and the fault prediction model outputs 0. is the weight matrix, is the multi-dimensional feature tensor, is the bias term;

[0136] Based on the predicted binary label and the actual binary label, the binary cross-entropy loss function is used to calculate the loss value of the fault prediction model. The expression is as follows: ; Among them, is the binary cross-entropy loss value, is the number of training samples in the training set, is the index of the number of training samples in the training set, is the actual binary label of the training sample, is the binary label predicted by the fault prediction model;

[0137] Calculate the gradient of the loss with respect to the parameters of the fault prediction model through the gradient descent algorithm and update the parameters of the fault prediction model;

[0138] Based on the Adam optimization algorithm, dynamically adjust the parameters of the fault prediction model to minimize the loss function;

[0139] After each training is completed, evaluate the performance of the fault prediction model (such as loss value, accuracy, precision, recall, etc.) on the validation set and record it;

[0140] When all the training samples in the training set have participated in the training of the fault prediction model, it indicates that the training is completed, and the performance of the trained fault prediction model is tested using the training samples in the test set;

[0141] Integrate the trained fault prediction model into the automated test equipment;

[0142] Input the mechanical performance data and optical wave signal integrity data of the multi-Rank combination obtained by real-time monitoring into the fault prediction model, and output a binary label representing fault and normal.

[0143] S5. Based on the fault prediction result of the fault prediction model, combined with the conversion between linear address and physical address, locate the faulty memory granular unit.

[0144] When the prediction result of the fault prediction model represents a normal binary label, it means that all the memory granules in the multi-Rank combination are operating normally;

[0145] When the prediction result of the fault prediction model represents a faulty binary label, it means that a fault has occurred in the memory granules in the multi-Rank combination, and record the fault occurrence time;

[0146] Establish a mapping relationship between the linear address and the physical address according to the linear address range and the physical address range of the memory granule on the test board. The expression is as follows: ; ; ; Among them, is the physical address, is the scale factor, is the linear address, represents the starting offset of the physical address, and respectively represent the starting physical address and the ending physical address, and respectively represent the starting linear address and the ending linear address;

[0147] According to the fault time detected by the fault prediction model, extract the corresponding linear address range from the input data;

[0148] Specifically, according to the output time of the fault prediction model, determine the fault occurrence time window in the input data, screen the linear addresses within the fault time window from the data set, and extract the linear address range related to the fault;

[0149] Use the mapping relationship between the linear address and the physical address to convert the linear address into the physical address;

[0150] Determine the Rank number and the memory granule number by comparing the faulty physical address with the physical address intervals of each Rank. The expression is as follows: ; ; Among them, is the Rank number at the time of fault occurrence, and respectively represent the starting physical address and the ending physical address of the th Rank, is the memory die number at the time of fault occurrence, is the physical address span of a single memory die, is the starting physical address allocated by the Rank numbered in the memory physical address space;

[0151] Use an automated test equipment (ATE) to perform unit tests on the memory die with fault location, and verify the read / write performance and data integrity.

[0152] This embodiment also provides a multi-dimensional test system for memory dies, including: a multi-Rank combination module, a mechanical property data module, an integrity data module, a fault prediction module, and a fault location module.

[0153] The multi-Rank combination module is used to install multiple memory dies to be tested to form a multi-Rank combination, and simulate a high-load environment in actual use by setting an interleaved mapping mode; the mechanical property data module is used to perform high-frequency vibration and stress tests using SAW sensors, monitor the vibration and strain of the multi-Rank combination in real time, and output mechanical property data; the integrity data module is used to perform non-contact optical wave signal integrity tests using photonic crystal sensors, and output optical wave signal integrity data; the fault prediction module is used to predict potential faults using a fault prediction model based on the mechanical property data and optical wave signal integrity data of the multi-Rank combination; the fault location module is used to locate the faulty memory die unit based on the fault prediction result of the fault prediction model and in combination with the conversion between the linear address and the physical address.

[0154] This embodiment also provides a computer device applicable to the case of the multi-dimensional test method for memory dies, including: a memory and a processor; the memory is used to store computer-executable instructions, and the processor is used to execute the computer-executable instructions to implement the multi-dimensional test method for memory dies proposed in the above embodiment.

[0155] The computer device can be a terminal, which includes a processor, a memory, a communication interface, a display screen, and an input device connected via a system bus. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage medium. The communication interface of the computer device is used to communicate with external terminals in a wired or wireless manner, and the wireless manner can be implemented through WIFI, carrier network, NFC (Near Field Communication), or other technologies. The display screen of the computer device can be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer device can be a touch layer covering the display screen, or buttons, trackballs, or touchpads provided on the outer shell of the computer device, or an external keyboard, touchpad, or mouse, etc.

[0156] This embodiment also provides a storage medium, on which a computer program is stored. When the program is executed by a processor, it implements the multi-dimensional test method for memory particles as proposed in the above embodiment; the storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as Static Random Access Memory (SRAM for short), Electrically Erasable Programmable Read-Only Memory (EEPROM for short), Erasable Programmable Read-Only Memory (EPROM for short), Programmable Read-Only Memory (PROM for short), Read-Only Memory (ROM for short), magnetic memory, flash memory, magnetic disk, or optical disc.

[0157] In summary, the present invention: installs a multi-Rank combination and sets an interleaved mapping mode to simulate an actual high-load environment, making the test closer to the real application scenario, exposing potential problems in advance, uses a SAW sensor for high-frequency vibration and stress testing, and real-time collects mechanical performance data to evaluate the reliability of the particles in a dynamic stress environment. Through the non-contact optical wave signal integrity test of the photonic crystal sensor, accurately captures anomalies in high-speed signal transmission to ensure the stability of signal transmission. Combines the mechanical performance data and the optical wave signal integrity data, and through the fault prediction model, realizes the intelligent analysis and early warning of potential faults, improves the stability and reliability of the memory particles, and based on the mapping of the linear address and the physical address, accurately locates the faulty particle unit to provide support for the rapid maintenance of the fault.

[0158] Example 2. Referring to Table 1, this is the second example of the present invention. To further verify the technical solution of the present invention, experimental simulation data of the multi-dimensional test method for memory particles is given.

[0159] To verify the performance of memory particles with multi-Rank combinations in a high-load environment and the effectiveness of the fault prediction model, an experimental scheme was designed. First, 8 DDR4 memory particles (each with a capacity of 8GB and a frequency of 3200MHz) were selected, and a test board was made using FR-4 PCB material. According to the size and pin distribution of the memory particles to be tested, a multi-Rank structure with a double-sided layout was designed, with 4 Ranks arranged on each side, for a total of 8 Ranks. A JTAG interface was integrated on the test board for signal transmission and monitoring.

[0160] The memory particles were precisely soldered onto the pads by an automatic chip mounter. After soldering, an X-ray detection device was used to detect each solder joint to ensure the quality of the solder joints. Subsequently, the test board was connected to an automated test equipment (ATE), and the self-check program of the ATE was run to verify the hardware functions of the test board.

[0161] At the beginning of the experiment, each memory particle was initialized by the BIOS, and at the same time, the address mapping register configuration of the memory controller was verified to ensure that the interleaved mapping mode was enabled normally. On this basis, the mechanical properties of the memory particles were tested using SAW sensors.

[0162] SAW sensors were installed at the four corners of each memory particle, and by applying mechanical stresses with different frequencies and intensities, the acoustic wave propagation speed, phase change, and vibration frequency were recorded. In addition, non-contact optical wave signal integrity testing was carried out based on photonic crystal sensors to monitor key parameters such as the signal propagation speed, attenuation value, and reflection coefficient.

[0163] To compare the performance of the existing technology, a single-Rank memory particle layout was selected as the control group, and the same test steps were used for performance evaluation. All data in the experiment were automatically collected by the ATE and recorded in the experiment log. The following is a summary of the experimental data.

[0164] Specifically, as shown in Table 1 below:

[0165] Table 1 Comparison table of experimental data

[0166] From the analysis of the above experimental data, it can be seen that the use of the multi-Rank combination design of the present invention shows a significant performance improvement compared with the single-Rank combination layout;

[0167] In terms of fault prediction, the failure rate predicted by the multi-Rank combination of the present invention is 0.002, while that of the single-Rank combination is 0.035, and the failure rate is reduced by 94.3%. This result fully demonstrates that by combining the mechanical property data and optical wave signal integrity data of the multi-Rank combination through the fault prediction model, the present invention can more accurately predict potential faults, thereby significantly improving the reliability of memory particles.

[0168] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit them. Although the present invention has been described in detail with reference to the preferred embodiments, those of ordinary skill in the art should understand that the technical solutions of the present invention can be modified or equivalently replaced without departing from the spirit and scope of the technical solutions of the present invention, and they should all be covered by the scope of the claims of the present invention.

Claims

1. A memory chip multi-dimensional testing method, characterized by: include, Install multiple memory chips to form a multi-rank combination, and set the interleaved mapping mode to simulate the high-load environment in actual use; Use SAW sensors to perform high-frequency vibration and stress testing, monitor the vibration and strain of multi-Rank combinations in real time, and output mechanical performance data; Use photonic crystal sensors to conduct non-contact light wave signal integrity testing and output light wave signal integrity data; Based on the multi-rank combination of mechanical performance data and optical wave signal integrity data, the fault prediction model is used to predict potential faults; Based on the fault prediction results of the fault prediction model, combined with the conversion of linear address and physical address, the faulty memory particle unit is located.

2. The memory chip multi-dimensional testing method according to claim 1, characterized in that: The method comprises installing multiple memory chips to be tested to form a multi-rank combination, and simulating a high-load environment in actual use by setting an interleaved mapping mode. The specific steps are as follows: According to the size and pin distribution of the memory chip to be tested, a multi-rank layout of the test board is constructed. Each rank corresponds to a group of memory chips, and different ranks are arranged on both sides of the test board. Integrate an interface for connecting with test equipment on the test board; Use an automatic placement machine to mount the memory chips onto the pads of the test board; Connect the test board to the automated test equipment; Start the self-test program of the automated test equipment to check whether the hardware on the test board is working properly; Set the interleaved mapping mode to simulate the high-load environment in actual use; Configure the timing parameters, voltage parameters, and frequency parameters of the memory controller according to the specifications of the memory particles to be tested.

3. The memory chip multi-dimensional testing method according to claim 2, characterized in that: The SAW sensor is used to perform high-frequency vibration and stress testing, monitor the vibration and strain of the multi-Rank combination in real time, and output mechanical performance data. The specific steps are as follows: Use SAW sensors based on piezoelectric materials and evenly arrange multiple SAW sensors on the test board pads and signal channels; Use conductive glue to fix the SAW sensor; Under no-load conditions, the initial response characteristics of the SAW sensor were recorded; Apply mechanical stress and vibration, record the response changes of the SAW sensor, and adjust the sensitivity and linearity of the sensor by comparing the actual values ​​of strain and vibration frequency with the measured values ​​of the SAW sensor; Set the vibration frequency range according to the application scenario of the memory particles; Set stress intensity according to the memory chip specifications and application scenarios; Apply vibration and stress to the test plate according to the settings of vibration frequency and stress intensity; While applying vibration and stress to the test board, the SAW sensor outputs the propagation speed and phase change of the sound wave through the reflection propagation of the sound wave on the surface of each memory particle; By measuring the propagation time difference of the sound wave on the surface of the memory particle, the vibration frequency of the memory particle is calculated; By analyzing the phase change of the sound wave and combining it with the elastic mechanics formula, the strain of the memory particles is calculated; The vibration frequency and strain of the memory particles are output as mechanical property data.

4. The memory chip multi-dimensional testing method according to claim 3, characterized in that: The non-contact light wave signal integrity test using a photonic crystal sensor to output light wave signal integrity data is specifically performed as follows: Install photonic crystal sensors on the signal pins of each memory chip to form a surrounding array; The photonic crystal sensor is calibrated under no-load conditions and under conditions of applying light wave signals; Set the frequency range of light wave signal transmission according to the working frequency and application scenario of the memory particles; Set the signal transmission intensity range according to the voltage parameters of the memory chips and the application scenarios; Based on the pin distribution and signal routing design of memory particles, differential signal transmission is used; The signal generator is controlled by the automated test equipment to send a light wave signal with a set frequency and intensity range to the memory chip; Real-time monitoring of the propagation speed, amplitude and phase changes of light wave signals through photonic crystal sensors; Calculate the attenuation value of the light wave signal based on the amplitude change of the light wave signal monitored in real time; Based on the propagation speed of the light wave signal, the reflection coefficient of the light wave signal is calculated; By monitoring the phase change of the light wave signal, the phase difference between the input light wave signal and the output light wave signal is calculated; The light wave signal attenuation value, reflection coefficient and phase difference are output as light wave signal integrity data.

5. The memory chip multi-dimensional testing method according to claim 4, characterized in that: The mechanical performance data and optical wave signal integrity data based on the multi-rank combination are used to predict potential faults using a fault prediction model. The specific steps are as follows: Collect and process the historical data of mechanical performance and optical signal integrity of memory chips in the multi-rank combination under normal working conditions and fault conditions; Shuffle the processed training samples and divide them into training set, validation set and test set; Based on the convolutional neural network, a fault prediction model is constructed, and the training set is input into the fault prediction model. According to the fault risk score output by the fault prediction model, it is judged whether a fault occurs and the predicted binary label is output; Based on the predicted binary labels and the actual binary labels, the loss value of the fault prediction model is calculated using the binary cross entropy loss function; Calculate the gradient of the loss to the fault prediction model parameters through the gradient descent algorithm, and update the fault prediction model parameters; Based on the Adam optimization algorithm, the fault prediction model parameters are dynamically adjusted to minimize the loss function; After each training, evaluate the performance of the fault prediction model on the validation set and record the results; When all training samples in the training set participate in the training of the fault prediction model, the training is completed, and the training samples in the test set are used to perform a performance test on the trained fault prediction model; Integrate the trained fault prediction model into automated test equipment; The multi-rank combined mechanical performance data and optical wave signal integrity data obtained by real-time monitoring are input into the fault prediction model, and the output is a binary label representing fault and normal.

6. The memory chip multi-dimensional testing method according to claim 5, characterized in that: The historical data of mechanical properties and optical wave signal integrity of memory particles in the multi-Rank combination under normal working conditions and fault conditions are collected and processed. The specific steps are as follows: Add a unified timestamp based on the collection time of each piece of historical data; The mechanical performance data and optical wave signal integrity data in the historical data are integrated into training samples, and a binary label representing normal and fault is added to each training sample; Use filtering algorithms to remove high-frequency noise and statistical methods to remove outliers; The Min-Max normalization method is used to map historical data to a specific range.

7. The memory chip multi-dimensional testing method according to claim 6, characterized in that: The fault prediction result based on the fault prediction model is combined with the conversion of linear address and physical address to locate the faulty memory particle unit. The specific steps are as follows: When the fault prediction model prediction result indicates a normal binary label, it means that the memory particles in the multi-rank combination are operating normally; When the fault prediction model predicts a binary label of a fault, it means that a memory particle in the multi-rank combination fails, and the time of the failure is recorded; According to the linear address range and physical address range of the memory particles on the test board, a mapping relationship between the linear address and the physical address is established; According to the fault time detected by the fault prediction model, the corresponding linear address range is extracted from the input data; Using the mapping relationship between linear addresses and physical addresses, the linear address is converted into a physical address; The Rank number and memory particle number are determined by comparing the fault physical address and the physical address interval of each Rank. The expression is as follows: ； ； in, It is the Rank number when the fault occurs. is the physical address, and Respectively represent The starting and ending physical addresses of each Rank. The memory chip number when the fault occurred. is the physical address span of a single memory particle, Number The starting physical address of the Rank allocated in the memory physical address space; Use automated testing equipment to perform unit tests on the fault-located memory particles to verify read and write performance and data integrity.

8. A memory chip multi-dimensional testing system, based on the memory chip multi-dimensional testing method according to any one of claims 1 to 7, characterized in that: Including multi-rank combination module, mechanical performance data module, integrity data module, fault prediction module and fault location module. The multi-rank combination module is used to install multiple memory particles to be tested to form a multi-rank combination, and simulate the high-load environment in actual use by setting an interleaved mapping mode; The mechanical performance data module is used to perform high-frequency vibration and stress testing using a SAW sensor, monitor the vibration and strain of a multi-Rank combination in real time, and output mechanical performance data; The integrity data module is used to perform non-contact light wave signal integrity testing using a photonic crystal sensor and output light wave signal integrity data; The fault prediction module is used to predict potential faults using a fault prediction model based on the mechanical performance data and light wave signal integrity data of the multi-rank combination; The fault location module is used to locate the faulty memory particle unit based on the fault prediction result of the fault prediction model in combination with the conversion of the linear address and the physical address.

9. A computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the memory particle multi-dimensional testing method described in any one of claims 1 to 7 are implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the multi-dimensional testing method for memory particles described in any one of claims 1 to 7 are implemented.

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