A testing method and system for industrial-grade memory

Abstract

The present invention discloses a method and system for testing industrial-grade memory, which relates to the technical field of computer hardware testing. The method includes collecting memory status data and preprocessing the memory status data; based on the preprocessed memory status data, simulating the load on the memory and predicting the memory performance level; simulating memory errors through the fault injection method, analyzing the error detection probability of the memory in real time, and evaluating the fault repair level of the memory; and generating a memory test report based on the memory performance level and the fault repair level. The present invention can not only simulate and evaluate the real error response of the memory in an experimental environment, but also provide an important basis for optimizing the stability and reliability of the memory, and is particularly applicable to industrial-grade memory applications with high load and high reliability requirements.

Description

Technical Field

[0001] The present invention relates to the technical field of computer hardware testing, and particularly to a testing method and system for industrial-grade memory. Background Art

[0002] In modern computing systems, memory, as the core component for data storage and processing, its performance and reliability play a crucial role in the overall operating efficiency of the memory. With the rapid development of information technology, the application scenarios of industrial-grade memory are becoming increasingly complex, not only requiring higher read / write speeds and lower latencies, but also having to possess powerful error detection and correction capabilities. Traditional memory testing methods mainly focus on the measurement of static parameters and simple load testing. Although this method can reflect the basic performance of the memory to a certain extent, it is unable to cope when faced with dynamically changing workloads and complex error patterns. In recent years, with the development of technologies such as machine learning and big data analysis, more and more research has begun to focus on how to improve the effectiveness of memory testing through intelligent means to meet the growing data processing requirements.

[0003] There are two main deficiencies in the existing related technologies: First, traditional methods lack comprehensive preprocessing of memory state data, resulting in inaccurate and unstable test results. For example, directly analyzing raw data without standardization and noise removal may introduce a large amount of error, affecting the accuracy of the final evaluation. Second, existing technologies mostly adopt static or semi-static methods in fault injection and error detection, and fail to fully consider the change of memory state over time and its impact on the error correction mechanism. This limitation makes it difficult for traditional testing methods to capture the dynamic behavior of the memory during actual operation, especially its performance under high load and complex environments. Summary of the Invention

[0004] In view of the above existing problems, the present invention is proposed.

[0005] Therefore, the present invention provides a testing method for industrial-grade memory to solve the problems of inaccurate test results and difficulty in capturing the actual operating behavior of the memory in the prior art.

[0006] To solve the above technical problems, the present invention provides the following technical solutions:

[0007] In a first aspect, the present invention provides a testing method for industrial-grade memory, which includes collecting memory state data and preprocessing the memory state data; based on the preprocessed memory state data, simulating the load on the memory to predict the memory performance level; simulating memory errors through the fault injection method, analyzing the error detection probability of the memory in real time, and evaluating the fault repair level of the memory; generating a memory test report based on the memory performance level and the fault repair level.

[0008] As a preferred solution of the test method for industrial-grade memory described in the present invention, wherein: the memory state data includes the temperature, voltage, frequency, read / write rate, error rate, and usage rate of the memory.

[0009] As a preferred solution of the test method for industrial-grade memory described in the present invention, wherein: the preprocessing of the memory state data is specifically carried out as follows.

[0010] Standardization is adopted to adjust different types of memory state data to a unified dimension and range.

[0011] The memory state data is smoothed by the moving average method.

[0012] The memory state data is time-aligned and synchronized through timestamp alignment.

[0013] The outlier correction method is adopted to remove the noise data in the memory state data.

[0014] As a preferred solution of the test method for industrial-grade memory described in the present invention, wherein: based on the preprocessed memory state data, the memory is subjected to load simulation to predict the memory performance level, and the specific steps are as follows.

[0015] The preprocessed memory state data is used as different dimensions to define the high-dimensional space of the memory state.

[0016] Based on the high-dimensional space of the memory state, a load simulation model is constructed through a nonlinear dynamics model.

[0017] By analyzing the interaction relationship between memory state data from historical data, the dynamic evolution law of memory state data during the load change process is extracted, and the simulation rules are defined.

[0018] In the high-dimensional space of the memory state, based on the simulation rules, the evolution law of the memory state with the load change is simulated to predict the memory performance level, and the expression is:

[0019] ;

[0020] Wherein, is the memory performance level, represents the start time of the load simulation, represents the end time of the load simulation, represents the total number of memory state data, is the weight coefficient of the is the nonlinear attenuation factor of the influence of the represents the The value of a memory state data at time , is the amplitude factor of the sine function, represents the frequency factor indicating the load change, represents the overall load intensity at time .

[0021] As a preferred solution of the test method for the industry - level memory described in the present invention, wherein: simulating memory errors through the fault injection method and analyzing the error detection probability of the memory in real - time, the specific steps are as follows,

[0022] Defining memory error types based on historical fault data and memory error patterns;

[0023] Adopting a random distribution method to randomly distribute memory error types at different positions in the memory and monitoring the dynamic changes of memory state data in real - time;

[0024] According to the dynamic changes of memory state data, through complex integral and product operations combined with the Logistic function and power function, capturing the combined influence of the dynamic changes of each memory state data on the ECC error detection efficiency and the time - cumulative effect, and analyzing the error detection probability of the memory in real - time. The expression is:

[0025] ;

[0026] Wherein, is the error detection probability of the memory at time , is the initial time point of error detection, represents the current time, represents the total number of memory state data, is the sensitivity factor of the influence of the th memory state data on error detection, is the standard value of the th memory state data, is the slope parameter of the Logistic function, is the decision threshold of the th memory state data, is the maximum expected value of the th memory state data, is the weight coefficient of the th memory state data during the error detection process.

[0027] As a preferred solution of the test method for the industry - level memory described in the present invention, wherein: evaluating the fault repair level of the memory, the specific steps are as follows,

[0028] After the memory completes error detection through ECC, combined with the error detection probability of the memory and the time from the discovery of a memory error to the completion of repair, by introducing logarithmic and squared sine functions to capture the error correction efficiency and the impact of uncorrected errors, and comprehensively considering the recovery time and state changes, the memory fault repair level is evaluated. The expression is:

[0029] ;

[0030] where, is the memory fault repair score at time , is the total number of faults, is the weight coefficient of the th fault, is the proportion of the th fault that has been repaired, is the proportion of the th fault that has not been corrected, is the recovery time of the th fault, is the time that the memory remains unstable after the th fault occurs, is the sensitivity factor of the memory state data to the impact on the recovery time, is the th change in the memory state before and after the

[0031] As a preferred solution of the test method for the industry-level memory described in the present invention, wherein: the memory test report includes the memory performance level, the error detection probability of the memory, the memory fault repair score, and optimization suggestions.

[0032] In a second aspect, the present invention provides a test system for industry-level memory, including a data acquisition module, a performance level prediction module, a repair level evaluation module, and a test report generation module; the data acquisition module is used to collect memory state data and preprocess the memory state data; the performance level prediction module is used to simulate the load of the memory based on the preprocessed memory state data and predict the memory performance level; the repair level evaluation module is used to simulate memory errors by the fault injection method, analyze the error detection probability of the memory in real time, and evaluate the memory fault repair level; the test report generation module is used to generate a memory test report based on the memory performance level and the fault repair level.

[0033] In a third aspect, the present invention provides a computer device, including a memory and a processor, where: when the computer program stored in the memory is executed by the processor, any step of the test method for the industry-level memory described in the first aspect of the present invention is implemented.

[0034] In a fourth aspect, the present invention provides a computer-readable storage medium having a computer program stored thereon, wherein: when the computer program is executed by a processor, any step of the method for testing an industrial-grade memory as described in the first aspect of the present invention is implemented.

[0035] The beneficial effects of the present invention are as follows: By using the fault injection method to simulate memory errors, combining historical fault data and memory error patterns, the change of the memory state is monitored in real time, and the error detection probability of the memory is evaluated through complex mathematical operations. This method can accurately simulate the performance of the memory under different fault conditions, quantify the efficiency of memory error detection, and provide data support for the memory fault tolerance mechanism and repair ability. The present invention can not only simulate and evaluate the real error response of the memory in the experimental environment, but also provide an important basis for optimizing the stability and reliability of the memory, and is particularly suitable for industrial-grade memory applications with high load and high reliability requirements. Description of the Drawings

[0036] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0037] Figure 1 It is a flowchart of the method for testing an industrial-grade memory in Embodiment 1.

[0038] Figure 2 It is a schematic diagram of the system for testing an industrial-grade memory in Embodiment 1. Detailed Embodiments

[0039] In order to make the above objects, features, and advantages of the present invention more obvious and understandable, the following will make a detailed description of the specific embodiments of the present invention with reference to the drawings in the specification.

[0040] Many specific details are set forth in the following description in order to fully understand the present invention. However, the present invention can also be implemented in other ways different from those described herein. Those skilled in the art can make similar extensions without departing from the connotation of the present invention. Therefore, the present invention is not limited by the specific embodiments disclosed below.

[0041] Secondly, the so-called "one embodiment" or "embodiment" herein refers to a specific feature, structure, or characteristic that can be included in at least one implementation of the present invention. The phrase "in one embodiment" appearing in different places in this specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment that excludes other embodiments.

[0042] Embodiment 1, refer toFigure 1 and Figure 2 , which is the first embodiment of the present invention. This embodiment provides a method for testing industrial-grade memory, including the following steps:

[0043] S1: Collect memory status data and preprocess the memory status data;

[0044] S1.1: The memory status data includes the temperature, voltage, frequency, read / write rate, error rate, and utilization rate of the memory.

[0045] Furthermore, the memory status data is collected separately by a variety of high-precision sensors: the temperature is monitored by a thermistor, the voltage is recorded by a voltage sensor, the frequency is measured by a frequency meter, the read / write rate is obtained with the help of a performance monitoring tool, the error rate is detected by a built-in ECC module, and the utilization rate is statistically analyzed through system monitoring software. These sensors capture and record the key operating parameters of the memory in real time to ensure the accuracy and reliability of the data.

[0046] S1.2: Adopt standardization to adjust different types of memory status data to a unified dimension and range;

[0047] Specifically, through the standardization process, the temperature data range from 50°C to 80°C is converted to a unified dimension from 0 to 1, ensuring that different types of data can be compared and processed on the same scale.

[0048] S1.3: Smooth the memory status data by the moving average method;

[0049] Specifically, use the moving average method to smooth the temperature data at the past 10 time points to reduce sudden temperature fluctuations and obtain a more stable temperature trend.

[0050] S1.4: Align and synchronize the memory status data in time through timestamp alignment;

[0051] Specifically, through timestamp alignment, synchronize the temperature and voltage data from different sources at the same time point so that these data can correctly reflect within the same time window.

[0052] S1.5: Adopt the outlier correction method to remove the noise data in the memory status data.

[0053] Specifically, through the outlier correction method, remove the obviously unreasonable data points, such as the abnormal voltage reading of 0V. These data points may be noise data caused by sensor failures or acquisition errors.

[0054] S2: Based on the preprocessed memory status data, perform a load simulation on the memory and predict the memory performance level;

[0055] S2.1: Define the high-dimensional space of the memory state by using the preprocessed memory state data as different dimensions.

[0056] Furthermore, consider the preprocessed memory state data (such as temperature, voltage, frequency, read / write rate, error rate, and utilization rate) as multiple different dimensions, where each dimension represents a specific memory state feature. Then, map the specific value of each memory state to the corresponding dimension to form a multi-dimensional memory state vector. To ensure the consistency and comparability of the data in each dimension, all the values will be standardized to the same dimension and range. Finally, define a high-dimensional space through these standardized data, where each memory state sample corresponds to a point in this space, which can reflect the mutual relationship and dynamic evolution between different memory states.

[0057] S2.2: Based on the high-dimensional space of the memory state, construct a load simulation model through a non-linear dynamics model.

[0058] Furthermore, utilize the memory state features (such as temperature, voltage, frequency, etc.) corresponding to each dimension in the high-dimensional space and their mutual relationship to construct a dynamic equation reflecting the change of the memory state. Analyze the interaction between memory states through historical data, and extract the non-linear behavior and time-series dependence relationship that each state feature may present during the load change process. Then, describe these rules through non-linear dynamics equations (such as introducing an exponential decay term and a sine oscillation term), and define the simulation rules. Finally, based on these rules, simulate the evolution process of the memory state under different loads, so as to predict the change trend of the memory performance. This model can effectively capture the dynamic response of the memory state under complex load conditions and provide accurate mathematical support for memory performance prediction.

[0059] S2.3: Analyze the interaction relationship between memory state data from historical data, extract the dynamic evolution law of memory state data during the load change process, and define the simulation rules.

[0060] Furthermore, historical memory state data covering a variety of workload conditions are collected, including multi-dimensional information such as temperature, voltage, frequency, read / write rate, error rate, and utilization rate. Then, advanced data analysis algorithms (such as time series analysis and association rule mining) are applied to identify the complex dependencies between these state parameters and their evolution patterns under different load conditions. Based on this, a non-linear dynamics model is used to model these interaction relationships, capturing the dynamic characteristics of the memory state changing over time. Next, according to the extracted dynamic evolution rules, detailed simulation rules are defined to describe the changes in each state parameter and their cooperation mechanism under specific load conditions. Finally, these rules are applied to load simulation in a high-dimensional space to ensure that the simulation results can truly reflect the performance of the memory in the actual operating environment, thereby achieving accurate prediction of the memory performance level.

[0061] S2.4: In the high-dimensional space of the memory state, simulate the evolution law of the memory state changing with the load based on the simulation rules, and predict the memory performance level. The expression is:

[0062] ;

[0063] where, is the memory performance level, represents the start time of the load simulation, represents the end time of the load simulation, represents the total number of memory state data, is the weight coefficient of the th memory state data, is the non-linear attenuation factor of the th memory state data on the performance impact, represents the th memory state data at time is the amplitude factor of the sine function, represents the frequency factor of the load change, represents at time the overall load intensity.

[0064] The specific process is as follows: The preprocessed multi-dimensional memory state data are mapped into a high-dimensional space to comprehensively capture various characteristics of the memory and their interactions. Then, combined with the exponential decay and sine wave functions, the changing characteristics of the memory state and their impact on performance are dynamically simulated. Through integral operation, the time cumulative effect of the memory performance under different states and the periodic change of the overall load intensity are comprehensively considered. This method not only reflects the memory performance under the current load conditions but also considers the dynamic change trends in historical data, thereby achieving accurate prediction of the memory performance level and ensuring the authenticity and reliability of the test results.

[0065] S3: Simulate memory errors through the fault injection method, analyze the error detection probability of the memory in real time, and evaluate the fault repair level of the memory;

[0066] S3.1: Define memory error types based on historical fault data and memory error patterns;

[0067] It should be noted that the memory error patterns include the occurrence frequencies and distributions of single-bit errors, multi-bit errors, transient errors, permanent errors, and intermittent errors, as well as the performance characteristics of these errors under different workloads;

[0068] Memory error types include bit flips, address line faults, data line faults, uncorrectable errors (such as errors that cannot be repaired by ECC), and errors caused by other hardware defects, such as errors caused by power fluctuations or instability caused by overheating.

[0069] S3.2: Adopt a random distribution method to randomly distribute memory error types at different positions in the memory, and monitor the dynamic changes of memory status data in real time;

[0070] The specific process is as follows. According to the defined memory error types (such as bit flips, address line faults, etc.), these error types are injected into different areas of the memory by random selection to simulate various error situations that may occur during actual operation. At the same time, a real-time monitoring system is used to continuously track the changes in memory status data, including key indicators such as temperature, voltage, frequency, read / write rate, error rate, and utilization rate, to ensure that any abnormal behavior and its impact on memory performance can be captured in a timely manner.

[0071] S3.3: According to the dynamic changes of memory status data, capture the combined impact of the dynamic changes of each memory status data on the ECC error detection efficiency and the time cumulative effect through complex integration and multiplication operations combined with the Logistic function and the power function, and analyze the error detection probability of the memory in real time. The expression is:

[0072] ;

[0073] where, is the error detection probability of the memory at time , is the initial time point of error detection, represents the current time, represents the total number of memory status data, is the sensitivity factor of the th memory status data on error detection, is the standard value of the th memory status data, is the slope parameter of the Logistic function, is the decision threshold for the th memory state data, is the maximum expected value for the th memory state data, is the weight coefficient for the th memory state data during the error detection process.

[0074] It should be noted that the standard value of the memory state data is obtained by analyzing the normal operating state in historical data and determining the typical or average value of each memory state data.

[0075] The decision threshold of the memory state data is set based on historical failure data and experimental tests, and is a critical value used to distinguish normal operation from potential error states;

[0076] S3.4: After the memory completes error detection through ECC, combined with the error detection probability of the memory and the time from discovering a memory error to completing the repair, by introducing logarithmic and sine-squared functions to capture the error correction efficiency and the impact of uncorrected errors, and comprehensively considering the recovery time and state changes, evaluate the memory fault repair level. The expression is:

[0077] ;

[0078] where, is the memory fault repair score at time , is the total number of fault occurrences, is the weight coefficient for the th fault, is the proportion of the th fault that has been repaired, is the proportion of the th fault that has not been corrected, is the recovery time for the th fault, is the time that the memory remains unstable after the th fault occurs, is the sensitivity factor of the memory state data to the impact of the recovery time, is the change in the memory state before and after the th fault.

[0079] The specific process is as follows: evaluate the error correction efficiency of each fault according to the error detection probability, and use the logarithmic function to capture the change of this efficiency; then, use the squared sine function to quantify the impact of uncorrected errors, reflecting the cumulative effect of these errors in the memory; at the same time, comprehensively consider the recovery time of each fault and the change of the memory state, analyze the time when the memory remains unstable after the fault occurs and its impact on the overall performance; finally, integrate these factors and obtain a comprehensive score through mathematical operations to comprehensively evaluate the fault repair level of the memory.

[0080] S4: Generate a memory test report based on the memory performance level and the fault repair level.

[0081] S4.1: The memory test report includes the memory performance level, the error detection probability of the memory, the fault repair score of the memory, and optimization suggestions.

[0082] Furthermore, the memory test report reflects the operating conditions and reliability of the memory under different load conditions. By analyzing the performance level in detail, key parameters such as the read / write rate, temperature, and voltage of the memory are evaluated; the error detection probability reveals the efficiency of the ECC mechanism in capturing and correcting errors; the fault repair score comprehensively considers the error correction efficiency, recovery time, and state change to ensure an accurate assessment of the memory stability. Based on these data, the report also provides targeted optimization suggestions to help users improve the memory configuration and management strategy, thereby enhancing the overall operating efficiency and stability of the memory.

[0083] This embodiment also provides a test system for industrial-grade memory, including: a data acquisition module, a performance level prediction module, a repair level evaluation module, and a test report generation module; the data acquisition module is used to collect memory state data and preprocess the memory state data; the performance level prediction module is used to simulate the load of the memory based on the preprocessed memory state data and predict the memory performance level; the repair level evaluation module is used to simulate memory errors through the fault injection method, analyze the error detection probability of the memory in real time, and evaluate the fault repair level of the memory; the test report generation module is used to generate a memory test report based on the memory performance level and the fault repair level.

[0084] This embodiment also provides a computer device applicable to the case of the test method for industrial-grade memory, including: a memory and a processor; the memory is used to store computer-executable instructions, and the processor is used to execute the computer-executable instructions to implement the test method for industrial-grade memory as proposed in the above embodiment.

[0085] The computer device may be a terminal, which includes a processor, a memory, a communication interface, a display screen, and an input device connected via a system bus. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage medium. The communication interface of the computer device is used to communicate with external terminals in a wired or wireless manner, and the wireless manner can be implemented through WIFI, a carrier network, NFC (Near Field Communication), or other technologies. The display screen of the computer device can be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer device can be a touch layer covered on the display screen, or a button, a trackball, or a touchpad set on the outer shell of the computer device, or an external keyboard, touchpad, or mouse, etc.

[0086] This embodiment also provides a storage medium, on which a computer program is stored. When the program is executed by a processor, it implements the method for testing industry-level memory proposed in the above embodiment; the storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (abbreviated as SRAM), electrically erasable programmable read-only memory (abbreviated as EEPROM), erasable programmable read-only memory (abbreviated as EPROM), programmable read-only memory (abbreviated as PROM), read-only memory (abbreviated as ROM), magnetic memory, flash memory, a magnetic disk, or an optical disc.

[0087] In summary, the present invention: simulates memory errors through the fault injection method, combines historical fault data and memory error patterns, monitors the change of memory status in real time, and evaluates the error detection probability of the memory through complex mathematical operations. This method can accurately simulate the performance of the memory under different fault conditions, quantify the efficiency of memory error detection, and provide data support for the fault tolerance mechanism and repair ability of the memory. The present invention can not only simulate and evaluate the real error response of the memory in an experimental environment, but also provide an important basis for optimizing the stability and reliability of the memory, and is especially applicable to industry-level memory applications with high load and high reliability requirements.

[0088] Example 2. Referring to Table 1, this is the second example of the present invention. To further verify the technical solution of the present invention, experimental simulation data of the test method for industrial-grade memory is given.

[0089] To verify the effectiveness of an industrial-grade memory test method proposed by the present invention, a set of comparative experiments was designed. The experimental objects included two different test methods: one was traditional memory using traditional methods, and the other was improved memory applying the method of the present invention. Each memory instance was tested under the same hardware configuration and environmental conditions to ensure fairness and comparability.

[0090] First of all, to verify the effectiveness of the method of the present invention, a set of comparative experiments was designed. The experimental objects included traditional memory using traditional methods and improved memory applying the method of the present invention. Both were tested under the same hardware configuration and environment to ensure fairness. Data such as temperature, voltage, frequency, read / write rate, error rate, and usage rate were collected in real time through high-precision sensors and transmitted to the central processing unit.

[0091] Secondly, the method of the present invention preprocessed the collected data, including standardization, smoothing processing by the moving average method, timestamp alignment, and outlier correction. Based on these preprocessed data, a high-dimensional space was constructed, memory state characteristics were defined, and a nonlinear dynamics model was introduced to simulate the dynamic changes under different load conditions.

[0092] Then, to evaluate the error detection and repair capabilities, a fault injection experiment was carried out. According to common memory error patterns, error types were randomly distributed and the changes in memory state data were monitored in real time. The method of the present invention used complex operations combined with the Logistic function and power function to analyze the error detection probability, and evaluated the fault repair level by introducing the logarithmic function and the sine squared function.

[0093] Finally, a detailed memory test report was generated, including performance level, error detection probability, fault repair score, and optimization suggestions. The experimental data showed that the method of the present invention was significantly superior to the traditional method in terms of performance, error detection, and fault repair.

[0094] The traditional method adopted simple data aggregation and preliminary analysis, relied on preset fixed thresholds to detect abnormal situations, and in terms of load simulation and fault injection, used relatively static and linear models, which could not comprehensively capture the dynamic changes and nonlinear behaviors of the memory state.

[0095] Specifically, as shown in Table 1 below:

[0096] Table 1 Comparison data table of memory performance and fault repair

[0097]

[0098] Through the data analysis of the above table, it can be clearly seen that the method of the present invention is significantly superior to the traditional method in multiple key performance indicators. By introducing comprehensive preprocessing steps, non-linear dynamic models, and complex mathematical operations, the present invention has greatly improved the accuracy and reliability of memory testing. For example, at a temperature of 63.1°C and a voltage of 1.21V, the read / write rate of the method of the present invention reaches 3410 MB / s, while the traditional method is only 3175 MB / s; at the same time, the error detection probability of the method of the present invention is as high as 98.4%, far higher than 94.6% of the traditional method. In addition, in terms of the fault repair score, the method of the present invention also performs excellently, with a score of 91.8, showing a significant improvement compared to 77.2 of the traditional method. These data fully demonstrate the superiority of the method of the present invention in improving memory performance, enhancing error detection ability, and optimizing fault repair.

[0099] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit them. Although the present invention has been described in detail with reference to the preferred embodiments, those of ordinary skill in the art should understand that the technical solutions of the present invention can be modified or equivalently replaced without departing from the spirit and scope of the technical solutions of the present invention, and they should all be covered within the scope of the claims of the present invention.

Claims

1. A testing method for industrial-grade memory, characterized in that: including collecting memory status data and preprocessing the memory status data; simulating the memory load based on the preprocessed memory status data to predict the memory performance level; simulating memory errors through the fault injection method, analyzing the error detection probability of the memory in real time, and evaluating the memory fault repair level; generating a memory test report based on the memory performance level and the fault repair level; The step of simulating the memory load based on the preprocessed memory status data to predict the memory performance level is as follows Taking the preprocessed memory status data as different dimensions to define the high-dimensional space of the memory status; Based on the high-dimensional space of the memory status, constructing a load simulation model through a non-linear dynamics model; By analyzing the interaction relationship between memory status data from historical data, extracting the dynamic evolution law of memory status data during the load change process, and defining the simulation rules; In the high-dimensional space of the memory status, simulating the evolution law of the memory status with the change of the load based on the simulation rules to predict the memory performance level, and the expression is: ； Among them, is the memory performance level, represents the start time of load simulation, represents the end time of load simulation, represents the total number of memory state data, is the weight coefficient of the th memory state data, is the non-linear attenuation factor of the th memory state data on performance, represents the value of the th memory state data at time is the amplitude factor of the sine function, represents the frequency factor of load change, represents the overall load intensity at time ; The step of simulating memory errors through the fault injection method and analyzing the error detection probability of the memory in real time is as follows Defining memory error types based on historical fault data and memory error patterns; Using a random distribution method to randomly distribute the memory error types at different positions in the memory, and monitoring the dynamic changes of the memory status data in real time; According to the dynamic changes of the memory status data, through complex integration and multiplication operations combined with the Logistic function and the power function, capturing the joint influence of the dynamic changes of each memory status data on the ECC error detection efficiency and the time cumulative effect, and analyzing the error detection probability of the memory in real time, and the expression is: ； wherein, is the time when the error detection probability of the memory, is the initial time point of error detection, represents the current time, represents the total number of memory state data, is the sensitivity factor of the th memory state data pair on error detection, is the standard value of the th memory state data, is the slope parameter of the Logistic function, is the th decision threshold of the memory state data, is the th maximum expected value of the memory state data, is the th weight coefficient of the memory state data in the error detection process.

2. The test method for industrial-level memory according to claim 1, wherein: The memory status data includes the temperature, voltage, frequency, read / write rate, error rate, and usage rate of the memory.

3. The test method for industrial-grade memory according to claim 2, characterized in that: The step of preprocessing the memory status data is as follows Adopting standardization to adjust different types of memory status data to a unified dimension and range; Smoothing the memory status data through the moving average method; Aligning and synchronizing the memory status data in time through timestamp alignment; Adopting the outlier correction method to remove the noise data in the memory status data.

4. The test method for industrial-grade memory according to claim 1, characterized in that: The step of evaluating the memory fault repair level is as follows After the memory completes error detection through ECC, combined with the error detection probability of the memory and the time from the discovery of a memory error to the completion of repair, by introducing logarithmic and squared sine functions to capture the error correction efficiency and the impact of uncorrected errors, and comprehensively considering the recovery time and state changes, the memory fault repair level is evaluated. The expression is as follows: ； Among them, is the fault repair score of the memory at time . is the total number of fault occurrences, is the weight coefficient of the -th fault, is the repaired proportion of the -th fault, is the proportion of the -th fault that is not corrected, is the recovery time of the -th fault, is the time that the memory remains unstable after the -th fault occurs, is the sensitivity factor of the memory state data to the recovery time, is the change amount of the memory state before and after the -th fault.

5. The test method for industrial-level memory according to claim 4, characterized in that: The memory test report includes the memory performance level, the error detection probability of the memory, the memory fault repair score, and optimization suggestions.

6. An industry-level memory test system, based on the industry-level memory test method according to any one of claims 1 to 5, characterized in that: including a data acquisition module, a performance level prediction module, a repair level evaluation module, and a test report generation module; The data acquisition module is used to collect memory status data and preprocess the memory status data; The performance level prediction module is used to simulate the memory load based on the preprocessed memory status data to predict the memory performance level; The repair level evaluation module is used to simulate memory errors through the fault injection method, analyze the error detection probability of the memory in real time, and evaluate the memory fault repair level; The test report generation module is used to generate a memory test report based on the memory performance level and the fault repair level.

7. A computer device, comprising a memory and a processor, the memory storing a computer program, characterized in that: When the processor executes the computer program, the steps of the test method for the industrial-level memory according to any one of claims 1 to 5 are implemented.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by the processor, the steps of the test method for the industrial-level memory according to any one of claims 1 to 5 are implemented.

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