Implementation method of FIR multiphase filter based on FPGA
By setting multiple coefficient groups and configuring coefficient selection switches and multipliers on the FPGA, and selecting coefficients by rotary cycle method for multiplication and accumulation, the optimization space for the computing resource utilization and power consumption of FPGA multiphase filters in the prior art is solved, and more efficient resource use and flexible selection are achieved.
Patent Information
- Application Number
- CN202411370592.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-29
- Publication Date
- 2025-05-30
AI Technical Summary
The existing FPGA-based FIR polyphase filter has room for optimization in terms of computing resource utilization and power consumption, especially when dealing with multiple bandwidth filters, resource usage efficiency is low.
By setting multiple coefficient groups, setting D coefficient fill bits in each coefficient group, and configuring coefficient selection switches and multipliers, selecting coefficients for multiplication and accumulation in a rotary cycle manner, achieving efficient processing of multiple bandwidth filters.
Optimize the use and power consumption of FPGA computing resources, increase the flexibility of FPGA selection, simplify code, and reduce the airworthiness review cost of electronic complex hardware.
Smart Images
Figure CN120074447A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of digital signal processing, and particularly relates to a method for implementing an FIR polyphase filter based on FPGA. Background Art
[0002] The signal processing technology of FIR digital filters based on FPGA has been widely applied in industries such as radar, communication, and image processing. By utilizing the flexible parallel processing ability of FPGA, the operation speed is improved, but the cost is an increase in the use of operation resources. Summary of the Invention
[0003] In view of this, the present invention provides a method for implementing an FIR polyphase filter based on FPGA. For a specific digital filtering application scenario, based on the original polyphase filtering algorithm and combined with the FPGA architecture, the coefficient group setting method, coefficient update method, and operation method are set, effectively optimizing the utilization rate of operation resources.
[0004] The technical solution of the present invention is as follows:
[0005] A method for implementing an FIR polyphase filter based on FPGA is used to perform filtering operations on filters of N bandwidths; the implementation method includes:
[0006] When the number of filtering coefficients of each filter in the FIR polyphase filter is M, and the filtering decimation factor of each filter is D, then multiple coefficient groups are set, D coefficient filling bits are set in each coefficient group, and a coefficient selection switch and a multiplier are configured for each coefficient group;
[0007] The FIR polyphase filter performs the following steps on the filter of the first bandwidth:
[0008] S101: Fill the M coefficients corresponding to the filter of the first bandwidth in the filling bits of each coefficient group;
[0009] S102: When the first data of the filter of the first bandwidth arrives, select one coefficient in each coefficient group for multiplication and accumulation;
[0010] S103: When the next data of the filter of the first bandwidth arrives, select the next coefficient in each coefficient group for multiplication and accumulation;
[0011] S104: Repeat the S103 (D - 1) times;
[0012] S105: Output the convolution result of S102 - S104;
[0013] Among them: in the above S102 - S104, the coefficients on each of the coefficient filling positions are selected in a rotating cycle manner for D times.
[0014] Further, after the above S105, the following steps are performed on the second type of filter:
[0015] S201: Fill the M coefficients corresponding to the second type of filter with the second bandwidth in the filling positions of each of the coefficient groups;
[0016] S202: When the first data of the second type of filter with the second bandwidth arrives, select one coefficient from each of the coefficient groups for multiplication and accumulation;
[0017] S203: When the next data of the second type of filter with the second bandwidth arrives, select the next coefficient from each of the coefficient groups for multiplication and accumulation;
[0018] S204: Repeat the above S203 for D - 1 times;
[0019] S205: Output the convolution result of the above S202 - S204;
[0020] Among them: in the above S202 - S204, the coefficients on each of the coefficient filling positions are selected in a rotating cycle manner for D times.
[0021] Further, after the above S205, the following steps are performed on the third type of filter:
[0022] S301: Fill the M coefficients corresponding to the third type of filter with the third bandwidth in the filling positions of each of the coefficient groups;
[0023] After the above S305, the following steps are performed on the Nth type of filter:
[0024] SN05: Output the convolution result of the above SN02 - SN04.
[0025] Further, a synchronous clock is provided on the FIR polyphase filter; the output end of the synchronous clock is connected to each of the coefficient selection switches, and the rotating cycle selection action of the coefficient selection switches is triggered based on the synchronous clock.
[0026] Further, the output end of the synchronous clock is connected to each of the multipliers; each of the multipliers performs multiplication actions simultaneously based on the synchronous clock.
[0027] Further, a bandwidth switching module is provided on the FIR polyphase filter; the output end of the bandwidth switching module is connected to each of the coefficient groups and is used to replace the coefficients in each of the coefficient groups when dealing with filters of different bandwidth types.
[0028] Further, a delay unit is provided on the FIR polyphase filter, and the number of delay units is the same as the number of coefficient groups;
[0029] Each of the delay units is arranged in series, and the output end of each group of delay units is connected to one of the multipliers;
[0030] Each of the delay units is used to ensure that each input signal of the FIR polyphase filter is a real-time unique input.
[0031] Further, a group of adders is provided on the FIR polyphase filter; the adders are connected to the output ends of the multipliers and are used to implement the addition process in the convolution operation.
[0032] The beneficial effects of the present invention are as follows:
[0033] The present invention optimizes and reduces the use of FPGA computing resources and certain power consumption, increases the flexibility of FPGA selection, and can streamline the code to reduce the airworthiness review cost of complex electronic hardware. Description of the Drawings
[0034] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.
[0035] Figure 1 It is the schematic diagram of the FIR polyphase filter in the specific embodiment of the present invention;
[0036] Figure 2 It is the schematic diagram of the FIR polyphase filter when M = 24, D = 6, and N = 4 in the specific embodiment of the present invention. Specific Embodiments
[0037] The embodiments of the present disclosure will be described in detail below with reference to the drawings.
[0038] The following describes the embodiments of the present disclosure through specific examples, and those skilled in the art can easily understand the other advantages and effects of the present disclosure from the content disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all the embodiments. The present disclosure can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present disclosure. It should be noted that, without conflict, the following embodiments and the features in the embodiments can be combined with each other. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present disclosure without creative efforts belong to the scope of protection of the present disclosure.
[0039] It should be noted that the following describes various aspects of the embodiments within the scope of the appended claims. It should be obvious that the aspects described herein can be embodied in a wide variety of forms, and any specific structure and / or function described herein is merely illustrative. Based on the present disclosure, those skilled in the art should understand that one aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number of aspects described herein can be used to implement the device and / or practice the method. Additionally, this device and / or method can be implemented using other structures and / or functions in addition to one or more of the aspects described herein.
[0040] It should also be noted that the drawings provided in the following embodiments only illustrate the basic concept of the present disclosure schematically, and only show the components related to the present disclosure rather than being drawn according to the number, shape, and size of the components in actual implementation. The type, quantity, and ratio of each component in its actual implementation can be arbitrarily changed, and the component layout type may also be more complex.
[0041] In addition, in the following description, specific details are provided to facilitate a thorough understanding of the examples. However, those skilled in the art will understand that the described aspects can be practiced without these specific details.
[0042] In an embodiment of the present invention, a method for implementing an FIR polyphase filter based on FPGA is proposed. Refer to Figure 1 , which is used to perform filtering operations on filters of N bandwidths; the implementation method includes:
[0043] When the number of filter coefficients of each filter in the FIR polyphase filter is M, and the decimation factor of each filter is D, then a plurality of coefficient groups are set, D coefficient filling bits are set in each coefficient group, and a coefficient selection switch and a multiplier are configured for each coefficient group;
[0044] The FIR polyphase filter performs the following steps on the filter of the first bandwidth:
[0045] S101: Fill the M coefficients corresponding to the filter of the first bandwidth in the padding bits of each coefficient group;
[0046] S102: When the first data of the filter of the first bandwidth arrives, select one coefficient in each coefficient group for multiplication and accumulation;
[0047] S103: When the next signal of the filter of the first bandwidth arrives, select the next coefficient in each coefficient group for multiplication and accumulation;
[0048] S104: Repeat the S103 D - 1 times;
[0049] S105: Output the convolution result of S102 - S104;
[0050] Wherein: in S102 - S104, D coefficients on each coefficient padding bit are selected in a rotating cycle manner.
[0051] In this embodiment, after S105, the following steps are performed on the second filter:
[0052] S201: Fill the M coefficients corresponding to the filter of the second bandwidth in the padding bits of each coefficient group;
[0053] S202: When the first data of the filter of the second bandwidth arrives, select one coefficient in each coefficient group for multiplication and accumulation;
[0054] S203: When the next data of the filter of the second bandwidth arrives, select the next coefficient in each coefficient group for multiplication and accumulation;
[0055] S204: Repeat the S203 D - 1 times;
[0056] S205: Output the convolution result of S202 - S204;
[0057] Wherein: in S202 - S204, D coefficients on each coefficient padding bit are selected in a rotating cycle manner.
[0058] Furthermore, after S205, the following steps are performed on the third filter:
[0059] S301: Fill the M coefficients corresponding to the filter of the third bandwidth in the padding bits of each coefficient group;
[0060] After the step S305, the following steps are performed on the Nth filter:
[0061] SN05: Output the convolution result of SN02 - SN04.
[0062] In this embodiment, a synchronous clock is provided on the FIR polyphase filter; the output end of the synchronous clock is connected to each coefficient selection switch, and the rotation cycle selection action of the coefficient selection switch is triggered based on the synchronous clock.
[0063] In this embodiment, the output end of the synchronous clock is connected to each multiplier; each multiplier performs a multiplication operation simultaneously based on the synchronous clock.
[0064] In this embodiment, a bandwidth switching module is provided on the FIR polyphase filter; the output end of the bandwidth switching module is connected to each coefficient group, and is used to replace each coefficient in each coefficient group for filters of different bandwidth types.
[0065] In this embodiment, a delay unit is provided on the FIR polyphase filter, and the number of delay units is the same as the number of coefficient groups;
[0066] Each delay unit is serially arranged, and the output end of each group of delay units is connected to a multiplier;
[0067] Each delay unit is used to ensure that each input signal of the FIR polyphase filter is a real - time and unique input.
[0068] A group of adders is provided on the FIR polyphase filter of this embodiment; the adder is connected to the output ends of each multiplier and is used to implement the addition process in the convolution operation.
[0069] The bandwidth switching trigger signal of this embodiment is generated according to the actual application situation. The coefficients of different bandwidth filters can be stored in ROM / RAM or directly placed in a register.
[0070] In this embodiment, for the application scenario of the same sampling rate and multiple bandwidth filtering requirements, a FIR polyphase filter structure based on FPGA is realized. Its advantages are saving the use of computing resources. For example, for D - fold decimation and N filtering bandwidth requirements, the FPGA computing resources used by the existing FIR polyphase filtering technology are 1 / D of the resources used by the conventional FIR filter, while the FPGA computing resources used by the FIR polyphase filtering technology of the present invention are 1 / (D*N) of the resources used by the conventional FIR filter. It provides more computing resources for other signal processing modules, reduces a certain amount of power consumption, and expands the FPGA selection range.
[0071] The following is based on asFigure 2 Taking the FPGA of Xilnix shown below, with D = 6-fold decimation and N = 4 low-pass digital filters with different bandwidths as an example, this embodiment will be further described:
[0072] 1) Using the filter tool in Matlab software, generate filter coefficients with 4 different bandwidths. Here, it is described with the number of each filter coefficient being M = 24, and store the 4 filter coefficients in a file in.coe data format in sequence, or store them in a reg variable.
[0073] 2) According to the polyphase filtering principle, as Figure 2 shown, the M = 24 filter coefficients of each bandwidth are divided into M / D = 4 groups, with each group having D = 6 filter coefficients. Each group of coefficients shares one multiplier. Under the control of the input signal synchronous clock, the multiplier cyclically multiplies with the input digital signal, and the results of each group of multiplications are added, that is, convolution operation is performed to complete the decimation and filtering of the input data signal. Compared with the conventional FIR polyphase filter, the use of FPGA computing resources is reduced by D - 1 = 5 times.
[0074] 3) The switching of the 4 filter coefficients is triggered by the bandwidth switching trigger signal, and the filter coefficients in ROM / RAM or reg are read into the reg participating in the multiplication operation. Since the same filter is used for the 4 different filter coefficients, compared with the conventional FIR polyphase filter, the use of FPGA computing resources is reduced by D * N - 1 = 23 times.
[0075] As described above, it is only the specific implementation manner of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present disclosure should be covered by the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.
Claims
1. A method for implementing a FIR polyphase filter based on FPGA, characterized in that: Used to perform filtering operations on filters of N bandwidths; the implementation method includes: When the number of filter coefficients of each filter in the FIR polyphase filter is M, and the filter decimation multiple of each filter is D, a plurality of coefficient groups are set, D coefficient padding bits are set in each coefficient group, and a coefficient selection switch and a multiplier are configured for each coefficient group; The FIR polyphase filter performs the following steps on the filter of the first bandwidth: S101: Filling the filling bits of each coefficient group with M coefficients corresponding to the filter of the first bandwidth; S102: When the first data of the filter of the first bandwidth arrives, select one coefficient in each coefficient group to multiply and accumulate; S103: when the next data of the filter of the first bandwidth arrives, the next coefficient is selected in each coefficient group for multiplication and accumulation; S104: repeat S103D-1 times; S105: output the convolution result of S102-S104; Wherein: in the S102-S104, the coefficients on the coefficient filling positions are selected for D numbers by a rotation cycle.
2. The FPGA-based FIR polyphase filter implementation method according to claim 1, characterized in that: After S105, the following steps are performed on the second filter: S201: Filling the filling bits of each coefficient group with M coefficients corresponding to the filter of the second bandwidth; S202: When the first data of the filter of the second bandwidth arrives, select one coefficient in each coefficient group to multiply and accumulate; S203: when the next data of the filter of the second bandwidth arrives, the next coefficient is selected in each coefficient group for multiplication and accumulation; S204: repeat S203D-1 times; S205: output the convolution result of S202-S204; Wherein: in S202-S204, the coefficients on the coefficient filling positions are selected for D numbers by a rotation cycle.
3. The FPGA-based FIR polyphase filter implementation method according to claim 2, characterized in that: After S205, the following steps are performed on the third filter: S301: Filling the filling bits of each coefficient group with M coefficients corresponding to the filter of the third bandwidth; After S305, the following steps are performed on the Nth filter: SN05: Output the convolution result of SN02-SN04.
4. The FPGA-based FIR polyphase filter implementation method according to claim 3, characterized in that: The FIR polyphase filter is provided with a synchronous clock; the output end of the synchronous clock is connected to each of the coefficient selection switches, and the rotation cycle selection action of the coefficient selection switch is triggered based on the synchronous clock.
5. The method for realizing a FIR polyphase filter based on FPGA according to claim 4, characterized in that: The output end of the synchronous clock is connected to each of the multipliers; each of the multipliers simultaneously performs a multiplication action based on the synchronous clock.
6. The method for realizing a FIR polyphase filter based on FPGA according to claim 5, characterized in that: The FIR polyphase filter is provided with a bandwidth switching module; the output end of the bandwidth switching module is connected to each of the coefficient groups, and is used to replace each of the coefficients in each of the coefficient groups when targeting filters of different bandwidth types.
7. The method for realizing a FIR polyphase filter based on FPGA according to claim 6, characterized in that: The FIR polyphase filter is provided with delay units, and the number of the delay units is the same as the number of coefficient groups; The delay units are arranged in series, and the output end of each group of delay units is connected to one of the multipliers; Each of the delay units is used to ensure that each input signal of the FIR polyphase filter is a real-time unique input.