Anti-aliasing down-sampling circuit, circuit module, chip and signal processing device

Abstract

The invention provides an anti-aliasing down-sampling circuit, a circuit module, a chip and a signal processing device. The anti-aliasing down-sampling circuit comprises a register, a mode I counter, a multiplier, an adder tree, a multiplexer, an adder, an accumulation register and a latch register. The register stores different data in different clock periods; the numerical value of a counting variable of the modulus I counter increases progressively along with the change of a clock period, and a filter coefficient selected according to the numerical value of the counting variable and data stored in a preset register are input into a corresponding multiplier; the adder tree carries out additive operation on the output result of the multiplier; under the numerical control of the counting variable, the multiplexer selectively outputs 0 or an output result of the accumulation register, and the adder performs additive operation on an output result of the adder tree and a result selectively output by the multiplexer; and the accumulation register stores an output result of the adder, and takes the stored result as an I-time down-sampling result or inputs the stored result into the adder through the multiplexer.

Description

Technical Field

[0001] This application relates to the field of digital signal processing, and particularly to an anti-aliasing decimation circuit, a circuit module, a chip, and a signal processing device. Background Art

[0002] In the field of digital signal processing, decimation, as a common technique for reducing the signal sampling rate, has important application value. However, direct decimation easily causes high-frequency components in the signal spectrum to fold into the low-frequency part, resulting in an aliasing phenomenon, which seriously affects the signal quality. To effectively solve this problem, an anti-aliasing filter is usually used before decimation to remove high-frequency components above the Nyquist frequency. Currently, the anti-aliasing filter usually adopts an FIR filter, which, as a non-recursive filter, has the advantages of linear phase and stability, and its output only depends on the input.

[0003] However, the existing decimation techniques have certain defects. In the decimation circuit, if the anti-aliasing filter and the decimation extraction circuit are implemented separately, a large amount of redundant operations will be generated. These redundant operations not only increase the processing complexity but also cause a significant increase in the power consumption of the decimation circuit, which is not conducive to the energy conservation and efficient operation of digital signal processing devices and limits their application in scenarios with strict power consumption requirements. Therefore, there is an urgent need for a new anti-aliasing decimation circuit to reduce redundant operations. Summary of the Invention

[0004] Based on the above situation, the main purpose of this application is to provide an anti-aliasing decimation circuit, a circuit module, a chip, and a signal processing device to reduce redundant operations.

[0005] To achieve the above purpose, the technical solution adopted in this application is as follows: An embodiment of this application provides an anti-aliasing decimation circuit, including: a register, a modulo I counter, a multiplier, an adder tree, a multiplexer, an adder, and an accumulator register; The register stores different data in different clock cycles; The modulo I The value of the counting variable of the counter increases with the change of the clock cycle, and the filter coefficient is selected according to the value of the counting variable. The filter coefficient and the data stored in the preset register are input into the corresponding multiplier for multiplication operation; The adder tree performs an addition operation on the output results of all the multipliers; The multiplexer, under the control of the value of the counting variable of the modulo I counter, selects to output 0 or the output result of the accumulator register, and the adder performs an addition operation on the output result of the adder tree and the result selected and output by the multiplexer; The accumulative register stores the output result of the adder and uses the stored result as I the output result of the decimation output, or inputs the stored result into the adder through the multiplexer.

[0006] Optionally, the register is a shift register, and the shift register is set to M pieces according to the order of the filter.

[0007] Optionally, M pieces of the shift registers are divided into register groups, and each register group includes I shift registers, I among the shift registers, the data stored in 1 register participates in the multiplication operation, I the data stored in - 1 registers is shifted to the adjacent next register according to the change of the clock cycle; among them, the register participating in the multiplication operation is the last register in the register group where it is located.

[0008] Optionally, according to the number of the shift registers M and the modulus I of the modulus counter I , M +1 filter coefficients are written into coefficient tables, and each coefficient table has I filter coefficients.

[0009] Optionally, is provided with pieces. In one clock cycle, the adder tree performs an addition operation on the output results of pieces of the multipliers.

[0010] Optionally, the value range of the count variable is 0 to I - 1.

[0011] Optionally, when the value of the count variable is 0, the multiplexer selects to output 0, the adder performs an addition operation on 0 and the output result of the 0th group of the adder tree, and the output result of the adder is stored in the accumulative register.

[0012] Optionally, the output result of the 0th group of the adder tree is: , wherein, , , ……, respectively represent the filter coefficients corresponding to when the value of the count variable is 0, respectively represent the input data of the anti-aliasing downsampling circuit and the input data stored in the last register of the 1st, 2nd, ……, ( M +1) / I -1 register groups, r represents the index of the downsampled data.

[0013] Optionally, when M +1 is not I an integer multiple of part of the filter coefficients in the

[0014] Optionally, when the value of the counting variable is greater than 0 and less than or equal to I -1, the multiplexer selects and outputs the data stored in the accumulation register, and the adder performs iterative addition operations on the data stored in the accumulation register and the output results of the 1st to the I -1 groups of the adder tree, and the output result of the adder is stored in the accumulation register.

[0015] Optionally, when the value of the counting variable is I -1, the result stored in the accumulation register is used as the I -fold downsampling result, and the I -fold downsampling result is input to the latch register for temporary storage.

[0016] The embodiment of the present application also provides a circuit module, including the anti-aliasing downsampling circuit described in any one of the above.

[0017] The embodiment of the present application also provides a chip, including the anti-aliasing downsampling circuit described in any one of the above.

[0018] The embodiment of the present application also provides a signal processing device, including the above circuit module or chip.

[0019] The anti-aliasing downsampling circuit provided by the embodiment of the present application distributes multiplication operations and addition operations evenly within I clock cycles by setting registers, modulo I counters, multipliers, adder trees, multiplexers, adders, and accumulation registers, and IThe secondary multiplexing can remove redundant operations, save a large amount of computing time, enable the calculations that originally required multiple clock cycles to be completed in a shorter time, thereby improving the operation speed of the entire circuit system. Redundant operations usually occupy logical resources such as multipliers and adders in the circuit. By removing redundant operations, these logical resources can be released, thus improving resource utilization. The intermediate results generated by redundant operations usually need to be stored in registers. By removing redundant operations, storage resources can be saved.

[0020] The circuit module provided by the embodiment of the present application has excellent anti-aliasing performance and flexible downsampling ability. At the same time, it integrates other practical functions, which can meet the diverse requirements of different applications for signal processing.

[0021] The chip provided by the embodiment of the present application integrates the above anti-aliasing downsampling circuit, which can prevent spectral aliasing, ensure the integrity of the sampled signal spectrum; improve the signal quality and filter out high-frequency noise interference; reduce the sampling rate requirement, and reduce the hardware cost and power consumption.

[0022] Other beneficial effects of the present application will be described in the specific implementation manner through the introduction of specific technical features and technical solutions. Those skilled in the art should be able to understand the beneficial technical effects brought by the technical features and technical solutions through these introductions. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The preferred embodiments of the present application will be described below with reference to the accompanying drawings.

[0024] Figure 1 is the structural block diagram of the anti-aliasing downsampling module in the prior art; Figure 2 is Figure 1 the specific implementation structural block diagram of the anti-aliasing downsampling module in Figure 3 is the structural block diagram of the anti-aliasing downsampling circuit of a preferred embodiment of the present application.

[0025] In the figure: 1. Register; 2. Mod I Counter; 3. Multiplier; 4. Adder tree; 5. Multiplexer; 6. Accumulation register; 7. Adder; 8. Latch register. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0026] The following describes the present application based on embodiments, but the present application is not limited to these embodiments. In the following detailed description of the present application, some specific details are described in detail. In order to avoid obscuring the essence of the present application, well-known methods, processes, procedures, and components are not described in detail.

[0027] In addition, those of ordinary skill in the art should understand that the attached drawings provided herein are for illustrative purposes only, and the drawings are not necessarily drawn to scale.

[0028] Unless the context clearly requires otherwise, the words such as "including", "comprising" and the like in the whole specification and claims should be interpreted in an inclusive sense rather than an exclusive or exhaustive sense; that is, it is the meaning of "including but not limited to".

[0029] In the description of this application, it should be understood that the terms "first", "second", etc. are only used for descriptive purposes and cannot be construed as indicating or implying relative importance. In addition, in the description of this application, unless otherwise specified, the meaning of "a plurality" is two or more.

[0030] In a digital signal processing system, sometimes it is necessary to reduce the sampling rate of a signal, that is, to perform a downsampling operation. Before downsampling, it is necessary to filter the digital signal using an anti-aliasing filter. This is because downsampling will change the spectrum of the signal. If the components with frequencies higher than half of the new sampling rate (i.e., the Nyquist frequency) are not filtered out in advance, aliasing will occur. For example, in video processing, when it is necessary to downsample a high-frame-rate video to a low-frame-rate video, the video signal is first processed by a digital anti-aliasing filter to remove high-frequency components, and then the downsampling operation is performed to avoid aliasing distortion in the picture.

[0031] Since the FIR (Finite Impulse Response) filter can precisely control the frequency response and good low-pass characteristics can be achieved by designing appropriate filter coefficients, the FIR filter is often used as an anti-aliasing filter.

[0032] As Figure 1 shown, the anti-aliasing downsampling module in the prior art mainly includes an anti-aliasing filter and I a downsampling decimator. The output end of the anti-aliasing filter is connected to the I input end of the downsampling decimator, and the I downsampling decimator is used to output the downsampled result. Assume that the anti-aliasing filter adopts the Figure 2 order FIR filter as M shown. The unit impulse response of this FIR filter is represented by , the input of the FIR filter is , and the output is .

[0033] Among them, M the unit impulse response of the order FIR filter is expressed as: (1) With the condition of having a generalized linear phase characteristic, that is: or .

[0034] The output of the FIR filter is: (2) In Equation (2), h ( k ) represents the k th coefficient of the FIR filter, x ( n − k ) represents the input signal x ( n ) after being delayed by k clock cycles.

[0035] I The I -times decimation extractor outputs 1 valid result every clock cycles: (3) In Equation (3), x ( rI − k ) represents the value of the input signal x ( n ) at the discrete time rI − k , rI represents the current discrete time, r represents the index of the decimated data.

[0036] From the expressions of Figure 2 and the output of the FIR filter , it can be seen that in the anti-aliasing decimation module of the prior art, when using an FIR filter to remove high-frequency components, for each sample of the input signal, multiplication and addition operations are required, and M +1 multipliers and an adder tree for implementing M +1 numerical additions are needed. When the order of the filter M is relatively high, or the reduction multiple of the sampling rate IIn the case of a relatively large [quantity], a large number of operations will be generated. In these operations, there is actually a certain degree of redundancy. For example, for some adjacent samples, the multiplication operations in the filtering process may have some identical coefficients. However, due to the traditional implementation method failing to effectively optimize these redundant operations, each sample needs to perform a complete multiplication operation during the calculation, which undoubtedly increases the number of multipliers used. Correspondingly, it also increases the number of additions to be processed in a single calculation of the adder tree.

[0037] The anti-aliasing decimation circuit provided in this application is implemented based on the circuit structure of a direct-form FIR filter. The anti-aliasing decimation circuit obtained through theoretical analysis and circuit structure design can effectively remove redundant operations. By evenly distributing the multiplication operations and addition operations and sharing the multipliers, it can effectively avoid the problem of excessive local computational load. At the same time, this application reduces the number of multipliers by a multiple and reduces the number of additions to be processed in a single calculation of the adder tree. This application can effectively solve the problem of redundant operations existing in the prior art, significantly reduce power consumption while reducing the circuit scale, and achieve an effective improvement in circuit performance.

[0038] Decompose and transform Equation (3). According to I the requirements for the [X]-fold decimation output, divide the calculation of into I groups, and calculate the sum result of multiplication operation results in each group.

[0039] Specifically, Equation (3) can be decomposed and transformed into: Based on the above decomposition and transformation process, the number of multiplication operation results can be reduced from M +1 to ; simplify the adder tree that needs to implement the addition of M +1 multiplication operation results to an adder tree that implements the addition of multiplication operation results. Through I times of multiplexing the multiplier and the adder tree, the addition operation of M +1 multiplication operation results can be achieved.

[0041] Based on the above theoretical analysis, the multiplication operations and addition operations can be evenly distributed within I clock cycles. By performing I times of multiplexing on the multiplier and the adder tree, only multipliers and an adder tree capable of adding numerical values are required to achieve the addition operation of M +1 multiplication operation results.

[0042] According to the above theoretical analysis results, the anti-aliasing downsampling circuit provided by the embodiments of the present application can be designed. The following will combine the accompanying drawings to give a detailed description of the anti-aliasing downsampling circuit provided by the embodiments of the present application.

[0043] Figure 3 is a schematic structural diagram of the anti-aliasing downsampling circuit provided by the embodiments of the present application, as Figure 3 shown, the anti-aliasing downsampling circuit includes: register 1, modulo I counter 2, multiplier 3, adder tree 4, multiplexer 5, accumulator register 6, adder 7 and latch register 8.

[0044] Among them, register 1 stores different data in different clock cycles. The value of the counting variable of modulo I counter 2 increases with the change of the clock cycle. According to the value of the counting variable, filter coefficients are selected. The filter coefficients and the data stored in the preset register 1 are input into the corresponding multiplier 3 for multiplication operation. The adder tree 4 performs an addition operation on the output results of all multipliers 3. The multiplexer 5, under the control of the value of the counting variable of modulo I counter 2, selects to output 0 or the output result of the accumulator register 6. The adder 7 performs an addition operation on the output result of the adder tree 4 and the result selected by the multiplexer 5. The accumulator register 6 stores the output result of the adder 7 and takes the stored result as I the downsampling result by a factor of, or inputs the stored result into the adder 7 through the multiplexer 5. Among them, the latch register 8 temporarily stores the I downsampling result by a factor of output by the accumulator register 6. Under the control of the value of the counting variable of modulo I counter 2, the latch register 8 outputs the I downsampling result by a factor of in the corresponding clock cycle.

[0045] It should be noted that more than one register 1 can be set. With the rhythm of the clock signal, the data stored in register 1 will be continuously updated. For example, during the operation of a processor, in the first clock cycle, register 1 stores the first operand obtained from one data source; while in the second clock cycle, register 1 stores the second operand obtained from another data source. This dynamic storage feature enables register 1 to flexibly participate in various complex operations.

[0046] According to modulo IThe value of the counting variable of counter 2 is used to select the filter coefficients in the coefficient table corresponding to the preset register 1, and the data stored in the preset register 1 is multiplied by the filter coefficients in its corresponding coefficient table. Here, the coefficient table can be a set of pre-set values, and these values are determined according to specific operation requirements. The multiplication operation is to multiply the data stored in register 1 by the corresponding coefficients in the coefficient table. For example, in digital signal processing, in order to filter or transform a signal, it is necessary to multiply the input signal (stored in register 1) by the filter coefficients (stored in the coefficient table) to achieve specific signal processing functions.

[0047] The result obtained from the multiplication operation is sent to adder tree 4 for addition operation. Adder tree 4 can be a circuit module formed by connecting multiple adders in a certain structure, and its function is to accumulate the results of multiple multiplication operations. The output result of adder tree 4 and the result selected and output by multiplexer 5 are sent to adder 7 for addition operation, and the addition operation result is stored in accumulator register 6. In the modulo I Under the control of the value of the counting variable of counter 2, multiplexer 5 selects and outputs 0 or the output result of accumulator register 6. In the modulo I Under the control of the value of the counting variable of counter 2, accumulator register 6 takes the stored result as I the decimation result, and this I decimation result is input into latch register 8 for temporary storage, or the stored result is selected and output through multiplexer 5 to adder 7 for iterative addition calculation. In a specific embodiment, register 1 can adopt a shift register, and the shift register can be set to M pieces according to the order of the filter. M These shift registers are connected in series in sequence. Each shift register can store different data in different clock cycles.

[0048] For example, assume that the number of shift registers is more than 3. In the initial state, the first shift register stores the first data. When the first clock cycle arrives, the second data is input to the first shift register, and the first data is shifted to the second shift register for storage. When the second clock cycle arrives, the third data is input to the first shift register, the second data is shifted to the second shift register for storage, and the first data is shifted to the third shift register for storage. And so on. As the clock cycles keep arriving, the data input into each shift register continues to shift to the adjacent next shift register.

[0049] In the above embodiment, according to the number of shift registers M and the modulo I value of counter 2 I , it is possible toM A shift register is divided into register groups, and each register group includes I shift registers. I Among the I shift registers, the data stored in one register participates in the multiplication operation, and the data stored in

[0050] -1 registers is shifted to the adjacent next register according to the change of the clock cycle. Among them, the register where the data participating in the multiplication operation is located is the last register in the register group where it is located. I Based on the above theoretical analysis, since the register where the data participating in the multiplication operation is located is the last register in the register group where it is located, finally M - I +1 shift registers are actually not needed during actual use. Therefore, actually

[0051] +1 shift registers can be set, which can further save circuit overhead. I For example, when the filter order is 14 (i.e., 14 shift registers are set) and the modulus value of the modulo counter 2 I is 3 (i.e., the anti-aliasing decimation circuit can achieve 3-fold decimation output), the 14 shift registers can be divided into 4 register groups, with 3 shift registers in each register group, and 2 shift registers are also connected in series after the fourth register group. During actual use, since only the input data of the anti-aliasing decimation circuit and the data stored in the 3rd, 6th, 9th, and 12th shift registers participate in the multiplication operation, the last 2 shift registers are not needed. Therefore, actually 12 shift registers can be set.

[0052] For each register group, assume that the 3 sequentially connected shift registers are the first shift register, the second shift register, and the third shift register respectively. In the initial state, the first shift register in the current register group stores the first data. When the first clock cycle arrives, the second data is input to the first shift register, and the first data is shifted to the second shift register for storage. When the second clock cycle arrives, the third data is input to the first shift register, the second data is shifted to the second shift register for storage, and the first data is shifted to the third shift register for storage. When the third clock cycle arrives, the fourth data is input to the first shift register, the third data is shifted to the second shift register for storage, the second data is shifted to the third shift register for storage, and the first data is shifted to the first shift register in the adjacent next register group for storage, and so on.

[0053] For the current register bank, according to the change of the clock cycle, the data stored in the first shift register and the second shift register is shifted to the adjacent next shift register, and the data stored in the third shift register participates in the multiplication operation. In the above embodiment, according to the number of shift registers M and the modulo I value of the modulo counter 2 I , M +1 filter coefficients can be written into coefficient tables, and each coefficient table has I filter coefficients. It should be noted that when M +1 is not an integer multiple of I , some filter coefficients in the th coefficient table are padded with 0.

[0054] For example, when M is 14 and I is 3, there are 15 filter coefficients, and these 15 filter coefficients can be written into 5 coefficient tables, and each coefficient table has 3 filter coefficients. When M is 13 and I is 3, there are 14 filter coefficients, and these 14 filter coefficients can be written into 5 coefficient tables. The first to the fourth coefficient tables each have 3 filter coefficients, the fifth coefficient table has 2 filter coefficients, and the other filter coefficient in the fifth coefficient table can be padded with 0.

[0055] In the above embodiment, according to the number of shift registers M and the modulo I value of the modulo counter 2 I , the multiplier 3 can be set to pieces. In one clock cycle, the adder tree 4 performs an addition operation on the output results of multipliers 3. Specifically, 1 multiplier can be used to perform a multiplication operation on the input data of the anti-aliasing downsampling circuit and the filter coefficients in the first coefficient table, and multipliers are respectively used to perform a multiplication operation on the data stored in the last register of register banks and the filter coefficients in the corresponding coefficient tables.

[0056] For example, when I is 3 and M is 12, 13 or 14, 5 multipliers can be set. In one clock cycle, the adder tree 4 needs to perform an addition operation on the output results of 5 multipliers 3.

[0057] The multiplier 3 is used to perform a multiplication operation on the filter coefficients and the data stored in the preset register 1, where the filter coefficients can be determined according to the moduloI selected according to the value of the counting variable of counter 2. The value range of the counting variable is 0 to I -1, that is, the value of the counting variable can be 0, 1, 2, 3, ……, I -1. When I is 3, the value of the counting variable can be 0, 1, 2. Each value of the counting variable corresponds to corresponding filter coefficients.

[0058] In the above embodiment, under the control of the value of the counting variable, the multiplexer 5 can select to output 0 or the data stored in the accumulator register 6.

[0059] Specifically, when the value of the counting variable is 0, the multiplexer 5 selects to output 0, and the adder 7 performs an addition operation on 0 and the output result of the 0th group of the adder tree 4. The output result of the adder 7 is stored in the accumulator register 6.

[0060] Among them, the output result of the 0th group of the adder tree 4 is: (4) In formula (4), , , ……, respectively represent the filter coefficients corresponding to when the value of the counting variable is 0, respectively represent the input data of the anti-aliasing downsampling circuit and the input data stored in the last register of the 1st, 2nd, ……, ( M +1) / I -1 register groups, r represents the index of the downsampled data.

[0061] When the value of the counting variable is greater than 0 and less than or equal to I -1, the multiplexer 5 selects to output the data stored in the accumulator register 6, and the adder 7 performs an iterative addition operation on the data stored in the accumulator register 6 and the output results of the 1st group to the I -1 group of the adder tree 4. The output result of the adder 7 is stored in the accumulator register 6.

[0062] When the value of the counting variable is I -1, the result stored in the accumulator register 6 is used as the I -fold downsampling result. This I -fold downsampling result is input to the latch register 8 for temporary storage. Under the control of the value of the counting variable of the modulo I counter 2, the latch register 8 outputs the I -fold downsampling result in the corresponding clock cycle.

[0063] It can be understood that in the actual circuit, the I- The calculation result of 1 clock cycle is latched and output by the latch register 8 at the rising edge of the clock when the value of the counting variable is 0. I The decimated result is latched and output by the latch register 8.

[0064] When the next clock cycle arrives, the value of the counting variable changes from I -1 to 0 again.

[0065] Assume that the anti-aliasing decimation circuit provided in the embodiment of the present application outputs n at the th clock cycle. The output results of the anti-aliasing decimation circuit at each clock cycle are described below.

[0066] At the th clock cycle, calculate and write the result into the accumulation register : , .

[0067] At the th clock cycle, calculate and accumulate the result into the accumulation register : ,

[0068] ... At the th clock cycle, calculate and accumulate the result into the accumulation register : , .

[0069] At the n th clock cycle, calculate and accumulate the result into the accumulation register , obtaining and outputting: , .

[0070] For each I input, the above operations are repeated, and 1 decimation result is output. The first calculation in each loop is , which is not an accumulation operation; the last calculation obtains the final result and outputs it.

[0071] Below, taking the filter order of 14 and the need to implement 3-fold decimation output as an example (i.e.,M is 14, I as 3), the structure and working principle of the anti-aliasing downsampling circuit provided by the embodiments of the present application will be described.

[0072] Set 14 shift registers, and the shift registers are connected in series in sequence. Divide the 14 shift registers into 4 register groups, with 3 shift registers in each register group. The last 2 shift registers do not need to be used during actual operation.

[0073] Write 15 filter coefficients into 5 coefficient tables, with 3 filter coefficients in each coefficient table.

[0074] Set 5 multipliers 3. In one clock cycle, the adder tree 4 can perform an addition operation on the output results of the 5 multipliers 3.

[0075] Modulo I The counter 2 uses a modulo-3 counter, and the value of its counting variable is 0, 1, and 2. When the value of the counting variable is 0, the filter coefficients in the corresponding coefficient tables are respectively h (2), h (5), h (8), h (11), and h (14). When the value of the counting variable is 1, the filter coefficients in the corresponding coefficient tables are respectively h (1), h (4), h (7), h (10), and h (13). When the value of the counting variable is 2, the filter coefficients in the corresponding coefficient tables are respectively h (0), h (3), h (6), h (9), and h (12). Different filter coefficients in the corresponding coefficient tables can be selected according to the value of the counting variable.

[0076] Assume that the output is at the 9th clock cycle , then calculate at the 7th clock cycle , and write the result into the accumulator register : , .

[0077] Calculate at the 8th clock cycle , and accumulate the result to the accumulator register : , .

[0078] Calculate in the 9th clock cycle and accumulate the result to the accumulator register to obtain and output: , .

[0079] Assume that 15 filter coefficients are shown in Table 1, then the coefficients in the 5 coefficient tables are shown in Table 2.

[0080] Table 1 Filter Coefficients

[0081] Table 2 Coefficient Table

[0082] When the input is applied, the output of the theoretical anti-aliasing filter and the output of the anti-aliasing decimation circuit are shown in Table 3. Compared with the anti-aliasing decimation module of the prior art, there is an additional latch register 8 at the output end of the anti-aliasing decimation circuit provided in the embodiments of the present application. Therefore the output is one clock cycle later than .

[0083] Table 3 Output Table of Anti-aliasing Decimation Circuit

[0084] The embodiments of the present application also provide a circuit module, including the above anti-aliasing decimation circuit. This circuit module integrates the anti-aliasing decimation circuit provided in the embodiments of the present application. On this basis, function expansion and optimization can be carried out, aiming to provide an efficient and reliable signal preprocessing solution for various digital signal processing scenarios. This circuit module has excellent anti-aliasing performance and flexible decimation ability, and at the same time integrates other practical functions, which can meet the diverse requirements of different applications for signal processing.

[0085] For example, in the field of audio processing, in audio recording, playback and editing devices, the circuit module provided in the embodiments of the present application can be used to decimate high-sampling-rate audio signals, and at the same time effectively suppress environmental noise and noise generated by the device itself, ensuring high-quality output of audio signals. Specifically, in a portable audio player, by using this circuit module to decimate high-sampling-rate audio files to a sampling rate suitable for device processing, while optimizing the quality of audio signals, the user's auditory experience can be improved.

[0086] In wireless and wired communication systems, the circuit module provided by the embodiments of the present application can be used to preprocess received signals. Through functions such as anti-aliasing downsampling and noise suppression, the reliability and transmission efficiency of signals are improved, and the bit error rate is reduced. At the same time, the signal format conversion function can achieve compatibility with different communication protocols and devices, meeting the diverse needs of communication systems.

[0087] In industrial automation and sensor signal processing, the circuit module provided by the embodiments of the present application can perform operations such as anti-aliasing downsampling, gain adjustment, and noise suppression on sensor signals, converting the original signals into a format suitable for industrial control system processing, and providing reliable data support for the monitoring and control of the production process.

[0088] In medical devices such as electrocardiographs and electroencephalographs, the circuit module provided by the embodiments of the present application can effectively remove noise interference in physiological signals, perform downsampling processing on signals to reduce the data volume, and at the same time ensure the integrity and accuracy of the signals, providing a reliable basis for medical diagnosis.

[0089] The embodiments of the present application also provide a chip, including the above anti-aliasing downsampling circuit, which is used to reduce the sampling rate of signals while avoiding aliasing distortion, thereby reducing the data volume. The anti-aliasing downsampling circuit can remove redundant calculations and has characteristics such as a small circuit scale and low power consumption.

[0090] The chip provided by the embodiments of the present application can be used in consumer electronic products such as smartphones, tablets, and smart speakers for audio and video signal processing. For example, during the audio recording and playback of a smartphone, the chip can perform anti-aliasing downsampling processing on the audio signals collected by the microphone, while optimizing the audio quality to provide a clear and realistic sound quality experience. In terms of video shooting and playback, the chip can efficiently process the video signals output by the camera to achieve video downsampling and format conversion to meet different storage and transmission requirements.

[0091] On an industrial automation production line, the chip can be used to process signals collected by various sensors, such as temperature sensors, pressure sensors, and acceleration sensors. By performing anti-aliasing downsampling and optimization processing on the sensor signals, various parameter information in the production process can be accurately obtained, providing reliable data support for the industrial control system. In the field of the Internet of Things, the chip can be applied to various intelligent devices and sensor nodes to achieve efficient processing and transmission of massive data, improving the performance and reliability of the Internet of Things system.

[0092] In medical devices such as electrocardiographs, electroencephalographs, and ultrasonic diagnostic instruments, this chip can effectively remove the noise interference in biomedical signals, perform precise anti-aliasing downsampling processing on the signals, and ensure that doctors can obtain accurate diagnostic information. At the same time, the multi-channel processing ability of this chip can achieve the synchronous processing of multiple biomedical signals, improving the working efficiency of medical devices.

[0093] In a communication system, this chip can be used for the processing of wireless signals and wired signals. For example, in base station equipment, this chip can perform anti-aliasing downsampling processing on the received radio frequency signals, improving the signal quality and transmission efficiency. In network equipment, this chip can process data signals, realizing the downsampling and format conversion of data to adapt to different network transmission protocols and bandwidth requirements.

[0094] The embodiment of this application also provides a signal processing device, including the above circuit module or chip. This signal processing device can be used in smart home systems, intelligent transportation systems, aerospace systems, and financial transaction systems, providing reliable solutions for various complex signal processing tasks.

[0095] Those skilled in the art can understand that, on the premise of no conflict, the above preferred solutions can be freely combined and superimposed. Among them, the flowcharts and block diagrams in the drawings illustrate the possible implementation architectures, functions, and operations of the systems according to various embodiments disclosed in this application. In this regard, each block in the flowchart or block diagram may represent a module, a program segment, or a part of code, and this module, program segment, or part of code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order from that marked in the drawings. For example, two consecutive blocks shown may actually be executed substantially in parallel, and they may sometimes be executed in the reverse order, depending on the functions involved. It should also be noted that each block in the block diagram and / or flowchart, as well as the combination of blocks in the block diagram and / or flowchart, can be implemented by a dedicated hardware-based system for performing the specified functions or operations, or can be implemented by a combination of dedicated hardware and computer instructions. The numbering of each step in this article is only for convenience of description and reference, and does not limit the sequence before and after. The specific execution sequence is determined by the technology itself, and those skilled in the art can determine various permitted and reasonable sequences according to the technology itself.

[0096] Those skilled in the art can understand that, on the premise of no conflict, the above preferred solutions can be freely combined and superimposed.

[0097] It should be understood that the above embodiments are merely exemplary and not restrictive. Without departing from the basic principles of the present application, various obvious or equivalent modifications or substitutions that those skilled in the art can make to the above details will all be included within the scope of the claims of the present application.

Claims

1. An anti-aliasing downsampling circuit, characterized in that: include: Register, module I counters, multipliers, adder trees, multiplexers, adders, accumulator registers, and latch registers; The register stores different data in different clock cycles; The model I The value of the count variable of the counter increases with the change of the clock cycle, and the filter coefficient is selected according to the value of the count variable. The filter coefficient and the data stored in the preset register are input into the corresponding multiplier for multiplication operation; The adder tree performs addition operation on the output results of all the multipliers; The multiplexer is in the mode I Under the numerical control of the counting variable of the counter, the output 0 or the output result of the accumulator register is selected, and the adder performs addition operation on the output result of the adder tree and the output result selected by the multiplexer; The accumulator register stores the output result of the adder and uses the stored result as I downsampling the result by a multiplexer, or inputting the stored result into the adder through the multiplexer; The latch register outputs the accumulator register I The downsampling result is temporarily stored in the model I Under the control of the value of the counter's count variable, the latch register outputs the corresponding clock cycle I Downsampling results.

2. The anti-aliasing downsampling circuit according to claim 1, characterized in that: The register adopts a shift register, and the shift register is set to M indivual.

3. The anti-aliasing downsampling circuit according to claim 2, characterized in that: M The shift register is divided into register groups, each of which includes I A shift register, I The data stored in one of the shift registers participates in the multiplication operation. I -The data stored in one register is shifted to the next adjacent register according to the change of the clock cycle; wherein the register participating in the multiplication operation is the last register in the register group.

4. The anti-aliasing downsampling circuit according to claim 2, characterized in that: According to the number of shift registers M and model I Modulus value of the counter I ,Will M +1 filter coefficient written coefficient tables, each with I filter coefficients.

5. The anti-aliasing downsampling circuit according to claim 2, characterized in that: The multiplier is provided with In one clock cycle, the adder tree The output results of the multipliers are added.

6. The anti-aliasing downsampling circuit according to claim 3, characterized in that: The value of the counting variable ranges from 0 to I -1.

7. The anti-aliasing downsampling circuit according to claim 6, characterized in that: When the value of the counting variable is 0, the multiplexer selects to output 0, the adder performs an addition operation on 0 and the output result of the 0th group of the adder tree, and the output result of the adder is stored in the accumulator register.

8. The anti-aliasing downsampling circuit according to claim 7, characterized in that: The output results of group 0 of the adder tree are: ， In the formula, , ,……, They respectively represent the filter coefficients corresponding to when the value of the count variable is 0, Respectively represent the input data of the anti-aliasing downsampling circuit and the 1st, 2nd, ..., ( M +1) / I -1 The input data stored in the last register of the register group, r Indicates the index of the downsampled data.

9. The anti-aliasing downsampling circuit according to claim 8, characterized in that: when M +1 Not I When the value is an integer multiple of Some filter coefficients in the coefficient table are padded with 0.

10. The anti-aliasing downsampling circuit according to claim 6, characterized in that: The value of the count variable is greater than 0 and less than or equal to I -1, the multiplexer selects to output the data stored in the accumulator register, and the adder performs summation on the data stored in the accumulator register and the data from the first group to the first group of the adder tree. I -1 group of output results are iteratively added, and the output results of the adder are stored in the accumulator register.

11. The anti-aliasing downsampling circuit according to claim 10, characterized in that: The value of the count variable is I -1, the accumulator register stores the result as I The downsampling result is I The down-sampling result is input into the latch register for temporary storage.

12. A circuit module, characterized in that: It comprises the anti-aliasing downsampling circuit as described in any one of claims 1 to 11.

13. A chip, characterized in that: It comprises the anti-aliasing downsampling circuit as described in any one of claims 1 to 11.

14. A signal processing device, characterized in that: Includes the circuit module as claimed in claim 12 or the chip as claimed in claim 13.

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