Clock synchronization method and device, electronic equipment and storage medium

Abstract

The invention provides a clock synchronization method and device, electronic equipment and a storage medium, and relates to the technical field of communication. The method comprises the following steps: determining an adjustment mode of a first clock; determining a frequency deviation and a time offset between the first clock and the second clock based on the acquired clock synchronization data; determining an adjustment strategy of parameters of the first clock and a target adjustment mode corresponding to the first clock according to the adjustment mode of the first clock and the frequency deviation and / or the time offset; wherein the target adjustment mode is any one of a frequency adjustment mode, a time adjustment mode, a fine adjustment mode and a silence mode; and re-determining the adjustment mode of the first clock based on the target adjustment mode. According to the invention, the time of the first clock after multiple times of adjustment is continuous, the stability of the first clock is relatively high, and the frequency deviation between the two clocks is combined during adjustment instead of only adjusting the time offset, so that the time accuracy of the adjusted first clock is relatively high.

Description

Background Art

[0002] In order to promote the application of Ethernet to network scenarios such as industrial and vehicle-mounted networks that require low latency and deterministic latency, the IEEE has developed the TSN (Time-Sensitive Network) protocol family. Among them, the 802.1AS protocol, as the basis of the TSN network, needs to provide accurate time to other TSN protocols to ensure the normal operation of the protocols and devices.

[0003] Since there is a certain difference between the hardware clock frequency of the local device and the clock frequency of the master clock (Grandmaster) in the network, if we want to maintain the time consistency of the TSN network, we need to regularly adjust the time of the hardware clock to keep it consistent with the time of the master clock in the network. In the related art, after obtaining the accurate time of the master clock according to the 802.1AS protocol, the time offset value between the local hardware clock and the master clock is directly adjusted. However, only the time offset between the hardware clock and the master clock is updated, but the frequencies of different clocks will not be exactly the same, and the time offset between the adjusted local clock and the master clock will soon increase continuously, resulting in poor accuracy of the time displayed by the hardware clock. And directly updating the hardware clock according to the time offset value obtained each time will cause clock jitter, or the time displayed by the hardware clock is discontinuous and jumps, resulting in poor stability of the hardware clock, and also having a greater impact on other devices that rely on the hardware clock.

[0004] It should be noted that the information disclosed in the above background art section is only used to strengthen the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to those of ordinary skill in the art. Summary of the Invention

[0005] The present disclosure provides a clock synchronization method, apparatus, electronic device and storage medium, which at least overcome to a certain extent the problems of poor time accuracy of the hardware clock and poor stability of the hardware clock in the related art.

[0006] Other features and advantages of the present disclosure will become apparent through the following detailed description, or be learned in part through the practice of the present disclosure.

[0007] According to a first aspect of the present disclosure, there is provided a clock synchronization method, including:

[0008] Determine the adjustment mode in which the first clock is located;

[0009] Based on the obtained clock synchronization data, determine the frequency deviation and time offset between the first clock and the second clock;

[0010] Determine an adjustment strategy for the parameters of the first clock and a target adjustment mode corresponding to the first clock according to the adjustment mode of the first clock and the frequency deviation and / or time offset between the first clock and the second clock; wherein, the target adjustment mode is any one of a frequency adjustment mode, a time adjustment mode, a fine-tuning mode, and a silent mode;

[0011] Redetermine the adjustment mode of the first clock based on the target adjustment mode.

[0012] In some embodiments of the present disclosure, the parameters of the first clock include at least one or any combination of the following: the frequency of the first clock, the time of the first clock, and the cumulative value of the time offset of the first clock.

[0013] In some embodiments of the present disclosure, when the adjustment mode of the first clock is the frequency adjustment mode, determining an adjustment strategy for the parameters of the first clock and a target adjustment mode corresponding to the first clock according to the adjustment mode of the first clock and the frequency deviation and / or time offset between the first clock and the second clock includes:

[0014] Judge whether the absolute value of the frequency deviation is greater than or equal to a first preset threshold;

[0015] If the absolute value of the frequency deviation is greater than or equal to the first preset threshold, determine that the target adjustment mode is the frequency adjustment mode, and determine the adjustment strategy for the parameters of the first clock as: adjusting the frequency of the first clock according to the frequency deviation.

[0016] In some embodiments of the present disclosure, when the adjustment mode of the first clock is the frequency adjustment mode, determining an adjustment strategy for the parameters of the first clock and a target adjustment mode corresponding to the first clock according to the adjustment mode of the first clock and the frequency deviation and / or time offset between the first clock and the second clock further includes:

[0017] If the absolute value of the frequency deviation is less than the first preset threshold, determine that the target adjustment mode is the time adjustment mode, and determine the adjustment strategy for the parameters of the first clock as: not adjusting the parameters of the first clock.

[0018] In some embodiments of the present disclosure, when the adjustment mode of the first clock is the time adjustment mode, determining an adjustment strategy for the parameters of the first clock and a target adjustment mode corresponding to the first clock according to the adjustment mode of the first clock and the frequency deviation and / or time offset between the first clock and the second clock includes:

[0019] Determine the cumulative value of the time offset of the first clock;

[0020] Determine whether the absolute value of the time offset is greater than a second preset threshold, and determine whether the absolute value of the cumulative time offset is greater than a third preset threshold;

[0021] If the absolute value of the time offset is greater than the second preset threshold or the absolute value of the cumulative time offset is greater than the third preset threshold, determine that the target adjustment mode is the silent mode, and determine the adjustment strategy for the parameters of the first clock as: adjusting the time of the first clock according to the time offset, and clearing the cumulative value of the time offset of the first clock.

[0022] In some embodiments of the present disclosure, the parameters of the first clock further include: a silent round value;

[0023] Determine the adjustment strategy for the parameters of the first clock as: setting the silent round value to a preset value.

[0024] In some embodiments of the present disclosure, when the adjustment mode of the first clock is the silent mode, according to the adjustment mode of the first clock and the frequency deviation and / or time offset between the first clock and the second clock, determine the adjustment strategy for the parameters of the first clock and the target adjustment mode corresponding to the first clock, including:

[0025] Determine the silent round value;

[0026] Determine whether the silent round value is zero;

[0027] If the silent round value is not zero, determine that the target adjustment mode corresponding to the first clock is the silent mode, and determine the adjustment strategy for the parameters of the first clock as: subtracting one from the silent round value;

[0028] If the silent round value is zero, determine that the target adjustment mode corresponding to the first clock is the fine-tuning mode, and determine the adjustment strategy for the parameters of the first clock as: not adjusting the parameters of the first clock.

[0029] In some embodiments of the present disclosure, when the adjustment mode of the first clock is the time adjustment mode, according to the adjustment mode of the first clock and the frequency deviation and / or time offset between the first clock and the second clock, determine the adjustment strategy for the parameters of the first clock and the target adjustment mode corresponding to the first clock, further including:

[0030] If the absolute value of the time offset is less than or equal to the second preset threshold, and the absolute value of the cumulative time offset is less than or equal to the third preset threshold, determine that the target adjustment mode is the fine-tuning mode, and determine the adjustment strategy for the parameters of the first clock as: not adjusting the parameters of the first clock.

[0031] In some embodiments of the present disclosure, when the adjustment mode of the first clock is the fine-tuning mode, according to the adjustment mode of the first clock, the frequency deviation and / or time offset between the first clock and the second clock, determine the adjustment strategy of the parameters of the first clock and the target adjustment mode corresponding to the first clock, including:

[0032] Judge whether the absolute value of the frequency deviation is greater than a fourth preset threshold;

[0033] If the absolute value of the frequency deviation is less than or equal to the fourth preset threshold, determine the cumulative value of the time offset of the first clock;

[0034] Judge whether the absolute value of the time offset is greater than a fifth preset threshold, and judge whether the absolute value of the cumulative value of the time offset is greater than a sixth preset threshold;

[0035] If the absolute value of the time offset is less than or equal to the fifth preset threshold, and the absolute value of the cumulative value of the time offset is less than or equal to the sixth preset threshold, determine that the target adjustment mode is the fine-tuning mode, and determine the adjustment strategy of the parameters of the first clock as: according to the frequency deviation and the time offset, adjust the frequency of the first clock to adjust the time of the first clock; update the cumulative value of the time offset.

[0036] In some embodiments of the present disclosure, according to the frequency deviation and the time offset, adjust the frequency of the first clock to adjust the time of the first clock, including:

[0037] According to the frequency deviation, the time offset, and the cumulative value of the time offset, use the PID algorithm to determine the adjustment value of the frequency of the first clock to adjust the time of the first clock.

[0038] In some embodiments of the present disclosure, when the adjustment mode of the first clock is the fine-tuning mode, according to the adjustment mode of the first clock, the frequency deviation and / or time offset between the first clock and the second clock, determine the adjustment strategy of the parameters of the first clock and the target adjustment mode corresponding to the first clock, further including:

[0039] If the absolute value of the frequency deviation is greater than the fourth preset threshold, determine that the target adjustment mode is the frequency adjustment mode, and determine the adjustment strategy of the parameters of the first clock as: do not adjust the parameters of the first clock.

[0040] In some embodiments of the present disclosure, when the adjustment mode of the first clock is the fine-tuning mode, according to the adjustment mode of the first clock, the frequency deviation and / or time offset between the first clock and the second clock, determining an adjustment strategy for the parameters of the first clock and a target adjustment mode corresponding to the first clock further includes:

[0041] If the absolute value of the time offset is greater than a fifth preset threshold or the absolute value of the cumulative time offset is greater than a sixth preset threshold, determining that the target adjustment mode is the time adjustment mode, and determining the adjustment strategy for the parameters of the first clock as: not adjusting the parameters of the first clock.

[0042] In some embodiments of the present disclosure, re-determining the adjustment mode of the first clock based on the target adjustment mode includes:

[0043] Determining the target adjustment mode as the adjustment mode of the first clock after re-determination.

[0044] According to a second aspect of the present disclosure, there is also provided a clock synchronization device, including:

[0045] A clock mode determination module, configured to determine the adjustment mode of the first clock;

[0046] A clock data determination module, configured to determine the frequency deviation and time offset between the first clock and the second clock based on the acquired clock synchronization data;

[0047] A clock adjustment module, configured to determine an adjustment strategy for the parameters of the first clock and a target adjustment mode corresponding to the first clock according to the adjustment mode of the first clock and the frequency deviation and / or time offset between the first clock and the second clock; wherein the target adjustment mode is any one of a frequency adjustment mode, a time adjustment mode, a fine-tuning mode, and a silent mode;

[0048] An adjustment mode determination module, configured to re-determine the adjustment mode of the first clock based on the target adjustment mode.

[0049] According to a third aspect of the present disclosure, there is also provided an electronic device, including: a processor; and a memory, configured to store executable instructions of the processor; wherein the processor is configured to execute the clock synchronization method according to any one of the above first aspects by executing the executable instructions.

[0050] According to a fourth aspect of the present disclosure, there is also provided a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, it implements the clock synchronization method according to any one of the above first aspects.

[0051] In the embodiments provided by the present disclosure, for the clock synchronization method, based on the adjustment mode of the first clock, as well as the frequency deviation and / or time offset between the first clock and the second clock, an adjustment strategy for the parameters of the first clock and the target adjustment mode corresponding to the first clock are determined, and the adjustment mode in which the first clock is located is re-determined according to the target adjustment mode, as the basis for determining the target adjustment mode corresponding to the first clock during the next synchronization. In this way, during each clock synchronization, based on the adjustment mode after the previous synchronization, combined with the frequency deviation and / or time offset between the first clock and the second clock, it is determined how to adjust the first clock, which can make the time of the first clock continuous after multiple adjustments, the stability of the first clock is relatively high, and the frequency deviation between the two clocks is considered during the adjustment, rather than only adjusting the time offset, which will make the time accuracy of the adjusted first clock higher.

[0052] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] The accompanying drawings herein are incorporated into the specification and form a part of the specification, showing embodiments consistent with the present disclosure, and are used together with the specification to explain the principles of the present disclosure. Obviously, the accompanying drawings in the following description are only some embodiments of the present disclosure, and those of ordinary skill in the art can obtain other drawings based on these drawings without creative efforts.

[0054] Figure 1 Schematic diagram showing the implementation process of a clock synchronization method in an embodiment of the present disclosure;

[0055] Figure 2 Schematic diagram showing the implementation process of S106 in some embodiments of the present disclosure;

[0056] Figure 3 Schematic diagram showing the implementation process of S106 in still some other embodiments of the present disclosure;

[0057] Figure 4 Schematic diagram showing the implementation process of S106 in some other embodiments of the present disclosure;

[0058] Figure 5 Schematic diagram showing the implementation process of S106 in yet some other embodiments of the present disclosure;

[0059] Figure 6 Showing Figure 5 Schematic diagram showing an implementation process of S106 in the shown embodiment;

[0060] Figure 7 Showing Figure 5Another schematic diagram of the implementation process of S106 in the illustrated embodiment;

[0061] Figure 8 Schematic diagram of the process of the clock synchronization algorithm developed in a specific example of the present disclosure;

[0062] Figure 9 Illustrated in this specific example the application of Figure 8 Schematic diagram of the time offset of the local hardware clock applying the clock synchronization algorithm shown compared to the master clock; and

[0063] Figure 10 Schematic diagram of the simple structure of a clock synchronization device in an embodiment of the present disclosure. Detailed implementation manners

[0064] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in various forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. The features, structures, or characteristics described may be combined in any suitable manner in one or more embodiments.

[0065] In addition, the drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and thus their repeated description will be omitted. Some of the block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities may be implemented in software form, or in one or more hardware modules or integrated circuits, or in different networks and / or processor devices and / or microcontroller devices.

[0066] The following will, with reference to the accompanying drawings, detail the specific implementation manners of the embodiments of the present disclosure.

[0067] The inventor found that when adjusting the local hardware clock, if only adjusted according to the time offset between the local hardware clock and the master clock in the network each time, after each adjustment, it can only be close to the time of the master clock briefly. Then, due to the inconsistent frequencies between the two, the time offset will quickly increase gradually, making the time of the local hardware clock very inaccurate. And continuously adjusting the time of the local hardware clock in a short period will also cause jitter in the local hardware clock. For example, the time of the local hardware clock after the previous adjustment is 2023-11-13 12:30:56.128000000, the time of the local hardware clock after the next adjustment is 2023-11-13 12:30:55.999999998, and the time of the local hardware clock after the next adjustment is 2023-11-13 12:30:56.580101708. It can be seen that the time of the local hardware clock is jumping, discontinuous, and even shows a situation of time regression, thus resulting in very poor stability of the local hardware clock and being difficult to meet the requirements for clock accuracy and stability in the TSN network.

[0068] In view of the above findings, the embodiments of the present disclosure provide a clock synchronization method, as Figure 1 shown, including the following steps:

[0069] S102, determining the adjustment mode in which the first clock is located;

[0070] It should be noted that clock synchronization is a continuous process, but in practice, synchronous adjustment cannot be continuously carried out all the time. Specifically, during implementation, each time synchronization process is performed according to a preset time interval or a preset adjustment frequency, and each time synchronization process is performed according to the process from step S102 to S108. Determining the adjustment mode in which the first clock is located means determining the adjustment mode in which the first clock is located before the start of the current time synchronization process, which can be the adjustment mode in which the first clock is located after being re-determined at the end of the previous time synchronization process. When the current time synchronization process is the first time synchronization process, it can also be the preset adjustment mode in which the first clock is located. Generally, considering that during the first time synchronization process, the time offset between the first clock and the second clock exceeds the threshold value of time without adjustment, and the time offset between the two is relatively large and needs to be adjusted, the preset adjustment mode in which the first clock is located is the frequency adjustment mode.

[0071] S104, based on the obtained clock synchronization data, determining the frequency deviation and time offset between the first clock and the second clock;

[0072] It should be noted that the obtained clock synchronization data refers to the relevant information about the second clock, which may include data such as time and frequency. In specific implementation, data can be obtained through the Sync packet of the 802.1AS protocol. Each time an 802.1AS protocol Sync packet is received, clock synchronization data can be obtained once. In specific implementation, the above preset adjustment frequency can also be set to the frequency of receiving Sync packets, that is, time synchronization processing is performed each time a Sync packet is received. Those skilled in the art can understand that there are various ways to obtain clock synchronization data, not limited to the 802.1AS protocol, and other methods such as the 1588 protocol can also be used to obtain clock synchronization data. The present disclosure does not make specific limitations here. Based on the obtained clock synchronization data, the frequency deviation and time offset between the first clock and the second clock can be calculated.

[0073] S106. Determine an adjustment strategy for the parameters of the first clock and a target adjustment mode corresponding to the first clock according to the adjustment mode in which the first clock is located and the frequency deviation and / or time offset between the first clock and the second clock.

[0074] It should be noted that the target adjustment mode is any one of a frequency adjustment mode, a time adjustment mode, a fine-tuning mode, and a silent mode.

[0075] S108. Re-determine the adjustment mode in which the first clock is located based on the target adjustment mode.

[0076] It should be noted that in specific implementation of S108, the target adjustment mode is determined as the adjustment mode in which the first clock is located after re-determination. The determined target adjustment mode may be the same as the adjustment mode in which the first clock is located determined in S102, or may not be the same. The value of the target adjustment mode is assigned to the adjustment mode in which the first clock is located after re-determination to obtain the adjustment mode in which the first clock is located after this time synchronization processing.

[0077] It should be noted that in some embodiments of the present disclosure, the first clock refers to a local hardware clock, and the second clock refers to a master clock in the network. The local hardware clock refers to the clock used on a local hardware device, such as the clock of a SoC (System-on-Chip) chip. The master clock in the network refers to the time source of all devices to be synchronized in the entire time domain. For example, it can be the Grandmaster defined in the 802.1AS protocol, which is usually elected through the BMCA (Best Master Clock Algorithm) or can also be manually configured. Among them, there is only one master clock in one clock domain.

[0078] As can be seen from the above steps, in the clock synchronization method provided in the embodiments of the present disclosure, the adjustment strategy of the parameters of the first clock and the target adjustment mode corresponding to the first clock are determined based on the adjustment mode of the first clock, as well as the frequency deviation and / or time offset between the first clock and the second clock. Then, the adjustment mode of the first clock is re-determined according to the target adjustment mode, which is used as the basis for determining the target adjustment mode corresponding to the first clock during the next synchronization. In this way, each time clock synchronization is performed, based on the adjustment mode after the previous synchronization, combined with the frequency deviation and / or time offset between the first clock and the second clock, it is determined how to adjust the first clock, which can make the time of the first clock continuous after multiple adjustments, the stability of the first clock is relatively high, and the frequency deviation between the two clocks is considered during the adjustment, rather than only adjusting the time offset, which will make the time accuracy of the adjusted first clock higher.

[0079] In some embodiments of the present disclosure, the parameters of the first clock include at least one of the following or any combination: the frequency of the first clock, the time of the first clock, and the cumulative value of the time offset of the first clock. It should be noted that the cumulative value of the time offset of the first clock refers to the cumulative value of the time offset of the first clock compared to the second clock within a period of time starting from 0, and the initial set value is 0.

[0080] Correspondingly, as Figure 2 shown, it is the implementation process of S106 in some embodiments of the present disclosure. Specifically, when the adjustment mode of the first clock is the frequency adjustment mode, based on the adjustment mode of the first clock, as well as the frequency deviation and / or time offset between the first clock and the second clock, the adjustment strategy of the parameters of the first clock and the target adjustment mode corresponding to the first clock are determined, including the following steps:

[0081] S202, determine whether the absolute value of the frequency deviation is greater than or equal to the first preset threshold;

[0082] S204, if the absolute value of the frequency deviation is greater than or equal to the first preset threshold, determine that the target adjustment mode is the frequency adjustment mode, and determine the adjustment strategy of the parameters of the first clock as: adjust the frequency of the first clock according to the frequency deviation.

[0083] S206, if the absolute value of the frequency deviation is less than the first preset threshold, determine that the target adjustment mode is the time adjustment mode, and determine the adjustment strategy of the parameters of the first clock as: do not adjust the parameters of the first clock.

[0084] It should be noted that the first preset threshold can be determined according to actual adjustment requirements, obtained by analyzing historical adjustment data, or determined as the optimal value of multiple tests. When the absolute value of the frequency deviation is greater than or equal to the first preset threshold, it means that the frequency deviation between the first clock and the second clock is large, and the frequency of the first clock needs to be adjusted. Adjust the frequency of the first clock according to the frequency deviation. According to the frequency deviation, combined with the design of the hardware chip, increase or decrease the frequency of the first clock so that the frequency of the first clock is consistent with the frequency of the second clock; when the absolute value of the frequency deviation is less than the first preset threshold, it means that the frequency deviation between the first clock and the second clock is already very weak, and there is no need to adjust the frequency of the first clock for the time being, that is, the parameters of the first clock are not adjusted in this time synchronization process.

[0085] Correspondingly, as Figure 3 shown, the implementation process of S106 in some embodiments of the present disclosure is as follows. Specifically, when the adjustment mode of the first clock is the time adjustment mode, according to the adjustment mode of the first clock, the frequency deviation and / or time offset between the first clock and the second clock, determine the adjustment strategy of the parameters of the first clock and the target adjustment mode corresponding to the first clock, including the following steps:

[0086] S302, determine the cumulative value of the time offset of the first clock;

[0087] It should be noted that the cumulative value of the time offset of the first clock refers to the cumulative value of the time offsets determined during multiple time synchronization processes starting from when the cumulative value of the time offset of the first clock is 0 until this time synchronization process.

[0088] S304, determine whether the absolute value of the time offset is greater than the second preset threshold, and determine whether the absolute value of the cumulative value of the time offset is greater than the third preset threshold;

[0089] It should be noted that those skilled in the art can understand that the specific values of the second preset threshold and the third threshold are not limited, and can be set according to actual needs, or determined by analyzing historical data, or determined as the optimal value of multiple tests, and used as the judgment condition for whether to adjust the time of the first clock.

[0090] S306, if the absolute value of the time offset is greater than the second preset threshold or the absolute value of the cumulative value of the time offset is greater than the third preset threshold, determine the target adjustment mode as the silent mode, and determine the adjustment strategy of the parameters of the first clock as: adjust the time of the first clock according to the time offset, and clear the cumulative value of the time offset of the first clock;

[0091] S308, if the absolute value of the time offset is less than or equal to a second preset threshold, and the absolute value of the cumulative time offset is less than or equal to a third preset threshold, determine that the target adjustment mode is the fine-tuning mode, and determine the adjustment strategy for the parameters of the first clock as: do not adjust the parameters of the first clock.

[0092] It should be noted that the absolute value of the time offset is less than or equal to the second preset threshold, and the absolute value of the cumulative time offset is less than or equal to the third preset threshold, indicating that the time offset of the first clock relative to the second clock is very small, and it is no longer necessary to directly adjust the time of the first clock. Therefore, the parameters of the first clock are not adjusted, and it is determined that the first clock enters the fine-tuning mode. When the absolute value of the time offset is greater than the second preset threshold or the absolute value of the cumulative time offset is greater than the third preset threshold, it indicates that the time offset of the first clock relative to the second clock is relatively large, and the time of the first clock needs to be adjusted. Specifically, the time of the first clock is adjusted according to the time offset so that the time of the first clock is consistent with the time of the second clock, and the cumulative value of the time offset of the first clock is cleared so that the subsequent processing process can re-accumulate the time offset of the first clock. Since frequent changes to the time of the clock will make the clock unstable, to ensure the stability of the first clock, after adjusting the time of the first clock according to the time offset, the first clock will enter the silent mode to avoid frequent adjustment of the time of the first clock within a short period.

[0093] Correspondingly, the parameters of the first clock further include: the silent round value. The implementation process of S106 further includes: setting the silent round value to a preset value. It should be noted that the silent round value refers to the number of times of time synchronization processing when the first clock needs to maintain the silent mode. For example, it can be 3, 4, or 5. Those skilled in the art can understand that the specific set value of the silent round value can be any value and is not specifically limited. In some embodiments of the present disclosure, the implementation process of S106 is as Figure 4 shown. Specifically, when the adjustment mode of the first clock is the silent mode, according to the adjustment mode of the first clock and the frequency deviation and / or time offset between the first clock and the second clock, determine the adjustment strategy for the parameters of the first clock and the target adjustment mode corresponding to the first clock, including the following steps:

[0094] S402, determine the silent round value;

[0095] It should be noted that what is determined is the silent round value for the current time synchronization processing, which can be the initial preset value or the value after the previous time synchronization processing.

[0096] S404, determine whether the silent round value is zero;

[0097] S406, if the silent round value is not zero, determine that the target adjustment mode corresponding to the first clock is the silent mode, and determine the adjustment strategy for the parameters of the first clock as: subtract one from the silent round value;

[0098] S408, if the silent round value is zero, determine that the target adjustment mode corresponding to the first clock is the fine-tuning mode, and determine the adjustment strategy for the parameters of the first clock as: do not adjust the parameters of the first clock.

[0099] It should be noted that time synchronization processing is performed multiple times until the silent round value is zero, and no processing is done on the parameters of the first clock, and the first clock enters the fine-tuning mode.

[0100] As Figure 5 shown, it is the implementation process of S106 in some embodiments of the present disclosure. Specifically, when the adjustment mode of the first clock is the fine-tuning mode, according to the adjustment mode of the first clock and the frequency deviation and / or time offset between the first clock and the second clock, determine the adjustment strategy for the parameters of the first clock and the target adjustment mode corresponding to the first clock, including the following steps:

[0101] S502, determine whether the absolute value of the frequency deviation is greater than the fourth preset threshold;

[0102] S504, if the absolute value of the frequency deviation is less than or equal to the fourth preset threshold, determine the cumulative value of the time offset of the first clock;

[0103] S506, determine whether the absolute value of the time offset is greater than the fifth preset threshold, and determine whether the absolute value of the cumulative value of the time offset is greater than the sixth preset threshold;

[0104] S508, if the absolute value of the time offset is less than or equal to the fifth preset threshold, and the absolute value of the cumulative value of the time offset is less than or equal to the sixth preset threshold, determine that the target adjustment mode is the fine-tuning mode, and determine the adjustment strategy for the parameters of the first clock as: adjust the frequency of the first clock according to the frequency deviation and the time offset to adjust the time of the first clock; update the cumulative value of the time offset.

[0105] It should be noted that the fourth preset threshold, the fifth preset threshold, and the sixth preset threshold can be determined according to actual needs, historical data analysis, or the optimal values obtained from multiple tests. The present disclosure does not make specific limitations here. In specific implementation, for the sake of simplicity in the processing procedure, in the specific embodiments, the fifth preset threshold can be the same as the second preset threshold, and the sixth preset threshold can be the same as the third preset threshold. When the absolute value of the frequency deviation is less than or equal to the fourth preset threshold, and the absolute value of the time offset is less than or equal to the fifth preset threshold, and the absolute value of the cumulative time offset is less than or equal to the sixth preset threshold, it indicates that both the time and frequency between the first clock and the second clock are close at this time, and fine-tuning is required. According to the frequency deviation and the time offset, the frequency of the first clock is adjusted to adjust the time of the first clock. And the cumulative time offset value is continuously updated. Subsequently, when the cumulative time offset value accumulates to a certain value and exceeds the third preset threshold or the sixth preset threshold, the first clock enters the time adjustment mode.

[0106] In specific implementation, according to the frequency deviation and the time offset, the frequency of the first clock is adjusted to adjust the time of the first clock, including: according to the frequency deviation, the time offset, and the cumulative time offset value, using the PID (Proportion Integral Differential) algorithm to determine the adjustment value of the frequency of the first clock to adjust the time of the first clock. Since in the PID algorithm control action, the proportional action is the basic control, the differential action is used to accelerate the system control speed, and the integral action is used to eliminate the static error. Specifically, when using the PID algorithm to adjust the clock, the values of the three parameters of the proportional gain, integral gain, and differential gain corresponding to different first clocks are not exactly the same, and the optimal values need to be selected through experience and continuous test comparison. Combining the three adjustment laws of proportion, integral, and differential, and coordinating the intensities of the three actions appropriately can not only quickly adjust, but also eliminate the residual error, and a satisfactory control effect can be obtained. In this PID algorithm, the frequency deviation and the time offset are used as inputs, and after proportional, integral, and differential controls, the adjustment value of the frequency of the first clock is obtained. Based on the obtained adjustment value of the frequency of the first clock, the frequency of the first clock is adjusted, thereby obtaining the new frequency deviation and time offset after adjustment, and then feeding them back to the input of the PID algorithm, so as to continuously obtain the adjustment value of the frequency of the first clock. And by adjusting the frequency of the first clock, the time of the first clock is adjusted to be consistent with the time of the second clock, so that the first clock always operates with high precision and high stability.

[0107] Further, in some embodiments of the present disclosure, the implementation process of S106 is as Figure 6 shown. On the basis of Figure 5 , it further includes the following steps:

[0108] S602. If the absolute value of the frequency deviation is greater than the fourth preset threshold, determine that the target adjustment mode is the frequency adjustment mode, and determine the adjustment strategy for the parameters of the first clock as: Do not adjust the parameters of the first clock.

[0109] It should be noted that when the absolute value of the frequency deviation is greater than the fourth preset threshold, it indicates that the frequency deviation of the first clock compared to the second clock is relatively large, and it is not possible to enter the fine-tuning mode. Instead, the frequency of the first clock needs to be readjusted. Therefore, the parameters of the first clock are not adjusted, and the target adjustment mode is set to the frequency adjustment mode so that the frequency of the first clock can be adjusted during the next time synchronization operation.

[0110] In some embodiments of the present disclosure, the implementation process of S106 is as Figure 7 shown. On the basis of Figure 5 , the following steps are further included:

[0111] S702. If the absolute value of the time offset is greater than the fifth preset threshold or the absolute value of the cumulative time offset is greater than the sixth preset threshold, determine that the target adjustment mode is the time adjustment mode, and determine the adjustment strategy for the parameters of the first clock as: Do not adjust the parameters of the first clock.

[0112] It should be noted that when the absolute value of the time offset is greater than the fifth preset threshold or the absolute value of the cumulative time offset is greater than the sixth preset threshold, it indicates that the time offset of the first clock compared to the second clock is relatively large, and it is not possible to enter the fine-tuning mode. Instead, the time of the first clock needs to be readjusted. Therefore, the parameters of the first clock are not adjusted, and the target adjustment mode is set to the time adjustment mode so that the time of the first clock can be adjusted during the next time synchronization operation.

[0113] In some embodiments of the present disclosure, for the provided clock synchronization method, on the basis of Figure 1 , after S106, it further includes: Adjust the parameters of the first clock according to the determined adjustment strategy for the parameters of the first clock, so that the parameters of the first clock are consistent with the adjustment strategy of the parameters given in the above embodiments. It can be understood that the parameters of the first clock may change or remain unchanged.

[0114] As can be seen from the above embodiments, in the clock synchronization method provided by the present disclosure, the adjustment strategy of the parameters of the first clock and the target adjustment mode corresponding to the first clock are determined based on the adjustment mode of the first clock and the frequency deviation and / or time offset between the first clock and the second clock, and the adjustment mode of the first clock is re-determined according to the target adjustment mode as the basis for determining the target adjustment mode corresponding to the first clock during the next synchronization, so that during each clock synchronization, based on the adjustment mode after the previous synchronization, combined with the frequency deviation and / or time offset between the first clock and the second clock, it is determined how to adjust the first clock. That is, in the initial stage of clock synchronization of the first clock, through the frequency adjustment mode and the time adjustment mode, the frequency deviation and time offset between the first clock and the second clock are quickly adjusted to a certain range, and then enter the fine-tuning mode. In this mode, the time offset is not directly adjusted, but the clock frequency is fine-tuned through the PID algorithm to achieve the purpose of adjusting the time offset, which can keep the time of the first clock continuous during the time synchronization process, the stability of the first clock is relatively high, and the adjustment combines the frequency deviation between the two clocks instead of only adjusting the time offset, which will make the time accuracy of the adjusted first clock higher. And for different adjustment modes of the first clock, different judgment conditions corresponding to different adjustment modes are set when determining the target adjustment mode and the adjustment strategy of the parameters of the first clock, so as to simplify the judgment process and quickly determine the target adjustment mode and the adjustment strategy of the parameters of the first clock.

[0115] To better illustrate the clock synchronization method provided by the embodiments of the present disclosure, a specific example is provided below for further illustration. In this specific example, data is obtained through the Sync packet of the 802.1AS protocol.

[0116] This specific example is applied to the clock synchronization algorithm developed by the clock synchronization method provided by the embodiments of the present disclosure as Figure 8 shown.

[0117] Initially, set the adjustment mode (ClockState) of the local hardware clock to the frequency adjustment mode (FreqOnly), and set the time offset accumulation value (Sum64) of the first clock to 0.

[0118] Receive the Sync packet of the 802.1AS protocol, and obtain the frequency deviation (FreqRateVsGm, unit: ppb) and time offset (OffsetVsGm, unit: ns) of the local hardware clock compared with the master clock in the network from the Sync packet.

[0119] First, determine whether ClockState is FreqOnly. If so, then determine whether the absolute value of the frequency deviation is less than A1 ppb (Abs(FreqRateVsGm) < A1). If it is less, then determine that the local hardware clock has a relatively small frequency deviation compared to the master clock, do not adjust the parameters of the first clock, and re-determine ClockState to be the time adjustment mode (OffsetOnly). Return to the step of receiving the Sync packet of the 802.1AS protocol, re-obtain FreqRateVsGm and OffsetVsGm, and then make a determination. If it is not less, then determine that the local hardware clock has a relatively large frequency deviation compared to the master clock, adjust the frequency of the local hardware clock based on FreqRateVsGm, and keep ClockState still as FreqOnly. Return to the step of receiving the Sync packet of the 802.1AS protocol, re-obtain FreqRateVsGm and OffsetVsGm, and then make a determination.

[0120] If it is determined that ClockState is not FreqOnly, then determine whether ClockState is OffsetOnly. If so, then determine whether the absolute value of the time offset is greater than A2 ns or the absolute value of the cumulative time offset is greater than A3 ns. If either condition is met, then the time offset between the local hardware clock and the master clock is relatively large. Based on OffsetVsGm, adjust the time of the local hardware clock, and re-determine ClockState to be the silent mode (Slient), set the silent round (SlientCounter) to A4, return to the step of receiving the Sync packet of the 802.1AS protocol, re-obtain FreqRateVsGm and OffsetVsGm, and then make a determination. If neither condition is met, it means that both the frequency deviation and the time offset of the local hardware clock compared to the master clock are relatively small, within the adjustment range of the fine-tuning mode. Do not adjust the parameters of the first clock, and re-determine ClockState to be the fine-tuning mode (FreqAdjustOffset), return to the step of receiving the Sync packet of the 802.1AS protocol, re-obtain FreqRateVsGm and OffsetVsGm, and then make a determination.

[0121] If it is determined that ClockState is not FreqOnly and it is determined that ClockState is not OffsetOnly, then determine whether ClockState is FreqAdjustOffset. If it is, determine whether Abs(FreqRateVsGm) is greater than A5ppb. If Abs(FreqRateVsGm) > A5ppb, it indicates that the frequency deviation is large. Do not adjust the parameters of the first clock, and re-determine ClockState to be FreqOnly. Return to the step of receiving the Sync packet of the 802.1AS protocol, re-obtain FreqRateVsGm and OffsetVsGm, and then make a determination. If Abs(FreqRateVsGm) ≤ A5ppb, then determine whether Abs(OffsetVsGm) is greater than A6ns and determine whether Abs(Sum64) is greater than A3ns. If Abs(OffsetVsGm) > A6ns or Abs(Sum64) > A3ns, it indicates that the time offset between the local clock and the master clock is large. Do not adjust the parameters of the first clock, and re-determine ClockState to be OffsetOnly. Return to the step of receiving the Sync packet of the 802.1AS protocol, re-obtain FreqRateVsGm and OffsetVsGm, and then make a determination. If Abs(OffsetVsGm) ≤ A6ns and Abs(Sum64) ≤ A3ns, based on FreqRateVsGm and OffsetVsGm, use the PID algorithm to determine the frequency adjustment value of the local hardware clock, and adjust the frequency of the local hardware clock to achieve the purpose of adjusting the offset of the local hardware clock. After adjusting the frequency of the local hardware clock based on the frequency adjustment value of the local hardware clock, keep ClockState as FreqAdjustOffset, return to the step of receiving the Sync packet of the 802.1AS protocol, re-obtain FreqRateVsGm and OffsetVsGm, and then make a determination.

[0122] If it is determined that ClockState is not FreqOnly, and it is determined that ClockState is not OffsetOnly, and it is determined that ClockState is not FreqAdjustOffset, then determine whether ClockState is Slient. If so, it means that the local hardware clock has paused adjusting time and / or frequency at this time. Determine whether SlientCounter is 0: If it is not 0, subtract 1 from the value of SlientCounter, keep ClockState as Slient, return to the step of receiving the Sync packet of the 802.1AS protocol, re-obtain FreqRateVsGm and OffsetVsGm, and then make a determination. If it is 0, it means that the silence has ended, do not adjust the parameters of the first clock, and re-determine ClockState as FreqAdjustOffset, return to the step of receiving the Sync packet of the 802.1AS protocol, re-obtain FreqRateVsGm and OffsetVsGm, and then make a determination.

[0123] If it is determined that ClockState is not FreqOnly, and it is determined that ClockState is not OffsetOnly, and it is determined that ClockState is not FreqAdjustOffset, and it is determined that ClockState is not Slient either, then report an error. After the error is excluded or ignored, return to the step of receiving the Sync packet of the 802.1AS protocol, re-obtain FreqRateVsGm and OffsetVsGm, and then make a determination. It should be noted that in the normal processing flow, the values of ClockState are only the above four cases. However, it does not rule out that due to certain failures or errors, extremely special cases may cause the value of ClockState to appear in a value other than the above four cases. At this time, it is necessary to understand that an error is reported to the operator. After the problem is solved, a new Sync packet is received again, and then subsequent operations are performed.

[0124] It should be noted that the calculation process of the PID algorithm used in the fine-tuning mode includes: adding the stored value of Sum64 to the newly obtained OffsetVsGm this time to obtain the latest Sum64 for the next PID algorithm use. Using OffsetVsGm, Sum64, and FreqRateVsGm as the inputs of the PID algorithm, calculate the local hardware clock frequency adjustment value.

[0125] Those skilled in the art can understand that the above parameter values A1, A2, A3, A4, A5, A6 are only examples. In specific implementation, the specific values of the above parameters can be set according to the actual clock synchronization requirements.

[0126] This specific embodiment applies Figure 8 the clock synchronization algorithm shown to record the time offset between the local hardware clock and the master clock, as Figure 9 shown. It can be seen that after a large error in the initial small period of time between the local hardware clock and the master clock, under the adjustment and control of the clock synchronization algorithm, the time offset between the local hardware clock and the master clock gradually becomes stable, and the error always remains within ±40ns, which is very small, indicating that the time of the local hardware clock is relatively accurate.

[0127] From this, it can be seen that when this specific example applies the clock synchronization algorithm, it will not continuously adjust the time of the local hardware clock. At the initial stage of the startup of the 802.1AS protocol, due to a large deviation between the local hardware clock and the master clock, the frequency and time of the local clock will be adjusted significantly first. At this time, there will be certain errors and jitters in the local hardware clock. However, after adjusting the frequency offset and time offset between the local hardware clock and the master clock to a certain range, it will quickly enter the fine-tuning mode. In this mode, the time of the clock will no longer be directly adjusted, but the frequency value for fine-tuning the local hardware clock will be calculated through the PID algorithm, and the purpose of adjusting the clock will be achieved by adjusting the frequency, making the time synchronization accuracy of the local hardware clock high and the stability strong.

[0128] With the same inventive concept, an embodiment of the present disclosure also provides a clock synchronization device as described in the following embodiments. Since the principle of solving problems in this embodiment of the clock synchronization device is similar to that of the above embodiment of the clock synchronization method, the implementation of this embodiment of the clock synchronization device can refer to the implementation of the above method embodiment, and the repeated parts will not be elaborated.

[0129] Figure 10 The structural schematic diagram of a clock synchronization device in an embodiment of the present disclosure is shown, as Figure 10 shown, and it includes:

[0130] A clock mode determination module 1001, configured to determine the adjustment mode in which the first clock is located;

[0131] A clock data determination module 1002, configured to determine the frequency deviation and time offset between the first clock and the second clock based on the acquired clock synchronization data;

[0132] A clock adjustment module 1003, configured to determine the adjustment strategy for the parameters of the first clock and the target adjustment mode corresponding to the first clock according to the adjustment mode in which the first clock is located and the frequency deviation and / or time offset between the first clock and the second clock; wherein, the target adjustment mode is any one of a frequency adjustment mode, a time adjustment mode, a fine-tuning mode, and a silent mode;

[0133] An adjustment mode determination module 1004 is configured to re-determine the adjustment mode of the first clock based on a target adjustment mode.

[0134] It should be noted that the parameters of the first clock include at least one of the following or any combination: the frequency of the first clock, the time of the first clock, and the cumulative value of the time offset of the first clock.

[0135] In some embodiments of the present disclosure, when the adjustment mode of the first clock is a frequency adjustment mode, the clock adjustment module 1003 is specifically configured to:

[0136] Determine whether the absolute value of the frequency deviation is greater than or equal to a first preset threshold;

[0137] If the absolute value of the frequency deviation is greater than or equal to the first preset threshold, determine that the target adjustment mode is a frequency adjustment mode, and determine the adjustment strategy for the parameters of the first clock as: adjusting the frequency of the first clock according to the frequency deviation.

[0138] In some embodiments of the present disclosure, when the adjustment mode of the first clock is a frequency adjustment mode, the clock adjustment module 1003 is further configured to:

[0139] If the absolute value of the frequency deviation is less than the first preset threshold, determine that the target adjustment mode is a time adjustment mode, and determine the adjustment strategy for the parameters of the first clock as: not adjusting the parameters of the first clock.

[0140] In some embodiments of the present disclosure, when the adjustment mode of the first clock is a time adjustment mode, the clock adjustment module 1003 is specifically configured to:

[0141] Determine the cumulative value of the time offset of the first clock;

[0142] Determine whether the absolute value of the time offset is greater than a second preset threshold, and determine whether the absolute value of the cumulative value of the time offset is greater than a third preset threshold;

[0143] If the absolute value of the time offset is greater than the second preset threshold or the absolute value of the cumulative value of the time offset is greater than the third preset threshold, determine that the target adjustment mode is a silent mode, and determine the adjustment strategy for the parameters of the first clock as: adjusting the time of the first clock according to the time offset, and clearing the cumulative value of the time offset of the first clock.

[0144] Correspondingly, the parameters of the first clock further include: a silent round value;

[0145] The clock adjustment module 1003 is specifically configured to: set the silent round value to a preset value.

[0146] In some embodiments of the present disclosure, when the adjustment mode of the first clock is a time adjustment mode, the clock adjustment module 1003 is further configured to:

[0147] If the absolute value of the time offset is less than or equal to a second preset threshold, and the absolute value of the cumulative time offset is less than or equal to a third preset threshold, determine that the target adjustment mode is the fine-tuning mode, and determine the adjustment strategy for the parameters of the first clock as: Do not adjust the parameters of the first clock.

[0148] In some embodiments of the present disclosure, when the adjustment mode of the first clock is the fine-tuning mode, the clock adjustment module 1003 is specifically configured to:

[0149] Judge whether the absolute value of the frequency deviation is greater than a fourth preset threshold;

[0150] If the absolute value of the frequency deviation is less than or equal to the fourth preset threshold, determine the cumulative value of the time offset of the first clock;

[0151] Judge whether the absolute value of the time offset is greater than a fifth preset threshold, and judge whether the absolute value of the cumulative time offset is greater than a sixth preset threshold;

[0152] If the absolute value of the time offset is less than or equal to the fifth preset threshold, and the absolute value of the cumulative time offset is less than or equal to the sixth preset threshold, determine that the target adjustment mode is the fine-tuning mode, and determine the adjustment strategy for the parameters of the first clock as: Adjust the frequency of the first clock according to the frequency deviation and the time offset to adjust the time of the first clock; Update the cumulative value of the time offset.

[0153] Further, the clock adjustment module 1003 is specifically configured to: Determine the adjustment value of the frequency of the first clock by using the PID algorithm according to the frequency deviation, the time offset, and the cumulative time offset to adjust the time of the first clock.

[0154] In some embodiments of the present disclosure, when the adjustment mode of the first clock is the fine-tuning mode, the clock adjustment module 1003 is further configured to:

[0155] If the absolute value of the frequency deviation is greater than the fourth preset threshold, determine that the target adjustment mode is the frequency adjustment mode, and determine the adjustment strategy for the parameters of the first clock as: Do not adjust the parameters of the first clock.

[0156] In some embodiments of the present disclosure, when the adjustment mode of the first clock is the fine-tuning mode, the clock adjustment module 1003 is further configured to:

[0157] If the absolute value of the time offset is greater than the fifth preset threshold or the absolute value of the cumulative time offset is greater than the sixth preset threshold, determine that the target adjustment mode is the time adjustment mode, and determine the adjustment strategy for the parameters of the first clock as: Do not adjust the parameters of the first clock.

[0158] In some embodiments of the present disclosure, when the adjustment mode of the first clock is the silent mode, the clock adjustment module 1003 is specifically configured to:

[0159] Determine the silent round value;

[0160] Determine whether the silent round value is zero;

[0161] If the silent round value is not zero, determine that the target adjustment mode of the first clock is the silent mode, and determine the adjustment strategy for the parameters of the first clock as: subtract one from the silent round value;

[0162] If the silent round value is zero, determine that the target adjustment mode of the first clock is the fine-tuning mode, and determine the adjustment strategy for the parameters of the first clock as: do not adjust the parameters of the first clock.

[0163] In some embodiments of the present disclosure, the adjustment mode determination module 1004 is specifically configured to: determine the target adjustment mode as the adjustment mode of the first clock after redetermination.

[0164] Embodiments of the present disclosure also provide an electronic device, which includes: a processor; and a memory for storing executable instructions of the processor; wherein, the processor is configured to execute the clock synchronization method described in the above embodiments by executing the executable instructions.

[0165] Embodiments of the present disclosure also provide a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the clock synchronization method described in the above embodiments is implemented.

[0166] Those skilled in the art to which the present disclosure pertains can understand that various aspects of the present disclosure can be implemented as a system, a method, or a program product. Therefore, various aspects of the present disclosure can be specifically implemented in the following forms, namely: a complete hardware implementation manner, a complete software implementation manner (including firmware, microcode, etc.), or an implementation manner combining hardware and software aspects, which can be collectively referred to as "circuit", "module", or "system" here. It should be noted that although several modules or units of the devices for action execution are mentioned in the above detailed description, this division is not mandatory. In fact, according to the embodiments of the present disclosure, the features and functions of the two or more modules or units described above can be embodied in one module or unit. Conversely, the features and functions of one module or unit described above can be further divided and embodied by multiple modules or units.

[0167] In addition, although the various steps of the methods in the present disclosure are described in a specific order in the drawings, this does not require or imply that the steps must be performed in that specific order, or that all of the steps shown must be performed to achieve the desired result. Additionally or alternatively, some steps may be omitted, multiple steps may be combined into one step for execution, and / or one step may be decomposed into multiple steps for execution, etc.

[0168] From the description of the above embodiments, those skilled in the art can easily understand that the exemplary embodiments described herein can be implemented by software, or by a combination of software and necessary hardware. Therefore, the technical solutions according to the embodiments of the present disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (such as a CD-ROM, a USB flash drive, a mobile hard disk, etc.) or on a network, and includes several instructions to enable a computing device (such as a personal computer, a server, a mobile terminal, or a network device, etc.) to execute the methods according to the embodiments of the present disclosure.

[0169] After considering the specification and practicing the invention disclosed herein, those skilled in the art will readily conceive of other embodiments of the present disclosure. The present disclosure is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include known common knowledge or conventional technical means in the technical field not disclosed herein. The specification and examples are only considered exemplary, and the true scope and spirit of the present disclosure are pointed out by the appended claims.

Claims

1. A clock synchronization method, characterized in that, it includes: Determine the adjustment mode in which the first clock is located; Based on the obtained clock synchronization data, determine the frequency deviation and time offset between the first clock and the second clock; According to the adjustment mode in which the first clock is located and the frequency deviation and / or time offset between the first clock and the second clock, determine the adjustment strategy for the parameters of the first clock and the target adjustment mode corresponding to the first clock; wherein, the target adjustment mode is any one of a frequency adjustment mode, a time adjustment mode, a fine-tuning mode, and a silent mode; Redetermine the adjustment mode in which the first clock is located based on the target adjustment mode.

2. The clock synchronization method according to claim 1, characterized in that, The parameters of the first clock include at least one or any combination of the following: The frequency of the first clock, the time of the first clock, and the cumulative value of the time offset of the first clock.

3. The clock synchronization method according to claim 2, characterized in that, When the adjustment mode in which the first clock is located is the frequency adjustment mode, according to the adjustment mode in which the first clock is located and the frequency deviation and / or time offset between the first clock and the second clock, determining the adjustment strategy for the parameters of the first clock and the target adjustment mode corresponding to the first clock includes: Judge whether the absolute value of the frequency deviation is greater than or equal to a first preset threshold; If the absolute value of the frequency deviation is greater than or equal to the first preset threshold, determine that the target adjustment mode is the frequency adjustment mode, and determine the adjustment strategy for the parameters of the first clock as: adjusting the frequency of the first clock according to the frequency deviation.

4. The clock synchronization method according to claim 3, characterized in that, When the adjustment mode in which the first clock is located is the frequency adjustment mode, according to the adjustment mode in which the first clock is located and the frequency deviation and / or time offset between the first clock and the second clock, determining the adjustment strategy for the parameters of the first clock and the target adjustment mode corresponding to the first clock further includes: If the absolute value of the frequency deviation is less than the first preset threshold, determine that the target adjustment mode is the time adjustment mode, and determine the adjustment strategy for the parameters of the first clock as: not adjusting the parameters of the first clock.

5. The clock synchronization method according to claim 2, characterized in that, When the adjustment mode in which the first clock is located is the time adjustment mode, according to the adjustment mode in which the first clock is located and the frequency deviation and / or time offset between the first clock and the second clock, determining the adjustment strategy for the parameters of the first clock and the target adjustment mode corresponding to the first clock includes: Determine the cumulative value of the time offset of the first clock; Judge whether the absolute value of the time offset is greater than a second preset threshold, and judge whether the absolute value of the cumulative value of the time offset is greater than a third preset threshold; If the absolute value of the time offset is greater than a second preset threshold or the absolute value of the cumulative time offset is greater than a third preset threshold, determine that the target adjustment mode is the silent mode, and determine the adjustment strategy for the parameters of the first clock as: adjusting the time of the first clock according to the time offset and clearing the cumulative value of the time offset of the first clock.

6. The clock synchronization method according to claim 5, wherein, the parameters of the first clock further include: a silent round value; determine the adjustment strategy for the parameters of the first clock as: setting the silent round value to a preset value.

7. The clock synchronization method according to claim 6, wherein, when the adjustment mode of the first clock is the silent mode, determining the adjustment strategy for the parameters of the first clock and the target adjustment mode corresponding to the first clock according to the adjustment mode of the first clock and the frequency deviation and / or time offset between the first clock and the second clock includes: determining the silent round value; judging whether the silent round value is zero; if the silent round value is not zero, determine that the target adjustment mode corresponding to the first clock is the silent mode, and determine the adjustment strategy for the parameters of the first clock as: subtracting one from the silent round value; if the silent round value is zero, determine that the target adjustment mode corresponding to the first clock is the fine-tuning mode, and determine the adjustment strategy for the parameters of the first clock as: not adjusting the parameters of the first clock.

8. The clock synchronization method according to claim 5, wherein, when the adjustment mode of the first clock is the time adjustment mode, determining the adjustment strategy for the parameters of the first clock and the target adjustment mode corresponding to the first clock according to the adjustment mode of the first clock and the frequency deviation and / or time offset between the first clock and the second clock further includes: if the absolute value of the time offset is less than or equal to a second preset threshold and the absolute value of the cumulative time offset is less than or equal to a third preset threshold, determine that the target adjustment mode is the fine-tuning mode, and determine the adjustment strategy for the parameters of the first clock as: not adjusting the parameters of the first clock.

9. The clock synchronization method according to claim 2, wherein, when the adjustment mode of the first clock is the fine-tuning mode, determining the adjustment strategy for the parameters of the first clock and the target adjustment mode corresponding to the first clock according to the adjustment mode of the first clock and the frequency deviation and / or time offset between the first clock and the second clock includes: judging whether the absolute value of the frequency deviation is greater than a fourth preset threshold; if the absolute value of the frequency deviation is less than or equal to the fourth preset threshold, determine the cumulative value of the time offset of the first clock; judging whether the absolute value of the time offset is greater than a fifth preset threshold and judging whether the absolute value of the cumulative time offset is greater than a sixth preset threshold; If the absolute value of the time offset is less than or equal to a fifth preset threshold and the absolute value of the accumulated time offset is less than or equal to a sixth preset threshold, determine that the target adjustment mode is the fine-tuning mode, and determine the adjustment strategy for the parameters of the first clock as: adjusting the frequency of the first clock according to the frequency deviation and the time offset to adjust the time of the first clock; updating the accumulated time offset value.

10. The clock synchronization method according to claim 9, wherein, adjusting the frequency of the first clock according to the frequency deviation and the time offset to adjust the time of the first clock includes: determining an adjustment value for the frequency of the first clock according to the frequency deviation, the time offset, and the accumulated time offset value by using a PID algorithm to adjust the time of the first clock.

11. The clock synchronization method according to claim 9, wherein, when the adjustment mode of the first clock is the fine-tuning mode, determining the adjustment strategy for the parameters of the first clock and the target adjustment mode corresponding to the first clock according to the adjustment mode of the first clock and the frequency deviation and / or time offset between the first clock and the second clock further includes: if the absolute value of the frequency deviation is greater than a fourth preset threshold, determining that the target adjustment mode is the frequency adjustment mode, and determining the adjustment strategy for the parameters of the first clock as: not adjusting the parameters of the first clock.

12. The clock synchronization method according to claim 9, wherein, when the adjustment mode of the first clock is the fine-tuning mode, determining the adjustment strategy for the parameters of the first clock and the target adjustment mode corresponding to the first clock according to the adjustment mode of the first clock and the frequency deviation and / or time offset between the first clock and the second clock further includes: if the absolute value of the time offset is greater than a fifth preset threshold or the absolute value of the accumulated time offset is greater than a sixth preset threshold, determining that the target adjustment mode is the time adjustment mode, and determining the adjustment strategy for the parameters of the first clock as: not adjusting the parameters of the first clock.

13. The clock synchronization method according to any one of claims 1 to 12, wherein, re-determining the adjustment mode of the first clock based on the target adjustment mode includes: determining the target adjustment mode as the adjustment mode of the first clock after re-determination.

14. A clock synchronization device, wherein, comprising: a clock mode determination module for determining the adjustment mode of a first clock; a clock data determination module for determining the frequency deviation and time offset between the first clock and a second clock based on the acquired clock synchronization data; A clock adjustment module, configured to determine an adjustment strategy for parameters of the first clock and a target adjustment mode corresponding to the first clock according to an adjustment mode in which the first clock is located, as well as a frequency deviation and / or a time offset between the first clock and a second clock; wherein the target adjustment mode is any one of a frequency adjustment mode, a time adjustment mode, a fine-tuning mode, and a silent mode; An adjustment mode determination module, configured to re-determine the adjustment mode in which the first clock is located based on the target adjustment mode.

15. An electronic device, characterized in that, it includes: a processor; and a memory for storing executable instructions of the processor; wherein the processor is configured to execute the clock synchronization method according to any one of claims 1 to 13 by executing the executable instructions.

16. A computer-readable storage medium, on which a computer program is stored, characterized in that, when the computer program is executed by a processor, it implements the clock synchronization method according to any one of claims 1 to 13.

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