Chip and message forwarding method

Abstract

The embodiment of the invention provides a chip and a message forwarding method, relates to the technical field of chips, and improves the performance of a network switching chip. According to the specific scheme, the chip comprises a switching unit and a plurality of distribution modules, and each distribution module comprises a receiving circuit and a transmitting circuit. The receiving circuit is used for receiving a message and determining an identifier of at least one transmitting circuit corresponding to the message based on the first routing table and the first link state table, and the switching unit is used for forwarding the message to the at least one transmitting circuit corresponding to the identifier of the at least one transmitting circuit, and the at least one sending circuit is used for determining the identifier of the target link based on the second routing table and the second link state table, and sending the message based on the target link corresponding to the identifier of the target link. The embodiment of the invention is used for a message forwarding process.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of chip technology, and in particular, to a chip and a method for packet forwarding. Background Art

[0002] Currently, in order to improve the packet switching ability of a network switching chip, the network switching chip is usually divided into multiple switching planes (SWPs), and the links of the entire network switching chip are evenly distributed on each switching plane. As Figure 1 shown, each switching plane can be divided into an ingress switch plane (ISWP) and an egress switch plane (ESWP). Figure 1 It shows n ingress switch planes (such as ISWP0 to ISWPn), n egress switch planes (such as ESWP0 to ESWPn), and a cross unit (CU). Specifically, the network switching chip distributes and processes packets through two-level switching planes to determine the final output link of the packets. Each switching plane distributes and processes the packets simultaneously. The ingress switch plane performs the first distribution and processing to select the egress switch plane of the output link, and transmits the packet to the egress switch plane through the cross unit. The egress switch plane then performs the second distribution and processing to select a link of the egress switch plane as the output link, and transmits the packet through the output link. For example, the traffic received by ISWP0 is transmitted through ESWPn.

[0003] In order to obtain the status of the link in real time, the network switching chip needs to sense the dynamic changes of the routing, establish routing information, and transmit the routing information to each ingress switch plane and egress switch plane. However, the routing refresh information is complex. If multiple interfaces are used for parallel transmission of routing information, more routing resources are required. If a single interface is used for serial transmission of routing information, the transmission time is long and the real-time performance of the routing information is poor. Moreover, as the specifications of the network switching chip become larger and larger, more routing information needs to be stored to implement the packet distribution function, which will increase the area and power consumption of the network switching chip. Therefore, how to improve the performance of the network switching chip has become an urgent problem to be solved. Summary of the Invention

[0004] The embodiments of the present application provide a chip and a method for packet forwarding, which improve the performance of the network switching chip.

[0005] To achieve the above object, the embodiments of the present application adopt the following technical solutions.

[0006] In a first aspect, an embodiment of the present application provides a chip, which includes a switching unit and a plurality of distribution modules, and each distribution module includes a receiving circuit and a transmitting circuit. The receiving circuit is configured to receive a packet and determine the identifiers of at least one transmitting circuit corresponding to the packet based on a first routing table and a first link state table. The first routing table stores the number of links from each transmitting circuit to each destination port, and the first link state table stores the first state of the links of each transmitting circuit. The switching unit is configured to forward the packet to at least one transmitting circuit corresponding to the identifiers of at least one transmitting circuit. The at least one transmitting circuit is configured to determine the identifier of the destination link based on a second routing table and a second link state table, and send the packet based on the destination link corresponding to the identifier of the destination link. The second routing table stores the second state of the links from the transmitting circuit to each destination port, and the second link state table stores the first state of each link of the transmitting circuit.

[0007] Thus, in the chip provided by the embodiment of the present application, the packet is scheduled in two levels, and the first state of the links of the transmitting circuit is considered simultaneously to determine the identifiers of at least one transmitting circuit, and the first state of each link of the transmitting circuit is considered to determine the target link. Since the first routing table in the receiving circuit of the chip provided by the embodiment of the present application only stores the number of links from each transmitting circuit to each destination port, and the second routing table in the transmitting circuit only stores the second state of the links from the transmitting circuit to each destination port, the amount of routing information stored in the chip is reduced, and the area and power consumption of the chip are reduced. In addition, the amount of data required for routing refresh can also be reduced, and the real-time performance of the routing state can be improved.

[0008] In a possible design, the receiving circuit is specifically configured to: query the first routing table based on the destination port of the packet to determine the identifiers of a plurality of first transmitting circuits in at least one transmitting circuit, and query the first link state table based on the identifiers of the at least one first transmitting circuit to determine the identifiers of at least one transmitting circuit corresponding to the packet. Thus, in the first-level scheduling, the identifiers of the first transmitting circuits that can reach the destination port are first determined, and then the identifiers of the transmitting circuits with non-faulty links among the identifiers of the plurality of first transmitting circuits are further determined, thereby realizing the forwarding of the packet.

[0009] In a possible design, the receiving circuit is further configured to: output the packet to the switching unit respectively based on the identifiers of at least one transmitting circuit and the weight of each transmitting circuit, and the weight of each transmitting circuit is related to the number of links from each transmitting circuit to the destination port. Thus, the packet can be forwarded through multiple transmitting circuits, which is not likely to cause link congestion and improves the forwarding efficiency.

[0010] In a possible design, the sending circuit is specifically configured to: query a second routing table based on the destination port of the message to determine the identifiers of multiple first links among the multiple links from the sending circuit to the destination port, query a second link status table based on the identifiers of the multiple first links to determine the identifiers of multiple second links among the multiple links, and use one of the multiple second links corresponding to the identifiers of the multiple second links as the destination link. Thus, the messages are polled and sent among the sending circuits, which can balance the bandwidth of each link, is not likely to cause link congestion, and improves the message forwarding efficiency.

[0011] In a possible design, the chip further includes: a routing establishment module. The routing establishment module is configured to generate a third routing table based on the received multiple control cells, and the second status of the link from each sending circuit to each destination port is stored in the third routing table.

[0012] In a possible design, the routing establishment module is further configured to: obtain a first routing table and a second routing table based on the third routing table, and output the first routing table to the receiving circuit and output the second routing table to the sending circuit. Thus, since only the flat reachable information is stored in the first routing table and only the link reachable information is stored in the second routing table, the amount of data transmitted by the routing is reduced, the routing refresh time is reduced, and the distribution is more real-time.

[0013] In a possible design, the receiving circuit is further configured to obtain the first routing table through a first interface, and the sending circuit is further configured to obtain the second routing table through the first interface.

[0014] In a second aspect, an embodiment of the present application provides a method for message forwarding. The method is applied to a chip, and the chip includes: a switching unit and multiple distribution modules, and each distribution module includes a receiving circuit and a sending circuit; the method includes: the receiving circuit receives a message, and determines the identifier of at least one sending circuit corresponding to the message based on the first routing table and the first link status table. The number of links from each sending circuit to each destination port is stored in the first routing table, and the first status of the link of each sending circuit is stored in the first link status table. The switching unit forwards the message to at least one sending circuit corresponding to the identifier of at least one sending circuit. At least one sending circuit determines the identifier of the destination link based on the second routing table and the second link status table, and sends the message based on the destination link corresponding to the identifier of the destination link. The second status of the link from the sending circuit to each destination port is stored in the second routing table, and the first status of each link of the sending circuit is stored in the second link status table.

[0015] In a possible design, the receiving circuit determines the identifiers of at least one transmitting circuit corresponding to a message based on a first routing table and a first link state table, including: the receiving circuit queries the first routing table based on the destination port of the message to determine the identifiers of at least one first transmitting circuit among multiple transmitting circuits, and the receiving circuit queries the first link state table based on the identifiers of at least one first transmitting circuit to determine the identifiers of at least one transmitting circuit corresponding to the message.

[0016] In a possible design, the method further includes: the receiving circuit outputs the message to the switching unit respectively based on the identifiers of at least one transmitting circuit and the weight of each transmitting circuit, and the weight of each transmitting circuit is related to the number of links of each transmitting circuit to the destination port.

[0017] In a possible design, at least one transmitting circuit determines the identifier of the destination link based on a second routing table and a second link state table, including: the transmitting circuit queries the second routing table based on the destination port of the message to determine the identifiers of multiple first links among multiple links from the transmitting circuit to the destination port, the transmitting circuit queries the second link state table based on the identifiers of multiple first links to determine the identifiers of multiple second links among multiple links, and the transmitting circuit uses one of the multiple second links corresponding to the identifiers of multiple second links as the destination link.

[0018] In a possible design, the chip further includes: a routing establishment module; the method further includes: the routing establishment module generates a third routing table based on multiple received control cells, and the second state of the link from each transmitting circuit to each destination port is stored in the third routing table.

[0019] In a possible design, the method further includes: the routing establishment module obtains the first routing table and the second routing table based on the third routing table, and outputs the first routing table to the receiving circuit and outputs the second routing table to the transmitting circuit.

[0020] For the beneficial effects of the second aspect, reference can be made to the description of the first aspect.

[0021] In a third aspect, an embodiment of the present application provides a chip system, which includes multiple line cards and multiple chips as in the first aspect, and the multiple line cards and multiple chips are interconnected through lines.

[0022] In a fourth aspect, an embodiment of the present application provides an electronic device, which includes one or more interface circuits, and one or more chip systems as in the third aspect, and the interface circuits and the chip systems are interconnected through lines.

[0023] Fifth aspect, an embodiment of the present application provides a computer-readable storage medium, including computer instructions, which, when running on an electronic device, cause the electronic device to execute the method for packet forwarding in any of the above aspects and any possible implementation manners.

[0024] Sixth aspect, an embodiment of the present application provides a computer program product, which, when running on a computer or a processor, causes the computer or the processor to execute the method for packet forwarding in any of the above aspects and any possible implementation manners.

[0025] It can be understood that any of the above provided chips, chip systems, electronic devices, computer-readable storage media or computer program products can be applied to the corresponding methods provided above. Therefore, the beneficial effects that can be achieved can refer to the beneficial effects in the corresponding methods, which will not be elaborated here.

[0026] These aspects or other aspects of the present application will be more clearly understood in the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 It is a schematic structural diagram of a network switching chip provided by an embodiment of the present application;

[0028] Figure 2 It is a schematic structural diagram of another network switching chip provided by an embodiment of the present application;

[0029] Figure 3 It is a schematic structural diagram of a chip system provided by an embodiment of the present application;

[0030] Figure 4 It is a schematic structural diagram of a chip provided by an embodiment of the present application;

[0031] Figure 5 It is a schematic structural diagram of another chip provided by an embodiment of the present application;

[0032] Figure 6 It is a configuration diagram of a routing table provided by an embodiment of the present application;

[0033] Figure 7 It is a flowchart of routing distribution provided by an embodiment of the present application;

[0034] Figure 8 It is a flowchart of packet forwarding provided by an embodiment of the present application;

[0035] Figure 9 It is a flowchart of a method for packet forwarding provided by an embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0036] For ease of understanding, some explanations of concepts related to the embodiments of the present application are given as examples for reference. As shown below:

[0037] 1. Cross port of line speed across segments

[0038] "Crossing segments" means that the reachable links of a destination port belong to multiple switching planes. A port that does not cause bandwidth waste during packet distribution is a cross port of line speed across segments.

[0039] 2. Upward plane and downward plane

[0040] The upward plane is the entry processing plane for forwarding packets to the switching unit, and the downward plane is the exit processing plane for sending packets to the destination port.

[0041] 3. Unicast packets and multicast packets

[0042] A unicast packet is a packet transmitted one-to-one between a server and a terminal, and a multicast packet is a packet transmitted one-to-many between a server and a terminal.

[0043] Next, the technical solutions in the embodiments of the present application will be described with reference to the accompanying drawings in the embodiments of the present application. Among them, in the description of the embodiments of the present application, unless otherwise specified, " / " means "or". For example, A / B can mean A or B. The "and / or" herein is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist simultaneously, and B exists alone. In addition, in the description of the embodiments of the present application, "a plurality of" means two or more than two.

[0044] Hereinafter, the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of this embodiment, unless otherwise specified, the meaning of "a plurality of" is two or more.

[0045] In a network switching chip, in order for the upward plane to complete the distribution of packets to the downward plane, the upward plane needs to obtain and store the reachable link information based on the destination port. Among them, a packet can also be understood as traffic. When the upward plane forwards a packet, it queries the reachable link information through the identifier of the destination port carried in the packet to determine the downward plane, and transmits the packet to the downward plane. The reachable link information based on the destination port in the downward plane is also stored in the downward plane. After receiving the packet, the downward plane queries the reachable link information according to the identifier of the destination port carried in the packet to determine the destination link, and transmits the packet through the destination link.

[0046] Such asFigure 2 As shown Figure 2 FIG. shows a schematic structural diagram of another network switching chip provided by an embodiment of the present application. The network switching chip includes a switching unit, n upstream planes (ISWP0 to ISWPn), and n downstream planes (ESWP0 to ESWPn). Among them, each upstream plane stores a routing table (rout table, RUT), and each downstream plane also stores a routing table.

[0047] In a possible example, taking 2048 destination ports, 480 links, and 24 switching planes as an example, for unicast packets, the ISWP needs to store 24×2048×480 bits (bit, b) of routing information. The routing table of the specific ISWPn is as Figure 2 shown Figure 2 FIG. shows the correspondence between the identities (identity, ID) of 480 links and the identities of 2048 destination ports. Among them, "1" can indicate that this link can reach the destination port, and "0" can indicate that this link cannot reach the destination port. Specifically, in the routing table of ISWPn, the link with the identity of "0" can reach the destination ports with the identities of "0" and "2", and the link with the identity of "1" can reach the destination port with the identity of "2".

[0048] In addition, for unicast packets, each ESWP includes 20 links, so the ESWP needs to store 24×2048×20 bits of routing information. The routing table of the specific ESWPn is as Figure 2 shown Figure 2 FIG. shows the correspondence between the identities of 20 links and the identities of 2048 destination ports. Among them, "1" can indicate that this link can reach the destination port, and "0" can indicate that this link cannot reach the destination port. Specifically, in the routing table of ESWPn, the link with the identity of "0" can reach the destination ports with the identities of "0" and "2", and the link with the identity of "1" can reach the destination port with the identity of "2". In addition, for multicast packets, each ISWP and ESWP also need to store various types of routing information such as line rate cross-segment port link sets and load balance tables (load balancetable, LBT).

[0049] Therefore, a large amount of routing information is stored in the ISWP, and the routing refresh information is complex. If parallel transmission of routing information through multiple interfaces is adopted, more routing resources are required. If single-interface transmission of routing information is adopted, the required transmission time is long, and the real-time performance of the routing information is poor. Moreover, as the specifications of network switching chips become larger and larger, more routing information needs to be stored to implement the packet distribution function, which will increase the area and power consumption of the network switching chip. In addition, when the ISWP distributes packets link by link, packets will burst into each downstream plane periodically, which is likely to cause congestion.

[0050] Therefore, an embodiment of the present application provides a chip, which may be a network switching chip. The chip may include a switching unit and multiple distribution modules. Among them, the chip schedules packets in two levels, and simultaneously considers the first state of the link of the sending circuit to determine the identifier of at least one sending circuit, and considers the first state of each link of the sending circuit to determine the target link. Since the chip provided by the embodiment of the present application only stores the number of links from each sending circuit to each destination port in the first routing table in the receiving circuit, and only stores the second state of the links from the sending circuit to each destination port in the second routing table in the sending circuit, the data volume of the routing information stored in the chip is reduced, and the area and power consumption of the chip are reduced. In addition, the data volume required for routing refresh can also be reduced, and the real-time performance of the routing state can be improved.

[0051] In the above scenario, the chip provided by the embodiment of the present application can be applied to different systems or devices, such as an execution device. The execution device may be a terminal, such as a server, a switch, and a router, etc. The packet forwarding method provided by the embodiment of the present application can be applied to the packet forwarding scenario involved in the execution device.

[0052] In some embodiments, the chip proposed by the embodiment of the present application may be a system-on-a-chip (SoC). The SoC includes a processor, a memory, and input / output (I / O) interfaces, etc. The processor may be a single-core processor or a multi-core processor. After loading the data and application programs in the memory, the processor processes the data, such as performing packet forwarding processing in the embodiment of the present application.

[0053] In some embodiments, the chip provided by the embodiment of the present application can be applied to a chip system, and the chip system may further include multiple line cards, such as Figure 3 shown Figure 3 is a schematic structural diagram of a chip system provided by an embodiment of the present application. Figure 3n line cards are shown, namely line card 0, line card 1, line card 2, line card 3, line card 4, ……, line card n, etc. Among them, a line card can also be understood as an interface board, and a line card can include multiple fabric interface controllers (FICs). Specifically, the chip can be coupled to each line card through a serializer / deserializer (serdes). A line card can be used as the source port of a packet, and a line card can also be used as the destination port of a packet. The chip can receive a packet from the source port and forward it to the destination port. Therefore, the chip needs to establish routing information based on multiple destination ports to implement the routing establishment, lookup, and distribution functions of each destination port.

[0054] Applied to the above device or chip system, the chip provided by the embodiment of the present application will be introduced below.

[0055] The embodiment of the present application provides a chip 40, as Figure 4 shown Figure 4 is a schematic structural diagram of a chip provided by the embodiment of the present application. The chip 40 includes a switching unit 41 and multiple distribution modules 42, and each distribution module 42 includes a receiving circuit 421 and a sending circuit 422. Figure 4 n distribution modules 42 are shown, namely distribution module 42_1, distribution module 42_2, ……, distribution module 42_n-1, and distribution module 42_n.

[0056] Among them, the receiving circuit 421 is used to receive a packet and determine the identifier of at least one sending circuit 422 corresponding to the packet based on the first routing table and the first link state table. The first routing table stores the number of links from each sending circuit 422 to each destination port, and the first link state table stores the first state of the link of each sending circuit 422.

[0057] Exemplarily, each distribution module 42 is equivalent to a switching plane. Among them, each receiving circuit 421 can be understood as an upstream plane, that is, the entry processing plane of the packet to the switching unit 41. Each sending circuit 422 can be understood as a downstream plane, that is, the exit processing plane for sending the packet to the destination port.

[0058] Exemplarily, the first routing table is used to store the number of links from each transmitting circuit 422 to each destination port. For example, the first routing table may store the correspondence between the identifier of each transmitting circuit, the identifier of each destination port, and the number of links from each transmitting circuit to each destination port. In a possible example, taking j destination ports, m distribution modules 42, and each distribution module 42 including n links as an example, where the chip 40 includes a total of m * n links, and the chip 40 includes m receiving circuits 421 and m transmitting circuits 422. For a certain destination port i, where the destination port i is one of the j destination ports, the chip 40 can calculate the number of links from each distribution module 42 to the destination port i. Here, the number of links from the distribution module 42 to the destination port i can also be understood as the reachable link number. Specifically, the identifier of the transmitting circuit 422 can be 0, 1, 2, ……, m - 1. For the transmitting circuit 422 with the identifier "0", the reachable link number can be expressed as: sum0 = sum[n - 1, 0], where sum0 is the reachable link number of the transmitting circuit 422 with the identifier "0", and sum[n - 1, 0] is to traverse the links from the identifier "0" to the identifier "n - 1" and sum the number of links that can reach the destination port among the n links. In a possible example, referring to Figure 4 the first routing table shown in Figure 4 , among the n links of the transmitting circuit 422 with the identifier "0", 2 links can reach the destination port 2, then sum0 = 2. Additionally, for the transmitting circuit 422 with the identifier "1", the reachable link number can be expressed as: sum1 = sum[2n - 1, n]. For the transmitting circuit 422 with the identifier "m - 1", the reachable link number can be expressed as sum(m - 1) = sum[m * n - 1, (m - 1) * n].

[0059] Thus, the first routing table stores {sum(m - 1), ……, sum1, sum0}, and {sum(m - 1), ……, sum1, sum0} can also be understood as planar reachable information. Compared with the first routing table that stores the correspondence between the identifier of the link of each transmitting circuit and the identifier of the destination port, the first routing table provided by the embodiment of the present application only stores the number of links from each transmitting circuit to each destination port, reducing the data volume of the routing information stored in the chip and reducing the area and power consumption of the chip.

[0060] In addition, the first link status table is used to store the first status of the link of each transmission circuit 422. Among them, the first status of the link of each transmission circuit 422 can be understood as whether the link is a faulty link or a faulty path, etc. In a possible example, if the first status of the link is "0", it indicates that the link of the transmission circuit 422 is a faulty link, and if the first status of the link is "1", it indicates that the link of the transmission circuit 422 is a non-faulty link. In another possible example, if the first status of the link is "1", it indicates that the link of the transmission circuit 422 is a faulty link, and if the first status of the link is "0", it indicates that the link of the transmission circuit 422 is a non-faulty link. Among them, the first link status table stores the first status of the link of the transmission circuit in terms of planes. Assuming that each transmission circuit 422 includes 20 links, if all the 20 links are faulty links, the first status of the link of the transmission circuit 422 is characterized as a faulty link, and if there is at least one non-faulty link among the 20 links, the first status of the link of the transmission circuit 422 is characterized as a non-faulty link. Continuing to refer to the above example, see Figure 4 In the first link status table shown in Figure 4 , the identifier of the transmission circuit 422 can be 0, 1, 2, ……, m - 1. If "0" represents a faulty link and "1" represents a non-faulty link, then the status of the link of the transmission circuit 422 with the identifier "0" is "1", that is, there is at least one non-faulty link in the transmission circuit 422. The status of the link of the transmission circuit 422 with the identifier "1" is "0", that is, all the links of the transmission circuit 422 are faulty links.

[0061] Exemplarily, for a unicast packet and when the data volume of the unicast packet is small, only one transmission circuit 422 can be determined to forward the packet. For a unicast packet with a large data volume or a multicast packet, multiple transmission circuits 422 can be determined to forward the packet.

[0062] Optionally, the receiving circuit 421 is specifically configured to: query the first routing table based on the destination port of the packet to determine the identifier of at least one first transmission circuit among the multiple transmission circuits, and query the first link status table based on the identifier of at least one first transmission circuit to determine the identifier of at least one transmission circuit corresponding to the packet.

[0063] Exemplarily, since the first routing table stores the correspondence relationship between the identifier of each transmission circuit 422, the identifier of each destination port, and the number of links from each transmission circuit 422 to each destination port, the identifiers of the multiple first transmission circuits can be the identifiers of the transmission circuits 422 corresponding to the reachable link number not being 0. In a possible example, refer to Figure 4For the first routing table shown in , since the number of reachable links from the transmission circuit 422 labeled "0" to destination port 0 in the first routing table is 1, the transmission circuit 422 labeled "0" is the first transmission circuit. Since the number of reachable links from the transmission circuit 422 labeled "1" to destination port 0 in the first routing table is 0, the transmission circuit 422 labeled "1" is not the first transmission circuit. Thus, the labels of multiple first transmission circuits among multiple transmission circuits 422 can be determined.

[0064] Exemplarily, since the first link state table stores the first state of the links of each transmission circuit 422, the labels of the transmission circuits that are not faulty links among the labels of multiple first transmission circuits can be determined based on the first link state table. In a possible example, if "0" represents a faulty link and "1" represents a non-faulty link, continue to refer to Figure 4 For the first link state table shown in , since the first state of the link of the transmission circuit 422 labeled "0" in the first link state table is "1", that is, a non-faulty link, the transmission circuit 422 labeled "0" is the determined transmission circuit for packet forwarding; the first state of the link of the transmission circuit 422 labeled "1" in the first link state table is "0", that is, a faulty link, so the transmission circuit 422 labeled "0" is not used for packet forwarding.

[0065] Specifically, continuing to refer to the above example, the labels of multiple transmission circuits can be expressed as: ISWP_RUT&ILST, where ISWP_RUT is the label of the first transmission circuit and ILST is the first state of the link of the transmission circuit. That is to say, if the label of a certain transmission circuit 422 is both the label of the first transmission circuit and a non-faulty link, then it is determined that the transmission circuit 422 corresponding to the label of this transmission circuit 422 is the transmission circuit 422 for packet forwarding. In a possible instance, among the transmission circuits 422 labeled "0", if it is both the first transmission circuit and a non-faulty link, then the transmission circuit 422 labeled "0" is the transmission circuit 422 for packet forwarding. The transmission circuit 422 labeled "1" is the first transmission circuit but a faulty link, so the transmission circuit 422 labeled "1" is not the transmission circuit 422 for packet forwarding.

[0066] Optionally, the receiving circuit 421 is further configured to: output the packet to the switching unit 41 based on the labels of at least one transmission circuit 422 and the weight of each transmission circuit 422. Wherein, the weight of each transmission circuit 422 is related to the number of links of each transmission circuit 422 to the destination port.

[0067] Exemplarily, the receiving circuit 421 may allocate bandwidth to the packets forwarded by each sending circuit 422 based on the reachable link number as the weight, and determine multiple sending circuits 422 for each packet. Specifically, taking the {sum(m - 1), ……, sum1, sum0} stored in the first routing table as an example, if the total traffic of the packet sent to a certain destination port is P, then the traffic size forwarded by the sending circuit 422 marked as "0" is: P * sum0 / (sum0 + sum1 + …… + sum(m - 1)), the traffic size forwarded by the sending circuit 422 marked as "1" is: P * sum1 / (sum0 + sum1 + …… + sum(m - 1)), and the traffic size forwarded by the sending circuit 422 marked as "m - 1" is: P * sum(m - 1) / (sum0 + sum1 + …… + sum(m - 1)). Thus, after the packet is distributed by the receiving circuit 421, it is output to the switching unit 41, and the switching unit 41 sends the packet to the selected sending circuit 422.

[0068] Thus, the packet can be forwarded through multiple sending circuits 422, which is not likely to cause link congestion and improves the forwarding efficiency.

[0069] Optionally, continue to refer to Figure 4 , the switching unit 41 is used to forward the packet to at least one sending circuit 422 corresponding to the identifier of at least one sending circuit 422.

[0070] Exemplarily, the switching unit 41 can be implemented by using a Crossbar. The Crossbar is also called a cross - point switch matrix or a cross - bar switch matrix. This structure uses cross - point switches to connect the input ports and output ports, thus forming multiple data paths. This structure is relatively simple and has no shared bandwidth limitation. In a possible example, if the scale of the switching unit 41 is N, then the switching unit 41 includes N * N cross - point switches, and the cross - point switches determine whether the data path from the input port to the output port is open or closed. When the cross - point switch is open, it is called the cross state, and when the cross - point switch is closed, it is called the bar state. Thus, the switching unit 41 can forward the packet to multiple sending circuits corresponding to the identifiers of multiple sending circuits 422 by opening or closing the cross - point switches.

[0071] Optionally, continue to refer to Figure 4 , at least one sending circuit 422 is used to determine the identifier of the destination link based on the second routing table and the second link status table, and send the packet based on the destination link corresponding to the identifier of the destination link. The second routing table stores the second status of the link from the sending circuit 422 to each destination port, and the second link status table stores the first status of each link of the sending circuit 422.

[0072] Exemplarily, the first state may be whether the link is a faulty link, and the second state may be whether the link can reach the destination port.

[0073] Exemplarily, the second routing table is used to store the second states of the links from the sending circuit 422 to each destination port. For example, the second routing table may store the correspondence between the identifiers of the links from each sending circuit 422 to each destination port, the identifiers of each destination port, and the second states of the links from each sending circuit 422 to each destination port. Among them, the second routing table can be understood as the reachable link information of the sending circuit 422. Continuing with the example of j destination ports, m distribution modules 42, and each distribution module including n links, for the sending circuit 422 with the identifier "k", its reachable link information can be [(k + 1)*n - 1, k*n], that is, traverse the links from the identifier "k*n" to the identifier "(k + 1)*n - 1", and determine the second states of the links that can reach the destination port among the n links.

[0074] In a possible example, referring to Figure 4 the second routing table shown in, if "1" indicates that the link can reach the destination port and "0" indicates that the link cannot reach the destination port, then in the sending circuit 422, the link with the identifier "0" can reach the destination port with the identifier "0", and the link with the identifier "0" can also reach the destination port with the identifier "2". In addition, the link with the identifier "n - 1" cannot reach the destination port with the identifier "0", and the link with the identifier "n - 1" cannot reach the destination port with the identifier "2" either.

[0075] Exemplarily, the second link state table is used to store the first states of each link of the sending circuit 422. Continuing with the example of j destination ports, m distribution modules 42, and each distribution module including n links, referring to Figure 4 the second link state table shown in, if "0" indicates a faulty link and "1" indicates a non-faulty link, then the first state of the link with the identifier "0" is "1", that is, the link is a non-faulty link, and the first state of the link with the identifier "1" is "0", that is, the link is a faulty link.

[0076] Optionally, the sending circuit 422 is specifically configured to: query the second routing table based on the destination port of the packet to determine the identifiers of multiple first links among the multiple links from the sending circuit 422 to the destination port, query the second routing table based on the identifiers of the multiple first links to determine the identifiers of multiple second links among the multiple links, and use one of the multiple second links corresponding to the identifiers of the multiple second links as the destination link.

[0077] Exemplarily, since the second routing table stores the correspondence relationship between the identifier of each link from each sending circuit 422 to each destination port, the identifier of each destination port, and the second state of each link from each sending circuit 422 to each destination port, the identifiers of multiple first links can be the identifiers of the links corresponding to the sending circuits 422 that can reach the destination ports. In a possible example, if "1" indicates that the link can reach the destination port and "0" indicates that the link cannot reach the destination port, then the identifiers of the links with the second state of "1" in the second routing table are the identifiers of multiple first links.

[0078] Exemplarily, since the second link state table stores the second state of each link of each sending circuit 422, the identifiers of multiple second links that are non-faulty links among the identifiers of multiple first links can be determined based on the second link state table.

[0079] Exemplarily, the identifiers of multiple second links can be represented as: ESWP_RUT&ELST, where ESWP_RUT is the identifier of the first link and ELST is the first state of each link of the sending circuit. That is, if the identifier of a certain link is both the identifier of the first link and the link is a non-faulty link, then it is determined that the identifier of this link is the identifier of the destination link. In a possible example, the link with the identifier of "0" is both the first link and a non-faulty link, then the link with the identifier of "0" is the destination link. Or, the link with the identifier of "1" is the first link but a faulty link, then the link with the identifier of "1" is not the destination link.

[0080] Exemplarily, if there are multiple second links that are destination links, the final destination link can be determined by polling. Thus, the message is sent by polling among each sending circuit 422, which can balance the bandwidth of each link, is not likely to cause link congestion, and improves the message forwarding efficiency.

[0081] Optionally, the chip 40 may further include a routing establishment module 43, as Figure 5 shown, Figure 5 which is a schematic structural diagram of another chip system provided by the embodiment of the present application. Among them, the routing establishment module 43 is used to generate a third routing table based on the received multiple control cells, and the second state of each link from each sending circuit 422 to each destination port is stored in the third routing table.

[0082] Exemplarily, Figure 5A chip 40 and n line cards are shown, namely line card 0, line card 1, line card 2, line card 3, line card 4, ……, line card n, etc. Among them, the chip 40 includes a switching unit 41, a plurality of distribution modules 42, and a routing establishment module 43. Among them, the plurality of distribution modules 42 may include distribution module 42_1, distribution module 42_2, ……, distribution module 42_n-1, and distribution module 42_n. Before the chip system transmits packets, control cells are generated between each line card and the chip 40 and sent to each other. The chip 40 can establish the routing information of the entire chip system according to the received multiple control cells.

[0083] Specifically, the routing establishment module 43 in the chip 40 can generate a third routing table based on the received multiple control cells. Continuing with the example of j destination ports, m distribution modules 42, and each distribution module including n links, the third routing table may include the correspondence between the identifiers of m*n links and the second states of the j destination ports.

[0084] Optionally, the routing establishment module 43 is further configured to: obtain a first routing table and a second routing table based on the third routing table, and output the first routing table to the receiving circuit 421 and output the second routing table to the sending circuit 422.

[0085] Exemplarily, as Figure 6 shown, Figure 6 is a configuration diagram of a routing table provided by an embodiment of the present application. Figure 6 Only the routing establishment module 43 and one distribution module 42 are shown. Among them, after receiving the control cell, the routing establishment module 43 generates a third routing table. Specifically, the third routing table may include the correspondence between the identifier of the link from the sending circuit 422 to the destination port, the identifier of the destination port, and the second state of the link from the sending circuit 422 to the destination port. Continuing with the example of j destination ports, m distribution modules 42, and each distribution module including n links, the identifier of the link from the sending circuit 422 to the destination port is from "0" to "(m-1)*(n-1)", and the identifier of the destination port is from "0" to "j-1". The routing establishment module 43 generates a first routing table based on the correspondence between the identifier of each sending circuit 422, the identifier of each destination port, and the number of links from each sending circuit 422 to each destination port in the third routing table, and outputs the first routing table to the receiving circuit 421 through routing refresh. In addition, the routing establishment module 43 also generates a second routing table based on the correspondence between the identifier of the link from each sending circuit 422 to each destination port, the identifier of each destination port, and the second state of the link from each sending circuit 422 to each destination port in the third routing table, and outputs the second routing table to the sending circuit 422 through routing refresh.

[0086] In addition, the routing establishment module 43 can also generate a third link state table based on multiple control cells, obtain a first link state table and a second link state table based on the third link state, and output the first link state table to the receiving circuit 421 and output the second link state table to the transmitting circuit 422 through routing refresh.

[0087] In addition to this, the routing establishment module 43 can also generate a load balancing table based on control cells and output the load balancing table to the receiving circuit 421 and the transmitting circuit 422.

[0088] It can be understood that only the flat reachability information is stored in the first routing table, and only the link reachability information is stored in the second routing table, reducing the amount of data transmitted by routing, reducing the routing refresh time, and making the distribution more real-time.

[0089] Optionally, the receiving circuit 421 is further configured to obtain the first routing table through the first interface, and the transmitting circuit 422 is further configured to obtain the second routing table through the first interface.

[0090] Exemplarily, the first interface can be a peripheral component interconnect express (PCIE) interface. Among them, the receiving circuit 421 can directly obtain the first routing table through the PCIE interface, and the transmitting circuit 422 can obtain the second routing table through the PCIE interface.

[0091] Specifically, as Figure 7 shown, Figure 7 is a flowchart of a routing distribution provided by an embodiment of the present application. Among them, Figure 7 shows the PCIE interface, the routing establishment module 43, and n distribution modules 42. The n distribution modules 42 can include a distribution module 42_1, a distribution module 42_2, and a distribution module 42_n. The distribution module 42_1 includes an ISWP1 and an ESWP1, the distribution module 42_2 includes an ISWP2 and an ESWP2, and the distribution module 42_n includes an ISWPn and an ESWPn. Among them, each ISWP and ESWP can obtain the routing table in three ways. The first way is that the ISWP obtains the first routing table through the PCIE interface, and the ESWP obtains the second routing table through the PCIE interface. The second way is that the routing establishment module generates a third routing table, the ISWP obtains the first routing table from the routing establishment module 43, and the ESWP obtains the second routing table from the routing establishment module 43. The third way is that the routing establishment module 43 obtains the third routing table through the PCIE interface, the ISWP obtains the first routing table from the routing establishment module 43, and the ESWP obtains the second routing table from the routing establishment module 43.

[0092] In summary, the process of packet forwarding is asFigure 8 As shown in the figure, a message is transmitted to a certain receiving circuit 421 (such as ISWPx). In the receiving circuit 421, a route search operation is performed to search for the first routing table. After determining the identifier of the sending circuit 422 (such as ESWPy), a route distribution operation is carried out, and the message is transmitted to the switching unit 41. The switching unit 41 forwards the message to the sending circuit 422 corresponding to the identifier of the sending circuit 422. After receiving the message, the sending circuit 422 performs a route search operation to search for the second routing table. After determining the identifier of the destination link, a route distribution operation is carried out, and the message is sent out based on the destination link.

[0093] Applied to the above chip, the method for message forwarding provided by the embodiments of the present application will be introduced below.

[0094] As Figure 9 shown, Figure 9 is a flowchart of a method for message forwarding provided by an embodiment of the present application. The method includes the following processes.

[0095] S901. The receiving circuit receives the message and determines the identifiers of at least one sending circuit corresponding to the message based on the first routing table and the first link status table.

[0096] Among them, the first routing table stores the number of links from each sending circuit to each destination port, and the first link status table stores the first status of the links of each sending circuit.

[0097] S902. The switching unit forwards the message to at least one sending circuit corresponding to the identifiers of at least one sending circuit.

[0098] S903. At least one sending circuit determines the identifier of the destination link based on the second routing table and the second link status table, and sends the message based on the destination link corresponding to the identifier of the destination link.

[0099] Among them, the second routing table stores the second status of the links from the sending circuit to each destination port, and the second link status table stores the first status of each link of the sending circuit.

[0100] Accordingly, the chip provided by the embodiment of the present application schedules messages in two levels, and simultaneously considers the first state of the link of the sending circuit to determine the identifier of at least one sending circuit, and considers the first state of each link of the sending circuit to determine the target link. Since the chip provided by the embodiment of the present application only stores the number of links from each sending circuit to each destination port in the first routing table in the receiving circuit, and only stores the second state of the links from the sending circuit to each destination port in the second routing table in the sending circuit, the amount of routing information stored in the chip is reduced, and the area and power consumption of the chip are reduced. In addition, the amount of data required for routing refresh can also be reduced, and the real-time performance of the routing state can be improved.

[0101] Optionally, S901 may include: the receiving circuit queries the first routing table based on the destination port of the message to determine the identifier of at least one first sending circuit among multiple sending circuits, and the receiving circuit queries the first link status table based on the identifier of at least one first sending circuit to determine the identifier of at least one sending circuit corresponding to the message.

[0102] Optionally, the method may further include: the receiving circuit outputs the message to the switching unit respectively based on the identifier of at least one sending circuit and the weight of each sending circuit, and the weight of each sending circuit is related to the number of links from each sending circuit to the destination port.

[0103] Optionally, S903 may include: the sending circuit queries the second routing table based on the destination port of the message to determine the identifier of multiple first links among multiple links from the sending circuit to the destination port, the sending circuit queries the second link status table based on the identifier of multiple first links to determine the identifier of multiple second links among multiple links, and the sending circuit uses one of the multiple second links corresponding to the identifier of multiple second links as the destination link.

[0104] Optionally, the method may further include: the routing establishment module generates a third routing table based on the received multiple control cells, and the second state of the links from each sending circuit to each destination port is stored in the third routing table.

[0105] Optionally, the method may further include: the routing establishment module obtains the first routing table and the second routing table based on the third routing table, and outputs the first routing table to the receiving circuit and outputs the second routing table to the sending circuit.

[0106] Optionally, the method may further include: the receiving circuit obtains the first routing table through the first interface, and the sending circuit obtains the second routing table through the first interface.

[0107] An embodiment of the present application provides a chip system, which includes multiple line cards and multiple chips, and the multiple line cards and multiple chips are interconnected through lines.

[0108] Embodiments of the present application provide an electronic device, which includes one or more interface circuits and one or more chip systems, and the interface circuits and the chip systems are interconnected through lines.

[0109] Embodiments of the present application also provide a computer device, including one or more processors and one or more memories. The one or more memories are coupled to the one or more processors, and the one or more memories are used to store computer program codes, and the computer program codes include computer instructions. When the one or more processors execute the computer instructions, the electronic device is caused to execute the above-related method steps to implement the method for packet forwarding in the above embodiments.

[0110] Embodiments of the present application also provide a computer storage medium, in which computer instructions are stored. When the computer instructions run on the electronic device, the electronic device is caused to execute the above-related method steps to implement the method for packet forwarding in the above embodiments.

[0111] Embodiments of the present application also provide a computer program product. When the computer program product runs on a computer, the computer is caused to execute the above-related steps to implement the method for packet forwarding executed by the electronic device in the above embodiments.

[0112] In addition, embodiments of the present application also provide a device, which may specifically be a chip, a component or a module. The device may include a processor and a memory connected to each other. The memory is used to store computer execution instructions. When the device runs, the processor may execute the computer execution instructions stored in the memory, so that the chip executes the method for packet forwarding executed by the electronic device in the above method embodiments.

[0113] Among them, the chip, chip system, electronic device, computer device, computer storage medium, computer program product or chip provided in this embodiment are all used to execute the corresponding method provided above. Therefore, the beneficial effects that can be achieved can refer to the beneficial effects in the corresponding method provided above, and will not be elaborated here.

[0114] Through the description of the above embodiments, those skilled in the art can understand that for the convenience and simplicity of description, only the above division of each functional module is used as an example. In practical applications, the above functions can be allocated to different functional modules according to needs, that is, the internal structure of the device is divided into different functional modules to complete all or part of the functions described above.

[0115] In several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the modules or units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components can be combined or integrated into another device, or some features can be ignored or not executed. Another point is that the displayed or discussed coupling or direct coupling or communication connection to each other can be through some interfaces. The indirect coupling or communication connection of the devices or units can be in electrical, mechanical or other forms.

[0116] The units described as separate components may or may not be physically separated. The components displayed as units may be one physical unit or multiple physical units, that is, they can be located in one place, or they can be distributed to multiple different places. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0117] In addition, each functional unit in various embodiments of the present application can be integrated in a processing unit, or each unit can exist physically alone, or two or more units can be integrated in one unit. The above-mentioned integrated units can be implemented in the form of hardware or in the form of software functional units.

[0118] If the above-mentioned integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a readable storage medium. Based on such an understanding, the technical solution of the embodiments of the present application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. The software product is stored in a storage medium and includes several instructions for causing a device (which can be a single-chip microcomputer, a chip, etc.) or a processor to execute all or part of the steps of the methods described in various embodiments of the present application. The foregoing storage medium includes: various media such as USB flash drives, mobile hard disks, read-only memories (ROM), random access memories (RAM), magnetic disks, or optical discs that can store program codes.

[0119] The above content is only the specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed in the present application can easily think of changes or substitutions, which should all be covered by the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A chip, characterized in that, it includes: a switching unit and multiple distribution modules, each distribution module includes a receiving circuit and a transmitting circuit; the receiving circuit is used to receive a message, and determine the identifiers of at least one transmitting circuit corresponding to the message based on a first routing table and a first link state table, the first routing table stores the number of links from each transmitting circuit to each destination port, and the first link state table stores the first state of the links of each transmitting circuit; the switching unit is used to forward the message to at least one transmitting circuit corresponding to the identifiers of the at least one transmitting circuit; the at least one transmitting circuit is used to determine the identifier of the destination link based on a second routing table and a second link state table, and send the message based on the destination link corresponding to the identifier of the destination link, the second routing table stores the second state of the links from the transmitting circuit to each destination port, and the second link state table stores the first state of each link of the transmitting circuit.

2. The chip according to claim 1, characterized in that, the receiving circuit is specifically used for: query the first routing table based on the destination port of the message to determine the identifier of at least one first transmitting circuit among the multiple transmitting circuits; query the first link state table based on the identifier of the at least one first transmitting circuit to determine the identifier of the at least one transmitting circuit corresponding to the message.

3. The chip according to claim 2, characterized in that, the receiving circuit is further used for: output the message to the switching unit respectively based on the identifier of the at least one transmitting circuit and the weight of each transmitting circuit, and the weight of each transmitting circuit is related to the number of links from each transmitting circuit to the destination port.

4. The chip according to claim 1, characterized in that, the transmitting circuit is specifically used for: query the second routing table based on the destination port of the message to determine the identifiers of multiple first links among the multiple links from the transmitting circuit to the destination port; query the second link state table based on the identifiers of the multiple first links to determine the identifiers of multiple second links among the multiple links; take one of the multiple second links corresponding to the identifiers of the multiple second links as the destination link.

5. The chip according to any one of claims 1-4, characterized in that, the chip further includes: a routing establishment module; the routing establishment module is used to generate a third routing table based on multiple received control cells, and the third routing table stores the second state of the links from each transmitting circuit to each destination port.

6. The chip according to claim 5, characterized in that, the routing establishment module is further used for: obtain the first routing table and the second routing table based on the third routing table, and output the first routing table to the receiving circuit and output the second routing table to the transmitting circuit.

7. The chip according to any one of claims 1-4, characterized in that, The receiving circuit is further configured to obtain the first routing table through the first interface; The sending circuit is further configured to obtain the second routing table through the first interface.

8. A method for packet forwarding, characterized in that, the method is applied to a chip, the chip includes a switching unit and a plurality of distribution modules, and each distribution module includes a receiving circuit and a sending circuit; the method includes: The receiving circuit receives a packet, and determines identifiers of at least one sending circuit corresponding to the packet based on a first routing table and a first link state table, where the first routing table stores the number of links from each sending circuit to each destination port, and the first link state table stores a first state of the link of each sending circuit; The switching unit forwards the packet to at least one sending circuit corresponding to the identifiers of the at least one sending circuit; The at least one sending circuit determines an identifier of a destination link based on a second routing table and a second link state table, and sends the packet based on the destination link corresponding to the identifier of the destination link, where the second routing table stores a second state of the link from the sending circuit to each destination port, and the second link state table stores a first state of each link of the sending circuit.

9. The method according to claim 8, characterized in that, the receiving circuit determines the identifiers of at least one sending circuit corresponding to the packet based on the first routing table and the first link state table, including: The receiving circuit queries the first routing table based on the destination port of the packet to determine the identifiers of at least one first sending circuit among the plurality of sending circuits; The receiving circuit queries the first link state table based on the identifiers of the at least one first sending circuit to determine the identifiers of the at least one sending circuit corresponding to the packet.

10. The method according to claim 9, characterized in that, the method further includes: The receiving circuit outputs the packet to the switching unit respectively based on the identifiers of the at least one sending circuit and the weight of each sending circuit, and the weight of each sending circuit is related to the number of links from each sending circuit to the destination port.

11. The method according to claim 8, characterized in that, the at least one sending circuit determines the identifier of the destination link based on the second routing table and the second link state table, including: The sending circuit queries the second routing table based on the destination port of the packet to determine the identifiers of multiple first links among multiple links from the sending circuit to the destination port; The sending circuit queries the second link state table based on the identifiers of the multiple first links to determine the identifiers of multiple second links among the multiple links; The sending circuit uses one of the multiple second links corresponding to the identifiers of the multiple second links as the destination link.

12. The method according to any one of claims 8-11, characterized in that, the chip further includes: a routing establishment module; the method further includes: The routing establishment module generates a third routing table based on the received multiple control cells, and the second status of the link from each sending circuit to each destination port is stored in the third routing table.

13. The method according to claim 12, wherein, the method further includes: The routing establishment module obtains the first routing table and the second routing table based on the third routing table, and outputs the first routing table to the receiving circuit and outputs the second routing table to the sending circuit.

14. The method according to any one of claims 8-11, wherein, the method further includes: The receiving circuit obtains the first routing table through a first interface; The sending circuit obtains the second routing table through the first interface.

15. A chip system, wherein, it includes a plurality of line cards and a plurality of chips according to any one of claims 1-7, and the plurality of line cards and the plurality of chips are interconnected through lines.

16. An electronic device, wherein, it includes one or more interface circuits, and one or more chip systems according to claim 15, and the interface circuit and the chip system are interconnected through lines.

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