General three-speed Ethernet controller IP core based on domestic FPGA

Abstract

The invention designs a general three-speed Ethernet controller IP core based on a domestic FPGA. The general three-speed Ethernet controller IP core comprises a UDP protocol stack module compatible with multi-protocol processing and a processing module compatible with a three-speed Ethernet. The UDP protocol stack module compatible with multi-protocol processing is used for processing unpacking and framing of data messages of an MAC layer, an ARP layer, an IP layer, a UDP layer and an ICMP layer, and achieving the function of data arbitration processing when multiple protocols are sent at the same time. And the processing module compatible with the three-speed Ethernet is used for realizing the adaptation of the UDP protocol stack and the RGMII interface, the sequential control of the three-speed Ethernet and the function of caching data when the network speed is switched. According to the invention, the design of a general UDP protocol stack architecture is realized, the UDP protocol stack architecture can be transplanted and applied across various application fields, only the IPs of FIFO and RAM of most FPGAs are adopted, the UDP protocol stack architecture is easy to be subsequently transplanted to various domestic FPGA chips, and certain reference significance is provided for engineering application substitution of the domestic FPGAs.

Description

Technical Field

[0001] The present invention belongs to the field of industrial Internet of Things, and specifically relates to a general three-speed Ethernet controller IP core based on domestic FPGA, which is applied to the Ethernet controller of the Internet of Things gateway in the civil air defense project environment to facilitate data collection and transmission. Background Art

[0002] In the civil air defense project environment, the real-time and accuracy of information acquisition are important guarantees for people's lives. At present, Ethernet has become the main communication means. However, in edge devices, there are still communication methods such as RS485, RS232, and CAN bus for low-speed data acquisition buses. Therefore, it is necessary to convert the protocols of traditional communication acquisitions into Ethernet for communication transmission. The device that realizes this protocol conversion is called a gateway. Most of the existing gateway devices are implemented based on single-chip microcomputers or ARM systems, but the real-time performance of their transmissions cannot be guaranteed. In addition, there are also customized gateways using ASICs. Although ASICs are customized circuits with high speed, their portability and functional expandability are poor, and it is difficult to apply them across scenarios or application fields. Therefore, at present, gateway devices based on FPGA are becoming the main research direction. For FPGA gateways, the Ethernet interface controller is a very important part. It can realize functions such as network connection, protocol processing, data packet forwarding and filtering, and is a necessary condition for the gateway to perform protocol conversion later.

[0003] The research on existing Ethernet controllers mainly uses FPGAs from foreign companies such as Xilinx or Altera for design, and most of them use the integrated MAC IP provided by the manufacturers for development and design, which is difficult to meet the urgent need for domestic substitution in a large number of engineering applications. In addition, most of the current designs of Ethernet controllers are designed for specific scenarios, and most of them only support one or two protocol types and are not general protocol stacks, making it difficult to be transplanted to cross-domain application scenarios. Therefore, how to design from the two aspects of easy transplantation and compatibility with multiple protocol communications is a very crucial issue for the application of domestic gateways. Summary of the Invention

[0004] In view of the above-mentioned technical problems, a general three-speed Ethernet controller IP core based on domestic FPGA is proposed to solve the problems of difficult transplantation and poor generality of existing Ethernet controllers.

[0005] The technical solution adopted by the present invention to achieve the above object is as follows:

[0006] A general three-speed Ethernet controller IP core based on domestic FPGA, comprising:

[0007] A UDP protocol stack module compatible with multi - protocol processing, which is used to handle the unpacking and framing of data packets at the MAC layer, ARP layer, IP layer, UDP layer, and ICMP layer, and to implement data arbitration processing when multiple protocols are sent simultaneously;

[0008] A processing module compatible with three - speed Ethernet, which is used to implement the adaptation between the UDP protocol stack module and the RGMII interface, the timing control of three - speed Ethernet, and the caching of data when switching network speeds.

[0009] Both the UDP protocol stack module compatible with multi - protocol processing and the processing module compatible with three - speed Ethernet are implemented in the eLinx3.0 development environment.

[0010] The UDP protocol stack module compatible with multi - protocol processing includes:

[0011] A MAC - layer processing module, including a MAC transmission module, a MAC reception module, a CRC processing module, and a data shunt module, which is used to implement the unpacking and framing of MAC - layer data frames, CRC check processing, and data shunt output;

[0012] An ARP - layer processing module, including an ARP transmission module, an ARP reception module, and an ARP cache table, which is used to implement the unpacking and framing of ARP - layer data frames, the query and update of the ARP cache table;

[0013] An IP - layer processing module, including an IP transmission module and an IP reception module, which is used to implement the unpacking and framing of IP - layer data frames and the calculation of checksum;

[0014] A UDP - layer processing module, including a UDP transmission module and a UDP reception module, which is used to implement the unpacking and framing of UDP - layer data frames;

[0015] An ICMP - layer processing module, including an ICMP transmission module and an ICMP reception module, which is used to implement the unpacking and framing of ICMP - layer data frames;

[0016] A fixed - priority arbitration module, which is used for data arbitration processing when multiple protocols are sent simultaneously.

[0017] The processing module compatible with three - speed Ethernet includes:

[0018] A data caching module, which is used to cache data between the GMII and RGMII interfaces across clock domains;

[0019] A three - speed Ethernet control module, which is used to obtain the connection status and communication rate of the PHY chip, control the timing of three - speed Ethernet data reception and transmission, and manage the routing of clock resources.

[0020] A data receiving method for a general three-speed Ethernet controller IP core based on domestic FPGA, comprising the following steps:

[0021] S1 The three-speed Ethernet control module uses the RGMII interface to convert the data transmitted by the PHY chip from the format of transmitting 4-bit data at both the rising and falling edges of the clock to the format of transmitting 8-bit data at the rising edge of the clock through IDDR, and transmits it to the data buffer module; during the frame gap, the connection status and communication rate of the PHY chip are obtained through the In-Band Status of the RGMII and passed to the data buffer module;

[0022] S2 The data buffer module uses true dual-port RAM and asynchronous FIFO to cross the clock domain and transfer the 8-bit wide data in the PHY input clock domain transmitted by the three-speed Ethernet control module to the UDP protocol stack module;

[0023] S3 The MAC receiving module uses pipeline processing to first check the MAC frame header and the destination MAC of the data transmitted by the data buffer module, then perform CRC verification, and then transfer the verification result and the data stream to the CRC processing module;

[0024] S4 The CRC processing module processes the data transmitted by the MAC receiving module through true dual-port RAM and synchronous FIFO; when the CRC verification is correct, the data is output to the data shunt module; when the CRC verification is incorrect, the length of the current frame error data packet is recorded, and the current address of the RAM is subtracted by the length of the error frame, so that the next frame of data starts to be written from the RAM address after subtracting the length of the error frame;

[0025] S5 The data shunt module shunts and outputs according to the data type received by the CRC processing module; if the data type is IP data, the data is output to the IP receiving module; if the data type is ARP data, the data is output to the ARP receiving module;

[0026] S6 If the current data type is ARP data, the ARP receiving module unpacks the data transmitted by the data shunt module and determines whether it is an ARP request or an ARP reply; if it is an ARP request and the requested address is the IP of the FPGA, the ARP reply signal is sent to the ARP sending module to let it send an ARP reply message; if it is an ARP reply, the IP and the corresponding MAC in the message are output to the ARP cache table to update the ARP cache table; if the current data is IP data, the IP receiving module unpacks the data transmitted by the data shunt module and determines whether it is a UDP packet or an ICMP packet; if it is a UDP packet, the data is passed to the UDP receiving module, and if it is an ICMP packet, the data is passed to the ICMP receiving module;

[0027] If the current data is a UDP packet, the UDP receiving module unpacks the data transmitted by the IP receiving module and then transmits the unpacked data to the user through the user interface; if the current data is an ICMP packet, the ICMP receiving module unpacks the data transmitted by the IP receiving module and then transmits the ICMP reply signal to the ICMP sending module to send an ICMP reply packet to complete the data reception.

[0028] A data sending method for a general three-speed Ethernet controller IP core based on a domestic FPGA includes the following steps:

[0029] S1 First, the user obtains the successful connection signal of the FPGA and the PHY chip through the data receiving part, then waits for 100 clock cycles to send an active ARP to the target device through the ARP sending module, stores the obtained MAC address of the target in the ARP cache table, and then raises the data ready to send valid signal to the UDP sending module;

[0030] S2 After the UDP sending module obtains the data ready to send valid signal, it frames the data sent by the user according to the UDP frame format and then sends the framed data to the fixed priority arbitration module A;

[0031] S3 The fixed priority arbitration module A is set so that the priority of port A is higher than that of port B. If the data type of port A is a UDP packet at this time, the UDP packet is first passed to the IP sending module; if the data type of port A is an ICMP packet at this time, the ICMP packet is first passed to the IP sending module;

[0032] S4 The IP sending module packs the data transmitted by the fixed priority arbitration module A according to the IP data frame format and calculates the IP header checksum. At the same time of packing, it queries the MAC address corresponding to the destination IP in the ARP cache table, and then passes the data packet to the fixed priority arbitration module B and passes the destination MAC address to the MAC sending module;

[0033] S5 The fixed priority arbitration module B is set so that the priority of port A is higher than that of port B. If the data type of port A is an ARP packet at this time, the ARP packet is first passed to the MAC sending module; if the data type of port A is an IP packet at this time, the IP packet is first passed to the MAC sending module;

[0034] S6 The MAC sending module packs the data according to the MAC frame format and performs CRC check based on the destination MAC and the data transmitted by the fixed priority arbitration module B, and then passes the data to the data cache module through the GMII interface;

[0035] The S7 data cache module uses a true dual-port RAM and an asynchronous FIFO to transfer the data sent by the MAC transmission module in the UDP protocol stack clock domain to the data transmission clock domain of the PHY chip across clock domains.

[0036] The S8 three-speed Ethernet control module converts the data format of transmitting 8 bits at the rising edge of the clock into the format of transmitting 4 bits at both the rising and falling edges of the clock through ODDR, and then outputs it to the PHY chip to complete the data transmission.

[0037] The beneficial effects of the present invention are:

[0038] The present invention has established a relatively complete UDP protocol stack, designed the communication functions of common protocols, ensured the universality and convenience of its transplantation, and at the same time adapted to the three-speed Ethernet, and can be applied to applications with 10M, 100M, and 1000M rate requirements. Description of the Drawings

[0039] Figure 1 is the overall schematic diagram of the general three-speed Ethernet controller IP core of the present invention;

[0040] Figure 2 is the overall architecture schematic diagram of the MAC layer of the present invention;

[0041] Figure 3 is the timing schematic diagram of processing data in a pipeline of the present invention;

[0042] Figure 4 is the overall framework schematic diagram of the ARP layer of the present invention;

[0043] Figure 5 is the schematic diagram of the ARP table processing flow of the present invention;

[0044] Figure 6 is the ODDR data transmission timing schematic diagram. Detailed Embodiments

[0045] The following further elaborates on the present invention in conjunction with the drawings.

[0046] A general three-speed Ethernet controller IP core based on a domestic FPGA has an architecture as Figure 1As shown in the figure, it includes: a UDP protocol stack module compatible with multi-protocol processing and a processing module compatible with tri-speed Ethernet. The UDP protocol stack module compatible with multi-protocol processing includes: a MAC layer processing module for realizing the functions of unpacking and framing MAC layer data frames, CRC check processing, and data shunt output; an ARP layer processing module for realizing the functions of unpacking and framing ARP layer data frames, querying and updating the ARP cache table; an IP layer processing module for realizing the functions of unpacking and framing IP layer data frames and checksum calculation; a UDP layer processing module for realizing the unpacking and framing of UDP layer data frames; an ICMP layer processing module for realizing the unpacking and framing of ICMP layer data frames; a fixed-priority arbitration module for realizing the function of data arbitration processing when multiple protocols are sent simultaneously. The processing module compatible with tri-speed Ethernet includes: a data cache module for caching data between GMII and RGMII interfaces across clock domains to prevent packet loss; a tri-speed Ethernet control module for obtaining the connection status and communication rate of the PHY chip, controlling the timing of tri-speed Ethernet data reception and transmission, and managing the routing of clock resources.

[0047] Both the UDP protocol stack module compatible with multi-protocol processing and the processing module compatible with tri-speed Ethernet are implemented in the eLinx3.0 development environment of Suzhou Zhongke Yihai Microelectronics Co., Ltd.

[0048] A general tri-speed Ethernet controller IP core based on domestic FPGA. For the data reception part, it includes the following steps:

[0049] S1 The tri-speed Ethernet control module converts the data transmitted by the PHY chip through the RGMII interface from the form of transmitting 4-bit data at both the rising and falling edges of the clock to the form of transmitting 8-bit data at the rising edge of the clock through IDDR, and transmits it to the data cache module; during the frame gap, the connection status and communication rate of the PHY chip are obtained through the In-Band Status of the RGMII and passed to the data cache module;

[0050] S2 The data cache module uses true dual-port RAM and asynchronous FIFO to transfer the 8-bit wide data in the PHY input clock domain passed by the tri-speed Ethernet control module across the clock domain to the UDP protocol stack;

[0051] S3 The MAC receiving module uses pipeline processing to first check the MAC frame header and the destination MAC of the data passed by the data cache module, then perform CRC check, and then pass the check result and the data stream to the CRC processing module;

[0052] The S4 CRC processing module processes the data transmitted by the MAC receiving module through a true dual-port RAM and a synchronous FIFO. When the CRC check is correct, the data is output to the data shunting module; when the CRC check is incorrect, the length of this frame of error data packet is recorded, and the current address of the RAM is subtracted by the length of the error frame, so that the next frame of data is written starting from the RAM address after subtracting the length of the error frame;

[0053] The S5 data shunting module shunts and outputs according to the data type received by the CRC processing module. If the data type is 16’h0800, the data is output to the IP receiving module; if the data type is 16’h0806, the data is output to the ARP receiving module;

[0054] If the current data type is ARP data, the ARP receiving module unpacks the data transmitted by the data shunting module and determines whether it is an ARP request or an ARP reply. If it is an ARP request and the requested address is the IP of the FPGA, the ARP reply signal is sent to the ARP sending module to let it send an ARP reply message. If it is a reply message, the IP and the corresponding MAC in the message are output to the ARP cache table to update the ARP cache table; if the current data is IP data, the IP receiving module unpacks the data transmitted by the data shunting module and determines whether it is a UDP packet or an ICMP packet. If it is a UDP packet, the data is passed to the UDP receiving module, and if it is an ICMP packet, the data is passed to the ICMP receiving module;

[0055] If the current data is a UDP packet, the UDP receiving module unpacks the data transmitted by the IP receiving module and then transmits the unpacked data to the user through the user interface; if the current data is an ICMP packet, the ICMP receiving module unpacks the data transmitted by the IP receiving module and then passes the ICMP reply signal to the ICMP sending module to let it send an ICMP reply message, thus completing the data reception.

[0056] A general three-speed Ethernet controller IP core based on domestic FPGA, for the data sending part, includes the following steps:

[0057] S1 First, the user obtains the successful connection signal between the FPGA and the PHY chip through the data receiving part, then waits for 100 clock cycles to send an active ARP to the target device through the ARP sending module, stores the obtained MAC address of the target in the ARP cache table, and then raises the data ready to send valid signal to the UDP sending module

[0058] After the S2 UDP sending module obtains the valid signal for data transmission, it frames the data sent by the user according to the UDP frame format, and then sends the framed data to the fixed-priority arbitration module A;

[0059] S3 The fixed-priority arbitration module A is set such that the priority of port A is higher than that of port B. If the data type at port A is a UDP packet at this time, the UDP packet is first passed to the IP sending module. If the data type at port A is an ICMP packet at this time, the ICMP packet is first passed to the IP sending module;

[0060] S4 The IP sending module packets the data received from the fixed-priority arbitration module A according to the IP data frame format and calculates the IP header checksum. At the same time of packetizing, it queries the MAC address corresponding to the destination IP in the ARP cache table, and then passes the data packet and the destination MAC address to the fixed-priority arbitration module B;

[0061] S5 The fixed-priority arbitration module B is set such that the priority of port A is higher than that of port B. If the data type at port A is an ARP packet at this time, the ARP packet is first passed to the MAC sending module. If the data type at port A is an IP packet at this time, the IP packet is first passed to the MAC sending module;

[0062] S6 The MAC sending module packets the data according to the destination MAC and the data received from the fixed-priority arbitration module B in the MAC frame format and performs CRC check, and then passes the data to the data cache module through the GMII interface;

[0063] S7 The data cache module uses true dual-port RAM and asynchronous FIFO to cross the clock domain and pass the data sent by the MAC sending module in the UDP protocol stack clock domain to the data sending clock domain of the PHY chip;

[0064] S8 The three-speed Ethernet control module converts the data format of transmitting 8-bit data on the rising edge of the clock into the format of transmitting 4-bit data on both the rising and falling edges of the clock through ODDR and the data sending control module, and then outputs it to the PHY chip, thus completing the data transmission.

[0065] Embodiment

[0066] In the described general three-speed Ethernet controller IP core based on domestic FPGA, the architecture diagram of the MAC layer processing module in the UDP protocol stack module that is compatible with multi-protocol processing is as Figure 2As shown in the figure, it includes a MAC transmission module and a MAC reception module. The MAC transmission module includes a CRC check module, and the MAC reception module includes a CRC check module, a CRC processing module, and a data shunt module. For the MAC transmission module, first, the Preamble field in the MAC frame header is checked. When 7 8’h55 (or 6 8’h55) and 1 8’hD5 are correctly obtained, the r_header_access signal is pulled high, indicating that the MAC header check is correct. Then, the destination MAC address is checked. When the destination MAC sent by the PC is equal to the FPGA local MAC or the broadcast MAC (FF-FF-FF-FF-FF-FF) is sent, the r_rec_mac_access signal is pulled high, indicating that the destination MAC check is correct. When both of these signals are valid and the counter counts to 21, the data valid signal is pulled high, indicating that the data received from this moment is valid data. The data valid signal is pulled low at the falling edge of i_GMII_valid, indicating that the valid data ends here. For the MAC transmission module, a FIFO is added at its data input end to buffer the data stream that arrives during frame assembly, so as to realize that when the MAC header is assembled, the data is taken out from the FIFO and connected behind the assembled MAC header. Since the assembled MAC header includes 7 bytes of 8’h55, 1 byte of 8’hD5, 6 bytes of destination MAC address, 6 bytes of source MAC address, and 2 bytes of data type, at least 22 clock cycles of data need to be buffered, that is, the depth of the FIFO is at least 22. However, when the FIFO is normally used, the power of 2 is generally taken, so a synchronous FIFO with a depth of 64 and a width of 8 bits is selected for this module. In addition to buffering data with the FIFO, a ro_udp_ready handshake signal is also set in this module to prompt the upper-layer module to send data only every 12 cycles to meet the frame interval requirements of the standard Ethernet. The MAC reception module uses pipeline technology to perform CRC data verification, and its timing is as Figure 3 shown, and the received data stream is pipelined for five beats to realize the CRC calculation and verification functions.

[0067] The ARP layer processing module described above has an architecture as Figure 4 shown. The ARP layer processing module includes an ARP reception module, an ARP table cache module, and an ARP transmission module. The ARP table cache module mainly includes a state machine module for managing the update storage and query output of MAC and IP. In addition, the ARP reception module is mainly used to process the unpacking of data frames, and the ARP transmission module is mainly used to assemble data frames. The specific execution process of ARP table processing is as Figure 5As shown in the figure, first, the system will query the connection status between the PC and the FPGA. If a connection is established, it will first execute the operation shown as label ① in the flowchart, that is, send a request broadcast ARP after an interval of 100 clock cycles to obtain the ARP response packet of the other party, and then store the IP address and MAC address in the ARP response packet in the RAM, thus configuring the mapping relationship between the IP address and the MAC address; there is no priority in the execution order of label ② and label ③ in the flowchart. When an ARP request packet is sent by the other party, this module will update the IP address and MAC address in the other party's request packet in the RAM (10 IP and MAC data can be cached in the RAM); when the subsequent FPGA wants to send a data packet to a specified IP host, it will query the MAC corresponding to the IP from the ARP table cache module for frame assembly. For the ARP receiving module, according to the data valid signal transmitted by the MAC receiving module, the counter is incremented, and then according to the frame structure of ARP, when counting to the specific frame field, the destination MAC address and destination IP address sent by the PC are extracted and then stored in the ARP table cache module. If the value of the received operation field is 1, that is, an ARP request signal, the response valid signal is pulled high to send an ARP response packet. For the ARP table cache module, this module designs a state machine to find the corresponding MAC address from the ARP table when sending an IP packet. The specific states include the idle state P_ST_IDLE, the query state P_ST_SEEK, the pre-update query state P_ST_UPDATE_S, the update state P_ST_UPDATE, and the MAC output state P_ST_MAC. The default is the idle state. When detecting the rising edge of the query valid signal, it jumps to the query state; when finding a value equal to the currently received IP in the RAM storing IP, the corresponding MAC address is taken out and passed to the MAC sending module. If a value equal to the currently received IP cannot be found in the RAM storing IP, the sent MAC address is the broadcast MAC. For the ARP sending module, if it is an active ARP, it will be sent after obtaining the signal that the connection of the PHY register is successful; if it is a response packet, it will frame the ARP packet according to the value of the counter according to the frame structure of ARP, and then send it to the fixed-priority arbitration module B.

[0068] The described three-speed Ethernet control module has the following data transmission timing as Figure 6As shown in the figure, the left diagram shows the data transmission timing at gigabit speed. Since the RGMII interface is adopted and there are only four data lines for TXD, data needs to be transmitted simultaneously at the rising edge and falling edge of the 125MHz clock to meet the network speed requirement of 125×4×2 = 1000MHz. As shown by label ① in the figure, data is sampled at the rising edge of the output clock o_txc and output at the moment of label ②. Then, data is sampled at the falling edge of the clock, i.e., at label ③, and output at label ④. In this way, an 8-bit signal can be output within one clock cycle. The right diagram shows the data transmission timing at 10M and 100M speeds. At 10M speed, the clock is 2.5MHz and there are also four TXD data lines. To meet the network speed requirement of 2.5×4 = 10MHz, 4-bit data needs to be output within one clock cycle, that is, an 8-bit data needs to be output within two clock cycles. To achieve this function, this design processes the data output in the data cache module to output one data from the RAM cache every two clocks. As shown in the right diagram, at label ①, the lower four bits of data data1 are sampled at the rising edge of the clock o_txc and then the data is output. Then, at the position of label ③, the upper four bits of data1 are sampled and the data is output. In this way, the requirement for the 10M data transmission rate is achieved. The principle is the same for 100M speed.

[0069] Experiments show that for the general three-speed Ethernet controller IP based on domestic FPGA of the present invention, its resource occupancy is relatively small, which is sufficient for subsequent expansion into a multi-network port controller to implement the network card function. And its power consumption is only 0.209W, which can meet the power consumption requirements of embedded devices in civil air defense environments. Through simulation verification, the Ethernet controller of the present invention can be normally used for multi-protocol communication, can meet the actual communication requirements in the Internet of Things, and provides certain reference significance for subsequent transplantation to other domestic FPGAs.

[0070] The above is the preferred implementation mode of the present invention. It should be pointed out that for those of ordinary skill in the art in this technical field, without departing from the principle described in the present invention, several improvements and refinements can still be made, and these improvements and refinements should be regarded as the protection scope of the present invention.

Claims

1. A general three-speed Ethernet controller IP core based on domestic FPGA, characterized in that, it includes: A UDP protocol stack module compatible with multi-protocol processing, which is used to process the unpacking and framing of data packets at the MAC layer, ARP layer, IP layer, UDP layer and ICMP layer, and to implement data arbitration processing when multiple protocols are sent simultaneously; A processing module compatible with three-speed Ethernet, which is used to implement the adaptation between the UDP protocol stack module and the RGMII interface, the three-speed Ethernet timing control, and the caching of data when switching network speeds.

2. The general three-speed Ethernet controller IP core based on domestic FPGA according to claim 1, characterized in that, both the UDP protocol stack module compatible with multi-protocol processing and the processing module compatible with three-speed Ethernet are implemented in the eLinx3.0 development environment.

3. The general three-speed Ethernet controller IP core based on domestic FPGA according to claim 1, characterized in that, the UDP protocol stack module compatible with multi-protocol processing includes: A MAC layer processing module, including a MAC sending module, a MAC receiving module, a CRC processing module and a data shunting module, which is used to implement the unpacking and framing of MAC layer data frames, CRC check processing, and data shunting output; An ARP layer processing module, including an ARP sending module, an ARP receiving module and an ARP cache table, which is used to implement the unpacking and framing of ARP layer data frames, the query and update of the ARP cache table; An IP layer processing module, including an IP sending module and an IP receiving module, which is used to implement the unpacking and framing of IP layer data frames and the checksum calculation; A UDP layer processing module, including a UDP sending module and a UDP receiving module, which is used to implement the unpacking and framing of UDP layer data frames; An ICMP layer processing module, including an ICMP sending module and an ICMP receiving module, which is used to implement the unpacking and framing of ICMP layer data frames; A fixed-priority arbitration module, which is used for data arbitration processing when multiple protocols are sent simultaneously.

4. The general three-speed Ethernet controller IP core based on domestic FPGA according to claim 1, characterized in that, the processing module compatible with three-speed Ethernet includes: A data caching module, which is used to cache data between the GMII and RGMII interfaces across clock domains; A three-speed Ethernet control module, which is used to obtain the connection status and communication rate of the PHY chip, control the timing of three-speed Ethernet data reception and transmission, and manage the routing of clock resources.

5. A data reception method for a general three-speed Ethernet controller IP core based on domestic FPGA, characterized in that, it includes the following steps: S1 The three-speed Ethernet control module converts the data transmitted from the PHY chip through the RGMII interface from the format of transmitting 4-bit data at each of the clock rising and falling edges to the format of transmitting 8-bit data at the clock rising edge through the IDDR, and transmits it to the data caching module; during the frame gap period, the connection status and communication rate of the PHY chip are obtained through the In-Band Status of the RGMII and passed to the data caching module; The S2 data cache module uses a true dual-port RAM and an asynchronous FIFO to transfer the 8-bit wide data in the PHY input clock domain passed by the three-speed Ethernet control module to the UDP protocol stack module across clock domains. The S3 MAC receiving module uses pipeline processing to first verify the MAC frame header and the destination MAC of the data passed by the data cache module, then perform CRC verification, and then transfer the verification result and the data stream to the CRC processing module. The S4 CRC processing module processes the data passed by the MAC receiving module through a true dual-port RAM and a synchronous FIFO. When the CRC verification is correct, the data is output to the data shunt module. When the CRC verification is incorrect, record the length of the current frame error data packet, subtract the length of the error frame from the current address of the RAM, and let the next frame of data be written starting from the RAM address after subtracting the length of the error frame. The S5 data shunt module performs shunt output according to the data type received by the CRC processing module; if the data type is IP data, the data is output to the IP receiving module; if the data type is ARP data, the data is output to the ARP receiving module. If the current data type is ARP data, the ARP receiving module unpacks the data passed by the data shunt module and determines whether it is an ARP request or an ARP reply; if it is an ARP request and the requested address is the IP of the FPGA, send the ARP reply signal to the ARP sending module to let it send an ARP reply message. If it is an ARP reply, output the IP and the corresponding MAC in the message to the ARP cache table to update the ARP cache table; if the current data is IP data, the IP receiving module unpacks the data passed by the data shunt module and determines whether it is a UDP packet or an ICMP packet. If it is a UDP packet, transfer the data to the UDP receiving module; if it is an ICMP packet, transfer the data to the ICMP receiving module. If the current data is a UDP packet, the UDP receiving module unpacks the data passed by the IP receiving module and then transfers the unpacked data to the user through the user interface; if the current data is an ICMP packet, the ICMP receiving module unpacks the data passed by the IP receiving module and then transfers the ICMP reply signal to the ICMP sending module to let it send an ICMP reply message to complete the data reception.

6. A data sending method for a general three-speed Ethernet controller IP core based on a domestic FPGA, characterized in that, it includes the following steps: S1 First, the user obtains the signal indicating successful connection between the FPGA and the PHY chip through the data receiving part, then waits for 100 clock cycles to send an active ARP to the target device through the ARP sending module, stores the obtained MAC address of the target in the ARP cache table, and then raises the data ready to send valid signal to the UDP sending module. After the S2 UDP sending module obtains the valid signal for data sending preparation, it frames the data sent by the user in the UDP frame format and then sends the framed data to the fixed-priority arbitration module A; S3 The fixed-priority arbitration module A is set such that the priority of port A is higher than that of port B. If the data type at port A is a UDP packet at this time, the UDP packet is first passed to the IP sending module. If the data type at port A is an ICMP packet at this time, the ICMP packet is first passed to the IP sending module; S4 The IP sending module packets the data received from the fixed-priority arbitration module A in the IP data frame format and calculates the IP header checksum. At the same time as packetizing, it queries the MAC address corresponding to the destination IP in the ARP cache table, and then passes the data packet to the fixed-priority arbitration module B and the destination MAC address to the MAC sending module; S5 The fixed-priority arbitration module B is set such that the priority of port A is higher than that of port B. If the data type at port A is an ARP packet at this time, the ARP packet is first passed to the MAC sending module. If the data type at port A is an IP packet at this time, the IP packet is first passed to the MAC sending module; S6 The MAC sending module packets the data according to the destination MAC and the data received from the fixed-priority arbitration module B in the MAC frame format and performs CRC check, and then passes the data to the data cache module through the GMII interface; S7 The data cache module uses true dual-port RAM and asynchronous FIFO to cross the clock domain and passes the data sent by the MAC sending module in the UDP protocol stack clock domain to the data sending clock domain of the PHY chip; S8 The three-speed Ethernet control module converts the data format of transmitting 8 bits on the rising edge of the clock to the format of transmitting 4 bits on each of the rising and falling edges of the clock through ODDR, and then outputs it to the PHY chip to complete the data sending.

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