Semiconductor device and manufacturing method thereof

Abstract

A semiconductor device capable of improving power distribution efficiency and a method of manufacturing the same are disclosed. The semiconductor device includes: a first substrate; a memory cell array including memory cells vertically stacked over the first substrate; a second substrate including a front surface facing the memory cell array and a back surface at a higher level than the front surface, and including a plurality of control circuits; and a backside power distribution network including power supply interconnects penetrating the second substrate and powering the control circuitry from a backside of the second substrate.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10 - 2023 - 0171285, filed on November 30, 2023, and Korean Patent Application No. 10 - 2024 - 0171665, filed on November 27, 2024, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical field

[0003] Exemplary embodiments of the present invention relate to a semiconductor device, and more particularly, to a semiconductor device including a back - side power distribution network (BSPDN) and a method of manufacturing the same. Background art

[0004] Recently, in order to meet the demand for large capacity and fine patterning of memory devices, technologies for providing three - dimensional (3D) memory devices in which multiple memory cells are stacked are being proposed. Summary of the invention

[0005] Embodiments of the present invention relate to a semiconductor device capable of improving power distribution efficiency and a method of manufacturing the semiconductor device.

[0006] According to an embodiment of the present invention, a semiconductor device includes: a first substrate; a memory cell array including memory cells vertically stacked on the first substrate; a second substrate including a front surface facing the memory cell array and a back surface at a higher level than the front surface, and including a plurality of control circuits; and a back - side power distribution network including power interconnections that penetrate the second substrate and supply power to the control circuits from the back surface of the second substrate.

[0007] According to another embodiment of the present invention, a method of manufacturing a semiconductor device includes: forming a memory cell array on a first substrate; forming an array - side interconnect structure coupled to the memory cell array; forming a plurality of control circuits on a front surface of a second substrate including a back surface and a front surface, and an embedded power interconnect partially buried from the front surface into the second substrate and coupled to the control circuits; forming a front - side interconnect structure coupled to the embedded power interconnect; flipping the second substrate after forming the front - side interconnect structure; forming a back - side interconnect structure extending downward from the back surface of the flipped second substrate and coupled to the embedded power interconnect; and performing a bonding process to electrically connect the memory cell array and the control circuits to each other. Brief description of the drawings

[0008] Figure 1 is a schematic cross - sectional view showing a semiconductor device according to an embodiment of the present invention.

[0009] Figure 2is a schematic cross-sectional view showing a semiconductor device according to another embodiment of the present invention.

[0010] Figure 3 is a schematic cross-sectional view showing a semiconductor device according to a comparative example.

[0011] Figure 4 is a schematic cross-sectional view showing a semiconductor device according to another embodiment of the present invention.

[0012] Figure 5A is showing Figure 4 a schematic perspective view of a three-dimensional array of memory cells shown in

[0013] Figure 5B is showing Figure 4 a schematic perspective view of a memory cell shown in

[0014] Figure 5C is showing Figure 4 a schematic cross-sectional view of a memory cell shown in

[0015] Figure 5D is showing Figure 5B and Figure 5C a schematic plan view of a switching element shown in

[0016] Figures 6 to 8 is a side view showing a memory cell array according to other embodiments of the present invention.

[0017] Figure 9 is showing another semiconductor device according to another embodiment of the present invention.

[0018] Figure 10 and Figure 11 shows an example of a direct power supply interconnection according to another embodiment of the present invention.

[0019] Figures 12 to 23 shows a method for manufacturing Figure 4 the semiconductor device shown in

[0020] Figure 24 is a schematic cross-sectional view showing a semiconductor device according to another embodiment of the present invention. Detailed Description

[0021] Exemplary embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. However, the present invention can be implemented in different forms and should not be construed as limited to the embodiments described herein. On the contrary, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. Throughout the disclosure, the same reference numerals refer to the same components in multiple figures and embodiments of the present invention.

[0022] In the following, various embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0023] The accompanying drawings are not necessarily drawn to scale, and in some cases, the scale may be exaggerated to clearly illustrate the features of the embodiments. When a first layer is referred to as being "on a second layer" or "on" a substrate, it refers not only to the case where the first layer is directly formed on the second layer or the substrate, but also to the case where a third layer exists between the first layer and the second layer or the substrate.

[0024] The following embodiments of the present disclosure relate to a three-dimensional (3D) memory cell structure, which can increase the memory cell density and reduce the parasitic capacitance by vertically stacking memory cells.

[0025] The following embodiments of the present disclosure may propose a backside power distribution network (BSPDN), which can be used in a three-dimensional integrated circuit in which a memory cell array and a peripheral circuit are bonded by a wafer bonding process.

[0026] Figure 1 is a schematic cross-sectional view showing a semiconductor device 100 according to an embodiment of the present invention.

[0027] Referring to Figure 1 , the semiconductor device 100 may include: a substrate WF, the substrate WF including an isolation layer ISO between control circuits CL; metal contact plugs M1C and metal lines MT1, which are coupled to the control circuits CL; and a direct power interconnect DPI, which is coupled to the control circuits CL through the metal lines MT1.

[0028] The direct power interconnect DPI may include a buried power rail BPR buried in the substrate WF, a buried power rail via VBPR coupled to a first surface of the buried power rail BPR, a post-power via PM1C coupled to a second surface of the buried power rail BPR, a post-power metal line PM1 coupled to the post-power via PM1C, and a post-multilayer metal line PMLM coupled to the post-power metal line PM1. The buried power rail BPR and the buried power rail via VBPR may be referred to as a buried power interconnect.

[0029] The substrate WF may include a front surface FS and a back surface BS. The substrate WF may be flipped over by wafer flip-chip, such that the back surface BS is at a higher level than the front surface FS. Thus, the front surface FS of the substrate WF may refer to the surface facing the metal lines MT1, and the back surface BS of the substrate WF may refer to the surface facing the post-power metal line PM1. The lower-level surface of the substrate WF may refer to the front surface FS.

[0030] The isolation layer ISO may be formed in the substrate WF, and the isolation layer ISO may be located between the control circuits CL.

[0031] The first surface of the embedded power rail BPR can be electrically connected to the metal contact plug M1C and the metal line MT1, and the second surface of the embedded power rail BPR can be electrically connected to the post-power via PM1C and the post-power metal line PM1.

[0032] The post-multilayer metal line PMLM can include a plurality of post-metal lines TMT and RDA, and a plurality of post-vias TMC and RDV. The post-power via PM1C and the post-power metal line PM1 can be electrically connected to the post-multilayer metal line PMLM. According to another embodiment of the present disclosure, the post-power via PM1C and the post-power metal line PM1 can be part of the post-multilayer metal line PMLM. In other words, the post-power via PM1C and the post-power metal line PM1 can be formed when the post-multilayer metal line PMLM is formed.

[0033] The post-interlayer dielectric layer PILD can be formed on the back surface BS of the substrate WF. The post-interlayer dielectric layer PILD can be disposed between the back surface BS of the substrate WF and the post-power metal line PM1. The post-power via PM1C can extend through the post-interlayer dielectric layer PILD and the substrate WF into the isolation layer ISO.

[0034] The post-power via PM1C can have a low aspect ratio. The post-power via PM1C can be referred to as a 'nano-through-silicon via NTSV'. The embedded power rail via VBPR can be referred to as a via that lands on the embedded power rail BPR, i.e., a 'Via-to-BPR' VBPR.

[0035] The embedded power rail via VBPR can extend from the front surface FS of the substrate WF into the isolation layer ISO. The embedded power rail BPR can extend from the front surface FS of the substrate WF through the isolation layer ISO into the interior of the substrate WF. The embedded power rail BPR can have a form embedded inside the substrate WF. The vertical structures of the post-power via PM1C, the embedded power rail BPR, and the embedded power rail via VBPR can be structures that penetrate the post-interlayer dielectric layer PILD, the substrate WF, and the isolation layer ISO.

[0036] Dielectric spacers (not shown) can be disposed on the outer walls of the post-power via PM1C and the embedded power rail BPR, so that the post-power via PM1C and the embedded power rail BPR can be electrically isolated from the substrate WF.

[0037] The metal line MT1 and the metal contact plug M1C can be coupled to the control circuit CL. The metal line MT1 and the metal contact plug M1C can provide a path for transmitting power to the control circuit CL. The metal line MT1 and the metal contact plug M1C can be part of a multilayer metal line. The metal line MT1 can be spaced apart from the front surface FS of the substrate WF.

[0038] The embedded power rail via VBPR can be coupled to the metal trace MT1 and the metal contact plug M1C. The metal contact plug M1C and the embedded power rail via VBPR can be disposed at the same level. The control circuit CL can be electrically connected to the backside multi-layer metal line PMLM through the metal contact plug M1C, the metal trace MT1, the embedded power rail via VBPR, the embedded power rail BPR, the backside power via PM1C, and the backside power trace PM1.

[0039] The direct power interconnect DPI can be used to directly transfer power from the backside BS of the substrate WF. In other words, the combination of the backside multi-layer metal line PMLM and the direct power interconnect DPI can be referred to as a backside power distribution network (BSPDN) for transferring power to the control circuit CL.

[0040] As described above, the semiconductor device 100 can include the metal trace MT1 disposed at a level lower than the control circuit CL, the backside multi-layer metal line PMLM disposed at a level higher than the control circuit CL, and the direct power interconnect DPI that penetrates the substrate WF to be coupled to the control circuit CL through the metal trace MT1 and the metal contact plug M1C.

[0041] In the semiconductor device 100, the direct power interconnect DPI can directly supply power to the control circuit CL by penetrating the substrate WF via the metal trace MT1 and the metal contact plug M1C. Since the direct power interconnect DPI penetrates the thin substrate WF, the path (see reference numeral 'PW') for transferring power to the control circuit CL becomes shorter. The power transfer path PW can include the backside multi-layer metal line PMLM, the backside power trace PM1, the backside power via PM1C, the embedded power rail BPR, the embedded power rail via VBPR, the metal trace MT1, and the metal contact plug M1C.

[0042] As described above, the method of supplying power to the control circuit CL in the semiconductor device 100 can be a top-down power supply from the backside multi-layer metal line PMLM to the control circuit CL.

[0043] Figure 2 FIG. is a schematic cross-sectional view showing a semiconductor device 200 according to another embodiment of the present invention.

[0044] See Figure 2 , the semiconductor device 200 can include a first semiconductor device 110, a second semiconductor device 120, a bonding structure 130 between the first semiconductor device 110 and the second semiconductor device 120, and a direct power interconnect DPI coupled to the second semiconductor device 120. Hereinafter, a detailed description of the direct power interconnect DPI can refer to Figure 1 .

[0045] The first semiconductor device 110 may include a first substrate W10, an array AR, and a front multi-layer metal line FMLM. The array AR may be disposed on the first substrate W10, and the front multi-layer metal line FMLM may be disposed on the array AR. The array AR may include a transistor array, a capacitor array, a memory cell array, or a combination thereof. The memory cell array may include a three-dimensional array of memory cells. The memory cell array may include a buried-gate-based dynamic random access memory (DRAM), a three-dimensional (3D) DRAM, 3D NAND, flash memory, spin torque transfer random access memory (STTRAM), resistive random access memory (RRAM), magnetic random access memory (MRAM), thyristor, a vertical-gate-based DRAM, etc. The front multi-layer metal line FMLM may include a plurality of front metal lines and a plurality of front vias. The front multi-layer metal line FMLM may be referred to as an array-side interconnect structure.

[0046] The second semiconductor device 120 may include a second substrate W20 having a front side FS and a back side BS, a plurality of control circuits CL disposed on the front side FS of the second substrate W20, and a multi-layer metal line MLM coupled to the control circuits CL. The back side BS of the second substrate W20 may be disposed at a level higher than the front side FS. The second substrate W20 may be flipped over by wafer flip-chip so that the back side BS is disposed at a level higher than the front side FS. The multi-layer metal line MLM may include a plurality of metal lines and a plurality of vias. The multi-layer metal line MLM may include at least one metal line MT1 and a metal contact plug M1C. The metal line MT1 and the metal contact plug M1C may be coupled to the control circuits CL, respectively. The metal line MT1 and the metal contact plug M1C may be metal lines and metal contacts for transmitting power. A plurality of isolation layers ISO may be formed in the second substrate W20, and the isolation layers ISO may be disposed between the control circuits CL. Each control circuit CL may include at least one transistor. The control circuit CL may include a circuit for controlling the array AR of the first semiconductor device 110. Each transistor may include a gate, a gate spacer, and a source / drain. The isolation layer ISO may have a shallow trench isolation (STI) structure.

[0047] The bonding structure 130 may include a first bonding pad CBD coupled to the first semiconductor device 110 and a second bonding pad PBD coupled to the second semiconductor device 120. The wafer bonding structure 130 may further include a first bonding contact plug CBC and a second bonding contact plug PBC. The first bonding contact plug CBC may be coupled to the front multi-layer metal line FMLM and the first bonding pad CBD of the first semiconductor device 110. The second bonding contact plug PBC may be coupled to the multi-layer metal line MLM and the second bonding pad PBD of the second semiconductor device 120. A bonding dielectric layer may be disposed between the first bonding pads CBD of the same layer, and the bonding dielectric layer may be disposed between the second bonding pads PBD of the same layer. The first bonding pad CBD and the second bonding pad PBD may be coupled by direct bonding or hybrid bonding. Direct bonding may refer to the direct bonding of the first bonding pad CBD and the second bonding pad PBD to each other, for example, it may refer to metal-metal bonding. Hybrid bonding may refer to a combination of metal-metal bonding and dielectric-dielectric bonding. Dielectric-dielectric bonding may refer to the bonding of bonding dielectrics. Dielectric-dielectric bonding may include oxide-oxide bonding.

[0048] The direct power interconnect DPI may include a buried power rail BPR buried in the second substrate W20, a buried power rail via VBPR coupled to the first surface of the buried power rail BPR, a post-power via PM1C coupled to the second surface of the buried power rail BPR, a post-power metal line PM1 coupled to the post-power via PM1C, and a post-multi-layer metal line PMLM coupled to the post-power metal line PM1. The first surface of the buried power rail BPR may be electrically connected to the metal contact plug M1C and the metal line MT1 of the multi-layer metal line, and the second surface of the buried power rail BPR may be electrically connected to the post-power via PM1C and the power metal line PM1. The post-multi-layer metal line PMLM may include a plurality of post-metal lines TMT and RDA, and a plurality of post-vias TMC and RDV. The post-power via PM1C and the post-power metal line PM1 may be part of the post-multi-layer metal line PMLM. The post-multi-layer metal line PMLM may have a backside interconnect structure, and the multi-layer metal line MLM may have a frontside interconnect structure.

[0049] The post-interlayer dielectric layer PILD may be formed on the backside BS of the second substrate W20.

[0050] The buried power rail via VBPR can extend from the front surface FS of the second substrate W20 into the interior of the isolation layer ISO. The buried power rail BPR can extend from the front surface FS of the second substrate W20 through the isolation layer ISO into the interior of the second substrate W20. The vertical structures of the post-power via PM1C, the buried power rail BPR, and the buried power rail via VBPR can have a structure that penetrates the post-interlayer dielectric PILD, the second substrate W20, and the isolation layer ISO.

[0051] The buried power rail via VBPR can be coupled to the metal line MT1 and the metal contact plug M1C of the multi-layer metal line MLM. The metal contact plug M1C and the buried power rail via VBPR can be disposed at the same level.

[0052] The direct power interconnect DPI can function to directly transfer power from the back surface BS of the second substrate W20. In other words, the direct power interconnect DPI can be a backside power distribution network (BSPDN) for transferring power to the control circuit CL.

[0053] As described above, the semiconductor device 200 can be a semiconductor device including a first semiconductor device 110, a bonding structure 130, and a second semiconductor device 120 stacked in the described order. The control circuit CL of the second semiconductor device 120 can be coupled to the array AR of the first semiconductor device 110 through the bonding structure 130.

[0054] The semiconductor device 200 can directly supply power to the control circuit CL of the second semiconductor device 120 through the direct power interconnect DPI, the metal line MT1, and the metal contact plug M1C. Therefore, the path (see reference numeral 'PW') for transferring power to the control circuit CL can be shortened. The power transfer path PW can include the post-multi-layer metal line PMLM, the power metal line PM1, the post-power via PM1C, the buried power rail BPR, the buried power rail via VBPR, the metal line MT1, and the metal contact plug M1C.

[0055] As described above, the method of supplying power to the control circuit CL in the semiconductor device 200 can be a top-down power supply from the post-multi-layer metal line PMLM to the control circuit CL.

[0056] The first semiconductor device 110 and the second semiconductor device 120 can be bonded to each other through a wafer bonding process. In other words, the first semiconductor device 110 and the second semiconductor device 120 can be bonded to each other through the bonding structure 130. The bonding structure 130 can improve the integration degree, for example, overcome process limitations and maximize the net die.

[0057] Since a direct power interconnect (DIP) through the second substrate W20 is formed, the power consumption of the semiconductor device 200 can be reduced by about 15% or more when the wafer bonding process is applied. In addition, the current resistance of the semiconductor device 200 can be reduced by about 20% or more.

[0058] Figure 3 is a schematic cross-sectional view showing a semiconductor device 201 according to a comparative example.

[0059] Reference Figure 3 , the semiconductor device 201 according to the comparative example may include a first substrate W10 formed with an array AR and front multi-layer metal lines FMLM, a second substrate W20 formed with a control circuit CL and multi-layer metal lines MLM, bonding structures CBD and PBD between the front multi-layer metal lines FMLM and the multi-layer metal lines MLM, and post multi-layer metal lines PMLM located at a level higher than the first substrate W10. In the semiconductor device 201 of the comparative example, the first substrate W10 formed with the array AR and the front multi-layer metal lines FMLM may be turned over. In other words, the first substrate W10 may be disposed at a level higher than the second substrate W20.

[0060] The semiconductor device 201 of the comparative example may supply power to the control circuit CL through the post multi-layer metal lines PMLM, and through-silicon vias TSVs with a high aspect ratio are required to penetrate the array AR to interconnect the control circuit CL and the post multi-layer metal lines PMLM with each other. Since power is supplied to the control circuit CL through the through-silicon vias TSVs with a high aspect ratio, the bonding structures CBD and PBD, and the plurality of multi-layer metal lines MLM, the power consumption and resistance will increase.

[0061] As described above, the semiconductor device 201 of the comparative example may require a high aspect ratio contact etching (HARC) process for the first substrate W10 and the array AR to form through-silicon vias TSVs with a high aspect ratio that penetrate the array AR. Therefore, an increase in the number of memory cells stacked in the array AR will inevitably increase the production cost and technical difficulty. In addition, since the semiconductor device 201 of the comparative example has a long power transmission path PW1 due to the through-silicon vias TSVs with a high aspect ratio, the power consumption and production cost will increase.

[0062] Figure 4 is a schematic cross-sectional view showing a semiconductor device 300 according to another embodiment of the present invention.

[0063] See Figure 4, the semiconductor device 300 may include a memory cell array MCA, a peripheral circuit PERI, a bonding structure WBD between the memory cell array MCA and the peripheral circuit PERI, and a direct power supply interconnect DPI coupled to the peripheral circuit PERI. Hereinafter, for a detailed description of the direct power supply interconnect DPI, reference may be made to Figure 1 .

[0064] The memory cell array MCA may be disposed on a first substrate W10. The memory cell array MCA may include a three-dimensional array of memory cells MC and front multi-layer metal lines FMLM. The three-dimensional array of memory cells MC may be disposed on the first substrate W10, and the front multi-layer metal lines FMLM may be disposed on the three-dimensional array of memory cells MC. The memory cell array MCA may include a first region R1 and a second region R2. The first region R1 may be a region where the memory cells MC are formed, and the second region R2 may be a region where cell contact plugs coupled to the memory cells MC are formed. The second region R2 may have a stepped structure.

[0065] Each memory cell MC may include a first wire BL, a switching element TR, and a data storage element CAP. The three-dimensional array of memory cells MC may include a column array of memory cells MC and a row array of memory cells MC. The column array of memory cells MC may have a plurality of memory cells MC stacked along a first direction D1, and the row array of memory cells MC may have a plurality of memory cells MC horizontally disposed along a second direction D2 and a third direction D3. The memory cell array MCA may have a mirror image structure in which two memory cells MC share the first wire BL. According to another embodiment of the present invention, the memory cell array MCA may further include a mirror image structure in which two memory cells MC share the data storage element CAP. The multi-layer metal lines MLM may include a plurality of metal lines MT1, MT2, MT3, MT4, and MT5 and a plurality of metal contact plugs M1C, M2C, M3C, M4C, and M5C.

[0066] The memory cell array MCA may include first to third hard mask layers TIL1, TIL2, and TIL3. The upper surfaces of the first wire BL and the common plate PL may be disposed at the same level as the upper surface of the second hard mask layer TIL2. The front multi-layer metal lines FMLM of the memory cell array MCA may include a first front via F1B, a first front metal line FM1, a second front via F2C, and a second front metal line FM2. The first front via F1B may penetrate the third hard mask layer TIL3 to be coupled to the first wire BL and the common plate PL, respectively. The second front metal line FM2 may be coupled to a first bonding contact plug CBC and a first bonding pad CBD.

[0067] In the second region R2 of the memory cell array MCA, each step of the stepped structure may include an upper horizontal line G1, a lower horizontal line G2, and a pad GP located between the upper horizontal line G1 and the lower horizontal line G2. An inter-cell dielectric layer IL may be provided between the steps. The inter-cell dielectric layer IL may include silicon oxide. The inter-cell dielectric layer IL may be referred to as a horizontal inter-cell dielectric layer. Each upper horizontal line G1 of the stepped structure may be coupled to a first front contact plug F1C and a first front metal line FM1. The first front contact plug F1C may be referred to as a cell contact plug. The first front contact plug F1C may penetrate the first to third hard mask layers TIL1, TIL2, and TIL3 and the interlayer dielectric layer ILD.

[0068] A buffer layer BF may be provided on the bottom surface of the first wire BL and the bottom surface of the common plate PL, respectively.

[0069] The peripheral circuit PERI may include at least one control circuit CL, SA, and SWD for driving the memory cell array MCA. At least one control circuit CL, SA, and SWD of the peripheral circuit PERI may include an N-channel transistor, a P-channel transistor, a CMOS circuit, or a combination thereof. At least one control circuit CL, SA, and SWD of the peripheral circuit PERI may include an address decoder circuit, a read circuit, a write circuit, and the like. At least one control circuit CL, SA, and SWD of the peripheral circuit PERI may include a planar channel transistor, a recessed channel transistor, a buried gate transistor, a fin-type channel transistor (FinFET), and the like. The control circuits CL, SA, and SWD may be referred to as peripheral transistors.

[0070] For example, the peripheral circuit PERI may include a common plate control circuit CL, a sub-word line driver SWD, and a sense amplifier SA. The first wire BL of the memory cell array MCA may be coupled to the sense amplifier SA, and the second wire DWL may be coupled to the sub-word line driver SWD. The common plate PL may be coupled to the common plate control circuit CL. Each transistor for the common plate control circuit CL, the sub-word line driver SWD, and the sense amplifier SA may include a gate, a gate spacer, and a source / drain. The isolation layer ISO may be a shallow trench isolation (STI) structure.

[0071] The peripheral circuit PERI can be formed on the second substrate W20, and it can also include multi-layer metal lines MLM coupled to the control circuits CL, SA, and SWD. The multi-layer metal lines MLM can include a plurality of metal lines MT1 to MT5 and a plurality of metal contact plugs M1C to M5C. The multi-layer metal lines MLM can include at least one first-layer metal line MT1 and at least one first-layer metal contact plug M1C. The first-layer metal line MT1 and the first-layer metal contact plug M1C can be coupled to the control circuits CL, SA, and SWD, respectively. A plurality of isolation layers ISO can be formed in the second substrate W20, and the isolation layers ISO can be disposed between the control circuits CL, SA, and SWD. The isolation layers ISO can have a shallow trench isolation (STI) structure.

[0072] The second substrate W20 can include a front side FS and a back side BS, and the back side BS of the second substrate W20 can be disposed at a level higher than the front side FS. The second substrate W20 can be flipped over by wafer flip-chip so that the back side BS is disposed at a level higher than the front side FS. The first-layer metal line MT1 and the first-layer metal contact plug M1C of the multi-layer metal lines MLM can provide a power transmission path PW.

[0073] The bonding structure WBD can include a first bonding pad CBD coupled to the memory cell array MCA and a second bonding pad PBD coupled to the peripheral circuit PERI. The bonding structure WBD can also include a first bonding contact plug CBC and a second bonding contact plug PBC. The first bonding contact plug CBC can be coupled to the front multi-layer metal lines FMLM of the memory cell array MCA and the first bonding pad CBD. The second bonding contact plug PBC can be coupled to the multi-layer metal lines MLM of the peripheral circuit PERI and the second bonding pad PBD. A bonding dielectric layer can be disposed between the first bonding pads CBD at the same level, and the bonding dielectric layer can be disposed between the second bonding pads PBD at the same level. The first bonding pad CBD and the second bonding pad PBD can be coupled by direct bonding or hybrid bonding. Direct bonding can mean that the first bonding pad CBD and the second bonding pad PBD are directly bonded to each other, and it can refer to, for example, metal-metal bonding. Hybrid bonding can refer to a combination of metal-metal bonding and dielectric-dielectric bonding. Dielectric-dielectric bonding can refer to the bonding of the bonding dielectric layer. Dielectric-dielectric bonding can include oxide-oxide bonding.

[0074] A direct power interconnect (DPI) may include a buried power rail (BPR) embedded in a second substrate (W20), a buried power rail via (VBPR) coupled to a first surface of the buried power rail (BPR), a post - power via (PM1C) coupled to a second surface of the buried power rail (BPR), a post - power metal line (PM1) coupled to the post - power via (PM1C), and a post - multi - layer metal line (PMLM) coupled to the post - power metal line (PM1). The first surface of the buried power rail (BPR) may be electrically connected to a first - layer metal contact plug (M1C) and a first - layer metal line (MT1) of the multi - layer metal line. The second surface of the buried power rail (BPR) may be electrically connected to the post - power via (PM1C) and the post - power metal line (PM1). The post - multi - layer metal line (PMLM) may include a plurality of post - metal lines (TMT and RDA) and a plurality of post - vias (TMC and RDV). The post - power via (PM1C) and the post - power metal line (PM1) may be part of the post - multi - layer metal line (PMLM).

[0075] A post - inter - layer dielectric layer (PILD) may be formed on a back surface (BS) of the second substrate (W20).

[0076] The buried power rail via (VBPR) may extend from a front surface (FS) of the second substrate (W20) into the interior of an isolation layer (ISO). The buried power rail (BPR) may extend from the front surface (FS) of the second substrate (W20) through the isolation layer (ISO) into the interior of the second substrate (W20). The vertical structures of the post - power via (PM1C), the buried power rail (BPR), and the buried power rail via (VBPR) may be structures that penetrate the post - inter - layer dielectric layer (PILD), the second substrate (W20), and the isolation layer (ISO).

[0077] The buried power rail via (VBPR) may be coupled to the first - layer metal line (MT1) and the first - layer metal contact plug (M1C) of the multi - layer metal line (MLM). The first - layer metal contact plug (M1C) and the buried power rail via (VBPR) may be disposed at the same level.

[0078] The direct power interconnect (DPI) may function to directly transfer power from the back surface (BS) of the second substrate (W20). In other words, the direct power interconnect (DPI) may be a back - side power distribution network (BSPDN) for delivering power to control circuits (CL, SA, and SWD).

[0079] As described above, the semiconductor device 300 may have a POC (PERI - Over - Cell array, where the peripheral circuit is above the cell array) structure in which a memory cell array (MCA), a bonding structure (WBD), and a peripheral circuit (PERI) are stacked in that order. The control circuits (CL, SA, and SWD) of the peripheral circuit (PERI) may be electrically connected to the memory cell array (MCA) through the bonding structure 130.

[0080] In the semiconductor device 300, power can be supplied to the post multi-layer metal line PMLM, and power can be directly supplied from the post multi-layer metal line PMLM to the control circuits CL, SA, and SWD of the peripheral circuit PERI through the direct power interconnect DPI, the first-layer metal line MT1, and the first-layer metal contact plug M1C. Therefore, the path (see reference numeral 'PW') for transmitting power to the control circuits CL, SA, and SWD can be shortened. The power transmission path PW may include the post multi-layer metal line PMLM, the power metal line PM1, the post power via PM1C, the buried power rail BPR, the buried power rail via VBPR, the first-layer metal line MT1, and the first-layer metal contact plug M1C.

[0081] As described above, the method of supplying power to the control circuits CL, SA, and SWD in the semiconductor device 300 can be a top-down power supply from the post multi-layer metal line PMLM to the control circuits CL, SA, and SWD.

[0082] The memory cell array MCA and the peripheral circuit PERI can be bonded to each other through a wafer bonding process. In other words, the memory cell array MCA and the peripheral circuit PERI can be bonded to each other through the bonding structure WBD. The bonding structure WBD can improve the integration degree, for example, overcome process limitations and maximize the net die.

[0083] Since the direct power interconnect DIP is formed through the second substrate W20, when the wafer bonding process is applied, the power consumption of the semiconductor device 300 can be reduced by about 15% or more. In addition, the current resistance of the semiconductor device 300 can be reduced by about 20% or more.

[0084] Figure 5A is a schematic perspective view Figure 4 showing the three-dimensional array of the memory cells shown in Figure 5B is a schematic perspective view Figure 4 showing the memory cells shown in Figure 5C is a schematic cross-sectional view Figure 4 showing the memory cells shown in Figure 5D is a schematic plan view Figure 5B and 5C showing the switching elements shown in

[0085] Referring to Figures 5A to 5D , the memory cell array MCA may include a three-dimensional array of memory cells MC, and each memory cell MC may include a first wire BL, a switching element TR, and a data storage element CAP.

[0086] The first wire BL can be vertically oriented along a first direction D1. The first wire BL can include a bit line. The first wire BL can be referred to as a vertical wire, a vertically oriented bit line, a vertically extending bit line, or a columnar bit line. The first wire BL can include a conductive material. The first wire BL can include a silicon-based material, a metal-based material, or a combination thereof. The first wire BL can include polysilicon, metal, metal nitride, metal silicide, or a combination thereof. The first wire BL can include polysilicon, titanium nitride, tungsten, or a combination thereof. For example, the first wire BL can include a stack of titanium nitride / tungsten (TiN / W), where titanium nitride and tungsten are stacked sequentially.

[0087] The switching element TR can have a function of controlling the voltage (or current) supplied to the data storage element CAP during a data write operation and a data read operation of the data storage element CAP. The switching element TR can include a nanosheet HL, a nanosheet dielectric layer GD, and a second wire DWL. The second wire DWL can include a horizontal wire or a horizontal word line, and the nanosheet HL can include an active layer. The switching element TR can include a transistor. In this case, the second wire DWL can be used as a gate electrode. The switching element TR can also be referred to as a cell transistor, a nanosheet transistor, an access element, or a selection element. The second wire DWL can be referred to as a horizontal gate electrode or a horizontal word line.

[0088] The nanosheet HL can extend in a second direction D2 intersecting the first direction D1. The second wire DWL can extend in a third direction D3 intersecting the first direction D1 and the second direction D2. The first direction D1 can be a vertical direction, the second direction D2 can be a first horizontal direction, and the third direction D3 can be a second horizontal direction. The nanosheet HL can extend along the first horizontal direction (i.e., the second direction D2), and the second wire DWL can extend along the second horizontal direction (i.e., the third direction D3). The nanosheet HL can be referred to as a 'horizontal layer'.

[0089] The nanosheet HL can include a channel CH, a first doped region SR between the channel CH and the first wire BL, and a second doped region DR between the channel CH and the data storage element CAP. The first doped region SR can be coupled to the first wire BL, and the second doped region DR can be coupled to the data storage element CAP. The height of the second doped region DR in the first direction D1 can be greater than the height of the channel CH in the first direction D1. The length of the second doped region DR in the second direction D2 can be less than the length of the channel CH in the second direction D2. The lengths of the first doped region SR, the channel CH, and the second doped region DR in the third direction D3 can be the same.

[0090] The nanosheet HL can be horizontally oriented along the second direction D2 starting from the first wire BL. The second wire DWL can have a dual structure. For example, the second wire DWL can include an upper horizontal line G1 and a lower horizontal line G2, the upper horizontal line G1 and the lower horizontal line G2 face each other, and the nanosheet HL is interposed therebetween. A nanosheet dielectric layer GD can be formed on the upper and lower surfaces of the nanosheet HL. The upper horizontal line G1 can be disposed above the nanosheet HL, and the lower horizontal line G2 can be disposed below the nanosheet HL. The second wire DWL can include a pair of upper horizontal line G1 and lower horizontal line G2. In the second wire DWL, the same driving voltage can be applied to the upper horizontal line G1 and the lower horizontal line G2. For example, the upper horizontal line G1 and the lower horizontal line G2 can be formed as a pair and can be coupled to one memory cell MC. According to another embodiment of the present disclosure, different driving voltages can be applied to the upper horizontal line G1 and the lower horizontal line G2. In this case, one of the upper horizontal line G1 and the lower horizontal line G2 can be used as a back gate or a shielding gate. According to another embodiment of the present disclosure, the second wire DWL can have a gate-all-around structure (GAA).

[0091] See Figure 5D , each of the upper horizontal line G1 and the lower horizontal line G2 can have a width in the second direction D2. For example, the width of the overlapping portion overlapping with the nanosheet HL is greater than the width of the portion not overlapping with the nanosheet HL, and the portion not overlapping with the nanosheet HL is the channel non-overlapping portion NOL. Due to the width difference, the second wire DWL can have a notched sidewall. The second wire DWL can include a channel overlapping portion WLP and a channel non-overlapping portion NOL. The channel overlapping portion WLP can refer to the portion overlapping with the channel CH of the nanosheet HL, and the channel non-overlapping portion NOL can refer to the portion not overlapping with the nanosheet HL. The channel overlapping portion WLP can have a cross shape or a diamond shape.

[0092] Viewed from a top-down perspective, the nanosheet HL can have a cross shape or a diamond shape. According to another embodiment of the present disclosure, the side surface of the nanosheet HL can have a curved shape or a rounded shape.

[0093] The nanosheet HL can include a semiconductor material. For example, the nanosheet HL can include polysilicon, single-crystalline silicon, germanium, or silicon germanium. According to another embodiment of the present disclosure, the nanosheet HL can include an oxide semiconductor material. For example, the oxide semiconductor material can include IGZO (indium gallium zinc oxide), InSnZnO, ZnSnO, or a combination thereof. According to another embodiment of the present disclosure, the nanosheet HL can include a conductive metal oxide. According to another embodiment of the present disclosure, the nanosheet HL can include a two-dimensional material, such as MoS 2 , WS 2 or MoSe 2 .

[0094] When the nanosheet HL is an oxide semiconductor material, the channel CH can be formed of an oxide semiconductor material, and the first doping region SR and the second doping region DR can be omitted. The nanosheet HL can also be referred to as an active layer or a thin body.

[0095] The upper and lower surfaces of the nanosheet HL can have flat surfaces. In other words, the upper and lower surfaces of the nanosheet HL can be parallel to each other in the second direction D2.

[0096] The channel overlap portion WLP between the channel CH of the nanosheet HL and the second wire DWL can overlap with each other. The channel CH of the nanosheet HL can have a cross shape or a rhombus shape. The size of the channel overlap portion WLP of the second wire DWL can be larger than the size of the channel CH. The channel overlap portion WLP of the second wire DWL can completely overlap with the channel CH.

[0097] The first doping region SR and the second doping region DR can be doped with impurities of the same conduction type. The first doping region SR and the second doping region DR can be doped with N-type conductive impurities or P-type conductive impurities. The first doping region SR and the second doping region DR can include at least one impurity selected from arsenic (As), phosphorus (P), boron (B), indium (In), and combinations thereof. The first doping region SR can be coupled to the first wire BL, and the second doping region DR can be coupled to the data storage element CAP. The first doping region SR and the second doping region DR can be referred to as the first source / drain region and the second source / drain region.

[0098] The nanosheet dielectric layer GD can be disposed between the nanosheet HL and the second wire DWL. The nanosheet dielectric layer GD can be referred to as a 'gate dielectric layer' or a channel side dielectric layer. The nanosheet dielectric layer GD can include silicon oxide, silicon nitride, metal oxide, metal oxynitride, metal silicate, high-k material, ferroelectric material, antiferroelectric material, or a combination thereof. The nanosheet dielectric layer GD can include SiO2, Si3N4, HfO2, Al2O3, ZrO2, AlON, HfON, HfSiO, HfSiON, HfZrO, or a combination thereof. The nanosheet dielectric layer GD can be formed by a thermal oxidation process of a semiconductor material.

[0099] The second wire DWL may include a metal-based material, a semiconductor material, or a combination thereof. The second wire DWL may include molybdenum, molybdenum nitride, ruthenium, titanium nitride, tungsten, polysilicon, or a combination thereof. For example, the second wire DWL may include a TiN / W stack, where titanium nitride and tungsten are stacked sequentially. The second wire DWL may include an N-type work function material or a P-type work function material. The N-type work function material may have a low work function of about 4.5 eV or lower, while the P-type work function material may have a high work function of about 4.5 eV or higher. The second wire DWL may include a stack of a low work function material and a high work function material.

[0100] The data storage element CAP may include a storage element, such as a capacitor. The data storage element CAP may be horizontally disposed from the switching element TR in the second direction D2. The data storage element CAP may include a first electrode SN that horizontally extends from a horizontal layer HL in the second direction D2. The data storage element CAP may further include a second electrode PN disposed on the first electrode SN, and a dielectric layer DE disposed between the first electrode SN and the second electrode PN. The first electrode SN, the dielectric layer DE, and the second electrode PN may be horizontally disposed along the second direction D2. The first electrode SN may include an internal space and a plurality of outer surfaces, and the internal space of the first electrode SN may include a plurality of inner surfaces. The outer surfaces of the first electrode SN may include vertical outer surfaces and a plurality of horizontal outer surfaces. The vertical outer surfaces of the first electrode SN may vertically extend along the first direction D1, and the horizontal outer surfaces of the first electrode SN may horizontally extend along the second direction D2 or the third direction D3. The internal space of the first electrode SN may be a three-dimensional space. The dielectric layer DE may conformally cover the inner and outer surfaces of the first electrode SN. The second electrode PN may be disposed in the internal space of the first electrode SN on the dielectric layer DE. Some of the outer surfaces of the first electrode SN may be electrically connected to a second doped region DR of the horizontal layer HL. The second electrode PN of the data storage element CAP may be coupled to a common plate PL.

[0101] The data storage element CAP may have a three-dimensional structure. The first electrode SN may have a three-dimensional structure, and the three-dimensional first electrode SN may be a horizontally three-dimensional structure oriented along the second direction D2. As an example of the three-dimensional structure, the first electrode SN may have a cylindrical shape. The cylindrical shape of the first electrode SN may include a cylindrical inner surface and a cylindrical outer surface. Some of the cylindrical outer surfaces of the first electrode SN may be electrically connected to a second doped region DR of the horizontal layer HL. The dielectric layer DE and the second electrode PN may be disposed on the cylindrical inner surface of the first electrode SN.

[0102] According to another embodiment of the present disclosure, the first electrode SN may have a columnar or columnar-cylindrical shape. The columnar-cylindrical shape may refer to a structure in which a columnar shape and a cylindrical shape are fused.

[0103] The first electrode SN and the second electrode PN may include a metal, a noble metal, a metal nitride, a conductive metal oxide, a conductive noble metal oxide, a metal carbide, a metal silicide, or a combination thereof. For example, the first electrode SN and the second electrode PN may include titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO 2 ), iridium (Ir), iridium oxide (IrO 2 ), platinum (Pt), molybdenum (Mo), molybdenum nitride (MoN), molybdenum oxide (MoO), a titanium nitride / tungsten (TiN / W) stack, a tungsten nitride / tungsten (WN / W) stack, a titanium silicon nitride / titanium nitride (TiSiN / TiN) stack, a titanium nitride / titanium silicon nitride (TiN / TiSiN) stack, or a combination thereof. The second electrode PN may also include a combination of a metal-based material and a silicon-based material. For example, the second electrode PN may be a stack of titanium nitride / silicon germanium / tungsten nitride (TiN / SiGe / WN). In the titanium nitride / silicon germanium / tungsten nitride (TiN / SiGe / WN) stack, silicon germanium may be a gap-filling material filling the interior of the first electrode SN, titanium nitride (TiN) may serve as the second electrode PN of the data storage element CAP, and tungsten nitride may be a low-resistance material. According to another embodiment of the present disclosure, the second electrode PN may include titanium nitride, tungsten, and polysilicon stacked in that order.

[0104] The dielectric layer DE may be referred to as a capacitor dielectric layer or a storage layer. The dielectric layer DE may include silicon oxide, silicon nitride, a high-k material, a perovskite material, or a combination thereof. The dielectric layer DE may include hafnium oxide (HfO 2 ), zirconium oxide (ZrO 2 ), aluminum oxide (Al 2 O 3 ), lanthanum oxide (La 2 O 3 ), titanium oxide (TiO 2 ), tantalum oxide (Ta 2 O 5 ), niobium oxide (Nb 2 O 5 ), or strontium titanate (SrTiO 3 ). According to another embodiment of the present disclosure, the dielectric layer DE may be formed of a composite layer including two or more layers of the above high-k materials.

[0105] The dielectric layer DE may include a zirconium-based oxide. The dielectric layer DE may have a stacked structure including zirconium oxide (ZrO 2 ). The dielectric layer DE may include ZA (ZrO 2 / Al 2 O 3)Stack or ZAZ (ZrO 2 / Al 2 O 3 / ZrO 2 ) stack. The ZA stack can have a structure in which aluminum oxide (Al 2 O 3 ) is stacked on zirconia (ZrO 2 ). The ZAZ stack can have a structure in which zirconia (ZrO 2 ), aluminum oxide (Al 2 O 3 ) and zirconia (ZrO 2 ) are sequentially stacked. The ZA stack and the ZAZ stack can be referred to as zirconia (ZrO 2 )-based layers. According to another embodiment of the present disclosure, the dielectric layer DE can be formed of a hafnium (Hf)-based oxide. The dielectric layer DE can have a stacked structure including hafnium oxide (HfO 2 ). The dielectric layer DE can include a HA (HfO 2 / Al 2 O 3 ) stack or a HAH (HfO 2 / Al 2 O 3 / HfO 2 ) stack. The HA stack can have a structure in which aluminum oxide (Al 2 O 3 ) is stacked on hafnium oxide (HfO 2 ). The HAH stack can have a structure in which hafnium oxide (HfO 2 ), aluminum oxide (Al 2 O 3 ) and hafnium oxide (HfO 2 ) are sequentially stacked. The HA stack and the HAH stack can be referred to as hafnium oxide (HfO 2 )-based layers. In the ZA stack, ZAZ stack, HA stack, and HAH stack, the bandgap energy of aluminum oxide (Al 2 O 3 ) can be larger than that of zirconia (ZrO 2 ) and hafnium oxide (HfO 2 ). The dielectric constant of aluminum oxide (Al 2 O 3 ) can be smaller than that of zirconia (ZrO 2 ) and hafnium oxide (HfO 2 ). Therefore, the dielectric layer DE can include a stack of a high-k material and a high-bandgap material, and the bandgap energy of the high-bandgap material is greater than that of the high-k material. In addition to aluminum oxide (Al 2 O 3) In addition to this, the dielectric layer DE may include silicon oxide (SiO 2 ) as another high bandgap material. The dielectric layer DE can suppress leakage current by including a high bandgap material. The high bandgap material can be thinner than the high-k material.

[0106] According to another embodiment of the present disclosure, the dielectric layer DE may include a stacked structure in which the high-k material and the high bandgap material are alternately stacked. For example, the dielectric layer DE may include ZA (ZrO 2 / Al 2 O 3 ) stack, ZAZ (ZrO 2 / Al 2 O 3 / ZrO 2 ) stack, ZAZA (ZrO 2 / Al 2 O 3 / ZrO 2 / Al 2 O 3 ) stack, ZAZAZ (ZrO 2 / Al 2 O 3 / ZrO 2 / Al 2 O 3 / ZrO 2 ) stack, HA (HfO 2 / Al 2 O 3 ) stack, HAH (HfO 2 / Al 2 O 3 / HfO 2 ) stack, HAHA (HfO 2 / Al 2 O 3 / HfO 2 / Al 2 O 3 ) stack, HAHAA (HfO 2 / Al 2 O 3 / HfO 2 / Al 2 O 3 / HfO 2 ) stack, HZAZH (HfO 2 / ZrO 2 / Al 2 O 3 / ZrO 2 / HfO 2 ) stack, ZHZAZHZ (ZrO 2 / HfO 2 / ZrO 2 / Al 2 O 3 / ZrO 2 / HfO 2 / ZrO 2 ) stack, HZHZ (HfO 2 / ZrO 2 / HfO 2 / ZrO 2 ) stack, AHZAZHA (Al 2 O 3 / HfO 2 / ZrO 2 / Al 2 O 3 / ZrO 2 / HfO 2 / Al 2 O 3 ) stack or AHZAHZA (Al 2 O 3 / HfO 2 / ZrO 2 / Al 2 O 3 / HfO 2 / ZrO 2 / Al 2 O 3 ) stack. In the above stack structure, aluminum oxide (Al 2 O 3 ) can be thinner than zirconium oxide (ZrO 2 ) and hafnium oxide (HfO 2 ).

[0107] According to another embodiment of the present disclosure, the dielectric layer DE may include a high-k material and a high-bandgap material. The dielectric layer DE may have a stacked structure in which a plurality of high-k materials and a plurality of high-bandgap materials are stacked, or a hybrid structure in which the high-k material and the high-bandgap material are hybridized.

[0108] According to another embodiment of the present disclosure, the dielectric layer DE may include a ferroelectric material, an antiferroelectric material, or a combination thereof. For example, the dielectric layer DE may include HfZrO.

[0109] According to another embodiment of the present disclosure, the dielectric layer DE may include a combination of a high-k material and a ferroelectric material, a combination of a high-k material and an antiferroelectric material, or a combination of a high-k material or a ferroelectric material and an antiferroelectric material.

[0110] According to another embodiment of the present disclosure, a lower interface control layer for improving leakage current may be formed between the first electrode SN and the dielectric layer DE, and an upper interface control layer may be formed between the second electrode PN and the dielectric layer DE. The lower interface control layer and the upper interface control layer may include titanium oxide (TiO 2 ), tantalum oxide (Ta 2 O 5 ), niobium, niobium oxide (Nb 2 O 5 ), niobium nitride (NbN), niobium oxynitride (NbON), or a combination thereof. The lower interface control layer and the upper interface control layer may include a single-layer structure or a bilayer structure. For example, the upper interface control layer may include a stack of titanium oxide (TiO 2 ) and niobium oxide (NbO).

[0111] The data storage element CAP may include a three-dimensional capacitor. The data storage element CAP may include a MIM (metal-insulator-metal) capacitor. The data storage element CAP may also be replaced with other data storage materials. For example, the data storage material may be a thyristor, a phase change material, a magnetic tunnel junction (MTJ), or a variable resistance material.

[0112] For example, the storage cell MC may include a thyristor, the first wire BL may be a cathode wire, and the data storage element CAP may be replaced with an anode wire. Thus, the nanosheet HL may include four semiconductor layers stacked along the second direction D2. The thyristor may include a first diode and a second diode coupled in series. When a forward bias of the same voltage is applied to the thyristor, the thyristor may have a high-conductance state with a large amount of current flowing, or a low-conductance state with a small amount of current flowing or no current flowing. According to the high-conductance state and the low-conductance state of the thyristor, the storage cell MC may have a '1' state and a '0' state, respectively.

[0113] Referring back to Figure 5B and Figure 5C , the storage cell MC may further include a first contact node BLC and a second contact node SNC. The first contact node BLC may surround the outer wall of the first wire BL. The second contact node SNC may be disposed between the nanosheet HL and the first electrode SN. The first contact node BLC may include a metal-based material or a semiconductor material. The second contact node SNC may include a metal-based material or a semiconductor material. For example, the first contact node BLC and the second contact node SNC may include titanium, titanium nitride, tungsten, or a combination thereof. In addition, the first contact node BLC and the second contact node SNC may include doped polysilicon, and the first doping region SR and the second doping region DR may respectively include impurities diffused from the first contact node BLC and the second contact node SNC.

[0114] Figures 6 to 8is a side view showing a memory cell array according to other embodiments of the present invention. Memory cell arrays MCA100, MCA200, and MCA300 may be similar to Figure 4 and Figure 5A 's memory cell array MCA. Hereinafter, for a detailed description of the constituent elements that also appear in Figure 4 and Figure 5A , reference may be made to the above embodiments of the present disclosure.

[0115] Referring to Figure 6 , the memory cell array MCA100 may include a plurality of memory cells MC10.

[0116] The memory cell array MCA100 may include a three-dimensional array of memory cells MC10. The three-dimensional array of memory cells MC10 may include a column array of memory cells MC10 and a row array of memory cells MC10. The column array of memory cells MC10 may include a plurality of memory cells MC10 stacked along a first direction D1, and the row array of memory cells MC10 may include a plurality of memory cells MC10 horizontally arranged along a second direction D2 and a third direction D3.

[0117] Each memory cell MC10 may include a first wire BL, a switching element TR, and a data storage element CAP. Hereinafter, for a detailed description of the first wire BL and the data storage element CAP, reference may be made to the above embodiments of the present disclosure.

[0118] The switching element TR may include a nanosheet HL and a second wire DWL. The nanosheet HL may extend along the second direction D2. The second wire DWL may extend along the third direction D3.

[0119] The second wire DWL may have a dual structure. For example, the second wire DWL may include an upper horizontal line G1 and a lower horizontal line G2 that face each other with a horizontal layer HL therebetween. As Figure 5C shown, a nanosheet dielectric layer GD may be formed on the upper and lower surfaces of the horizontal layer HL.

[0120] Each of the upper horizontal line G1 and the lower horizontal line G2 may include a pair of flat sidewalls FSW extending along the third direction D3. The flat sidewalls FSW may be referred to as vertical sidewalls. The flat sidewalls FSW may have a linear shape extending along the third direction D3.

[0121] Referring to Figure 7 , the memory cell array MCA200 may include a plurality of memory cells MC20.

[0122] The memory cell array MCA200 may include a three-dimensional array of memory cells MC20. The three-dimensional array of memory cells MC20 may include a column array of memory cells MC20 and a row array of memory cells MC20. The column array of memory cells MC20 may include a plurality of memory cells MC20 stacked along a first direction D1, and the row array of memory cells MC20 may include a plurality of memory cells MC20 horizontally arranged along a second direction D2 and a third direction D3.

[0123] Each memory cell MC20 may include a first wire BL, a switching element TR, and a data storage element CAP. Hereinafter, for a detailed description of the first wire BL and the data storage element CAP, reference may be made to the above embodiments of the present disclosure.

[0124] The switching element TR may include a nanosheet HL and a second wire SWL. The nanosheet HL may extend in the second direction D2. The second wire SWL may extend in the third direction D3.

[0125] The second wire SWL may have a single structure. For example, the second wire SWL may be disposed on the upper portion of the nanosheet HL. As Figure 5C shown, a nanosheet dielectric layer GD may be formed between the upper surface of the nanosheet HL and the second wire SWL. According to another embodiment of the present disclosure, the second wire SWL may be disposed on the lower portion of the nanosheet HL.

[0126] The second wire SWL may include a pair of flat sidewalls FSW extending in the third direction D3. The flat sidewalls FSW may be referred to as vertical sidewalls.

[0127] According to another embodiment of the present disclosure, the second wire SWL may include a channel overlap portion WLP and a channel non-overlap portion NOL, as Figure 5D shown.

[0128] Reference Figure 8 , the memory cell array MCA300 may include a plurality of memory cells MC30.

[0129] The memory cell array MCA300 may include a three-dimensional array of memory cells MC30. The three-dimensional array of memory cells MC30 may include a column array of memory cells MC30 and a row array of memory cells MC30. The column array of memory cells MC30 may include a plurality of memory cells MC30 stacked along a first direction D1, and the row array of memory cells MC30 may include a plurality of memory cells MC30 horizontally arranged along a second direction D2 and a third direction D3.

[0130] Each memory cell MC30 may include a first wire BL, a switching element TR, and a data storage element CAP. In the following, for a detailed description of the first wire BL and the data storage element CAP, reference may be made to the above embodiments of the present disclosure.

[0131] The switching element TR may include a nanosheet HL and a second wire GAA-WL. The nanosheet HL may extend along a second direction D2. The second wire GAA-WL may extend along a third direction D3.

[0132] The second wire GAA-WL may be a gate-all-around structure GAA. For example, the second wire GAA-WL may extend along the third direction D3 while surrounding the nanosheets HL at the same horizontal height. A nanosheet dielectric layer GD may be formed between the nanosheet HL and the second wire GAA-WL. The nanosheet dielectric layer GD may surround each nanosheet HL.

[0133] The second wire GAA-WL may include a pair of flat sidewalls FSW extending along the third direction D3. The flat sidewalls FSW may be referred to as vertical sidewalls.

[0134] Figure 9 Another semiconductor device according to another embodiment of the present invention is shown.

[0135] Reference Figure 9 , the semiconductor device 400 may include a memory cell string MCS, a peripheral circuit PERI, a bonding structure WBD between the memory cell string MCS and the peripheral circuit PERI, and a direct power supply interconnect DPI coupled to the peripheral circuit PERI. In the following, for a detailed description of the direct power supply interconnect DPI, reference may be made to Figure 1 .

[0136] The memory cell string MCS may include a three-dimensional vertical NAND. The memory cell string MCS may be disposed on a first substrate W10, and the memory cell string MCS may include front multi-layer metal lines FMLM. A first bonding contact plug CBC and a first bonding pad CBD may be formed on the front multi-layer metal lines FMLM. The memory cell string MCS may include a first region R1 and a second region R2. The first region R1 may be a region where memory cells are formed, and the second region R2 may be a region where cell contact plugs coupled to the memory cells are formed. The second region R2 may have a stepped structure.

[0137] The memory cell string MCS may include an alternating stack in which word lines WL and inter-word line dielectric layers IL are alternately stacked. The memory cell string MCS may further include a vertical channel VCH penetrating the alternating stack, a storage layer CTD surrounding the vertical channel VCH, and a bit line BL coupled to an upper end portion of the vertical channel VCH. The storage layer CTD may include a stack of a tunneling dielectric layer, a charge storage layer, and a gate dielectric layer.

[0138] The memory cell string MCS and the peripheral circuit PERI can be interconnected with each other through the bonding structure WBD. The memory cell string MCS and the peripheral circuit PERI can be bonded to each other through a wafer bonding process. In other words, the memory cell string MCS and the peripheral circuit PERI can be bonded to each other through the wafer bonding structure 140.

[0139] The peripheral circuit PERI may include at least one control circuit CL1, CL2, and CL3 for driving the memory cell array MCA.

[0140] The peripheral circuit PERI may be formed in the second substrate W20 and may further include a multilayer metal line MLM coupled to the plurality of control circuits CL1, CL2, and CL3. The multilayer metal line MLM may include a plurality of metal lines MT1 to MT5 and a plurality of metal contact plugs M1C to M5C. The multilayer metal line MLM may include at least one first-layer metal line MT1 and at least one first-layer metal contact plug M1C. The first-layer metal line MT1 and the first-layer metal contact plug M1C may be coupled to the control circuits CL1, CL2, and CL3, respectively. A plurality of isolation layers ISO may be formed in the second substrate W20, and the isolation layers ISO may be disposed between the control circuits CL1, CL2, and CL3. The isolation layer ISO may have a shallow trench isolation (STI) structure.

[0141] The second substrate W20 may include a front surface FS and a back surface BS, and the back surface BS of the second substrate W20 may be disposed at a level higher than the front surface FS. The second substrate W20 may be flipped over by wafer flip-chip so that the back surface BS is disposed at a level higher than the front surface FS. The first-layer metal line MT1 and the first-layer metal contact plug M1C of the multilayer metal line MLM may provide a power transmission path PW.

[0142] The direct power interconnect DPI may include a buried power rail BPR buried in the second substrate W20, a buried power rail via VBPR coupled to the first surface of the buried power rail BPR, a post-power via PM1C coupled to the second surface of the buried power rail BPR, a post-power metal line PM1 coupled to the post-power via PM1C, and a post-multilayer metal line PMLM coupled to the post-power metal line PM1. The first surface of the buried power rail BPR may be electrically connected to the first-layer metal contact plug M1C and the first-layer metal line MT1 of the multilayer metal line, and the second surface of the buried power rail BPR may be electrically connected to the post-power via PM1C and the power metal line PM1. The post-multilayer metal line PMLM may include a plurality of post-metal lines TMT and RDA, and a plurality of post-vias TMC and RDV. The post-power via PM1C and the post-power metal line PM1 may be part of the post-multilayer metal line PMLM.

[0143] The embedded power rail via VBPR can extend from the front surface FS of the second substrate W20 to the inside of the isolation layer ISO. The embedded power rail BPR can extend from the front surface FS of the second substrate W20 through the isolation layer ISO to the inside of the second substrate W20. The vertical structures of the post-power via PM1C, the embedded power rail BPR, and the embedded power rail via VBPR can be structures that penetrate the post-interlayer dielectric PILD, the second substrate W20, and the isolation layer ISO.

[0144] The direct power interconnect DPI can function to directly transfer power from the back surface BS of the second substrate W20. In other words, the direct power interconnect DPI can be a backside power distribution network (BSPDN) for delivering power to the control circuits CL1, CL2, and CL3.

[0145] As described above, the semiconductor device 400 can be a POC (PERI-Over-Cell array, with the peripheral circuit located above the cell array) structure, in which the memory cell string MCS, the bonding structure WBD, and the peripheral circuit PERI are stacked in the stated order. The control circuits CL1, CL2, and CL3 of the peripheral circuit PERI can be electrically connected to the memory cell array MCA through the bonding structure WBD.

[0146] The semiconductor device 400 can directly supply power to the control circuits CL1, CL2, and CL3 of the peripheral circuit PERI through the direct power interconnect DPI, the first-layer metal wire MT1, and the first-layer metal contact plug M1C. Therefore, the path (see reference numeral "PW") for delivering power to the control circuits CL1, CL2, and CL3 can be shortened. The power delivery path PW can include the post-multi-layer metal wire PMLM, the power metal wire PM1, the post-power via PM1C, the embedded power rail BPR, the embedded power rail via VBPR, the first-layer metal wire MT1, and the first-layer metal contact plug M1C.

[0147] As described above, the method of supplying power to the control circuits CL1, CL2, and CL3 in the semiconductor device 400 can be a top-down power supply from the post-multi-layer metal wire PMLM to the control circuits CL1, CL2, and CL3.

[0148] Figure 10 and Figure 11 An example of a direct power interconnect according to another embodiment of the present invention is shown.

[0149] Reference Figure 10, the buried power rail BPR and the buried power rail via VBPR of the direct power interconnect DPI can be formed separately. In other words, the buried power rail via VBPR can be of such a structure that the buried power rail via VBPR lands on the buried power rail BPR.

[0150] Reference Figure 11 , the buried power rail BPR' and the buried power rail via VBPR of the direct power interconnect DPI can have an integrated structure, and the buried power rail BPR' can also be used as the buried power rail via VBPR. For example, when forming the buried power rail BPR', the part to form the buried power rail via VBPR can be formed simultaneously.

[0151] Figures 12 to 23 An example of a method for manufacturing Figure 4 the semiconductor device shown in

[0152] Reference Figure 12 , a memory cell array MCA can be formed on a first substrate W10. The first substrate W10 can be a material suitable for semiconductor processing. The first substrate W10 can include at least one of a conductive material, a dielectric material, and a semiconductor material. The first substrate W10 can include silicon, single-crystalline silicon, polycrystalline silicon, amorphous silicon, silicon germanium, single-crystalline silicon germanium, polycrystalline silicon germanium, carbon-doped silicon, a combination thereof, or multiple layers of the above. The first substrate W10 can also include other semiconductor materials, such as germanium. The first substrate W10 can also include a III / V group semiconductor substrate, such as a compound semiconductor substrate, such as gallium arsenide (GaAs). The first substrate W10 can include a SOI (Silicon-On-Insulator) substrate.

[0153] The memory cell array MCA can include a three-dimensional array of memory cells MC. Each memory cell MC can include a first wire BL, a switching element TR, and a data storage element CAP. The switching element TR can include a nanosheet HL, a nanosheet dielectric layer GD, and a second wire DWL. Hereinafter, for a detailed description of the memory cell array MCA, reference can be made to Figures 5A to 5D .

[0154] The memory cell array MCA can include a first region R1 and a second region R2. The first region R1 can be a region where the memory cells MC are formed, and the second region R2 can be a region where unit contact plugs coupled to the memory cells MC are formed. The second wire DWL in the first region R1 can extend horizontally to the second region R2, and the second wire DWL in the second region R2 can have a stepped structure. In the second region R2 of the memory cell array MCA, each step of the stepped structure can include an upper horizontal line G1, a lower horizontal line G2, and a pad GP between the upper horizontal line G1 and the lower horizontal line G2.

[0155] The front multi-layer metal line FMLM can be formed over the memory cell array MCA. The front multi-layer metal line FMLM can be an array-side interconnect structure. The front multi-layer metal line FMLM can include a first front via F1B, a first front contact plug F1C, a first front metal line FM1, a second front via F2C, and a second front metal line FM2. The first front via F1B can penetrate the third hard mask layer TIL3 to be coupled to the first wire BL and the common plate PL respectively. The upper horizontal line G1 and the lower horizontal line G2 of the second wire DWL in the second region R2 of the memory cell array MCA can be coupled to the first front contact plug F1C and the first front metal line FM1.

[0156] The first bonding contact plug CBC and the first bonding pad CBD can be formed over the second front metal line FM2 of the front multi-layer metal line FMLM.

[0157] Reference Figure 13 , an orbital trench RT can be formed in the second substrate W20. A portion of the second substrate W20 can be etched to form the orbital trench RT. The second substrate W20 can be a material suitable for semiconductor processing. The second substrate W20 can include at least one of a conductive material, a dielectric material, and a semiconductor material. The second substrate W20 can include silicon, single-crystalline silicon, polycrystalline silicon, amorphous silicon, silicon germanium, single-crystalline silicon germanium, polycrystalline silicon germanium, carbon-doped silicon, a combination thereof, or multiple layers of the above. The second substrate W20 can further include other semiconductor materials, such as germanium. The second substrate W20 can further include a III / V group semiconductor substrate, such as a compound semiconductor substrate, such as gallium arsenide (GaAs). The second substrate W20 can include a SOI (Silicon-On-Insulator) substrate.

[0158] Reference Figure 14 , the buried power rail BPR can be formed to fill the orbital trench RT. Forming the buried power rail BPR can include processes of depositing and etching a conductive material. The buried power rail BPR can include polycrystalline silicon, metal, or a combination thereof.

[0159] Reference Figure 15 , a portion of the second substrate W20 can be etched to form an isolation trench ISO' that exposes the upper end portion of the buried power rail BPR.

[0160] Reference Figure 16 , the isolation layer ISO can be formed to fill the isolation trench ISO'. The isolation layer ISO can include silicon oxide, silicon nitride, or a combination thereof.

[0161] According to another embodiment of the present disclosure, the buried power rail BPR can be formed after the isolation layer ISO is formed.

[0162] Reference Figure 17 , a plurality of transistors for controlling circuits CL, SA, and SWD can be formed over the second substrate W20. The transistors can include gates, gate spacers, and source / drains. The control circuits CL, SA, and SWD can include a common board control circuit CL, a sub-word line driver SWD, and a sense amplifier SA.

[0163] Reference Figure 18 , a first layer of metal contact plugs M1C coupled to the control circuits CL, SA, and SWD can be formed. When forming the first layer of metal contact plugs M1C, buried power rail vias VBPR coupled to the buried power rail BPR can be formed. The first layer of metal contact plugs M1C and the buried power rail vias VBPR can include a metal-based material. Forming the first layer of metal contact plugs M1C and the buried power rail vias VBPR can include forming an interlayer dielectric layer, forming contact holes and via holes in the interlayer dielectric layer, forming the first layer of metal contact plugs M1C in the contact holes, and forming the buried power rail vias VBPR in the via holes. Forming the first layer of metal contact plugs M1C and forming the buried power rail vias VBPR can be performed simultaneously.

[0164] Reference Figures 13 to 19 , a plurality of control circuits CL, SA, and SWD can be formed in the front side FS of the substrate W20 including a back side and a front side, and a buried power interconnect can be formed, the buried power interconnect being partially buried from the front side FS in the second substrate W20 to be coupled to the control circuits CL, SA, and SWD. Here, the buried power interconnect can include a combination of a buried power rail BPR and buried power rail vias VBPR.

[0165] Reference Figure 19 , a multi-layer metal line MLM can be formed. The multi-layer metal line MLM can have a structure of at least five layers. For example, it can include a plurality of metal lines MT1 to MT5 and a plurality of metal contact plugs M2C to M5C. The multi-layer metal line MLM can have a front side interconnect structure that is coupled to the buried power interconnect of the buried power rail BPR and the buried power rail vias VBPR. The multi-layer metal line MLM can include Figure 18 the first layer of metal contact plugs M1C. The buried power rail BPR can be electrically connected to the first layer of metal contact plugs M1C and the first layer of metal lines MT1 of the multi-layer metal line MLM through the buried power rail vias VBPR.

[0166] A second bonding contact plug PBC and a second bonding pad PBD can be formed over the multi-layer metal line MLM.

[0167] See Figure 20, after forming the multi-layer metal lines MLM, the second substrate W20 can be flipped over. For example, the second substrate W20 can be flipped over by wafer flip-chip, such that the back surface of the second substrate W20 can be set at a level higher than the front surface. The second bonding pad PBD can be set at the bottom layer by wafer flip-chip.

[0168] Subsequently, back grinding BGR, such as chemical mechanical polishing (CMP), can be performed to reduce the thickness of the back surface of the second substrate W20.

[0169] Reference Figure 21 , a post-interlayer dielectric layer PILD can be formed on the back surface of the second substrate W20.

[0170] After etching the post-interlayer dielectric layer PILD, the back surface of the second substrate W20 can be etched to have a predetermined thickness. Thus, a nano-through silicon via NSV exposing the buried power rail BPR can be formed.

[0171] Reference Figure 22 , a post-power via PM1C can be formed to fill the nano-through silicon via NSV. The post-power via PM1C can include a metal-based material. The post-power via PM1C can be referred to as a nano-through silicon via NTSV.

[0172] Reference Figure 23 , a post-power metal line PM1 can be formed on the post-power via PM1C, and a post-multi-layer metal line PMLM can be formed on the post-power metal line PM1. The post-multi-layer metal line PMLM can include post-metal lines TMT and RDA and post-vias TMC and RDV. The post-power metal line PM1 can be part of the post-multi-layer metal line PMLM. The post-power via PM1C, the post-power metal line PM1, and the post-multi-layer metal line PMLM can have a backside interconnect structure.

[0173] Reference Figures 21 to 23 , the backside interconnect structure can be formed to extend downward from the back surface BS of the flipped and backside-grounded second substrate W20 and be coupled to the buried power rail BPR and the buried power rail via VBPR that are buried and power-interconnected.

[0174] Subsequently, reference Figure 4 , a bonding process for the electrical connection between the memory cell array MCA and the control circuits CL, SA, and SWD can be performed. For example, a wafer bonding process of the first substrate W10 and the second substrate W20 can be performed to bond the first bonding pad CBD and the second bonding pad PBD.

[0175] Figure 24 is a schematic cross-sectional view showing a semiconductor device according to another embodiment of the present invention. Figure 24 Shows includingFigure 11 A stacked semiconductor device with an embedded power rail BPR'. Figure 24 The semiconductor device 500 can be similar to Figure 4 the semiconductor device 200. Hereinafter, for a detailed description of the constituent elements that also appear in Figure 4 , reference can be made to Figure 4 .

[0176] Referring to Figure 24 , the semiconductor device 500 can include a memory cell array MCA, a peripheral circuit PERI, a bonding structure WBD between the memory cell array MCA and the peripheral circuit PERI, and a direct power interconnect DPI coupled to the peripheral circuit PERI. Hereinafter, for a detailed description of the direct power interconnect DPI, reference can be made to Figure 1 and Figure 4 .

[0177] The direct power interconnect DPI can include an embedded power rail BPR' that also serves as an embedded power rail via, a post-power via PM1C coupled to the embedded power rail BPR, a post-power metal line PM1 coupled to the post-power via PM1C, and a post-multilayer metal line PMLM coupled to the post-power metal line PM1. The first surface of the embedded power rail BPR' can be electrically connected to the first-layer metal contact plug M1C and the first-layer metal line MT1 of the multilayer metal line, and the second surface of the embedded power rail BPR' can be electrically connected to the post-power via PM1C and the post-power metal line PM1. The post-multilayer metal line PMLM can include a plurality of post-metal lines TMT and RDA, and a plurality of post-vias TMC and RDV. The post-power via PM1C and the post-power metal line PM1 can be part of the post-multilayer metal line PMLM.

[0178] Referring to Figure 24 , the embedded power rail BPR' can have an integrated structure including an embedded power via.

[0179] The above embodiments of the present disclosure can directly supply power to the transistors of the peripheral circuit unit in the stacked semiconductor device. This is a technology for providing optimal power when forming a stacked semiconductor device including a memory cell array and a peripheral circuit by wafer bonding. The embedded power rail for power supply can be embedded in the substrate during the process of forming the isolation layer. The embedded power rail can be directly coupled to the transistors through metal lines and metal contact plugs.

[0180] According to an embodiment of the present invention, since the direct power interconnect is formed to penetrate the substrate in which the control circuit of the peripheral circuit is formed, the process of etching high-aspect-ratio contacts can be omitted, thereby reducing the manufacturing cost of the semiconductor device.

[0181] According to an embodiment of the present invention, by bonding a memory cell array with a peripheral circuit wafer such that the peripheral circuit is disposed at a level higher than the memory cell array and forming a direct power supply interconnection for directly supplying power to a control circuit of the peripheral circuit, a path for supplying power to the control circuit of the peripheral circuit can be shortened. Therefore, power consumption and resistance of the semiconductor device can be reduced.

[0182] Although the present invention has been described with respect to specific embodiments, it will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the present invention as defined by the following claims.

Claims

1. A semiconductor device, comprising: a first substrate; a memory cell array comprising memory cells vertically stacked on the first substrate; A second substrate including a front side facing the memory cell array and a back side located at a higher level than the front side and including a plurality of control circuits; A backside power distribution network includes a power interconnect that penetrates the second substrate and supplies power to the control circuit from the backside of the second substrate.

2. The semiconductor device according to claim 1, further comprising: Metal contact plugs and metal lines are suitable for interconnecting the power interconnection and the control circuit to each other.

3. The semiconductor device according to claim 1, wherein the backside power distribution network comprises: After that, the multi-layer metal wires are powered; a buried power rail via electrically connected to the control circuit; as well as a buried power rail disposed between the buried power rail via and the rear multi-layer metal line, Wherein, the embedded power rail and the embedded power rail via are partially embedded in the second substrate.

4. The semiconductor device according to claim 3, wherein: The buried power rail via has a structure in which the buried power rail via falls onto the buried power rail.

5. The semiconductor device according to claim 3, wherein: The buried power rail and the buried power rail via have an integrated structure.

6. The semiconductor device according to claim 1, further comprising: An isolation layer, located between the control circuits, Wherein, the power interconnection penetrates the second substrate and the isolation layer.

7. The semiconductor device according to claim 1, further comprising: a front multi-layer metal line coupled to the memory cell array and located at a higher level than the memory cell array; a first bonding pad coupled to an upper end portion of the front multi-layer metal line; a multi-layer metal line coupled to the control circuit and located at a lower level than the control circuit; as well as a second bonding pad coupled to a lower end portion of the multi-layer metal line, Wherein, the first bonding pad and the second bonding pad have an interconnection structure.

8. The semiconductor device according to claim 1, wherein The memory cell array comprises a three-dimensional array of vertically stacked memory cells, and Each of the storage units comprises: Horizontally oriented nanosheets; a first conductive line coupled to a first side of the nanosheet and oriented vertically; A data storage element coupled to the second side of the nanosheet; and A second wire is oriented horizontally to cross the nanosheet.

9. The semiconductor device according to claim 1, wherein: The memory cell array comprises a three-dimensional array of vertically stacked memory cells, and Each storage unit includes: Horizontally oriented nanosheets; a bit line coupled to the first side of the nanosheet and oriented vertically; a capacitor coupled to the second side of the nanosheet; and A dual structure of word lines that are horizontally oriented to cross the nanosheets.

10. The semiconductor device according to claim 1, wherein The memory cell array comprises a three-dimensional array of vertically stacked memory cells, and Each of the storage units comprises: Horizontally oriented nanosheets; a bit line coupled to the first side of the nanosheet and oriented vertically; a capacitor coupled to the second side of the nanosheet; and The word lines of the gate-all-around structure are horizontally oriented and surround the nanosheet.

11. A method for manufacturing a semiconductor device, comprising: forming a memory cell array on a first substrate; forming an array-side interconnect structure coupled to the memory cell array; forming a plurality of control circuits on a front side of a second substrate including a back side and a front side, and an embedded power interconnect partially embedded in the second substrate from the front side and coupled to the control circuits; forming a front-side interconnect structure coupled to the buried power interconnect; flipping the second substrate after forming the front-side interconnect structure; forming a backside interconnection structure extending downward from the backside of the flipped second substrate and coupled to the embedded power interconnection; as well as A bonding process is performed to electrically connect the memory cell array and the control circuit to each other.

12. The method according to claim 11, wherein: The steps of forming a plurality of control circuits on a front side of a second substrate including a back side and a front side, and an embedded power interconnection partially buried in the second substrate from the front side and coupled to the control circuits include: forming a buried power rail buried in the second substrate from the front side of the second substrate; forming an isolation layer on the buried power rail; forming the control circuit on the front side of the second substrate between the isolation layers; and An embedded power rail via is formed to couple to the embedded power rail.

13. The method according to claim 12, further comprising: After forming the control circuit, forming a metal contact plug coupled to the control circuit, Wherein, the metal contact plug and the buried power rail via are formed simultaneously.

14. The method according to claim 13, further comprising: After forming the metal contact plug, Metal lines are formed that interconnect the metal contact plugs and the buried power rail vias.

15. The method according to claim 12, wherein: The buried power rail via is formed to have a structure in which the buried power rail via falls onto the buried power rail, or The buried power rail and the buried power rail via are formed to have an integrated structure.

16. The method according to claim 11, wherein: The step of forming a front-side interconnect structure coupled to the buried power interconnect comprises: forming nano through silicon via holes on the back side of the second substrate to expose the buried power interconnect; forming a nano-through-silicon via filling the nano-through-silicon via hole; and A multi-layer metal line coupled to the nano-through silicon via is formed.

17. The method according to claim 11, further comprising: After forming an array-side interconnect structure coupled to the memory cell array, A first bonding pad coupled to the array-side interconnect structure is formed.

18. The method according to claim 11, further comprising: After forming the front-side interconnect structure coupled to the buried power interconnect, A second bonding pad coupled to the front-side interconnect structure is formed.

19. The method according to claim 11, wherein: The bonding process includes direct bonding or hybrid bonding.

20. The method according to claim 11, wherein the step of forming a memory cell array on the first substrate comprises: vertically stacking memory cells on the first substrate, and Each of the storage units comprises: Horizontally oriented nanosheets; a bit line coupled to the first side of the nanosheet and oriented vertically; a capacitor coupled to the second side of the nanosheet; and A dual structure of word lines that are horizontally oriented to cross the nanosheets.

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