Storage array and manufacturing method thereof, storage device and electronic equipment

Abstract

The invention provides a storage array and a manufacturing method thereof, a storage device and electronic equipment, and relates to the technical field of storage. The memory array comprises a substrate, a plurality of first signal lines, a plurality of second signal lines and a plurality of layers of memory units, wherein the first signal lines and the second signal lines are arranged on the substrate, and the memory units are vertically stacked on the substrate. Wherein the extension direction of the first signal lines is parallel to the substrate, and the extension direction of the second signal lines is perpendicular to the substrate. The memory cell includes a selector and a capacitor disposed in a direction parallel to the substrate, and the selector and the capacitor are coupled in series between the first signal line and the second signal line. The second signal line is coupled with the plurality of stacked memory cells, and the first signal line is coupled with the plurality of memory cells arranged on the same layer. The cost (such as photoetching cost) of the storage array cannot be correspondingly increased along with the increase of the number of layers of the storage units, so that low-cost and high-density three-dimensional storage can be realized.

Description

Technical Field

[0001] The present application relates to the field of storage technologies, and particularly to a storage array, a manufacturing method thereof, a storage device, and an electronic device. Background Art

[0002] Dynamic random access memory (DRAM) has the advantages of fast read and write speeds and strong durability, but also has the disadvantages of small storage capacity and high power consumption. With the rapid development of the Internet of Things, big data, and artificial intelligence, traditional DRAM can no longer meet the requirements. Ferroelectric random access memory (FRAM) has the advantages of fast read and write speeds, low power consumption, and miniaturization, and has become an ideal memory to replace DRAM to provide large-capacity memory.

[0003] Compared with the 1T1C (1 transistor 1 capacitor) structure used in traditional DRAM memory cells, the 1S1C (1 selector 1 capacitor) structure is adopted in FRAM memory cells, which has good miniaturization potential and anti-interference ability in high-density architectures. Currently, in a three-dimensional storage architecture based on the 1S1C structure, multiple stacked memory cells need to be fabricated using separate processes (including photolithography processes), which will correspondingly increase the manufacturing cost of the device and limit the further development of the device. Summary of the Invention

[0004] The present application provides a storage array, a manufacturing method thereof, a storage device, and an electronic device, and provides a three-dimensional storage architecture with low cost and high density.

[0005] The present application provides a storage array, which includes a substrate, a plurality of first signal lines, a plurality of second signal lines disposed on the substrate, and a plurality of memory cells vertically stacked on the substrate. Among them, the extending direction of the first signal line is parallel to the substrate, and the extending direction of the second signal line is perpendicular to the substrate. The memory cell includes a selector and a capacitor serially coupled between the first signal line and the second signal line, and the selector and the capacitor are disposed along a direction parallel to the substrate. The first signal line is coupled to a plurality of memory cells disposed in the same layer. The second signal line is coupled to a plurality of memory cells stacked.

[0006] That is to say, the storage array provided by this application adopts an intersecting structure in the direction perpendicular to the substrate. By arranging the selector and capacitor in the storage unit along the transverse direction (i.e., parallel to the substrate), in this way, laterally stacked film layers can be prepared by an isotropic deposition method to form the selector and capacitor. The fabrication of multiple layers of storage units can be completed through a single manufacturing process, so that the manufacturing cost of the storage array (such as lithography cost) will not increase correspondingly with the increase in the number of storage unit layers, thus achieving the purpose of reducing the manufacturing cost and being more conducive to realizing high-density storage.

[0007] In some possible implementation manners, the number of layers of the above-mentioned multiple-layer storage units can be 64 to 200.

[0008] In some possible implementation manners, the capacitor includes a ferroelectric capacitor. The ferroelectric capacitor has good compatibility with the silicon-based semiconductor process, so that it can be fabricated using a mature manufacturing process without increasing the manufacturing cost.

[0009] In some possible implementation manners, the projections of the multiple-layer storage units on the substrate overlap, that is, multiple storage units in the lower layer are respectively aligned with multiple storage units in the upper layer one by one, so as to achieve the purpose of simplifying the manufacturing process and reducing the manufacturing cost.

[0010] In some possible implementation manners, the storage unit includes: a first metal wire, a ferroelectric layer, a first metal layer, and a resistive switching layer that are sequentially stacked along the direction parallel to the substrate. Wherein, the first end of the first metal wire is connected to the second signal line, and the second end of the first metal wire is connected to the first signal line through the sequentially arranged ferroelectric layer, first metal layer, and resistive switching layer, and the first metal wire and the first signal line are located in the same layer. The first metal wire, ferroelectric layer, and first metal layer are used to form a capacitor. The first signal line, resistive switching layer, and first metal layer are used to form a selector.

[0011] In some possible implementation manners, the storage array includes a trench, and the depth direction of the trench is parallel to the substrate. The resistive switching layer covers the bottom and side walls of the trench, and the first signal line is filled inside the resistive switching layer. In this case, the ferroelectric layer and the first metal layer cover the end face and side face of the second end of the first metal wire, so as to increase the capacitance of the capacitor and reduce the relative area of the selector. In this way, when operating the storage unit, at the moment of applying the operating voltage, the selector can obtain a larger voltage division, so that it can be instantaneously turned on. The turned-on selector is in a low-resistance state, so that most of the voltage falls on the ferroelectric capacitor, thereby accelerating the polarization reversal speed of the ferroelectric layer in the ferroelectric capacitor, and further accelerating the read / write speed of the storage unit.

[0012] In some possible implementations, the storage array includes holes, and the depth direction of the holes is parallel to the substrate. The ferroelectric layer and the first metal layer cover the bottom and the side walls of the holes, and the first metal layer is located inside the ferroelectric layer; the first metal wire is filled inside the first metal layer. In this case, the resistive switching layer covers the surface of the first signal line close to the first metal wire and the two surfaces in the direction perpendicular to the substrate.

[0013] In some possible implementations, multiple first signal lines connected to the stacked multi-layer memory cells are stacked in parallel and fabricated by the same photolithography process.

[0014] In some possible implementations, multiple second signal lines connected to the stacked multi-layer memory cells are arranged in parallel and fabricated by the same photolithography process.

[0015] In some possible implementations, the first metal wires in the multi-layer memory cells are fabricated by the same photolithography process.

[0016] In some possible implementations, the ferroelectric layer in the multi-layer memory cells is fabricated by the same photolithography process.

[0017] In some possible implementations, the resistive switching layer in the multi-layer memory cells is fabricated by the same photolithography process.

[0018] In some possible implementations, the resistive switching layer can transition between a high-resistance state and a low-resistance state under the voltage applied to the first signal line and the second signal line.

[0019] In some possible implementations, the material of the resistive switching layer includes at least one of silicon or silicon compounds, germanium or germanium compounds, metal oxides, materials with metal-insulator transition characteristics, mixed ionic-electronic conductor materials, perovskite-type composite oxides, solid electrolytes, or organic polymers.

[0020] In some possible implementations, the resistive switching layer includes a PNP junction or an NPN junction.

[0021] In some possible implementations, the ferroelectric layer may include a hafnium oxide-based ferroelectric material.

[0022] In some possible implementations, the ferroelectric layer may include a scandium (Sc)-doped aluminum nitride (AlN) material.

[0023] The present application also provides a method for manufacturing a storage array, which may include: fabricating a stacked structure on a substrate; wherein the stacked structure includes a plurality of first insulating layers and a plurality of second insulating layers that are alternately stacked. Remove the plurality of first insulating layers in the stacked structure, fabricate first signal lines, selectors, and capacitors in the removal regions of each first insulating layer, and form second signal lines perpendicular to the substrate on the side surfaces of the stacked structure; wherein the selectors and capacitors are arranged along a direction parallel to the substrate and are used to form storage cells, and the selectors and capacitors are serially coupled between the first signal lines and the second signal lines, the second signal lines are coupled to a plurality of stacked storage cells, and the first signal lines are coupled to a plurality of storage cells arranged in the same layer.

[0024] By using this manufacturing method, the fabrication of multiple layers of storage cells can be completed through a single manufacturing process, so that the manufacturing cost of the storage array (such as lithography cost) does not increase correspondingly with the increase in the number of storage cell layers. Furthermore, the purpose of reducing the manufacturing cost can be achieved, which is more conducive to realizing high-density storage. In addition, by using this manufacturing method, the selectors and capacitors can be self-aligned without lithography alignment, further saving the lithography cost and avoiding the problem of alignment deviation (overlap) that may occur in the lithography alignment process.

[0025] In some possible implementation manners, the above-mentioned fabricating a stacked structure on a substrate may include: alternately fabricating a plurality of first insulating layers and a plurality of second insulating layers on the substrate, and etching the plurality of first insulating layers and the plurality of second insulating layers as a whole to form a stacked structure; wherein the stacked structure is in a comb shape, and each film layer in the stacked structure includes a connecting portion and a plurality of comb tooth portions connected to the connecting portion.

[0026] In some possible implementation manners, the above-mentioned removing the plurality of first insulating layers in the stacked structure, fabricating first signal lines, selectors, and capacitors in the removal regions of each first insulating layer, and forming second signal lines perpendicular to the substrate on the side surfaces of the stacked structure may include: removing the plurality of first insulating layers in the stacked structure, fabricating first signal lines and selectors in the removal regions of the connecting portions in the first insulating layers, fabricating capacitors respectively in the removal regions of the plurality of comb tooth portions in the first insulating layers, and forming second signal lines perpendicular to the substrate at the ends of the comb tooth portions.

[0027] In some possible implementation manners, removing the multiple first insulating layers in the stacked structure, fabricating first signal lines and selectors in the removal regions of the connection portions in the first insulating layer, fabricating capacitors in the removal regions of the multiple comb-shaped portions in the first insulating layer respectively, and forming second signal lines perpendicular to the substrate at the ends of the comb-shaped portions may include: filling the gaps in the stacked structure with a first insulating material to form a filling structure. Removing the connection portions in the multiple first insulating layers to form multiple grooves on the side surfaces of the filling structure. Sequentially forming a resistive switching layer and first signal lines in the multiple grooves, and covering the side surfaces where the first signal lines are located with a second insulating material. Removing the comb-shaped portions in the multiple first insulating layers to form multiple holes. Sequentially forming a first metal layer, a ferroelectric layer, and first metal lines in the multiple holes, and forming second signal lines connected to the first metal lines on the opening sides of the holes.

[0028] In some possible implementation manners, removing the connection portions in the multiple first insulating layers to form multiple grooves on the side surfaces of the filling structure may include: on one side close to the connection portions, etching downward from the top of the filling structure to the substrate to remove a part of the connection portions on the side away from the comb-shaped portions. Removing the remaining connection portions by etching from the side surfaces of the filling structure to form multiple grooves.

[0029] In some possible implementation manners, sequentially forming a first metal layer, a ferroelectric layer, and first metal lines in the multiple holes, and forming second signal lines connected to the first metal lines on the opening sides of the holes may include: depositing a metal material in the multiple holes to form a first metal layer. Depositing a ferroelectric layer in the holes where the first metal layer is formed. Depositing a metal material in the holes where the ferroelectric layer is formed to form first metal lines in the holes, and simultaneously forming a metal thin film on the surface of the opening sides of the holes, and etching the metal thin film to form multiple second signal lines.

[0030] In some possible implementation manners, the first insulating material is the same as the insulating material in the second insulating layer.

[0031] In some possible implementation manners, the second insulating material is the same as the insulating material in the second insulating layer.

[0032] This application also provides a storage device, which includes a controller and a storage array provided in any of the foregoing possible implementation manners, and the storage array is electrically connected to the controller.

[0033] This application also provides an electronic device, which includes a circuit board and a storage device provided in any of the foregoing possible implementation manners, and the storage device is electrically connected to the circuit board. Description of the Drawings

[0034] Figure 1An architecture diagram of an electronic device provided by an embodiment of the present application;

[0035] Figure 2 An architecture diagram of a storage device provided by an embodiment of the present application;

[0036] Figure 3 A schematic diagram of a storage array provided by an embodiment of the present application;

[0037] Figure 4 A schematic structural diagram of a storage unit in a storage array provided by an embodiment of the present application;

[0038] Figure 5 is Figure 4 A schematic cross-sectional view along the AA' position (the substrate is omitted);

[0039] Figure 6 is Figure 4 A schematic cross-sectional view along the BB' position (the substrate is omitted);

[0040] Figure 7 A schematic structural diagram of a selector provided by an embodiment of the present application;

[0041] Figure 8 A schematic structural diagram of a ferroelectric capacitor provided by an embodiment of the present application;

[0042] Figure 9 A partial cross-sectional schematic diagram of a storage array provided by an embodiment of the present application;

[0043] Figure 10 A manufacturing flowchart of a storage array provided by an embodiment of the present application;

[0044] Figure 11 A schematic diagram of a storage array during the manufacturing process provided by an embodiment of the present application;

[0045] Figure 12 A manufacturing flowchart of a storage array provided by an embodiment of the present application;

[0046] Figure 13 A schematic diagram of a storage array during the manufacturing process provided by an embodiment of the present application;

[0047] Figure 14 A schematic diagram of a storage array during the manufacturing process provided by an embodiment of the present application;

[0048] Figure 15 A schematic diagram of a storage array during the manufacturing process provided by an embodiment of the present application;

[0049] Figure 16 A schematic diagram of a storage array during the manufacturing process provided by an embodiment of the present application;

[0050] Figure 17 A schematic diagram of a storage array provided for the implementation of this application during the manufacturing process;

[0051] Figure 18 A top view of a storage array provided for the implementation of this application;

[0052] Figure 19 A side view of a storage array provided for the implementation of this application. Detailed implementation manners

[0053] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions in this application will be clearly and completely described below with reference to the accompanying drawings in this application. Apparently, the described embodiments are some but not all of the embodiments of this application. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the scope of protection of this application.

[0054] Terms such as "first" and "second" in the description of the embodiments, claims, and drawings of this application are only used for the purpose of distinguishing descriptions, and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating or implying an order. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" may mean: only A exists, only B exists, and both A and B exist at the same time. Among them, A and B may be singular or plural. The character " / " generally indicates that the associated objects before and after are in an "or" relationship. "At least one (item)" means one or more, and "multiple" means two or more. Understandings of "installation", "connection", "coupling", etc. should be broad. For example, it may be an electrical connection or a mechanical connection; it may be a fixed connection, a detachable connection, or an integral connection; it may be a direct connection, an indirect connection through an intermediate medium, or a communication inside two components. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusions. For example, including a series of steps or units. The method, system, product, or device does not have to be limited to the clearly listed steps or units, but may include other steps or units not clearly listed or inherent to these processes, methods, products, or devices. "Upper", "lower", "left", "right", etc. are only relative to the orientation of the components in the drawings. These directional terms are relative concepts. They are used for relative descriptions and clarifications, and they may change accordingly with the change of the orientation of the components placed in the drawings.

[0055] An embodiment of this application provides an electronic device, and a new type of storage device with low cost and high density is adopted in the electronic device.

[0056] The present application does not limit the setting form of the above electronic device, and the electronic device can be any electronic product provided with a storage device, such as consumer electronic products, home electronic products, vehicle-mounted electronic products, financial terminal products, communication electronic products, etc.

[0057] Illustratively, the above consumer electronic products can be mobile phones, tablet computers, laptop computers, personal computers (PCs), personal digital assistants (PDAs), smart wearable products (e.g., smart watches, smart bracelets, etc.), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, drones, etc. Home electronic products can be smart door locks, TVs, smart speakers, refrigerators, floor cleaning robots, etc. Vehicle-mounted electronic products can be vehicle-mounted navigators, vehicle-mounted displays, etc. Financial terminal products can be automated teller machines (ATMs), electronic devices for self-service business handling, etc. Communication electronic products can be communication devices such as servers, memories, radars, base stations, etc.

[0058] According to actual requirements, other devices electrically connected to the storage device can also be provided in the above electronic device, such as printed circuit boards (PCBs; also known as printed wiring boards), input / output devices, etc., and the present application does not limit this.

[0059] Illustratively, taking the above electronic device as a mobile phone as an example. Refer to Figure 1As shown in the figure, the mobile phone 100 includes a bus 101, and a system on chip (SoC) 110, a second RAM 120, a communication chip 130, and a power management chip 140 connected to the bus 101. Among them, the SoC 110 can be used to process data, such as processing data of application programs, processing image data, and caching temporary data. The SoC 110 may include an application processor (AP) 111 for processing application programs, a graphics processing unit (GPU) 112 for processing image data, and a first RAM (random access memory) 113 for caching high-speed data. The AP 111, the GPU 112, and the first RAM 113 may be integrated in a single die, or may be separately provided in multiple dies. The first RAM 113 may be a static random access memory (SRAM) or an embedded flash (eflash). The second RAM 120 may be a dynamic random access memory (DRAM). The second RAM 120 can be used to store volatile data, such as temporary data generated by the SoC 110. The storage capacity of the second RAM 120 is generally larger than that of the first RAM 113, but the reading speed is generally slower than that of the first RAM 113. The communication chip 130 can be used for processing protocol stacks, or amplifying and filtering analog radio frequency signals, or implementing the above functions simultaneously. The power management chip 140 can be used to supply power to other chips.

[0060] Both the above-mentioned first RAM 113 and second RAM 120 can adopt the novel storage device provided by the embodiments of the present application.

[0061] The novel storage device provided by the embodiments of the present application can be any device with a storage function. The following further describes the storage device provided by the embodiments of the present application.

[0062] Schematically, the embodiments of the present application provide a memory, such as Figure 2 As shown in the figure, the memory (i.e., the storage device) includes one or more storage arrays (which can also be called storage circuits) and a controller, and the controller is electrically connected to the storage array to realize access to the storage array through the controller. The memory adopts a novel three-dimensional storage architecture, and the lithography cost of this storage architecture does not increase correspondingly with the increase in the number of stacked layers, so as to achieve low-cost and high-density storage.

[0063] Illustratively, the above-mentioned memory can be a ferroelectric random access memory (FRAM), but is not limited thereto. The following embodiments are all described by taking this as an example.

[0064] The following further describes the novel memory array adopted in the above-mentioned memory.

[0065] Figure 3 It is a schematic diagram of a memory array provided by an embodiment of the present application. Figure 4 It is a schematic diagram of the structure of the memory cell 10 in the memory array provided by an embodiment of the present application. Figure 5 For Figure 4 It is a schematic cross-sectional view along the AA' position (the substrate is omitted). Figure 6 For Figure 4 It is a schematic cross-sectional view along the BB' position (the substrate is omitted).

[0066] Illustratively, an embodiment of the present application provides a memory array. Referring to Figure 3 As shown, the memory array includes multiple layers of memory cells 10 vertically stacked on the substrate 1, and multiple first signal lines La and multiple second signal lines Lb provided on the substrate 1. Among them, each layer of memory cells 10 includes multiple memory cells 10 distributed parallel to the substrate 1. The first signal line La is parallel to the substrate 1, that is, the extending direction (X direction) of the first signal line La is parallel to the substrate 1. Of course, the first signal line La can also extend along the Y direction. The second signal line Lb is perpendicular to the substrate 1, that is, the extending direction (Z direction) of the second signal line Lb is perpendicular to the substrate 1.

[0067] The number of layers of the above-mentioned vertically stacked multiple layers of memory cells 10 can be 64 to 200 layers, but is not limited thereto. For example, in some embodiments, the memory array can be stacked with 64 layers of memory cells 10. Again, for example, in some embodiments, the memory array can be stacked with 128 layers of memory cells 10. Still again, for example, in some embodiments, the memory array can be stacked with 200 layers of memory cells 10.

[0068] Combined with Figure 3 、 Figure 4 And Figure 5 As shown, the memory cell 10 includes a selector S and a capacitor C (such as a ferroelectric capacitor), and the selector S and the capacitor C are stacked in the lateral direction (that is, the direction parallel to the substrate 1) (refer to Figure 5) That is, the selector S and the capacitor C in the storage unit 10 are distributed on the same layer. The selector S and the capacitor C are serially coupled between the first signal line La and the second signal line Lb. Among them, the first signal line La is coupled to the selector S in multiple storage units 10 arranged on the same layer, and the second signal line Lb is coupled to the capacitor C in multiple storage units 10 arranged in a stacked manner.

[0069] That is to say, the above storage array adopts an interleaved structure in the direction perpendicular to the substrate 1 (i.e., longitudinally), and the storage unit 10 can be located in the intersection area of the first signal line La and the second signal line Lb. The "intersection area" refers to the intersection position of the first signal line La and the second signal line Lb in space, and the two do not actually contact.

[0070] In addition, in the above storage array, multiple first signal lines La can be respectively located on the same layer as multiple layers of storage units 10 in the direction perpendicular to the substrate 1. That is to say, the first signal line La is respectively arranged at the spatial position corresponding to each layer of storage units 10. In this case, the selector S in multiple storage units 10 located on a certain layer is coupled to the first signal line La arranged on this layer. Of course, the first signal line La can also be on a different layer from the storage unit 10, and this application does not limit this.

[0071] Compared with the traditional 1T1C-structured storage unit (i.e., one transistor and one capacitor), the storage unit 10 of this application adopts a 1S1C structure (i.e., one selector tube S and one capacitor C), using the selector tube S to replace the traditional transistor. The selector S is a two-terminal device with on-off function, and it has the characteristic of being in a high-resistance state or a low-resistance state with the change of the voltage applied across its two ends. In this way, by controlling the selector S to be in a high-resistance state, the closing of the storage unit 10 where it is located can be achieved, and by controlling the selector S to be in a low-resistance state, the opening of the storage unit 10 where it is located can be achieved.

[0072] The structures and operating principles of the selector S and the capacitor C are briefly described below.

[0073] Schematically, referring to Figure 7 As shown, the selector S includes a first electrode and a second electrode arranged opposite to each other, and a resistive switching layer located between the first electrode and the second electrode. Among them, the resistive switching layer has the characteristic of resistance change. The resistive switching layer is in a high-resistance state or a low-resistance state with the change of the voltage applied across the first electrode and the second electrode. That is to say, with the change of the voltage applied across the first electrode and the second electrode, the selector S is equivalent to a high-resistance device or a low-resistance device, so as to be able to conduct or block the current on the path, and further be able to meet the opening and closing of the storage unit 10 where it is located.

[0074] Schematically, taking the capacitor C as a ferroelectric capacitor as an example. Referring to Figure 8As shown, the capacitor C includes a third electrode and a fourth electrode disposed opposite to each other, and a ferroelectric layer located between the third electrode and the fourth electrode. The polarization direction of the ferroelectric layer is reversed as the electric field between the third electrode and the fourth electrode changes, that is, the polarization direction is reversible, and different polarization directions correspond to different information states. The storage unit 10 uses the polarization direction of the ferroelectric layer in the ferroelectric capacitor C to store information. For example, when the polarization direction of the ferroelectric layer in the ferroelectric capacitor C is positive, the stored information is "0"; when the polarization direction of the ferroelectric layer in the ferroelectric capacitor C is negative, the stored information is "1". Another example is that when the polarization direction of the ferroelectric layer in the ferroelectric capacitor C is positive, the stored information is "1"; when the polarization direction of the ferroelectric layer in the ferroelectric capacitor C is negative, the stored information is "0".

[0075] It can be understood that the capacitor C uses a ferroelectric capacitor, which can have good compatibility with the silicon-based semiconductor process, so that it can be fabricated using a mature manufacturing process without increasing the manufacturing cost. The following embodiments are all described by taking this as an example.

[0076] In the traditional three-dimensional storage architecture, the devices (transistors and capacitors) in the storage unit are arranged in a vertical stack (i.e., in the direction perpendicular to the substrate), and the signal lines (word line, bit line, etc.) connected to the storage unit are arranged parallel to the substrate. In this case, the multi-layer stacked storage units need to be fabricated using independent processes (such as photolithography processes), resulting in problems such as high manufacturing costs.

[0077] In contrast, in the storage array provided in the embodiments of the present application, the selector S and the capacitor C in the storage unit 10 are stacked in a horizontal direction (i.e., in the direction parallel to the substrate 1) ( Figure 5 ), and among the two signal lines (La, Lb) connected to the storage unit 10, one is arranged perpendicular to the substrate 1 and the other is arranged parallel to the substrate 1. In this case, the laterally stacked film layers can be prepared by an isotropic deposition method to form the selector S and the capacitor C stacked in the horizontal direction. In this way, the multi-layer storage units stacked can be fabricated through a single manufacturing process (the specific manufacturing method can be referred to below), so that the manufacturing cost (such as the photolithography cost) of the storage array does not increase correspondingly as the number of storage unit layers increases, and thus the purpose of reducing the manufacturing cost can be achieved, which is more conducive to realizing high-density storage.

[0078] Schematically, in some possible implementation manners, the projections of the multi-layer storage units 10 stacked on the substrate 1 may overlap, that is, the multiple storage units located in the lower layer are respectively aligned with the multiple storage units located in the upper layer, so as to achieve the purpose of simplifying the manufacturing process and reducing the manufacturing cost. For specific details, reference can be made to the relevant descriptions below.

[0079] The stacking manner of the selector S and the capacitor C arranged horizontally in the storage unit 10 will be described below.

[0080] Schematically, referring to Figure 4 and Figure 5 and Figure 6 as described, in some possible implementation manners, the storage unit 10 includes a first metal wire 101, a ferroelectric layer 102, a first metal layer 103, and a resistive switching layer 104 that are stacked in sequence horizontally. Among them, one end (the right end) of the first metal wire 101 is connected to the second signal line Lb, and the other end (the left end) of the first metal wire 101 is connected to the first signal line La arranged in the same layer through the ferroelectric layer 102, the first metal layer 103, and the ferroelectric layer 102 in sequence.

[0081] In this case, referring to Figure 5 as shown, the first signal line La, the first metal layer 103, and the resistive switching layer 104 stacked horizontally therebetween can form the selector S. The first signal line La and the first metal layer 103 are equivalent to the two electrodes of the selector S. The resistive switching layer 104 can be switched between a high-resistance state and a low-resistance state under the voltage control of the first signal line La and the first metal layer 103. The voltage on the first metal layer 103 can be controlled through the second signal line La. The first metal layer 103, the first metal wire 101, and the ferroelectric layer 102 stacked horizontally therebetween can form the capacitor C. The first metal layer 103 and the first metal wire 101 are equivalent to the two electrodes of the capacitor C. The polarization direction of the ferroelectric layer 102 is reversed with the change of the electric field between the first metal layer 103 and the first metal wire 101, and the voltages on the first metal layer 103 and the first metal wire 101 can be controlled through the first signal line La and the second signal line Lb.

[0082] It should be understood that in the above storage unit 10, the first metal layer 103 serves as the common electrode of the selector S and the capacitor C, which can simplify the manufacturing process and reduce the manufacturing cost. However, the present application is not limited thereto. In some other possible implementation manners, the selector S and the capacitor C can adopt different electrode layers.

[0083] In addition, according to the actual needs of the storage unit 10, other film layers can also be provided in the stack formed by the first signal line La, the resistive switching layer 104, and the first metal layer 103, and other film layers can also be provided in the stack formed by the first metal layer 103, the ferroelectric layer 102, and the first metal wire 101. The present application does not limit this.

[0084] Regarding the setting of the above resistive switching layer 104 and the first signal line La:

[0085] Schematically, in some possible implementation manners, referring toFigure 5 and Figure 9 As shown in Figure 9 , when fabricating the resistive switching layer 104 and the first signal line La, a lateral trench 21 with an opening facing left (i.e., away from the capacitor C) can be formed first (i.e., the depth direction of the trench 21 is parallel to the substrate 1). The resistive switching layer 104 is deposited on the bottom and sidewalls of the trench 21 first, and then the first signal line La is filled inside the resistive switching layer 104. In this way, the resistive switching layer 104 can cover the right surface of the first signal line La (i.e., the surface close to the first metal line 101) and the upper and lower surfaces in the direction perpendicular to the substrate 1. The specific fabrication process of the resistive switching layer 104 and the first signal line La can be referred to in the following text.

[0086] Figure 9 The cross-sectional position of Figure 9 is for clearly showing the internal structure of the memory cell. For subsequent other similar drawings (such as Figure 11 , Figure 16 , Figure 17 ), it is the same.

[0087] It should be noted here that the "coverage" relationship between the two involved in this application only refers to the coverage of regions, and does not limit whether the two are in contact. For example, for the resistive switching layer 104 covering the surface of the first signal line La, the resistive switching layer 104 may be in direct contact with the first signal line La, may not be in contact, or there may be other film layers between them. This application does not make any restrictions on this, and it can be designed according to the functional requirements of the device in practice.

[0088] As shown schematically in reference to Figure 9 Figure 9 , the resistive switching layer 104 in the multi-layer memory cell 10 can be fabricated through one manufacturing process, that is, the resistive switching layer 104 in the multi-layer memory cell 10 can be obtained through one lithography process. The specific fabrication process can be referred to the manufacturing method in the following text.

[0089] As shown schematically in reference to Figure 9 Figure 9 , the multi-layer first signal line La connected to the multi-layer memory cell 10 can be fabricated through one manufacturing process, that is, the multi-layer first signal line La can be obtained through one lithography process. The specific fabrication process can be referred to the manufacturing method in the following text.

[0090] Regarding the settings of the above first metal line 101, ferroelectric layer 102, and first metal layer 103:

[0091] In some possible implementation manners, referring to Figure 5 and Figure 9As shown, when fabricating the first metal layer 103, ferroelectric layer 102, and first metal wire 101, a lateral hole 22 with an opening facing right (i.e., away from the selector S) can be formed first (i.e., the depth direction of the hole is parallel to the substrate 1). The first metal layer 103 and ferroelectric layer 102 are sequentially deposited on the bottom and side walls of the hole 22. Then, the inside of the ferroelectric layer 102 is filled with metal to form the first metal wire 101. In this way, the ferroelectric layer 102 and the first metal layer 103 can extend from the end face (left end) of the first metal wire 101 to cover the side of the first metal wire 101, thereby increasing the area of the capacitor C, and further increasing the capacitance of the capacitor C. The specific fabrication process of the first metal layer 103, ferroelectric layer 102, and first metal wire 101 can be referred to in the following text.

[0092] It can be understood that by increasing the area of the capacitor C, the relative area of the selector S can be reduced. In this way, when operating the memory cell 10, at the moment of applying the operating voltage, the selector S can obtain a larger voltage division, so that it can be instantaneously turned on. The turned-on selector S is in a low-resistance state, causing most of the voltage to fall on the capacitor C, thereby accelerating the polarization reversal speed of the ferroelectric layer 102 in the ferroelectric capacitor C, and further accelerating the read / write speed of the memory cell.

[0093] Schematically, refer to Figure 9 As shown, the first metal wire 101 in the multi-layer memory cell 10 can be fabricated through a single fabrication process, that is, the first metal wire 101 in the multi-layer memory cell 10 can be obtained through a single lithography process. The specific fabrication process can be referred to the fabrication method in the following text.

[0094] Schematically, refer to Figure 9 As shown, the ferroelectric layer 102 in the multi-layer memory cell 10 can be fabricated through a single fabrication process, that is, the ferroelectric layer 102 in the multi-layer memory cell 10 can be obtained through a single lithography process. The specific fabrication process can be referred to the fabrication method in the following text.

[0095] Schematically, refer to Figure 9 As shown, the first metal layer 103 in the multi-layer memory cell 10 can be fabricated through a single fabrication process, that is, the first metal layer 103 in the multi-layer memory cell 10 can be obtained through a single lithography process. The specific fabrication process can be referred to the fabrication method in the following text.

[0096] This application does not limit the specific materials used for the above-mentioned first signal line La, second signal line Lb, first metal wire 101, ferroelectric layer 102, first metal layer 103, and resistive switching layer 104. In practice, it can be set according to needs as long as it can meet the requirements of the memory array.

[0097] Schematically, the first signal line La, the second signal line Lb, the first metal line 101, and the first metal layer 103 can be made of one or more conductive materials such as metal, metal nitride, metal carbide, conductive metal nitride, conductive metal oxide, etc.

[0098] For example, in some possible implementations, the first signal line La, the second signal line Lb, the first metal line 101, and the first metal layer 103 can be made of titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), titanium carbonitride (TiCN), tantalum carbonitride (TaCN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), iridium (Ir), ruthenium oxide (RuO 2 ), niobium nitride (NbN), molybdenum nitride (MoN), iridium oxide (IrO 2 ), silicon (Si), germanium (Ge), silicon germanium (SiGe), or a combination thereof.

[0099] The materials forming the first signal line La, the second signal line Lb, the first metal line 101, and the first metal layer 103 can be the same or different, and this application does not limit this. In practice, it can be set according to needs.

[0100] Schematically, the ferroelectric layer 102 can be made of ferroelectric materials, antiferroelectric materials, etc.

[0101] For example, in some possible implementations, the ferroelectric layer 102 can be made of hafnium oxide-based ferroelectric materials.

[0102] The above hafnium oxide-based materials can be ferroelectric materials of the hafnium oxide (hafnium oxide, HfO) material system, such as zirconium (Zr)-doped hafnium dioxide (HfO 2 ), silicon (Si)-doped HfO 2 , aluminum (Al)-doped HfO 2 , lanthanum (La)-doped HfO 2 , yttrium (Y)-doped HfO 2 , gadolinium (Gd)-doped HfO 2 , strontium (Sr)-doped HfO 2 , etc.

[0103] The above hafnium oxide-based materials can also be ferroelectric materials of the hafnium zirconium oxide (HZO) material system, such as lanthanum (La)-doped HZO, yttrium (Y)-doped HZO, strontium (Sr)-doped HZO, gadolinium (Gd)-doped HZO, gadolinium / lanthanum (Gd / La) co-doped HZO, etc. The doping elements can also be one or more of nitrogen, iron, lutetium, praseodymium, germanium, scandium, cerium, neodymium, magnesium, barium, indium, gallium, calcium, carbon.

[0104] The above hafnium-based oxide materials may also be ferroelectric materials such as hafnium silicon oxide, hafnium aluminum oxide, hafnium lanthanum oxide, hafnium zirconium lanthanum oxide, hafnium zirconium cerium oxide, hafnium zirconium yttrium oxide, hafnium zirconium gadolinium oxide, etc.

[0105] For another example, in some possible implementations, the ferroelectric layer 102 may adopt a scandium (Sc)-doped aluminum nitride (AlN) material.

[0106] The above resistive switching layer 104 may adopt a material or device with resistive switching characteristics.

[0107] Illustratively, in some possible implementations, the resistive switching layer 104 may include one or more materials with resistive switching characteristics among silicon or silicon compounds, germanium or germanium compounds, metal oxides, materials with metal-insulator transition characteristics, phase change materials, mixed ionic-electronic conductor materials, perovskite-type composite oxides, solid electrolytes, or organic polymers.

[0108] For example, in some embodiments, the material forming the resistive switching layer 104 may include silicon (Si) or silicon compounds, germanium (Ge) or germanium compounds, or any combination thereof. Among them, silicon compounds may include, for example, silicon sulfide, silicon oxide, silicon nitride, silicon carbide, etc., and germanium compounds may include, for example, germanium sulfide, germanium oxide, germanium nitride, germanium carbide, etc.

[0109] For another example, in some embodiments, the material forming the resistive switching layer 104 may include metal oxides.

[0110] Illustratively, the above metal oxides may include tantalum oxide (Ta 2 O 5 ), niobium oxide (Nb 2 O 5 ), titanium dioxide (TiO 2 ), hafnium dioxide (HfO 2 ), or indium gallium zinc oxide (IGZO), etc., at least one of the materials.

[0111] Illustratively, the above metal oxides may include lanthanide oxides, that is, oxides containing lanthanide elements, such as lanthanum oxide (La 2 O 3 ), praseodymium oxide (Pr 6 O 11 ), etc.

[0112] For another example, in some embodiments, the material forming the resistive switching layer 104 may include materials with metal-insulator transition characteristics.

[0113] The above-mentioned metal-insulator transition (MIT) refers to the physical transition from a metal conductor to a non-conductive insulator (or semiconductor), or from an insulator to a conductor. The material of the resistive switching layer 104 has the characteristic that the resistance decreases non-linearly with the increase of voltage. Therefore, the material of the resistive switching layer 104 in the embodiments of the present application has the characteristics of being an insulator at low voltage and a metal at high voltage.

[0114] Illustratively, the above-mentioned MIT material may include vanadium dioxide (VO 2 ), niobium dioxide (NbO 2 ), titanium dioxide (TiO 2 ), tungsten dioxide (WO 2 ), etc., at least one of the materials.

[0115] For another example, in some embodiments, the material forming the resistive switching layer 104 may include a phase change material, which refers to a material having low resistance performance in the crystalline state and high resistance performance in the non-crystalline state.

[0116] For another example, in some embodiments, the material forming the resistive switching layer 104 may include a mixed ionic-electronic conductor (MIEC) material.

[0117] Among them, the MIEC material refers to a type of conductor in which ionic conduction and electronic conduction coexist. The MIEC material is also called a mixed conductor material, which is a type of solid material between ionic conductors and electronic conductors, and it has both ionic conductivity and electronic conductivity at the same time.

[0118] For another example, in some embodiments, in some embodiments, the material forming the resistive switching layer 104 may include a perovskite-type composite oxide.

[0119] The general formula of the above-mentioned perovskite-type composite oxide is ABO 3 . The perovskite-type composite oxide is a new type of inorganic non-metallic material with unique physical and chemical properties. The A site is generally a rare earth or alkaline earth element ion, and the B site is a transition element ion. Both the A site and the B site can be partially replaced by other metal ions with similar radii while maintaining the basic crystal structure unchanged.

[0120] Illustratively, the above-mentioned perovskite-type composite oxide may include doped strontium titanate (SrTiO 3 ), barium titanate (BaTiO 3 ), lanthanum manganite (LaMnO 3 ), etc., at least one of the materials.

[0121] For another example, in some embodiments, the material forming the resistive change layer 104 includes a solid electrolyte, which is a type of object that exhibits ionic conductivity in the solid state (i.e., below the melting point).

[0122] Illustratively, the above solid electrolyte may be germanium sulfide (Ge x S y ), silver sulfide (Ag 2 S), copper sulfide (Cu 2 S), etc. sulfides, silver iodide (AgI), rubidium silver iodide (RbAg 4 I 5 ), etc. iodides, germanium selenide (Ge x Se y ), etc. selenides, germanium telluride (Ge x Te y ), antimony telluride (Sb x Te y ), germanium antimony telluride alloy (GeSbTe), silver indium antimony telluride alloy (AgInSbTe), etc. tellurides.

[0123] For another example, in some embodiments, the material forming the resistive change layer 104 may include an organic polymer.

[0124] Illustratively, the above organic polymer may include at least one of materials such as poly ethylmethacrylate (PEMA), polyazomethine (PAM), polytriphenylamine (PTPA), or poly[2,7-(9,9-dihexylfluorene)]-block-polypendentisoindigo (PF 14 -b-Piso n ).

[0125] In some other possible implementations, the resistive change layer 104 may be an element with resistive change characteristics (i.e., a resistive change element), and the resistive change layer 104 exhibits a high resistance state or a low resistance state according to the magnitude of the applied voltage or current. For example, when the voltage applied to the resistive change layer 104 exceeds the threshold voltage (e.g., 1 / 2Vcc), the resistive change layer 104 is in the low resistance state. When the voltage applied to the resistive change layer 104 is less than the threshold voltage, the resistive change layer 104 is in the high resistance state.

[0126] Illustratively, the resistive change element in the resistive change layer 104 may be a PNP junction, an NPN junction, a back-to-back Schottky junction, an ovonic threshold switching (OST), etc.

[0127] For example, in some embodiments, the resistive change layer 104 may be a bi-directional threshold switch (OST) element and include a chalcogenide-based material such as arsenic telluride (As 2 Te 3 ), arsenic (As 2 ), or arsenic selenide (As 2 Se 3 ), or include TiO 2 , titanium suboxide (Ti 4 O 7 ), tantalum dioxide (TaO 2 ), tantalum pentoxide (Ta 2 O 5 ), nickel peroxide (NiO 2 ), HfO 2 , Ge, Sb, Te, etc.

[0128] In addition, the above-mentioned first signal line La, second signal line Lb, first metal line 101, ferroelectric layer 102, first metal layer 103, and resistive change layer 104 may be single-layer structures or multi-layer structures, and the present application does not limit this, and can be set according to needs in practice.

[0129] The following further describes the storage array provided by the embodiment of the present application in combination with the manufacturing method of the storage array.

[0130] Illustratively, the embodiment of the present application provides a manufacturing method of a storage array. As Figure 10 shown, the manufacturing method may include:

[0131] Step 10, as shown in (a) and (b) in Figure 11 , a stacked structure 12 is fabricated on the substrate 1. Among them, the stacked structure 12 includes a plurality of first insulating layers A1 and a plurality of second insulating layers A2 that are alternately stacked.

[0132] Illustratively, in some possible implementation manners, the above-mentioned stacked structure 12 may be in a comb shape, and each film layer in the stacked structure 12 is in a comb shape and includes a connecting portion a and a plurality of comb teeth portions b connected to the connecting portion a.

[0133] The present application does not limit the materials used for the first insulating layer A1 and the second insulating layer A2, as long as the first insulating layer A1 and the second insulating layer A2 use different insulating materials and can meet the selective etching of the first insulating layer A1 in the subsequent step 20. For example, the first insulating layer A1 may use silicon nitride Si 3 N 4 , and the second insulating layer A2 may use silicon oxide SiO 2 .

[0134] Schematically, in some possible implementations, step 10 above may include: referring to Figure 11 as shown in (a) therein, using Si 3 N 4 and SiO 2 , multiple Si 3 N 4 layers (A1) and multiple SiO 2 layers (A2) are alternately grown on the substrate 1 in sequence to form an initial stacked structure 11. Then, referring to Figure 11 as shown in (b) therein, using a photolithography mask and a dry etching process, the initial stacked structure 11 is etched to the substrate 1 to form a comb-shaped stacked structure 12.

[0135] Step 20, referring to Figure 11 as shown in (c) therein, removing the multiple first insulating layers A1 in the stacked structure 12, fabricating a first signal line La, a selector S, and a capacitor C in the removal area of each first insulating layer, and forming a second signal line Lb perpendicular to the substrate 1 on the side of the stacked structure 12. Among them, the selector S and the capacitor C are arranged along the direction parallel to the substrate 1 and are used to form a storage unit 10, and the selector S and the capacitor C are serially coupled between the first signal line La and the second signal line Lb, the second signal line Lb is coupled to multiple stacked storage units 10, and the first signal line La is coupled to multiple storage units 10 arranged in the same layer.

[0136] Schematically, when the stacked structure 12 is comb-shaped, step 20 above may include: removing the multiple first insulating layers A1 in the comb-shaped stacked structure 12, fabricating the first signal line La and the selector S stacked in the direction parallel to the substrate 1 in the removal area of the connection part a in the first insulating layer A1, fabricating the capacitor C stacked with the selector S in the direction parallel to the substrate 1 in the removal area of multiple comb teeth parts b in the first insulating layer A1, and fabricating the second signal line Lb perpendicular to the substrate 1 at the end of the comb teeth part b.

[0137] It should be understood that in this application, by removing the first insulating layer A1 (including the connection part and the comb teeth part) of the stacked structure 12, fabricating the selector S in the removal area of the connection part a, and fabricating the capacitor C in the removal area of the comb teeth part b, in this way, the selector S and the capacitor C can be self-aligned without photolithography alignment, further saving the photolithography cost and also avoiding the alignment deviation (overlap) problem that may occur in the photolithography alignment process.

[0138] In step 20 above, by removing the first insulating layer A1 to fabricate the storage unit 10 and the first signal line La and the second signal line Lb connected thereto, a suitable fabrication process can be selected according to actual needs, and this application does not limit this.

[0139] Schematically, refer to Figure 12 As shown, in some possible implementation manners, on the basis of forming the comb-shaped stacked structure 12 through step 10, the above step 20 may include step 201, step 202, step 203, step 204, step 205, which are specifically as follows:

[0140] Step 201, refer to Figure 13 As shown in (a) to (b) in, the gaps in the stacked structure 12 are filled with a first insulating material K1 to form a filling structure 13.

[0141] The above first insulating material K1 may be the same as the insulating material used for the second insulating layer A2, but it is not limited thereto, and it can be set according to the selection in practice.

[0142] Schematically, in some possible implementation manners, after the stacked structure 12 is formed through step 10, step 201 can be used to fill the regions such as the gaps between the comb teeth b and the side surfaces in the stacked structure 12 with SiO 2 (K1) by chemical vapor deposition (CVD) process, and after the deposition is completed, chemical mechanical planarization (CMP) process is used for planarization to form the filling structure 13.

[0143] Step 202, refer to Figure 14 As shown, the connecting parts a in the plurality of first insulating layers A1 are removed to form a plurality of grooves 21 on the side surface M1 of the filling structure 13.

[0144] Schematically, in some possible implementation manners, the above step 202 may include: refer to Figure 14 As shown in (a) in, on one side (position E1) close to the connecting part a, etching is performed from the top of the filling structure 13 downward to the surface of the substrate 1 (such as dry etching) to remove the part of the connecting part a far from the comb tooth b side. At this time, the remaining connecting parts a will be exposed on the side surface. Then, refer to Figure 14 As shown in (b) in, from the side surface M1 (i.e., the etched surface) of the filling structure 13, the remaining connecting parts a are removed (recess) by etching (such as wet etching) to form a plurality of grooves 21 on the side surface M1 of the filling structure 13.

[0145] Step 203, refer to Figure 15 As shown, a resistive switching layer 104 and a first signal line La are sequentially formed in the plurality of grooves 21, and the side surface where the first signal line La is located is covered with a second insulating material K2.

[0146] The above-mentioned second insulating material K2 may be the same as the insulating material used for the second insulating layer A2, but it is not limited thereto. In practice, it can be set according to the selection.

[0147] Illustratively, in some possible implementation manners, the above step 203 may include: Referring to Figure 15 As shown in (a), a chemical vapor deposition (CVD) process or an atomic layer deposition (ALD) process may be used to first fill the trench 21 with a resistive material (such as TiO2) to form a resistive layer 104, and then fill it with a metal material (such as TiN) to form first signal lines La that are distributed in multiple layers and arranged in parallel. Next, referring to Figure 15 As shown in (b), a chemical vapor deposition (CVD) process may be used to fill SiO 2 (K2) on one side of the first signal line La, and a chemical mechanical polishing (CMP) process is used for planarization.

[0148] Step 204, referring to Figure 16 As shown, the comb-shaped portions b in the multiple first insulating layers A1 are removed to form multiple holes 22.

[0149] Illustratively, in some possible implementation manners, the above step 205 may include: Referring to Figure 16 As shown, a photolithography mask and a dry etching process are used to remove the comb-shaped portions b from the side surface M2 (the end face of the end of the comb-shaped portion b) of the filling structure 13 to form multiple holes 22, and the resistive layer 104 is exposed at the bottom of the holes 22.

[0150] Step 205, referring to Figure 17 As shown, a first metal layer 103, a ferroelectric layer 102, and a first metal wire 101 are sequentially formed in the multiple holes 22, and a second signal line Lb connected to the first metal wire 101 is formed on the opening side of the holes 22.

[0151] Illustratively, in some possible implementation manners, the above step 205 may include step 2051, step 2052, and step 2053, specifically as follows:

[0152] Step 2051: Referring to Figure 17 As shown in (a), a metal material is deposited in the multiple holes 22 to form a first metal layer 103.

[0153] Illustratively, in some possible implementation manners, step 2051 may include: Using an atomic layer deposition (ALD) process to deposit a metal material (such as TiN) in the multiple holes 22 to form a first metal layer 103, and using an etching process (such as dry etching) to remove (recess) the metal material deposited on the surface (M2) of the opening side of the holes 22.

[0154] Step 2052: Refer to Figure 17 As shown in (b) of , deposit a ferroelectric layer 102 in the hole 22 formed with the first metal layer 103.

[0155] Illustratively, in some possible implementation manners, step 2052 may include: using an atomic layer deposition (ALD) process, deposit a ferroelectric material (such as HZO) in the hole 22 formed with the first metal layer 103 to form the ferroelectric layer 102. Of course, the ferroelectric material may extend to cover the surface (M2) on the opening side of the hole 22, and the present application does not limit this.

[0156] Step 2053: Refer to Figure 17 As shown in (b) and (c) of , deposit a metal material in the hole 22 formed with the ferroelectric layer, form a first metal wire 101 in the hole 22, and at the same time form a metal thin film 101a on the surface (M2) on the opening side of the hole 22, and etch the metal thin film 101a to form a plurality of second signal lines Lb.

[0157] Illustratively, in some possible implementation manners, step 2053 may include: Refer to Figure 17 As shown in (b) of , use an atomic layer deposition (ALD) process to deposit a metal material (such as TiN, W) in the hole 22 formed with the ferroelectric layer 102 to form the first metal wire 101, and form a metal thin film 101a on the surface (M2) on the opening side of the hole 22; next, refer to Figure 17 As shown in (c) of , use a photolithography mask and a dry etching process to etch the metal thin film 101a to form a plurality of second signal lines Lb that are parallel to each other and perpendicular to the substrate 1. That is to say, the first metal wire 101 and the second signal lines Lb are prepared by one process.

[0158] It should be understood that the resistive switching layer 104 and the first signal line La formed in step 203 are located in the removal area of the connection part a; the first metal layer 103, the ferroelectric layer 102, and the first metal wire 101 formed in step 205 are located in the removal area of the comb-shaped part b, and the connection part a and the comb-shaped part b are located in the same layer and are connected, so as to ensure that the first metal layer 103, the ferroelectric layer 102, and the first metal wire 101 are self-aligned with the resistive switching layer 104, that is, the self-alignment of the capacitor C and the selector S is realized.

[0159] In summary, adopting the above manufacturing method, the manufacturing of the multi-layer memory cell 10 is completed through one manufacturing process, so that the manufacturing cost (such as the lithography cost) of the memory array does not increase correspondingly with the increase in the number of memory cell layers, and thus the purpose of reducing the manufacturing cost can be achieved, which is more conducive to realizing high-density storage.

[0160] It should be noted that the foregoing manufacturing method is described by taking the manufacturing based on a comb-shaped stacked structure 12 as an example. In practice, in step 10, by etching the stacked structure of multiple first insulating layers A1 and multiple second insulating layers A2, multiple comb-shaped stacked structures 12 are formed, so that multiple storage modules can be obtained in subsequent manufacturing. One comb-shaped stacked structure 12 corresponds to one storage module.

[0161] Figure 18 The top view of a storage array provided by an embodiment of the present application. Figure 19 The side view of a storage array provided by an embodiment of the present application.

[0162] Refer to Figure 18 and Figure 19 As shown, in some possible implementation manners, the storage array provided by the embodiment of the present application has multiple storage modules U. One storage module U is manufactured based on a comb-shaped stacked structure 12, that is, one storage module U includes multiple layers of stacked storage units 10, multiple first signal lines La (X direction), and multiple second signal lines Lb (Z direction). The specific manufacturing process can refer to the foregoing content.

[0163] The layout of multiple storage modules U can be designed according to needs, and the present application does not limit this.

[0164] Schematically, in some possible implementation manners, refer to Figure 18 and Figure 19 As shown, in the storage array, two adjacent storage modules U can be arranged with their comb teeth portions facing each other or their connection portions facing each other. The present application does not limit this. In practice, the storage modules U can be arranged according to needs.

[0165] It should be understood that the magnitudes of the sequence numbers of the foregoing processes do not mean the order of execution. The order of execution of each process should be determined according to its function and internal logic, and should not constitute any limitation to the implementation process of the embodiment of the present application.

[0166] For other related contents in the foregoing manufacturing method, the corresponding parts in the foregoing storage array structure embodiment can be referred to correspondingly, and will not be elaborated here; for other setting structures in the foregoing storage array structure embodiment, they can be adjusted by referring to the foregoing manufacturing method and related manufacturing methods, and will not be elaborated one by one here.

[0167] The above is only the specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present application can easily think of changes or substitutions, which should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claimed rights.

Claims

1. A storage array, characterized in that, it includes: a substrate; a plurality of first signal lines and a plurality of second signal lines disposed on the substrate; the extending direction of the first signal lines is parallel to the substrate, and the extending direction of the second signal lines is perpendicular to the substrate; a plurality of layers of storage units vertically stacked on the substrate; the storage units include a selector and a capacitor disposed along a direction parallel to the substrate, and the selector and the capacitor are serially coupled between the first signal line and the second signal line; wherein, the second signal line is coupled to a plurality of the stacked storage units, and the first signal line is coupled to a plurality of the storage units disposed in the same layer.

2. The storage array according to claim 1, characterized in that, the capacitor is a ferroelectric capacitor.

3. The storage array according to claim 1 or 2, characterized in that, the projections of the plurality of layers of storage units on the substrate overlap.

4. The storage array according to any one of claims 1-3, characterized in that, the storage unit includes: a first metal line, a ferroelectric layer, a first metal layer, and a resistive switching layer stacked in sequence along a direction parallel to the substrate; a first end of the first metal line is connected to the second signal line, and a second end of the first metal line is connected to the first signal line through the ferroelectric layer, the first metal layer, and the resistive switching layer disposed in sequence, and the first metal line and the first signal line are in the same layer; the first metal line, the ferroelectric layer, and the first metal layer are used to form the capacitor; the first signal line, the resistive switching layer, and the first metal layer are used to form the selector.

5. The storage array according to claim 4, characterized in that, the storage array includes: a hole, the depth direction of the hole is parallel to the substrate; the ferroelectric layer and the first metal layer cover the bottom and side walls of the hole, and the first metal layer is located inside the ferroelectric layer; the first metal line is filled inside the first metal layer.

6. The storage array according to claim 4 or 5, characterized in that, the storage array includes: a trench, the depth direction of the trench is parallel to the substrate; the resistive switching layer covers the bottom and side walls of the trench, and the first signal line is filled inside the resistive switching layer.

7. The storage array according to any one of claims 1-6, characterized in that, a plurality of the first signal lines connected to the plurality of stacked storage units are parallelly stacked and fabricated by the same lithography process.

8. The storage array according to any one of claims 1-7, characterized in that, a plurality of the second signal lines connected to the plurality of stacked storage units are parallelly disposed and fabricated by the same lithography process.

9. The storage array according to any one of claims 4-8, characterized in that, the first metal line, the ferroelectric layer, the first metal layer, and the resistive switching layer in the plurality of layers of storage units are respectively fabricated by the same lithography process.

10. The storage array according to any one of claims 4-9, Characterized in that, the resistive switching layer can be switched between a high resistance state and a low resistance state under the voltage applied between the first signal line and the second signal line.

11. The memory array according to any one of claims 4-10, Characterized in that, the resistive switching layer includes at least one of silicon or silicon compound, germanium or germanium compound, metal oxide, material with metal-insulator transition characteristics, mixed ionic-electronic conductor material, perovskite-type composite oxide, solid electrolyte or organic polymer.

12. The memory array according to any one of claims 4-10, Characterized in that, the resistive switching layer includes a PNP junction or an NPN junction.

13. The memory array according to any one of claims 4-12, Characterized in that, the ferroelectric layer includes a hafnium oxide-based ferroelectric material or AlN-doped Sc.

14. A method for manufacturing a memory array, Characterized in that, comprising: forming a stacked structure on a substrate; wherein, the stacked structure includes a plurality of first insulating layers and a plurality of second insulating layers alternately disposed in a direction perpendicular to the substrate; removing the plurality of first insulating layers in the stacked structure, manufacturing a first signal line, a selector, and a capacitor in the removal area of each first insulating layer, and forming a second signal line perpendicular to the substrate on a side surface of the stacked structure; wherein, the selector and the capacitor are disposed along a direction parallel to the substrate and form a memory cell, and the selector and the capacitor are serially coupled between the first signal line and the second signal line, the second signal line is coupled to a plurality of the memory cells disposed in a stacked manner, and the first signal line is coupled to a plurality of the memory cells disposed on the same layer.

15. The method for manufacturing a memory array according to claim 14, Characterized in that, the forming a stacked structure on a substrate includes: alternately manufacturing a plurality of first insulating layers and a plurality of second insulating layers on the substrate, and etching the plurality of first insulating layers and the plurality of second insulating layers as a whole to form the stacked structure; wherein, the stacked structure is in a comb shape, and each film layer in the stacked structure includes a connecting portion and a plurality of comb teeth portions connected to the connecting portion; the removing the plurality of first insulating layers in the stacked structure, manufacturing a first signal line, a selector, and a capacitor in the removal area of each first insulating layer, and forming a second signal line perpendicular to the substrate on a side surface of the stacked structure includes: removing the plurality of first insulating layers in the stacked structure, manufacturing a first signal line and a selector in the removal area of the connecting portion in the first insulating layer, manufacturing the capacitors respectively in the removal areas of the plurality of comb teeth portions in the first insulating layer, and forming a second signal line perpendicular to the substrate at ends of the comb teeth portions.

16. The method for manufacturing a memory array according to claim 15, Characterized in that, Removing the plurality of first insulating layers in the stacked structure, fabricating a first signal line and a selector in a removal region of the connection portion in the first insulating layer, fabricating the capacitors in removal regions of the plurality of comb-shaped portions in the first insulating layer respectively, and forming a second signal line perpendicular to the substrate at an end of the comb-shaped portion, includes: Filling gaps in the stacked structure with a first insulating material to form a filling structure; Removing the connection portions in the plurality of first insulating layers to form a plurality of grooves on a side surface of the filling structure; Successively forming a resistive switching layer and the first signal line in the plurality of grooves, and covering a side surface where the first signal line is located with a second insulating material; Removing the comb-shaped portions in the plurality of first insulating layers to form a plurality of holes; Successively forming a first metal layer, a ferroelectric layer, and a first metal line in the plurality of holes, and forming a second signal line connected to the first metal line at an opening side of the holes.

17. The method for fabricating a memory array according to claim 16, wherein, the removing the connection portions in the plurality of first insulating layers to form a plurality of grooves on a side surface of the filling structure includes: Etching downward from a top of the filling structure to the substrate on a side close to the connection portion to remove a part of the connection portion on a side away from the comb-shaped portion; Removing the remaining connection portions by etching from a side surface of the filling structure to form a plurality of grooves.

18. The method for fabricating a memory array according to claim 16 or 17, wherein, the successively forming a first metal layer, a ferroelectric layer, and a first metal line in the plurality of holes, and forming a second signal line connected to the first metal line at an opening side of the holes includes: Depositing a metal material in the plurality of holes to form a first metal layer; Depositing a ferroelectric layer in the holes formed with the first metal layer; Depositing a metal material in the holes formed with the ferroelectric layer, forming a first metal line in the holes, and simultaneously forming a metal thin film on a surface of an opening side of the holes, and etching the metal thin film to form a plurality of the second signal lines.

19. The method for fabricating a memory array according to any one of claims 16 - 18, wherein, both the first insulating material and the second insulating material are the same as an insulating material in the second insulating layer.

20. A memory device, wherein, a controller and a memory array according to any one of claims 1 - 13, the memory array being electrically connected to the controller.

21. An electronic device, wherein, a circuit board and a memory device according to claim 20, the memory device being electrically connected to the circuit board.

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