Magnetic memory element and manufacturing method thereof

Abstract

The invention discloses a magnetic memory element and a manufacturing method thereof. The magnetic memory element comprises a substrate, a patterned conductive layer and a magnetic tunnel junction structure. The substrate includes a memory region and a circuit region. The patterned conductive layer comprises a first conductive pattern and a second conductive pattern which are isolated from each other. The first conductive pattern is located in the memory area and the second conductive pattern is located in the circuit area. The magnetic tunnel junction structure is located on the first conductive pattern and is in electrical contact with the first conductive pattern.

Description

Technical Field

[0001] The present invention relates to a memory element and a manufacturing method thereof, and particularly to a magnetic memory element and a manufacturing method thereof. Background Art

[0002] With the trend of miniaturization of various electronic devices, such as wearable devices and automotive chips, and in response to the future popularization of the Internet of Things (IoT) and the development of big data analysis technology, the control circuits of electronic devices have significantly increased requirements for the storage density and performance of built-in memory elements.

[0003] However, currently developed and mature static random access memory (SRAM) elements, dynamic random access memory (DRAM) elements, and flash memory elements have reached the development limits of size miniaturization and efficiency optimization. Therefore, providing a new generation of memory with small size, high storage density, fast read / write speed, energy saving, and non-volatility has become a key research topic in this field.

[0004] Magnetic memory elements, such as magnetoresistive random access memory (MRAM), are regarded as important new generation memory elements because of their advantages of fast read / write speed, non-volatility, and easy integration with semiconductor manufacturing processes. A typical magnetic random access memory element is generally formed between two interconnect metal layers (e.g., the second (M2) metal layer and the third (M3) metal layer) through a semiconductor back-end-of-line (BEOL) process and is not integrated with the manufacturing process of semiconductor control circuits (e.g., manufacturing). Multiple additional photomasks are required for multiple photolithography and etching processes. To embed the magnetic random access memory into the manufacturing process of semiconductor control circuits, additional costs will be incurred.

[0005] Therefore, there is a need to provide an advanced magnetic memory element and a manufacturing method thereof to solve the problems faced by the prior art. Summary of the Invention

[0006] According to an embodiment of the present specification, a magnetic memory device is disclosed, including: a substrate, a patterned conductive layer, a conductive pattern, and a magnetic tunneling junction (MTJ) structure. The substrate includes a memory region and a circuit region. The patterned conductive layer includes a first conductive pattern and a second conductive pattern isolated from each other. The first conductive pattern is located in the memory region, and the second conductive pattern is located in the circuit region. The magnetic tunneling junction structure is located on the first conductive pattern and is in electrical contact with the first conductive pattern.

[0007] According to another embodiment of the present specification, a method for manufacturing a magnetic memory device is disclosed, including the following steps: First, a substrate is provided, which includes a memory region and a circuit region. Then, a conductive layer is formed on the substrate. After that, a first magnetic layer, an insulating layer, and a second magnetic layer are sequentially formed on the conductive layer. Then, the conductive layer, the first magnetic layer, the insulating layer, and the second magnetic layer are patterned to form a first conductive pattern on the memory region and a magnetic tunneling junction structure located on the first conductive pattern; and a second conductive pattern is formed on the circuit region; wherein the second conductive pattern and the first conductive pattern are included in the patterned conductive layer and are isolated from each other.

[0008] According to the above embodiments, the present specification provides a magnetic memory device and a manufacturing method thereof. The manufacturing processes of spin-orbit torque magnetic random access memory cells and at least one resistive element in a semiconductor circuit of a magnetic memory device are integrated, such that the spin-orbit torque magnetic random access memory cells and the resistive elements share the same patterned conductive layer, thereby simplifying the manufacturing process steps of the magnetic memory device, saving the number of photomasks used in the manufacturing process, and significantly reducing the manufacturing cost of the magnetic memory device. In one embodiment, the patterned conductive layer may be a spin orbit torque (SOT) metal layer. Description of the Drawings

[0009] For a better understanding of the above and other aspects of the present specification, specific embodiments are hereinafter given and described in detail in conjunction with the accompanying drawings as follows:

[0010] Figures 1A to 1F is an embodiment of the present specification, showing a series of cross-sectional schematic diagrams of the manufacturing process for manufacturing a magnetic memory device; and

[0011] Figures 2A to 2F is another embodiment of the present specification, showing a series of cross-sectional schematic diagrams of the manufacturing process for manufacturing another magnetic memory device.

[0012] Symbol Description

[0013] 100: Magnetic memory element

[0014] 101: Substrate

[0015] 101A: Memory region

[0016] 101B: Circuit region

[0017] 102: Transistor cell

[0018] 102a: Gate structure

[0019] 102b: Source region

[0020] 102c: Drain region

[0021] 104: Interlayer dielectric layer

[0022] 103: Conductive layer

[0023] 105a: First magnetic layer

[0024] 105b: Insulating layer

[0025] 105c: Second magnetic layer

[0026] 105: Vertical magnetic tunneling junction structure

[0027] 109: Upper electrode layer

[0028] 109a: Tantalum metal layer

[0029] 109b: Ruthenium metal layer

[0030] 106: Bottom synthetic antiferromagnetic layer

[0031] 107: Coupling layer

[0032] 108: Upper synthetic antiferromagnetic layer

[0033] 109: Upper electrode layer

[0034] 110: Hard mask layer

[0035] 111: Insulating cover layer

[0036] 112: Interlayer dielectric layer

[0037] 113: Via plug

[0038] 114: Via plug

[0039] 115: Via plug

[0040] 116: Bit line

[0041] 117: External circuit

[0042] 119: Bridging layer

[0043] R1: Resistance unit

[0044] S1: Stacked structure

[0045] STT-MRAM: Spin-transfer torque magnetic random access memory cell

[0046] 200: Magnetic memory element

[0047] 201: Substrate

[0048] 201A: Memory area

[0049] 201B: Circuit area

[0050] 202: Transistor unit

[0051] 202a: Gate structure

[0052] 202b: Source region

[0053] 202c: Drain region

[0054] 204: Interlayer dielectric layer

[0055] 203: Conductive layer

[0056] 203a: First conductive pattern

[0057] 203b: Second conductive pattern

[0058] 205a: First magnetic layer

[0059] 205b: Insulating layer

[0060] 205c: Second magnetic layer

[0061] 205: Magnetic tunneling junction structure

[0062] 209: Upper electrode layer

[0063] 209a: Tantalum metal layer

[0064] 209b: Ruthenium metal layer

[0065] 206: Bottom synthetic antiferromagnetic layer

[0066] 207: Ruthenium coupling layer

[0067] 208: Upper synthetic antiferromagnetic layer

[0068] 209: Upper electrode layer

[0069] 210: Hard mask layer

[0070] 211: Insulating coating

[0071] 212: Interlayer dielectric layer

[0072] 213: Via plug

[0073] 214: Via plug

[0074] 215: Via plug

[0075] 216: Bit line

[0076] 217: External circuit

[0077] 218: Via plug

[0078] 219: Bridging layer

[0079] R2: Resistance unit

[0080] S2: Stacked structure

[0081] SOT-MRAM: Spin-orbit torque magnetic random access memory cell Detailed implementation manners

[0082] The present invention provides a magnetic memory element and a manufacturing method thereof, which can reduce the manufacturing cost when the magnetic memory element is embedded in a semiconductor circuit. In order to make the above embodiments, other purposes, features and advantages of this specification more obvious and understandable, multiple embodiments are specifically given below and detailed descriptions are made in conjunction with the accompanying drawings.

[0083] However, it must be noted that these specific implementation cases and methods are not used to limit the present invention. The present invention can still be implemented by using other features, elements, methods and parameters. The proposed preferred embodiments are only used to illustrate the technical features of the present invention and are not used to limit the claims of the present invention. Those of ordinary skill in the art can make equivalent modifications and changes within the spirit of the present invention according to the following description. In different embodiments and drawings, the same elements will be represented by the same element symbols.

[0084] Please refer to Figures 1A to 1F , Figures 1A to 1F which is a series of schematic cross-sectional diagrams of manufacturing processes for manufacturing a magnetic memory element 100 according to an embodiment of this specification. The manufacturing method of the magnetic memory element 100 includes the following steps: First, a substrate 101 is provided, which includes a memory area 101A and a circuit area 101B.

[0085] In some embodiments of the present specification, the substrate 101 may be a silicon-containing substrate, such as a silicon wafer, silicon-on-insulator (SOI) in an insulating layer, or other semiconductor substrates. In this embodiment, the substrate 101 may be a silicon wafer, and the memory region 101A of the substrate 101 may include (but is not limited to) a transistor unit 102, such as a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET). As Figure 1A shown, the transistor unit 102 includes a gate structure 102a, a source region 102b, and a drain region 102c.

[0086] Next, a conductive layer 103 is formed on the substrate 101. In some embodiments of the present specification, before forming the conductive layer 103, an interlayer dielectric layer (ILDs) 104 is first formed above the surface 101t of the substrate 101 through a deposition process, such as a chemical vapor deposition (CVD) process, covering the memory region 101A and the circuit region 101B. Then, a conductive layer 103 is formed on the interlayer dielectric layer 104 through a deposition process, such as a chemical vapor deposition (CVD) process (as Figure 1B shown). The material constituting the conductive layer 103 may include one of tantalum (Ta), tungsten (W), platinum (Pt), cobalt (Co), ruthenium (Ru), or a combination of the above. In this embodiment, the conductive layer 103 may be a tungsten metal layer.

[0087] After that, a first magnetic layer 105a, an insulating layer 105b, a second magnetic layer 105c, and an upper electrode layer 109 are sequentially formed on the conductive layer 103. In some embodiments of the present specification, the materials constituting the first magnetic layer 105a and the second magnetic layer 105c may include an iron-containing magnetic material, such as cobalt iron boron (CoFeB). In this embodiment, the first magnetic layer 105a and the second magnetic layer 105c have perpendicular magnetic anisotropy (PMA).

[0088] The material forming the insulating layer 105b may include magnesium oxide (MgO), amorphous aluminum oxide (AlOx), or amorphous hafnium oxide (HfOx). The conductive material forming the upper electrode layer 109 may include (but is not limited to) ruthenium, tantalum, platinum, copper (Cu), gold (Au), aluminum (Al), or any combination of the above. In this embodiment, the material forming the insulating layer 105b preferably includes magnesium oxide. The upper electrode layer 109 may be a laminated layer composed of a tantalum metal layer 109a and a ruthenium metal layer 109b.

[0089] In an embodiment of the present specification, after the second magnetic layer 105c is formed, a synthetic antiferromagnetic (SAF) structure may optionally be formed above the second magnetic layer 105c, and then the upper electrode layer 109 is formed. The bottom synthetic antiferromagnetic layer 106 is located between the second magnetic layer 105c and the upper electrode layer 109. Among them, the bottom synthetic antiferromagnetic layer 106 may be a periodic multi-layer laminated structure formed by stacking n cobalt / nickel (Co / Ni) layers alternately. Among them, n is greater than or equal to 1 (n≥1).

[0090] In this embodiment, another (upper) synthetic antiferromagnetic layer 108 may optionally be formed above the bottom synthetic antiferromagnetic layer 106 and connected to the bottom synthetic antiferromagnetic layer 106 through the coupling layer 107, so that the bottom synthetic antiferromagnetic layer 106, the coupling layer 107, and the upper synthetic antiferromagnetic layer 108 are combined to form a complete synthetic antiferromagnetic structure. The bottom synthetic antiferromagnetic layer 106, the coupling layer 107, and the upper synthetic antiferromagnetic layer 108 are located between the second magnetic layer 105c and the upper electrode layer 109 (as shown in FIG. 1C). Among them, the coupling layer 107 may include ruthenium (Ru). The structure and material of the upper synthetic antiferromagnetic structure 108 may be the same as or different from those of the bottom synthetic antiferromagnetic layer 106. The upper synthetic antiferromagnetic layer 108 may be a periodic multi-layer laminated structure formed by stacking m (for example, m is greater than or equal to 1 (m≥1)) cobalt / platinum (Co / Pt) layers alternately. Before the bottom synthetic antiferromagnetic layer 106 is formed, a bridging layer 119, such as a tungsten (W) metal layer with a thickness of about 0.3 nanometers (nm), may preferably be formed above the second magnetic layer 105c.

[0091] Then, a patterned hard mask layer 110 (e.g., made of silicon nitride) is used as an etching mask, with the conductive layer 103 as an etching stop layer, to etch the upper electrode layer 109, the upper synthetic antiferromagnetic layer 108, the coupling layer 107, the bottom synthetic antiferromagnetic layer 106, the second magnetic layer 105c, the insulating layer 105b, and the first magnetic layer 105a. A stacked structure S1 composed of a part of the remaining upper electrode layer 109, a part of the upper synthetic antiferromagnetic layer 108, a part of the coupling layer 107, a part of the bottom synthetic antiferromagnetic layer 106, a part of the second magnetic layer 105c, a part of the insulating layer 105b, and a part of the first magnetic layer 105a is formed above the memory region 101A; and a part of the conductive layer 103 above the circuit region 101B is exposed (at this time, the conductive layer 103 still covers above the circuit region 101B and the memory region 101A).

[0092] Among them, the second magnetic layer 105c, the insulating layer 105b, and the first magnetic layer 105a remaining above the memory region 101A together form a perpendicular magnetic tunneling junction (MTJ) structure 105 (as Figure 1D shown). The first magnetic layer 105a includes a ferromagnetic material that is not fixed or pinned in a specific magnetic orientation, and the magnetic direction of the ferromagnetic material in the first magnetic layer 105a can be rotated during the subsequent write process of the spin-transfer torque magnetic random access memory (STT-MRAM). The second magnetic layer 105c can serve as the free layer of the perpendicular magnetic tunneling junction structure 105, where the magnetization orientation of the second magnetic layer 105c can be fixed by the bottom synthetic antiferromagnetic layer 106, the coupling layer 107, and the upper synthetic antiferromagnetic layer 108, so that the magnetization orientations of the first magnetic layer 105a and the second magnetic layer 105c are in parallel or antiparallel directions; when the magnetization orientations of the first magnetic layer 105a and the second magnetic layer 105c are in the parallel direction (the perpendicular resistance reading parallel to the perpendicular magnetic tunneling junction is very small and is generally taken as the stored value = 0), when the magnetization orientations of the first magnetic layer 105a and the second magnetic layer 105c are in the antiparallel direction (the perpendicular resistance reading antiparallel to the perpendicular magnetic tunneling junction is very large and is generally taken as the stored value = 1).

[0093] The insulating layer 105b in the perpendicular magnetic tunneling junction structure 105 can serve as a tunneling barrier to block the free movement of electrons. However, it should be noted that although the bottom synthetic antiferromagnetic layer 106, the coupling layer 107, and the top synthetic antiferromagnetic layer 108 can be used to fix the magnetization direction of the second magnetic layer 105c. However, in the synthetic antiferromagnetic (SAF) structure, the magnetization directions of the bottom synthetic antiferromagnetic layer 106 and the top synthetic antiferromagnetic layer 108 are parallel or antiparallel, depending on the thickness of the coupling layer 107. The magnetization directions of the bottom synthetic antiferromagnetic layer 106 and the second magnetic layer 105c are parallel or antiparallel, depending on the thickness of the bridging layer 119 between the second magnetic layer 105c and the bottom synthetic antiferromagnetic layer 106.

[0094] After that, an insulating cover layer 111 is formed over the memory region 101A and the circuit region 101B, covering the stacked structure S1 and a part of the exposed conductive layer 103. Then, the insulating cover layer 111 and the conductive layer 103 are etched to remove a part of the insulating cover layer 111 and a part of the conductive layer 103 located in the memory region 101A, for forming a first conductive pattern 103a in the memory region 101A and a second conductive pattern 103b in the circuit region 101B. Among them, both the first conductive pattern 103a and the second conductive pattern 103b are included in the patterned conductive layer 103 and are isolated from each other.

[0095] In this embodiment, as Figure 1E shown, the stacked structure S1 is located above the first conductive pattern 103a, and the bottom size of the stacked structure S1 is substantially smaller than the area of the first conductive pattern 103a, so that a part of the first conductive pattern 103a does not overlap with the stacked structure S1. The perpendicular magnetic tunneling junction structure 105, together with the remaining part of the first conductive pattern 103a located below it, the upper electrode layer 109, the top synthetic antiferromagnetic structure 108, the coupling layer 107, and the bottom synthetic antiferromagnetic layer 106 located above it, jointly constitute a spin transfer torque (STT) magnetic random access memory cell STT-MRAM. The second conductive pattern 103b remaining on the circuit region 101B constitutes a resistance unit R1. In some embodiments, the part of the first conductive pattern 103a not covered by the stacked structure S1 can be completely removed.

[0096] Subsequently, a series of back-end manufacturing processes are performed through the back-end manufacturing process (BEOL). For example, a metal damascene process is performed to form an interlayer dielectric layer 112 covering the memory region 101A and the circuit region 101B, and a metal interconnect structure (including via plugs 113, 114, and 115) is formed to respectively penetrate through the interlayer dielectric layers 104 and 112 and / or the insulating cover layer 111. The upper electrode layer 109 of the spin-transfer torque magnetic random access memory cell STT-MRAM is electrically connected to the bit line 116 through the via plug 113; the spin-transfer torque magnetic random access memory cell STT-MRAM is electrically connected to the transistor cell 102 through the via plug 114. (For example, the first conductive pattern 103a of the spin-transfer torque magnetic random access memory cell STT-MRAM can be electrically connected to the drain region 102c of the transistor cell 102 through the via plug 114); and one end of the second conductive pattern 103b of the resistance unit R1 is electrically connected to the external circuit 117 through the via plug 115 (the other end of the second conductive pattern 103b is electrically connected to another electrode (not shown) through other wires), forming a semiconductor device 100 as shown in Figure 1F the illustrated.

[0097] Integrate the manufacturing processes of the vertical magnetic tunneling junction structure 105 of the spin-transfer torque magnetic random access memory cell STT-MRAM and at least one resistance unit R1 in the magnetic memory device 100, so that the spin-transfer torque magnetic random access memory cell STT-MRAM and the resistance unit R1 share the same patterned conductive layer 103. This simplifies the manufacturing process steps of the magnetic memory device 100, saves the number of photomasks used, and greatly reduces the manufacturing cost of the magnetic memory device 100.

[0098] Please refer to Figures 2A to 2F , Figures 2A to 2F FIG. is a schematic cross-sectional view of a series of manufacturing processes for manufacturing a magnetic memory device 200 according to an embodiment of the present specification. The manufacturing method of the magnetic memory device 200 includes the following steps: First, a substrate 201 is provided, which includes a memory region 201A and a circuit region 201B. In this embodiment, the substrate 201 can be a silicon wafer, and at least one transistor cell 202, such as a metal-oxide-semiconductor field-effect transistor (MOSFET), is included in the memory region 201A of the substrate 201. As shown in Figure 2A the illustration, the transistor cell 202 includes a gate structure 202a, a source region 202b, and a drain region 202c.

[0099] Next, a conductive layer 203 is formed on the substrate 201. In some embodiments of the present specification, before forming the conductive layer 203, an interlayer dielectric layer 204 is first formed on the surface 201t of the substrate 201 by a deposition process, such as a chemical vapor deposition process, covering the memory region 201A and the circuit region 201B. Then, a conductive layer 203 is formed on the interlayer dielectric layer 204 by a deposition process, such as a chemical vapor deposition process (as Figure 2B shown).

[0100] Among them, the conductive layer 203 can be a spin Hall metals layer (hereinafter referred to as a spin orbit torque (SOT) metal layer) that can generate a spin orbit torque (SOT) greater than 0.5. The materials constituting the conductive layer 203 include (but are not limited to) one of tantalum, tungsten, platinum, or a combination of the above. In this embodiment, the conductive layer 203 can be a platinum metal layer.

[0101] After that, a first magnetic layer 205a, an insulating layer 205b, a second magnetic layer 205c, and an upper electrode layer 209 are sequentially formed on the conductive layer 203. In some embodiments of the present specification, the materials constituting the first magnetic layer 205a and the second magnetic layer 205c can include a ferromagnetic material containing iron, such as cobalt iron boron. In this embodiment, the first magnetic layer 205a and the second magnetic layer 205c have in-plane magnetic anisotropy (IMA). The material constituting the insulating layer 205b can include magnesium oxide. The upper electrode layer 209 can be a laminate composed of a tantalum metal layer 209a and a ruthenium metal layer 209b.

[0102] In an embodiment of the present specification, after the second magnetic layer 205c is formed, two upper synthetic antiferromagnetic layers 208 and a bottom synthetic antiferromagnetic layer 206, which are the same or different in structure and material, may be selectively formed above the second magnetic layer 205c, so that the bottom synthetic antiferromagnetic layer 206, the ruthenium coupling layer 207, and the upper synthetic antiferromagnetic layer 108 are combined to form a complete synthetic antiferromagnetic structure. Then, the upper electrode layer 209 is formed. The upper synthetic antiferromagnetic layer 208 and the bottom synthetic antiferromagnetic layer 206 are located between the second magnetic layer 205c and the upper electrode layer 209. In this embodiment, both the upper synthetic antiferromagnetic layer 208 and the bottom synthetic antiferromagnetic layer 206 are a periodic multilayer stack structure formed by stacking n cobalt / nickel (Co / Ni) layers through alternating stacking, and are connected to each other through the ruthenium coupling layer 207. Wherein, n is greater than or equal to 1 (n≥1). Before forming the bottom synthetic antiferromagnetic layer 206, a bridging layer 219, such as a tungsten (W) metal layer with a thickness of about 0.3 nanometers (nm), may preferably be formed above the second magnetic layer 205c.

[0103] Then, a patterned (e.g., made of silicon nitride) hard mask layer 210 is used as an etching mask, and the conductive layer 203 is used as an etching stop layer to etch the upper electrode layer 209, the upper synthetic antiferromagnetic structure 208, the ruthenium coupling layer 207, the bridging layer 219, the bottom synthetic antiferromagnetic layer 206, the second magnetic layer 205c, the insulating layer 205b, and the first magnetic layer 205a. To form a stacked structure S2 composed of a part of the remaining upper electrode layer 209, a part of the upper synthetic antiferromagnetic structure 208, a part of the ruthenium coupling layer 207, a part of the bridging layer 219, a part of the bottom synthetic antiferromagnetic layer 206, a part of the second magnetic layer 205c, a part of the insulating layer 205b, and a part of the first magnetic layer 205a above the memory region 201A; and expose a part of the conductive layer 203 above the circuit region 201B (at this time, the conductive layer 203 still covers above the circuit region 201B and the memory region 201A).

[0104] Among them, the second magnetic layer 205c, the insulating layer 205b, and the first magnetic layer 205a remaining above the memory region 201A together constitute a magnetic tunneling junction structure with perpendicular anisotropy (as Figure 2D shown). The first magnetic layer 205a can be used as the free layer of the magnetic tunneling junction structure; the insulating layer 205b can be used as the tunneling barrier layer in the perpendicular magnetic tunneling junction structure; the magnetic direction of the second magnetic layer 205c will be fixed by the bottom synthetic antiferromagnetic layer 206, the ruthenium coupling layer 207, and the upper synthetic antiferromagnetic layer 208, and can be used as the magnetization reference magnetic layer of the magnetic tunneling junction structure.

[0105] Thereafter, an insulating cover layer 211 is formed over the memory region 201A and the circuit region 201B, covering the stacked structure S2 and a part of the exposed conductive layer 203. Then, the insulating cover layer 211 and the conductive layer 203 are etched to remove a part of the insulating cover layer 211 and a part of the conductive layer 203 located in the memory region 201A, for forming a first conductive pattern 203a in the memory region 201A and a second conductive pattern 203b in the circuit region 201B. Wherein, both the first conductive pattern 203a and the second conductive pattern 203b are included in the patterned conductive layer 103 and are isolated from each other.

[0106] In this embodiment, as Figure 2E shown, the stacked structure S2 is located above the first conductive pattern 203a, and the bottom size of the stacked structure S2 is substantially smaller than the area of the first conductive pattern 203a, such that a part of the first conductive pattern 203a does not overlap with the stacked structure S2. The magnetic tunneling junction structure, together with the remaining part of the first conductive pattern 203a located below it, the upper electrode layer 209, the upper synthetic antiferromagnetic structure 208, the ruthenium coupling layer 207, and the bottom synthetic antiferromagnetic layer 206 stacked above it, jointly constitute a spin-orbit torque magnetic random access memory cell SOT-MRAM. The second conductive pattern 203b remaining on the circuit region 201B constitutes a resistance unit R2.

[0107] Subsequently, a series of back-end manufacturing processes are performed, for example, a metal damascene manufacturing process is carried out to form an interlayer dielectric layer 212 covering the memory region 201A and the circuit region 201B, and to form metal interconnection structures (including via plugs 213, 214, 215, and 218) passing through the interlayer dielectric layers 204 and 212 and the insulating cover layer 211. Through the via plug 213, the upper electrode layer 209 of the magnetic random access memory cell SOT-MRAM is electrically connected to the bit line 216; it can be electrically connected to the transistor unit 202 through the via plug 214 or 218 (for example, the two ends of the first conductive pattern 203a on the left and right sides of the magnetic tunneling junction structure are respectively electrically connected to the drain region 202c of the transistor unit 202 and the write line / word line through the via plugs 214 and 218); and through the via plug 215, one end of the second conductive pattern 203b of the resistance unit R2 is electrically connected to the external circuit 217 (the other end of the second conductive pattern 203b is electrically connected to another electrode (not shown) through other wires), forming the semiconductor device 200 as Figure 2F shown.

[0108] Integrate the manufacturing process of the magnetic tunneling junction structure of the spin-orbit torque magnetic random access memory cell SOT-MRAM and at least one resistance unit R2 in the magnetic memory element 200, so that the spin-orbit torque magnetic random access memory cell SOT-MRAM and the resistance unit R2 share the same patterned conductive layer 203. Thereby, the manufacturing process steps of the magnetic memory element 200 are simplified, the number of photomasks used is saved, and the manufacturing cost of the magnetic memory element 200 is significantly reduced.

[0109] According to the above embodiments, this specification provides a magnetic memory element and a manufacturing method thereof. It integrates the manufacturing processes of the spin-orbit torque magnetic random access memory and at least one resistance unit in the semiconductor circuit of the magnetic memory element, so that the spin-orbit torque magnetic random access memory and the resistance unit share the same patterned conductive layer, thereby simplifying the manufacturing process steps of the magnetic memory element, saving the number of photomasks used in the manufacturing process, and significantly reducing the manufacturing cost of the magnetic memory element. In one embodiment, the patterned conductive layer may be a spin-orbit torque (SOT) metal layer.

[0110] Although the present invention is disclosed in combination with the above preferred embodiments, it is not intended to limit the present invention. Any person of ordinary skill in the art in this technical field can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be defined by the appended claims.

Claims

1. A magnetic memory device, comprising: A substrate including a memory region and a circuit region; A patterned conductive layer including a first conductive pattern and a second conductive pattern isolated from each other, the first conductive pattern being located in the memory region and the second conductive pattern being located in the circuit region; and A magnetic tunneling junction (MTJ) structure located on the first conductive pattern and in electrical contact with the first conductive pattern.

2. The magnetic memory device according to claim 1, further comprising: A dielectric layer covering the patterned conductive layer; At least one first via plug passing through the dielectric layer and in electrical contact with the first conductive pattern; and A second via plug passing through the dielectric layer and in electrical contact with the second conductive pattern.

3. The magnetic memory device according to claim 1, wherein the magnetic tunneling junction structure is a spin transfer torque (STT) structure.

4. The magnetic memory device according to claim 3, wherein the at least one first via plug is a metal plug.

5. The magnetic memory device according to claim 3, wherein the patterned conductive layer includes tungsten (W).

6. The magnetic memory device according to claim 2, wherein the magnetic tunneling junction structure is a spin orbit torque (SOT) structure.

7. The magnetic memory device according to claim 6, wherein the at least one first via plug includes two metal plugs.

8. The magnetic memory device according to claim 6, wherein the patterned conductive layer includes tantalum (Ta), tungsten, platinum (Pt), cobalt (Co), ruthenium (Ru), or a combination thereof.

9. The magnetic memory device according to claim 1, wherein the spin transfer torque structure includes a magnetic layer / non-magnetic layer / magnetic layer stack structure.

10. The magnetic memory device according to claim 9, wherein the magnetic layer / non-magnetic layer / magnetic layer stack structure includes a cobalt iron boron (CoFeB) / magnesium oxide (MgO) / cobalt iron boron (CoFeB) stack structure.

11. A method for manufacturing a magnetic memory device, comprising: Providing a substrate including a memory region and a circuit region; Forming a conductive layer on the substrate; Sequentially forming a first magnetic layer, an insulating layer, and a second magnetic layer on the conductive layer; Patterning the conductive layer, the first magnetic layer, the insulating layer, and the second magnetic layer to form a first conductive pattern on the memory region and a magnetic tunneling junction structure located on the first conductive pattern; And forming a second conductive pattern on the circuit region; wherein the second conductive pattern and the first conductive pattern are included in the patterned conductive layer and are isolated from each other.

12. The method for manufacturing a magnetic memory device according to claim 11, further comprising: Forming a dielectric layer covering the patterned conductive layer; Forming at least one first via plug passing through the dielectric layer and in electrical contact with the first conductive pattern; and A second via plug is formed to pass through the dielectric layer and make electrical contact with the second conductive pattern.

13. The method for manufacturing a magnetic memory element according to claim 11, wherein the magnetic tunneling junction structure is a spin transfer torque structure.

14. The method for manufacturing a magnetic memory element according to claim 13, wherein the at least one first via plug is a metal plug.

15. The method for manufacturing a magnetic memory element according to claim 13, wherein the patterned conductive layer includes tungsten.

16. The method for manufacturing a magnetic memory element according to claim 11, wherein the magnetic tunneling junction structure is a spin orbit torque structure.

17. The method for manufacturing a magnetic memory element according to claim 16, wherein the at least one first via plug includes two metal plugs.

18. The method for manufacturing a magnetic memory element according to claim 16, wherein the patterned conductive layer includes tantalum, tungsten, platinum, cobalt, ruthenium, or a combination thereof.

19. The method for manufacturing a magnetic memory element according to claim 11, wherein the spin transfer torque structure includes a magnetic layer / non-magnetic layer / magnetic layer stack structure.

20. The method for manufacturing a magnetic memory element according to claim 19, wherein the magnetic layer / non-magnetic layer / magnetic layer stack structure includes a cobalt iron boron / magnesium oxide / cobalt iron boron stack structure.

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