High dielectric constant insulating material, transistor and method for manufacturing the same

Abstract

The application relates to an insulating material with high dielectric constant, a transistor and a preparation method thereof, which adopts high-purity MoO3 powder, and a MoO3 thin layer is grown on a SiO2 / Si substrate by a physical vapor deposition process; the MoO3 powder is placed in an alumina boat; the substrate is inverted on the alumina boat, and then the alumina boat is placed in the heating center of a single-temperature-zone tubular furnace; the tubular furnace is vacuumized, heated to a target temperature under vacuum, argon is introduced after the target temperature is reached, and the argon is kept for a certain time; the argon is turned off after the heat preservation is finished, the furnace is naturally cooled, and a MoO3 thin layer which stands on the substrate is obtained; the material has the characteristics of high dielectric constant, ultra-thin equivalent oxide thickness and the like, a transistor is obtained through a polymer-free transfer method, the cleanliness of a device manufacturing contact surface is protected, the electrical performance is greatly improved, the structural stability of the material is maintained, and the device shows excellent transfer characteristics.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of microelectronic devices, and in particular to an insulating material with high dielectric constant, a transistor and a preparation method thereof. BACKGROUND

[0002] With the continuous reduction in the size of electronic devices, traditional silicon-based insulating materials are facing increasingly serious challenges. In particular, in high-integration integrated circuits, as the thickness of the gate dielectric continues to decrease, issues such as gate leakage current, interface quality, and material breakdown field strength become important factors that restrict the performance of the device. In order to meet the performance requirements of ultra-thin devices, developing new insulating materials with high dielectric constant, low leakage, and good interface quality has become a problem to be solved.

[0003] MoO3, as a two-dimensional insulating material, has excellent electrical properties and structural stability, and has become a research hotspot in recent years. The high dielectric constant and low equivalent oxide thickness (EOT) of MoO3 make it a potential gate dielectric material, but its growth process and interface performance still face challenges. The high dielectric constant MoO3 material and its preparation method proposed by the present application can overcome the defects of existing materials and provide more stable and reliable material support for the next generation of microelectronic devices. SUMMARY

[0004] The primary object of the present application is to provide an insulating material with high dielectric constant, a transistor and a preparation method thereof. The insulating material MoO3 has excellent electrical properties, especially in the application of gate dielectric in low-power-consumption, high-integration electronic devices. The characteristics of this material include: high dielectric constant, ultra-thin equivalent oxide thickness (EOT) and high breakdown field strength, which can effectively reduce the leakage current and enhance the performance of the device when applied to transistors.

[0005] The preparation method of the insulating material with high dielectric constant MoO3 provided by the present application uses a polymer-free mechanical pressing technology to efficiently grow MoO3 with a layered structure on the substrate, ensuring that it has a high dielectric constant and good electrical properties. The MoO3 material prepared is combined with MoS2, WSe2 and other two-dimensional semiconductor material layers to construct a field effect transistor, and the MoS2 / MoO3 transistor obtained exhibits excellent on-off ratio, extremely low subthreshold swing and top-gate leakage current. The material provided by the present application can be widely used in the fields of MoO3 electronic devices, MOSFET, CMOS technology, etc.

[0006] In one aspect, the present application provides a preparation method of an insulating material with high dielectric constant, which uses high-purity (>99.9%) MoO3 powder and grows a MoO3 thin layer on a SiO2 / Si substrate using a physical vapor deposition process:

[0007] The MoO3 powder is placed in an alumina boat;

[0008] The side of the substrate provided with the SiO2 layer is placed on the alumina boat, and then the alumina boat is placed in the heating center of the single-temperature-zone tube furnace;

[0009] The tube furnace is vacuumized, and heated to a target temperature under vacuum;

[0010] After the target temperature is reached, argon is introduced, and the temperature is kept constant for a certain period of time;

[0011] After the temperature keeping is completed, the argon is turned off, and the furnace is naturally cooled, and a MoO3 thin layer standing on the substrate is obtained on the substrate.

[0012] Further, in the step of heating to a target temperature under vacuum, the heating rate is 35℃ / min, and the target temperature is 740℃-790℃.

[0013] Further, the argon gas flow is 80-100sccm, and the temperature keeping for a certain period of time is 0.25-0.4 hours.

[0014] The present application provides an insulating material with high dielectric constant, which is a MoO3 thin layer with a layered structure, obtained by the above preparation method.

[0015] The present application provides a preparation method of a transistor, comprising the following steps:

[0016] A two-dimensional semiconductor material thin layer single crystal adhesive tape is obtained by a mechanical peeling process, and the two-dimensional semiconductor material thin layer single crystal adhesive tape is adhered to PDMS to obtain a two-dimensional semiconductor material thin layer / PDMS. The side of the two-dimensional semiconductor material thin layer / PDMS adhered with the two-dimensional semiconductor material thin layer is attached to the surface of the SiO2 layer of the SiO2 / Si substrate, and the PDMS layer is torn off to obtain a two-dimensional semiconductor material thin layer on the SiO2 / Si substrate. The two-dimensional semiconductor material thin layer obtained by the peeling method is larger, more uniform, and has less residual glue than the two-dimensional semiconductor material thin layer obtained by directly peeling the two-dimensional semiconductor material single crystal adhesive tape on the substrate.

[0017] First and second electrodes are prepared at both ends of the two-dimensional semiconductor material thin layer;

[0018] The substrate with the MoO3 thin layer standing on it obtained by the above preparation is used, and a MoO3 / PDMS is obtained by adhering the MoO3 thin layer to PDMS without polymer transfer.

[0019] attaching the MoO3 / PDMS to the two-dimensional semiconductor material thin layer with the MoO3 adhered side of the MoO3 / PDMS facing the two-dimensional semiconductor material thin layer, and obtaining a MoO3 thin layer on the two-dimensional semiconductor material thin layer after tearing off the PDMS;

[0020] transferring the third electrode to the MoO3 thin layer by using a PVA dry transfer process, and then soaking the substrate in deionized water, heating at 60-70℃ for 4 hours, and then taking out and drying.

[0021] Further, the two-dimensional semiconductor material thin layer is MoS2, WSe2 or WS2.

[0022] Further, the thickness of the MoO3 thin layer is 1-100 nm.

[0023] Further, the thickness of the two-dimensional semiconductor material thin layer is 5-50 nm.

[0024] Further, in the polymer-free transfer method, the PDMS is slowly brought close to the substrate with the MoO3 thin layer standing on the substrate, the MoO3 thin layer is adhered to the PDMS after the MoO3 thin layer is adhered to the PDMS, and then the PDMS is slowly lifted to obtain the MoO3 / PDMS.

[0025] Further, the first electrode and the second electrode are Cr / Au electrodes, the thickness of the Cr layer is 2-10 nm, and the thickness of the Au layer is 30-80 nm.

[0026] Further, the third electrode is an Au electrode, and the thickness is 50-80 nm.

[0027] In one aspect, the application provides a transistor obtained by using the above preparation method.

[0028] Compared with the prior art, the application has at least the following beneficial effects:

[0029] The application prepares MoO3 with the advantages of layered two-dimensional structure film, high dielectric constant and large yield by a PVD growth method, and the grown MoO3 is grown in a vertical state on a SiO2 / Si substrate, the material has high dielectric constant, ultra-thin equivalent oxide thickness (EOT), excellent interface quality and high breakdown field strength, and is suitable for gate dielectric in two-dimensional electronic device manufacturing and field effect transistor manufacturing. The MoO3 material is transferred by a polymer-free transfer method, the cleanliness of the contact surface in device manufacturing is protected, the electrical performance is greatly improved, and the structural stability of the material is maintained. The MoO3 can be successfully transferred to a target substrate by the polymer-free transfer method, the transfer method is not limited to MoS2 as the target substrate, and other two-dimensional materials such as WSe2 and WS2 can be used as the transfer target; and the MoS2 / MoO3 transistor prepared by combining the mechanical peeling process shows excellent transfer characteristics, in the range of top gate voltage-1.5V-0V, excellent on-off ratio (10 7 ), extremely low sub-threshold swing (78mV / dec) and low top gate leakage current (10 -4 A / cm 2 ) are shown. The material preparation process of the application is simple, mature, easy to obtain equipment and low cost, which is conducive to the further development and application of transistors and low-dimensional electronic devices. BRIEF DESCRIPTION OF DRAWINGS

[0030] Figure 1 SEM image of MoO3 material prepared in an embodiment of the application.

[0031] Figure 2 Schematic diagram of polymer-free transfer in the preparation process of an embodiment of the application.

[0032] Figure 3 Device structure schematic diagram of MoS2 / MoO3 transistor in an embodiment of the application.

[0033] Figure 4 Optical microscope image of MoS2 / MoO3 transistor in the preparation process of an embodiment of the application, and the inserted image is an AFM test image of thin layer MoO3.

[0034] Figure 5 Data curve of MoS2 / MoO3 transistor prepared in an embodiment of the application, wherein a is the transfer curve of the transistor under different bias; b is the comparison of gate leakage current between different devices. DETAILED DESCRIPTION

[0035] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings of the present application. The described embodiments are only some of the embodiments of the present application, rather than all the embodiments. Based on the embodiments of the present application, other embodiments obtained by those skilled in the art without creative efforts belong to the scope of the present application. In the following embodiments, the experimental methods are conventional methods unless otherwise specified, and the reagents and materials are commercially available unless otherwise specified.

[0036] Spatially relative terms such as "beneath", "below", "lower", "on", "above", "upper" and the like, are used herein for ease of description to explain the positioning of one element relative to a second element. The terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures.

[0037] In addition, terms such as "first", "second", and the like, are used to describe various elements, layers, regions, sections, and the like, and are not intended to be limiting. The use of "have", "has", "including", "comprising", "involving", and variations thereof, are open-ended terms that mean that the described elements or features are present, but not excluding additional elements or features. Unless the context clearly indicates otherwise.

[0038] An embodiment of the present application provides a preparation method of high dielectric constant insulating material, comprising the following steps:

[0039] First, the SiO2 / Si growth substrate is soaked in acetone solution, isopropyl alcohol solution and deionized water respectively, and each soaking process is kept for 4 minutes.

[0040] Then, a MoO3 thin layer is grown on the SiO2 layer of the Si substrate by a physical vapor deposition process. The high-purity (>99.9%) MoO3 powder is placed in the center of an alumina boat, and then the cleaned SiO2 / Si substrate with the SiO2 side facing the alumina boat is covered on the alumina boat, and then the alumina boat is pushed to the heating center of a tube furnace, which is a single-temperature-zone tube furnace.

[0041] Then, the whole tube furnace channel system is vacuumized by using a vacuum pump to isolate air, and the vacuum is kept during temperature rising, and the heating rate is 35℃ / min, and the temperature is heated to 740-790℃, and then argon is introduced, the flow rate is 80-100sccm, the keeping time is 0.25-0.4 hours, and the argon channel is closed after the keeping temperature ends to naturally cool the system to room temperature. A vertically grown MoO3 thin layer is obtained on the SiO2 / Si growth substrate, as shown in FIG. 2. Figure 1The image shows a SEM image of the prepared MoO3 material. The thin-layer MoO3 insulating material grown in this invention achieves controlled growth using the PVD method in a tube furnace. By adjusting the growth temperature and time, thin-layer MoO3 materials of different thicknesses and widths can be prepared. This method reliably, stably, and efficiently produces thin-layer MoO3 materials, enhancing their application value and providing excellent materials for the development of electronic devices. This achieves... Figure 1 The SEM images show the layered growth of thin MoO3 and its upright growth on the substrate.

[0042] Figure 2 The figure illustrates a polymer-free transfer method provided in one embodiment of the present invention. MoO3 grown upright on a SiO2 / Si substrate, along with the substrate, is placed under a transfer platform. PDMS is slowly brought close to the substrate on which a thin layer of MoO3 is grown. After the MoO3 adheres to the PDMS, the PDMS is slowly lifted. Then, the PDMS with the thin layer of MoO3 is attached to the target substrate to complete the transfer.

[0043] Figure 3 The diagram shows a schematic of the device structure of the MoS2 / MoO3 transistor of the present invention. The device utilizes thin layers of MoS2 and MoO3. Based on the high mobility of MoS2, the switching and transfer characteristics of the transistor are improved. A Cr / Au layer is deposited using existing technology to achieve... Figure 3 The structure of the device diagram.

[0044] An embodiment of the present invention provides Figure 3 The fabrication method of MoS2 / MoO3 transistors includes the following steps:

[0045] A mechanical peeling method was used to obtain MoS2 single crystal tape by using adhesive tape to adhere single crystal MoS2, and MoS2 / PDMS was obtained by using PDMS to adhere MoS2 single crystal tape. The PDMS with MoS2 attached was then placed on the surface of SiO2 / Si substrate, and after pressing lightly for 45 seconds, the PDMS layer was peeled off, resulting in a thin MoS2 layer on the surface of SiO2 / Si substrate. Subsequently, a thin MoS2 target layer of 5-50 nm was selected under an optical microscope.

[0046] Next, the mesa of the first and second electrodes was etched using ultraviolet laser lithography. The substrate containing a thin layer of MoS2 was placed on the chuck of the spin coater. The spin coater speed was set to 4000 revolutions per second and the spin coater duration was set to 1 minute. Then, the substrate was placed on a heating stage and cured at 100°C for 1 minute. The mesa was then etched using ultraviolet laser lithography.

[0047] Subsequently, a 10 nm Cr layer and a 35 nm Au layer were deposited using electron beam evaporation and thermal evaporation processes at a deposition rate of 0.01 nm / s. After deposition, the layers were placed in acetone for ten minutes to dissolve the photoresist, thereby removing the excess Cr / Au layer and forming the first and second electrodes at both ends of the thin MoS2 target layer.

[0048] Using the polymer-free transfer method described above, MoO3 grown upright on a SiO2 / Si substrate, along with the substrate, is placed under a transfer platform. PDMS is slowly brought close to the substrate on which the thin layer of MoO3 is grown. After the MoO3 adheres to the PDMS, it is slowly lifted. Then, the PDMS with the thin layer of MoO3 is bonded and covered onto the thin layer of MoS2 target layer.

[0049] A 45nm thick Au layer was deposited on a silicon wafer using a thermal evaporation process at a deposition rate of 0.01nm / s. The silicon wafer was then immersed in acetone for ten minutes to remove the photoresist. As the photoresist dissolved in the acetone, the excess gold film also detached. The wafer was then rinsed in deionized water and finally cleaned of moisture from the surface with a nitrogen gun.

[0050] Next, using the PVA transfer method, the prepared Au electrode was placed under a transfer platform and transferred onto the aforementioned thin MoO3 layer using dry PVA transfer. This electrode serves as the third electrode. The device substrate was then immersed in deionized water and placed on a heating stage, heated at 60–70°C for 4 hours. After heating, the surface moisture was removed using a nitrogen gun. This yields the desired result. Figure 4 The MoS2 / MoO3 transistor shown has a first electrode and a second electrode disposed at both ends of a thin layer of MoS2, and a third electrode disposed on a thin layer of MoO3.

[0051] Figure 5 Figure a shows the performance test curves of the transistors prepared in the above embodiments. Figure a shows the transfer curves of the prepared MoS2 / MoO3 transistor obtained by scanning from -2V to 2V. The thickness of the thin MoO3 layer is 9.31nm. The curves show that the transistor has good transfer characteristics. Under different bias voltages, the threshold voltage does not shift significantly, and the current reaches near saturation at a top gate voltage of 0V. At a top gate voltage of -1.5V, the off-state current of the transistor is as low as 10. -14Figure A indicates that this transistor has great potential in the field of low-power electronic devices. Furthermore, the thin MoO3 layer thickness corresponds to an ultrathin equivalent oxide (EOT) thickness of 0.31 nm, providing an excellent material for future transistor scaling, enabling effective transistor scaling to meet commercial requirements. Figure b shows a comparison of six MoS2 / MoO3 transistors prepared according to an embodiment of the present invention with different gate leakage currents. Through comparison of different gate leakage currents, the transistors manufactured in this invention have stable top-gate leakage currents and strong stability. As shown in the figure, the top-gate current has hardly changed after two months, and all have reached the low-power device level required by IRDS.

[0052] The above embodiments are preferred embodiments of the present invention, but the embodiments of the present invention are not limited to the above embodiments. Any changes, modifications, substitutions, combinations, or simplifications made without departing from the spirit and principle of the present invention shall be considered equivalent substitutions and shall be included within the protection scope of the present invention.

Claims

1. A method for fabricating a transistor, characterized in that, Includes the following steps: A two-dimensional semiconductor material thin film single crystal tape was obtained by mechanical peeling process. The two-dimensional semiconductor material thin film single crystal tape was then bonded with PDMS to obtain a two-dimensional semiconductor material thin film / PDMS. The side of the two-dimensional semiconductor material thin film / PDMS with the two-dimensional semiconductor material thin film bonded was attached to the surface of the SiO2 layer on the SiO2 / Si substrate. The PDMS layer was then peeled off on the SiO2 / Si substrate to obtain the two-dimensional semiconductor material thin film. A first electrode and a second electrode are fabricated at both ends of the thin layer of the two-dimensional semiconductor material; High-purity MoO3 powder was used to grow a thin MoO3 layer on a SiO2 / Si substrate using physical vapor deposition. The MoO3 powder was placed in an alumina boat. The substrate with the SiO2 layer facing the alumina boat was placed on the alumina boat, which was then placed in the heating center of a single-temperature zone tube furnace. The tube furnace was evacuated, and heating was maintained under vacuum until the target temperature of 740℃~790℃ was reached at a heating rate of 35℃ / min. After reaching the target temperature, argon gas was introduced at a flow rate of 80~100 sccm, and the temperature was maintained for 0.25~0.4 hours. After the holding period, the argon gas was turned off, and the furnace was allowed to cool naturally, resulting in a layered MoO3 thin layer standing upright on the substrate. Take the substrate with a layered structure and a MoO3 thin layer obtained above, and use a polymer-free method to adhere the MoO3 thin layer onto PDMS to obtain MoO3 / PDMS; With the side of MoO3 / PDMS with MoO3 attached facing the two-dimensional semiconductor material thin layer, the MoO3 thin layer is attached to the two-dimensional semiconductor material thin layer. After peeling off the PDMS, a MoO3 thin layer is obtained on the two-dimensional semiconductor material thin layer. The third electrode was transferred onto the MoO3 thin layer using a PVA dry transfer process. The substrate was then immersed in deionized water and heated at 60-70°C for 4 hours before being removed and dried.

2. The preparation method according to claim 1, characterized in that, The two-dimensional semiconductor material thin layer is MoS2 or WSe2, and its thickness is 5~50nm.

3. The preparation method according to claim 1 or 2, characterized in that, The thickness of the MoO3 thin layer is 1~100 nm.

4. The preparation method according to claim 3, characterized in that, In a polymer-free transfer method, PDMS is slowly brought close to the substrate with the upright MoO3 thin layer, the MoO3 thin layer is adhered to the PDMS, and then the PDMS is slowly lifted to obtain MoO3 / PDMS.

5. The preparation method according to claim 2 or 4, characterized in that, The first and second electrodes are Cr / Au electrodes, with the Cr layer having a thickness of 2~10 nm and the Au layer having a thickness of 30~80 nm; The third electrode is an Au electrode with a thickness of 50~80nm.

6. A transistor, characterized in that, It is obtained by the preparation method described in any one of claims 1 to 5.

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