Display substrate, display device and contact resistance test method

Abstract

The embodiment of the invention provides a display substrate, a display device and a contact resistance testing method. The display substrate comprises a display area and a first frame area located on at least one side, the first frame area comprises at least one test group, each test group comprises a plurality of driving test bonding pads, a plurality of binding test bonding pads and a plurality of test signal lines, and in the same test group, each binding test bonding pad comprises a plurality of binding test bonding pads and a plurality of test signal lines. The binding test bonding pads are located on the sides, away from the display area, of the driving test bonding pads, the multiple binding test bonding pads correspond to the multiple test signal lines in a one-to-one mode, and one binding test bonding pad is electrically connected with one driving test bonding pad through the corresponding test signal line. One driving test bonding pad is electrically connected with at least one binding test bonding pad through at least one test signal line, and the plurality of driving test bonding pads are located at positions adjacent to the plurality of binding test bonding pads. According to the technical scheme provided by the embodiment of the invention, the resistance of the test signal line can be reduced, and the accuracy of testing the contact resistance of the driving bonding pad can be improved.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to, but are not limited to, the field of display technologies, and in particular, to a display substrate, a display device, and a contact resistance testing method. Background Art

[0002] Organic Light Emitting Diode (OLED) and Quantum-dot Light Emitting Diodes (QLED) are active light-emitting display devices, which have the advantages of self-luminescence, wide viewing angle, high contrast ratio, low power consumption, extremely high response speed, thin and light, bendable, and low cost. With the continuous development of display technologies, flexible display devices (Flexible Display) using OLED or QLED as light-emitting devices and controlled by Thin Film Transistors (TFT) have become the mainstream products in the current display field.

[0003] Currently, there is a technical problem that the contact resistance test of the driving pads on the display substrate is inaccurate. Summary of the Invention

[0004] The problem to be solved by the embodiments of the present disclosure is to provide a display substrate, a display device, and a contact resistance testing method to solve the technical problem that the resistance test of the driving pads on the existing display substrate is inaccurate.

[0005] To solve the above technical problem, in a first aspect, embodiments of the present disclosure provide a display substrate, including:

[0006] A substrate, the substrate including a display area and a first border area located on at least one side of the display area;

[0007] At least one test group, located in the first border area, and a plurality of driving test pads, a plurality of bonding test pads, and a plurality of test signal lines are included in the same test group;

[0008] Among them, in the same test group: the multiple bonding test pads are located on a side of the multiple driving test pads away from the display area, the multiple bonding test pads correspond to the multiple test signal lines one by one, one bonding test pad among the multiple bonding test pads is electrically connected to one driving test pad among the multiple driving test pads through a corresponding test signal line, the one driving test pad is electrically connected to at least one bonding test pad among the multiple bonding test pads through at least one test signal line among the multiple test signal lines, at least two driving test pads among the multiple driving test pads are electrically connected, and the multiple driving test pads are located at positions adjacent to the multiple bonding test pads.

[0009] In an exemplary embodiment, the display substrate further includes:

[0010] Multiple driving pads, located in the first border area, in a first direction, the multiple driving test pads in at least one test group are located on at least one side of the multiple driving pads;

[0011] Multiple bonding pads, located in the first border area, the multiple bonding pads are located on a side of the multiple driving pads away from the display area, in the first direction, the multiple bonding test pads in at least one test group are located on at least one side of the multiple bonding pads;

[0012] In the same test group, in the first direction, the multiple driving test pads, the multiple bonding test pads, and the multiple test signal lines are located on the same side of the multiple driving pads and the multiple bonding pads.

[0013] In an exemplary embodiment, the display substrate further includes:

[0014] Multiple sub-pixels, located on one side of the substrate and in the display area;

[0015] Multiple data lines, located in the display area and electrically connected to the multiple sub-pixels, the multiple data lines are configured to provide data signals to the multiple sub-pixels;

[0016] Among them, the multiple driving pads include multiple first driving pads and multiple second driving pads, the multiple second driving pads are located on a side of the multiple first driving pads away from the display area, and the multiple first driving pads are electrically connected to the multiple data lines; at least some of the multiple bonding pads are electrically connected to the multiple second driving pads, and the conductivity of at least part of the structure of the multiple test signal lines in at least one test group is consistent with the conductivity of the multiple data lines.

[0017] In an exemplary embodiment, the at least one test group includes at least one first test group and at least one second test group;

[0018] In the same first test group: there are a plurality of first driving test pads, a plurality of first bonding test pads, and a plurality of first test signal lines. The plurality of first bonding test pads correspond to the plurality of first test signal lines one by one. One first bonding test pad among the plurality of first bonding test pads is electrically connected to one first driving test pad among the plurality of first driving test pads through a corresponding first test signal line. The one first driving test pad is electrically connected to at least one first bonding test pad among the plurality of first bonding test pads through at least one first test signal line among the plurality of first test signal lines;

[0019] In the same second test group: there are a plurality of second driving test pads, a plurality of second bonding test pads, and a plurality of second test signal lines. The plurality of second bonding test pads correspond to the plurality of second test signal lines one by one. One second bonding test pad among the plurality of second bonding test pads is electrically connected to one second driving test pad among the plurality of second driving test pads through a corresponding second test signal line. The one second driving test pad is electrically connected to at least one second bonding test pad among the plurality of second bonding test pads through at least one second test signal line among the plurality of second test signal lines;

[0020] Wherein, the plurality of second driving test pads are located on a side of the plurality of first driving test pads away from the display area.

[0021] In an exemplary embodiment, at least one test signal line among the plurality of test signal lines includes a first structure portion, a second structure portion, and a third structure portion;

[0022] In the same test signal line: one end of the second structure portion is connected to the first structure portion, and the other end is connected to the third structure portion; the other end of the first structure portion is electrically connected to one driving test pad among the plurality of driving test pads, and the other end of the third structure portion is electrically connected to the corresponding bonding test pad.

[0023] In an exemplary embodiment, in a direction perpendicular to the plane of the substrate, the first structure portion and the third structure portion are located on a side of the second structure portion close to the substrate, or the first structure portion and the third structure portion are located on a side of the second structure portion away from the substrate, or the first structure portion and the third structure portion are arranged on the same layer as the second structure portion.

[0024] In an exemplary embodiment, the display area includes a plurality of sub-pixels and a plurality of data lines. The plurality of data lines are electrically connected to the plurality of sub-pixels and are configured to provide data signals to the plurality of sub-pixels. At least one of the plurality of sub-pixels includes a pixel driving circuit, and the pixel driving circuit includes a plurality of transistors and at least one capacitor.

[0025] In a direction perpendicular to the plane of the substrate, the capacitor includes: a first electrode plate on one side of the substrate, and a second electrode plate on a side of the first electrode plate away from the substrate. The transistor includes: an active layer, a control electrode, a first pole, and a second pole. The active layer is located between the first electrode plate and the substrate, the control electrode is arranged on the same layer as the first electrode plate, the first pole and the second pole are located on a side of the second electrode plate away from the substrate, and the data line is located on a side of the first pole and the second pole away from the substrate.

[0026] The second structural portion is arranged on the same layer as at least one of the first pole, the second pole, and the data line.

[0027] In an exemplary embodiment, the first structural portion and the third structural portion are arranged on the same layer as at least one of the control electrode and the second electrode plate, or the first structural portion and the third structural portion are arranged on the same layer as at least one of the first pole, the second pole, and the data line.

[0028] In an exemplary embodiment, in the same test group, there are at least two driving test pads, at least two bonding test pads, and at least two test signal lines. The at least two driving test pads are electrically connected to the at least two bonding test pads through the at least two test signal lines.

[0029] In an exemplary embodiment, in the same test group: the number of the test signal lines and the number of the driving test pads are both integer multiples of 2, the number of the bonding test pads is the same as the number of the test signal lines, and is not less than the number of the driving test pads.

[0030] In an exemplary embodiment, in the same test group, the number of the driving test pads, the bonding test pads, and the test signal lines are all two. The first ends of the two test signal lines are respectively electrically connected to the two bonding test pads, and the second ends are respectively electrically connected to the two driving test pads.

[0031] In an exemplary embodiment, in the same test group, the number of driving test pads is two, and the number of bonding test pads and the number of test signal lines are both four. The first ends of the four test signal lines are respectively electrically connected to the four bonding test pads. The second ends of two of the test signal lines are electrically connected to one of the driving test pads, and the second ends of the other two test signal lines are electrically connected to the other driving test pad.

[0032] In an exemplary embodiment, in the same test group, the number of driving test pads is two, and the number of bonding test pads and the number of test signal lines are both six. The first ends of the six test signal lines are respectively electrically connected to the six bonding test pads. The second ends of three of the test signal lines are electrically connected to one of the driving test pads, and the second ends of the other three test signal lines are electrically connected to the other driving test pad.

[0033] In an exemplary embodiment, the at least one test group further includes a short circuit wire. In the same test group, the number of driving test pads is two, and the two driving test pads are electrically connected through the short circuit wire.

[0034] In a second aspect, the present disclosure further provides a display device, including the display substrate described in any one of the above embodiments.

[0035] In a third aspect, embodiments of the present disclosure further provide a contact resistance testing method for testing the contact resistance of the driving test pads in the display substrate described in any one of the above embodiments. The display substrate includes a display area and a first border area located on at least one side of the display area. The first border area includes at least one test group. The same test group includes a plurality of driving test pads, a plurality of bonding test pads, and a plurality of test signal lines. In the same test group, the plurality of bonding test pads are located on a side of the plurality of driving test pads away from the display area. The plurality of bonding test pads correspond to the plurality of test signal lines one by one. One bonding test pad among the plurality of bonding test pads is electrically connected to one of the driving test pads through the corresponding test signal line. One of the driving test pads is electrically connected to at least one of the bonding test pads among the plurality of bonding test pads through at least one of the plurality of test signal lines. At least two of the plurality of driving test pads are electrically connected. The plurality of driving test pads are located at positions adjacent to the plurality of bonding test pads. The plurality of bonding test pads include at least one first type of bonding test pad and at least one second type of bonding test pad. The method includes:

[0036] Apply a first electrical signal to the first type of bonding test pad, test the second electrical signal of the second type of bonding test pad, and obtain the first contact resistance of the drive test pad based on the first electrical signal and the second electrical signal.

[0037] In an exemplary embodiment, the at least one test group further includes a short wire; within the same test group: the number of drive test pads is two, and the two drive test pads are electrically connected through the short wire. The plurality of bonding test pads include two first type bonding test pads and two second type bonding test pads. The plurality of test signal lines include two first type test signal lines and two second type test signal lines. The two first type bonding test pads are electrically connected to the two drive test pads respectively through the two first type test signal lines, and the two second type bonding test pads are electrically connected to the two drive test pads respectively through the two second type test signal lines.

[0038] In an exemplary embodiment, applying a first electrical signal to the first type of bonding test pad and testing the second electrical signal of the second type of bonding test pad includes: applying a first current signal to one of the first type bonding test pads, applying a ground signal to the other first type bonding test pad, and testing the second voltage signals of the two second type bonding test pads; the first electrical signal includes the first current signal and the ground signal, and the second electrical signal includes the second voltage signal.

[0039] In an exemplary embodiment, within the same test group, the plurality of bonding test pads further include two third type bonding test pads, the plurality of test signal lines further include two third type test signal lines, and the two third type bonding test pads are electrically connected to the two drive test pads respectively through the two third type test signal lines;

[0040] Before applying the first electrical signal to the first type of bonding test pad, or after obtaining the first contact resistance of the drive test pad based on the first electrical signal and the second electrical signal, further include: applying a third electrical signal to the third type of bonding test pad, testing the fourth electrical signal of the third type of bonding test pad, and obtaining the second contact resistance of the drive test pad based on the third electrical signal and the fourth electrical signal.

[0041] The display substrate, display device, and resistance testing method provided by the embodiments of the present disclosure. The display substrate includes a display area and a first border area located on at least one side. The first border area includes at least one test group. The test group includes a plurality of driving test pads, a plurality of bonding test pads, and a plurality of test signal lines. The bonding test pads are located on the side of the driving test pads away from the display area. In the same test group, the plurality of bonding test pads correspond to the plurality of test signal lines one by one. The bonding test pads are electrically connected to one of the driving test pads through the corresponding test signal lines. The driving test pads are electrically connected to at least one bonding test pad through at least one test signal line. The plurality of driving test pads are located at positions adjacent to the plurality of bonding test pads, which can minimize the length of the test signal lines, reduce the resistance of the test signal lines, and improve the accuracy of testing the contact resistance of the driving test pads.

[0042] Other aspects will be apparent after reading and understanding the drawings and the detailed description. Description of the Drawings

[0043] The drawings are used to provide a further understanding of the technical solutions of the present disclosure, and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solutions of the present disclosure, and do not constitute a limitation to the technical solutions of the present disclosure. The shapes and sizes of the components in the drawings do not reflect the actual scale, and the purpose is only to illustrate the content of the present disclosure schematically.

[0044] Figure 1a A schematic diagram of a display substrate provided for an exemplary embodiment of the present disclosure;

[0045] Figure 1b Another schematic diagram of a display substrate provided for an exemplary embodiment of the present disclosure;

[0046] Figure 2 For Figure 1a A cross-sectional schematic diagram taken along the line aa' in the display area of the display substrate shown;

[0047] Figure 3 A partial schematic diagram of a first signal access area provided for an exemplary embodiment of the present disclosure;

[0048] Figure 4a For Figure 3 A detailed enlarged view of the area S in

[0049] Figure 4b For Figure 4a A cross-sectional structure schematic diagram at the position A-A in

[0050] Figure 5 A signal connection schematic diagram between the first signal access area and the second signal access area;

[0051] Figure 6aSchematic diagram of a structure for connecting a driving test pad and a bonding test pad provided by an exemplary embodiment of the present disclosure;

[0052] Figure 6b Schematic diagram of a structure for connecting a driving test pad and a bonding test pad provided by an exemplary embodiment of the present disclosure;

[0053] Figure 7 For Figure 6a An enlarged schematic diagram of the position of R1 in;

[0054] Figure 8 For Figure 6a Schematic diagram of a structure of a test group in;

[0055] Figure 9 For Figure 6a Schematic diagram of a test group in;

[0056] Figure 10 Schematic diagram of a test group provided by an exemplary embodiment of the present disclosure;

[0057] Figure 11 Schematic diagram of a test group provided by an exemplary embodiment of the present disclosure;

[0058] Figure 12 Schematic diagram of a test group provided by an exemplary embodiment of the present disclosure;

[0059] Figure 13 Schematic diagram of a test group provided by an exemplary embodiment of the present disclosure;

[0060] Figure 14 Schematic diagram of a test group provided by an exemplary embodiment of the present disclosure;

[0061] Figure 15 Schematic diagram of a test group provided by an exemplary embodiment of the present disclosure;

[0062] Figure 16 The figure shows a schematic diagram of a display device provided by an embodiment of the present disclosure. Detailed implementation manners

[0063] Next, the technical solutions in the embodiments of the present disclosure will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present disclosure without creative efforts shall fall within the protection scope of the present disclosure.

[0064] It is understood that the various drawings in the embodiments of the present disclosure are only used to schematically show the connection relationships between various components. The sizes of the various components in the drawings are not drawn to scale, and their relative positional relationships do not necessarily exactly correspond to the actual positions.

[0065] In the present disclosure, unless otherwise clearly specified and limited, terms such as "mounted", "connected", "connected to", "fixed" and the like should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or integrated; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the communication inside two elements or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present disclosure can be understood according to specific circumstances.

[0066] In the present disclosure, "electrically connected" includes the case where elements are connected together through an element having a certain electrical effect. There is no particular limitation on the "element having a certain electrical effect" as long as it can transfer and receive electrical signals between the constituent elements that can be connected. Examples of the "element having a certain electrical effect" include not only electrodes and wirings, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0067] In the present disclosure, "film" and "layer" can be interchanged. For example, sometimes the "conductive layer" can be changed to the "conductive film". Similarly, sometimes the "insulating film" can be changed to the "insulating layer".

[0068] The "lithography process" mentioned in the present disclosure includes processes such as depositing a film layer, coating a photoresist, mask exposure, development, etching, and stripping the photoresist. Deposition can be any one or more selected from sputtering, evaporation, and chemical vapor deposition. Coating can be any one or more selected from spraying and spin coating. Etching can be any one or more selected from dry etching and wet etching. A "thin film" refers to a thin film made of a certain material on a substrate by using a deposition or coating process. If the "thin film" does not require a lithography process during the entire manufacturing process, the "thin film" can also be called a "layer". When the "thin film" still requires a lithography process during the entire manufacturing process, it is called a "thin film" before the lithography process and a "layer" after the lithography process. The "layer" after the lithography process contains at least one "pattern".

[0069] Figure 1a It is a schematic diagram of a display substrate according to an embodiment of the present disclosure. Figure 1b It is another schematic diagram of a display substrate according to an embodiment of the present disclosure. Figure 1a and Figure 1b Both of the figures shown are plan schematic diagrams of the display substrate before the bending process.

[0070] In some examples, such as Figure 1a and Figure 1b shown, the display substrate may include: a display area AA, and a border area BB surrounding the periphery of the display area AA. For example, the border area BB may include: a first border area B1 located on one side of the display area AA, and border areas located on other sides of the display area AA (for example, may include a second border area B2, a third border area B3, and a fourth border area B4). Among them, the first border area B1 may be, for example, the lower border of the display substrate, the second border area B2 may be, for example, the upper border of the display substrate, the third border area B3 may be, for example, the left border of the display substrate, and the fourth border area B4 may be, for example, the right border of the display substrate.

[0071] In some examples, such as Figure 1a and Figure 1b shown, the display area AA may be a flat area, including a plurality of sub-pixels PX that make up a pixel array. The plurality of sub-pixels PX may be configured to display dynamic pictures or still images. The display area AA may be referred to as an active area. In some examples, the display area AA may be rectangular. However, the present embodiment does not limit this. For example, the display area AA may be other shapes such as circular or oval. In some examples, the display substrate may be a flexible panel, and thus the display substrate may be deformable, such as curling, bending, folding, or rolling up.

[0072] In some examples, such as Figure 1a and Figure 1b shown, the display area AA may at least include: a plurality of sub-pixels PX, a plurality of gate lines GL, and a plurality of data lines DL. The plurality of gate lines GL may extend along a first direction X, and the plurality of data lines DL may extend along a second direction Y. The orthographic projections of the plurality of gate lines GL and the plurality of data lines DL on the substrate may cross to form a plurality of sub-pixel areas, and one sub-pixel PX may be disposed in each sub-pixel area. The plurality of data lines DL may be electrically connected to the plurality of sub-pixels PX, and the plurality of data lines DL may be configured to provide data signals to the plurality of sub-pixels PX. The plurality of gate lines GL may be electrically connected to the plurality of sub-pixels PX, and the plurality of gate lines GL may be configured to provide gate control signals to the plurality of sub-pixels PX. In some examples, the gate control signal may include a scan signal and a light emission control signal, or may include a scan signal, or may include a scan signal, a reset control signal, and a light emission control signal.

[0073] In some examples, such as Figure 1a and Figure 1bAs shown, the first direction X may be the extending direction of the gate line GL in the display area AA (e.g., the row direction), and the second direction Y may be the extending direction of the data line DL in the display area AA (e.g., the column direction). The first direction X and the second direction Y may intersect with each other, for example, they may be perpendicular to each other.

[0074] In some examples, a pixel unit in the display area AA may include three sub-pixels, namely a red sub-pixel, a green sub-pixel, and a blue sub-pixel. However, this embodiment is not limited thereto. In some examples, a pixel unit may include four sub-pixels, namely a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel.

[0075] In some examples, the shape of the sub-pixel may be rectangular, rhombic, pentagonal, or hexagonal. When a pixel unit includes three sub-pixels, the three sub-pixels may be arranged in a horizontal side-by-side, vertical side-by-side, or staggered manner; when a pixel unit includes four sub-pixels, the four sub-pixels may be arranged in a horizontal side-by-side, vertical side-by-side, or square manner. However, this embodiment is not limited thereto.

[0076] In some examples, a sub-pixel may include: a pixel circuit and a light-emitting element electrically connected to the pixel circuit (as Figure 1a indicated by L. Note that for the sake of brevity, Figure 1a only the light-emitting element L is shown in one sub-pixel PX, which does not represent a limitation to the present disclosure). The pixel circuit may include a plurality of transistors and at least one capacitor. For example, the pixel circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. Herein, T in the above circuit structures refers to a thin-film transistor, C refers to a capacitor, the number before T represents the number of thin-film transistors in the circuit, and the number before C represents the number of capacitors in the circuit. In some examples, the plurality of transistors in the pixel circuit may include P-type transistors and N-type transistors. However, this embodiment is not limited thereto.

[0077] In some examples, multiple transistors in the pixel circuit can employ low-temperature polysilicon thin-film transistors and oxide thin-film transistors. The active layer of the low-temperature polysilicon thin-film transistor uses low-temperature polysilicon (LTPS, Low Temperature Poly-Silicon), and the active layer of the oxide thin-film transistor uses an oxide semiconductor (Oxide). The low-temperature polysilicon thin-film transistor has advantages such as high mobility and fast charging, and the oxide thin-film transistor has advantages such as low leakage current. Integrating the low-temperature polysilicon thin-film transistor and the oxide thin-film transistor on a display substrate, that is, an LTPS+Oxide (abbreviated as LTPO) display substrate, can utilize the advantages of both, can achieve low-frequency driving, can reduce power consumption, and can improve display quality.

[0078] In some examples, the light-emitting element can be any one of a light-emitting diode (LED, Light Emitting Diode), an organic light-emitting diode (OLED, Organic Light Emitting Diode), a quantum dot light-emitting diode (QLED, Quantum Dot Light Emitting Diode), a micro-LED (including: mini-LED or micro-LED), etc. For example, the light-emitting element can be an OLED, and the light-emitting element can emit red light, green light, blue light, or white light, etc. under the drive of its corresponding pixel circuit. The color of the light emitted by the light-emitting element can be determined according to needs. In some examples, the light-emitting element can include: an anode, a cathode, and an organic light-emitting layer located between the anode and the cathode. The anode of the light-emitting element can be electrically connected to the corresponding pixel circuit. However, this embodiment is not limited thereto.

[0079] In some examples, the display substrate can integrate a touch structure. The display substrate can include: an organic light-emitting diode display structure, or can be a plasma display structure, or can be an electrophoretic display structure. For example, the display substrate can include an OLED display structure and a touch structure. The touch structure can be disposed on the encapsulation layer of the display structure to form a structure of Touch on Thin Film Encapsulation (abbreviated as Touch on TFE). The display structure and the touch structure are integrated together, having advantages such as being thin, light, and foldable, and can meet product requirements such as flexible folding and narrow borders.

[0080] In some examples, the structure of the touch control structure on the thin film encapsulation mainly includes a Flexible Multi-Layer On Cell (FMLOC) structure and a Flexible Single-Layer On Cell (FSLOC) structure. The FMLOC structure is based on the working principle of mutual capacitance detection. Generally, two layers of metal are used to form the driving (Tx) electrode and the sensing (Rx) electrode. The integrated circuit (IC) realizes the touch control action by detecting the mutual capacitance between the driving electrode and the sensing electrode. The FSLOC structure is based on the working principle of self-capacitance (or voltage) detection. Generally, a single layer of metal is used to form the touch control electrode. The integrated circuit realizes the touch control action by detecting the self-capacitance (or voltage) of the touch control electrode.

[0081] Figure 2 For Figure 1a a schematic cross-sectional view taken along the line aa' in the display area of the shown display substrate. Figure 2 The structure of a sub-pixel in the display area is schematically shown as an example. In this example, it is described by taking the case where the types of multiple transistors in the pixel circuit are the same. For example, multiple transistors in the pixel circuit can all use low-temperature polysilicon thin-film transistors or all use oxide thin-film transistors. In some other examples, multiple transistors in the pixel circuit can use low-temperature polysilicon thin-film transistors and oxide thin-film transistors. In addition, this example is described by taking the display substrate integrated with a mutual capacitance type touch control structure to form an FMLOC structure as an example.

[0082] In some examples, as Figure 2 shown, in the direction Z perpendicular to the display substrate, the display area of the display substrate may include: a substrate 100, and a circuit structure layer 20, a light-emitting structure layer 30, a packaging structure layer 40, a touch control structure layer 50, and a color filter layer 60 sequentially disposed on the substrate 100. Among them, the display structure layer may at least include the circuit structure layer 20 and the light-emitting structure layer 30. The circuit structure layer 20 may at least include: pixel circuits of multiple sub-pixels, and the pixel circuit of each sub-pixel may include multiple transistors and at least one capacitor. The light-emitting structure layer 30 may at least include: light-emitting elements of multiple sub-pixels.

[0083] In some examples, Figure 2Taking an example of a thin film transistor 21 and a capacitor 22 included in each sub-pixel. In some examples, the circuit structure layer 20 of the display area may include: a semiconductor layer, a first gate metal layer, a second gate metal layer, a first source-drain metal layer, a second source-drain metal layer, and a third source-drain metal layer provided on the substrate 100. The multiple display area metal layers of the display structure layer in this example may include: a first gate metal layer, a second gate metal layer, a first source-drain metal layer, a second source-drain metal layer, and a third source-drain metal layer. A first gate insulating layer 201 may be provided between the semiconductor layer and the first gate metal layer, a second gate insulating layer 202 may be provided between the first gate metal layer and the second gate metal layer, an interlayer insulating layer 203 may be provided between the second gate metal layer and the first source-drain metal layer, a passivation layer 204 and a first planarization layer 205 may be provided between the first source-drain metal layer and the second source-drain metal layer, a second planarization layer 206 may be provided between the second source-drain metal layer and the third source-drain metal layer, and a third planarization layer 207 may be provided on the side of the third source-drain metal layer away from the substrate 100. Among them, the first gate insulating layer 201, the second gate insulating layer 202, the interlayer insulating layer 203, and the passivation layer 204 may be inorganic insulating layers, and the first planarization layer 205, the second planarization layer 206, and the third planarization layer 207 may be organic insulating layers. However, this embodiment is not limited thereto. In some other examples, a buffer layer may also be provided on the side of the semiconductor layer close to the substrate. The buffer layer can prevent harmful substances in the substrate from invading the interior of the display substrate and can also increase the adhesion of the film layers in the display substrate to the substrate. In some other examples, a bottom shielding metal layer (BSM, Bottom Shielding Metal) may be provided on the side of the buffer layer close to the substrate. The bottom shielding metal layer may be configured to at least partially cover the active layer of the thin film transistor of the pixel circuit to avoid the influence of external light on the performance of the thin film transistor. In some other examples, the passivation layer may be omitted between the first source-drain metal layer and the second source-drain metal layer, and only the first planarization layer may be provided between the first source-drain metal layer and the second source-drain metal layer.

[0084] In some examples, such as Figure 2As shown, the semiconductor layer of the display region may at least include: the active layer 210 of the thin-film transistor 21. The active layer 210 of the thin-film transistor 21 may include: a first region 2101, a second region 2102, and a channel region 2100 located between the first region 2101 and the second region 2102. The first gate metal layer may at least include: the gate 213 of the thin-film transistor 21, and the first electrode plate 221 of the capacitor 22. The orthogonal projection of the gate 213 of the thin-film transistor 21 on the substrate 100 may cover the orthogonal projection of the channel region 2100 of the active layer 210 on the substrate 100. The second gate metal layer may at least include: the second electrode plate 222 of the capacitor 22. The orthogonal projections of the second electrode plate 222 and the first electrode plate 221 of the capacitor 22 on the substrate 100 may at least partially overlap, for example, they may coincide. The first source-drain metal layer may at least include: the source 211 and the drain 212 of the thin-film transistor 21. The interlayer insulating layer 203 may be provided with a plurality of vias in the display region (for example, including a first pixel via and a second pixel via). The interlayer insulating layer 203, the second gate insulating layer 202, and the first gate insulating layer 201 within the first pixel via may be removed to expose at least a part of the surface of the first region 2101 of the active layer 210; the interlayer insulating layer 203, the second gate insulating layer 202, and the first gate insulating layer 201 within the second pixel via may be removed to expose at least a part of the surface of the second region 2102 of the active layer 210. The source 211 of the thin-film transistor 21 may be electrically connected to the first region 2101 of the active layer 210 through the first pixel via, and the drain 212 may be electrically connected to the second region 2102 of the active layer 210 through the second pixel via. The second source-drain metal layer may at least include: a first transfer electrode 231. The first transfer electrode 231 may be electrically connected to the drain 212 of the thin-film transistor 21 of the pixel circuit through a third pixel via opened in the passivation layer 204 and the first planarization layer 205. The third source-drain metal layer may at least include: a second transfer electrode 232. The second transfer electrode 232 may be electrically connected to the first transfer electrode 231 located in the second source-drain metal layer through a fourth pixel via opened in the second planarization layer 206. The second transfer electrode 232 may be electrically connected to the first electrode 301 (for example, the anode) of the light-emitting element through a fifth pixel via opened in the third planarization layer 207. In this example, the electrical connection between the pixel circuit and the light-emitting element may be achieved through the first transfer electrode 231 and the second transfer electrode 232.

[0085] In some examples, the gate lines of the display area may be located in the first gate metal layer or the second gate metal layer, for example, the data lines of the display area may be located in the second source-drain metal layer or the third source-drain metal layer, and the high-potential power supply line of the display area may be located in at least one of the second source-drain metal layer and the third source-drain metal layer. This embodiment is not limited thereto. The circuit structure layer of this example may include three source-drain metal layers, which can avoid arranging more traces in a single source-drain metal layer, thereby facilitating the implementation of a narrow border structure.

[0086] In some examples, as Figure 2 shown, the light-emitting structure layer 30 may include: a pixel definition layer 304 and a plurality of light-emitting elements. For example, each light-emitting element may include: a stacked first electrode 301, an organic light-emitting layer 302, and a second electrode 303 (cathode). The first electrode 301 of the light-emitting element may be an anode, and the first electrode 301 may be disposed on the third planar layer 207 and electrically connected to the second transfer electrode 232 through a fifth pixel via formed in the third planar layer 207. The pixel definition layer 304 is disposed on the first electrode 301 and the third planar layer 207. The pixel definition layer 304 may be provided with a plurality of pixel openings, and one pixel opening may expose at least a part of the surface of a corresponding first electrode 301. At least a part of the organic light-emitting layer 302 may be disposed in a pixel opening and connected to the corresponding first electrode 301. The second electrode 303 may be disposed on the organic light-emitting layer 302 and connected to the organic light-emitting layer 302. The organic light-emitting layer 302 can emit light of a corresponding color under the drive of the first electrode 301 and the second electrode 303. An isolation column layer may also be disposed on the side of the pixel definition layer 304 away from the substrate 100, and the isolation column layer may include a plurality of isolation columns (PS).

[0087] In some examples, the organic light-emitting layer 302 of the light-emitting element may include a light-emitting layer (EML, Emitting Layer), and one or more film layers including a hole injection layer (HIL, Hole Injection Layer), a hole transport layer (HTL, Hole Transport Layer), a hole block layer (HBL, Hole Block Layer), an electron block layer (EBL, Electron Block Layer), an electron injection layer (EIL, Electron Injection Layer), and an electron transport layer (ETL, Electron Transport Layer). Under the voltage drive of the first electrode 301 and the second electrode 303, the light-emitting characteristics of the organic material can be used to emit light according to the required gray level.

[0088] In some examples, the light-emitting layers of light-emitting elements of different colors may be different. For example, a red light-emitting element includes a red light-emitting layer, a green light-emitting element includes a green light-emitting layer, and a blue light-emitting element includes a blue light-emitting layer. To reduce the process difficulty and improve the yield, the hole injection layer and the hole transport layer on one side of the light-emitting layer may adopt a common layer, and the electron injection layer and the electron transport layer on the other side of the light-emitting layer may adopt a common layer. In some examples, any one or more of the hole injection layer, the hole transport layer, the electron injection layer, and the electron transport layer may be fabricated by a single process (a single evaporation process or a single inkjet printing process), and isolation may be achieved by the surface step difference of the formed film layer or by means such as surface treatment. For example, any one or more of the hole injection layer, the hole transport layer, the electron injection layer, and the electron transport layer corresponding to adjacent sub-pixels may be isolated. In some examples, the organic light-emitting layer may be formed by evaporation using a fine metal mask (FMM) or an open mask, or may be formed by an inkjet process.

[0089] In some examples, as Figure 2 shown, in a direction perpendicular to the substrate, the encapsulation structure layer 40 may include a stacked first encapsulation layer 401, a second encapsulation layer 402, and a third encapsulation layer 403. Among them, the first encapsulation layer 401 and the third encapsulation layer 403 may adopt inorganic materials such as silicon nitride, silicon oxide, silicon oxynitride, etc. The inorganic materials have high density and can prevent the intrusion of water, oxygen, etc. The second encapsulation layer 402 may adopt an organic material. The second encapsulation layer 402 may be disposed between the first encapsulation layer 401 and the third encapsulation layer 403 to ensure that external water vapor cannot enter the light-emitting element. The second encapsulation layer 402 may adopt an organic material. For example, it may be a polymer material containing a desiccant or a polymer material that can block water vapor, or may be a polymer resin, etc. to planarize the surface of the display substrate, and can relieve the stress between the first encapsulation layer 401 and the third encapsulation layer 403, and may also include water-absorbing materials such as desiccants to absorb substances such as water and oxygen that invade the interior. However, this embodiment is not limited thereto. For example, the encapsulation structure layer may adopt a five-layer stacked structure of inorganic / organic / inorganic / organic / inorganic.

[0090] In some examples, the touch structure layer in the display area may include: a plurality of first touch electrodes, a plurality of first connection parts, a plurality of second touch electrodes, and a plurality of second connection parts. The plurality of first touch electrodes may be arranged in the same layer, and adjacent first touch electrodes may be connected by the first connection parts. The plurality of second touch electrodes may be arranged in the same layer, and adjacent second touch electrodes may be connected by the second connection parts.

[0091] In some examples, as Figure 2As shown in the figure, in the direction perpendicular to the substrate, the touch structure layer 50 of the display area may include: a touch buffer layer (TBL) 501, a first touch conductive layer 511, a touch interlayer insulating layer (TLD) 502, and a second touch conductive layer 512, which are sequentially arranged. Among them, the touch buffer layer 501 and the touch interlayer insulating layer 502 may be inorganic insulating layers, such as SiNx layers. For example, the first touch conductive layer 511 may include a plurality of first touch electrodes, a plurality of second touch electrodes, and a plurality of first connection parts. The first touch electrodes and the first connection parts may be an integrally connected structure. The second touch conductive layer 512 may include a plurality of second connection parts. The second connection parts may be interconnected with adjacent second touch electrodes through vias formed in the touch interlayer insulating layer. However, this embodiment is not limited thereto. In some other examples, the first touch conductive layer may include a plurality of first touch electrodes, a plurality of second touch electrodes, and a plurality of second connection parts, and the second touch electrodes and the second connection parts may be an integrally connected structure; the second touch conductive layer may include a plurality of first connection parts, and the first connection parts may be interconnected with adjacent first touch electrodes through vias formed in the touch interlayer insulating layer. In some examples, the first touch electrodes may be driving (Tx) electrodes, and the second touch electrodes may be sensing (Rx) electrodes. Alternatively, the first touch electrodes may be sensing (Rx) electrodes, and the second touch electrodes may be driving (Tx) electrodes. This embodiment is not limited thereto.

[0092] In some examples, the first touch electrodes and the second touch electrodes may have a rhombus shape, such as a regular rhombus, or a horizontally elongated rhombus, or a vertically elongated rhombus. In some other examples, the first touch electrodes and the second touch electrodes may have any one or more of a triangle, a square, a trapezoid, a parallelogram, a pentagon, a hexagon, and other polygons. The embodiments of the present disclosure are not limited herein.

[0093] In some examples, the first touch electrodes and the second touch electrodes may be in the form of transparent conductive electrodes. In some other examples, the first touch electrodes and the second touch electrodes may be in the form of a metal mesh. The metal mesh may be formed by interweaving a plurality of metal wires. The metal mesh may include a plurality of mesh patterns, and the mesh patterns may be polygons formed by a plurality of metal wires. The first touch electrodes and the second touch electrodes in the form of a metal mesh have the advantages of low resistance, small thickness, and fast response speed.

[0094] In some examples, such as Figure 2As shown, in the direction perpendicular to the substrate, the color filter layer (Colorfilter On Encapsulation, COE) 60 may include: an insulating layer 601, a color film layer, and an overcoat (OC) film 602 arranged in sequence. The color film layer includes a black matrix 610 and color filter units 611 disposed between the black matrix 610. The color filter units 611 may be, for example, red filter units, green filter units, or blue filter units.

[0095] In some examples, as Figure 1a shown, the first border region B1 of the display substrate may include: a fan-out routing region B11 and a signal access region B12 arranged in sequence along the direction away from the display region AA. Figure 1a Only several traces within the first border region are schematically shown for illustration. The number of traces in the first border region is not limited in this example.

[0096] In some examples, as Figure 1a shown, the fan-out routing region B11 may be connected between the display region AA and the signal access region B12. The fan-out routing region B11 may be provided with at least multiple data fan-out lines 42. The multiple data fan-out lines 42 may be electrically connected to multiple data lines DL in the display region AA. For example, the multiple data fan-out lines 42 and the multiple data lines DL may be electrically connected in one-to-one correspondence. The multiple data fan-out lines 42 may extend towards the signal access region B12 in a fan-out routing manner. The multiple data fan-out lines 42 and the multiple data lines DL may be located in different film layers, and the data fan-out lines 42 may be connected to the data lines DL through vias formed in the insulating layer.

[0097] In some examples, as Figure 1a shown, the signal access region B12 may include at least one first signal access region B121. This example is schematically shown and described by taking one first signal access region as an example. In other examples, the display substrate is a large-sized panel, and the display substrate may include multiple first signal access regions, and the multiple first signal access regions may be arranged in sequence along the first direction X.

[0098] In some examples, as Figure 1aAs shown, the first signal access area B121 can also be referred to as the driving chip (IC) setting area. The first signal access area B121 can be provided with a plurality of driving pads 31, and the plurality of driving pads 31 can be configured to be bound and connected to at least one driving chip. The driving chip can be configured to generate driving signals required for driving sub-pixels and provide the driving signals to the data lines DL in the display area AA. For example, the driving signal can be a data signal for driving sub-pixels. In some examples, the driving chip can be a central processing unit, a digital signal processor, a system-on-chip (SoC), etc. For example, the driving chip can also include a hardware circuit and computer-executable code, etc. The hardware circuit can include conventional very large scale integration (VLSI) circuits or gate arrays and existing semiconductors such as logic chips and transistors or other discrete components; the hardware circuit can also include field programmable gate arrays, programmable array logic, programmable logic devices, etc.

[0099] In some examples, as Figure 1a shown, the signal access area B12 can be provided with at least a plurality of data line leads 101, and the plurality of data line leads 101 can be electrically connected to a plurality of data fan-out lines 42 in the fan-out line area B11, for example, in a one-to-one correspondence. For example, the data line lead 101 and the connected data fan-out line 42 can be an integrated structure connected to each other. That is, the plurality of data line leads 101 are electrically connected to the plurality of data lines DL through the plurality of data fan-out lines 42, for example, in a one-to-one correspondence. The plurality of data line leads 101 can extend into the first signal access area B121 and be electrically connected to the plurality of driving pads 31 in the first signal access area B121. For example, the plurality of data line leads 101 and the plurality of driving pads 31 can be electrically connected in a one-to-one correspondence, or one data line lead 101 can be electrically connected to at least one driving pad 31. The data line leads 101 and the data fan-out lines 42 can transmit the data signals provided by the driving chip to the data lines DL in the display area.

[0100] In some examples, as Figure 1b shown, the first border area B1 of the display substrate can include: a fan-out line area B11, a bending area B13, and a signal access area B12 arranged in sequence along the direction away from the display area AA. Figure 1b Only several traces in the first border area are schematically shown for illustration. The number of traces in the first border area in this example is not limited.

[0101] In some examples, as Figure 1bAs shown, the bending region B13 can be connected between the fan-out routing region B11 and the signal access region B12, and can be configured to bend the signal access region B12 to the back of the display region AA. The bending region B13 can be provided with at least multiple data bending connection lines 43. One end of the data bending connection line 43 can be connected to the data fan-out line 42 in the fan-out routing region B11, and the other end can be connected to the data line lead 101 in the signal access region B12. The multiple data bending connection lines 43 can be of the same layer structure, for example, located in the first source-drain metal layer or the second source-drain metal layer. For the remaining structure of the first border region B1 of this example, reference can be made to the description of the foregoing embodiments, and thus it will not be elaborated herein.

[0102] As Figure 1a and Figure 1b shown, the signal access region B12 may further include a second signal access region B122. Multiple bonding pads 32 are provided in the second signal access region B122 and are used for bonding with a flexible circuit board. The flexible circuit board (FPC) can be bonded to the second signal access region B122 through the FOP process (FPC On Panel). The driving pads 31 are used for bonding with at least one driving chip.

[0103] Figure 3 This is a partial enlarged view of the first signal access region of the embodiment of the present disclosure. In some examples, as Figure 3 shown, the multiple driving pads 31 of the first signal access region B121 can be arranged in multiple rows (for example, four rows). The multiple driving pads 31 included in each row can be arranged in sequence along the first direction X, and the multiple rows of driving pads 31 can be arranged in sequence along the second direction Y. The driving pads 31 in adjacent rows can be arranged in a staggered manner in the first direction X. However, this embodiment is not limited thereto. In other examples, the multiple pads of the first signal access region B121 can be arranged in one row.

[0104] In some examples, the multiple driving pads 31 of the first signal access region can be at least divided into multiple groups (for example, two groups). Figure 3Taking two sets of pads (for example, the first set of driving pads 31A and the second set of driving pads 31B) as an example for illustration and description. The second set of driving pads 31B can be located on a side of the first set of driving pads 31A away from the display area. The first set of driving pads 31A can include a plurality of first driving pads 311 arranged in three rows along the first direction X. The second set of driving pads 31B can include a plurality of second driving pads 312 arranged in one row along the first direction X. In some examples, the second set of driving pads 31B is used to input signals, and after signal conversion by the bonded IC, the signals are output to the first set of driving pads 31A. The first set of driving pads 31A transmits the signals (such as data signals) to a plurality of sub-pixels PX through a plurality of signal lines (such as a plurality of data lines DL). The first set of driving pads 31A and the second set of driving pads 31B can be arranged in a staggered manner in the first direction X. For example, the pads in the first set of driving pads 31A and the second set of driving pads 31B may not be aligned in the second direction Y. There is a gap between adjacent pads in the same set, and there is a gap between pads in adjacent sets. In some embodiments, a set of pads can be one row of pads, two rows of pads, or three rows of pads. The present disclosure does not limit the number of rows of pads and the number of pads in each row.

[0105] Figure 4a For Figure 3 a detailed enlarged view of the region S in. In some examples, as Figure 4a shown, a plurality of data line leads 101 can extend substantially along the second direction Y in the gaps between a plurality of driving pads 31. For example, two data line leads 101 can be provided between adjacent two driving pads 31 in a set of pads. One data line lead 101 can be electrically connected to at least one driving pad 31. For example, one data line lead 101 can be connected to one driving pad 31.

[0106] Figure 4b For Figure 4a a schematic cross-sectional structure view at the position A-A in, at least one driving pad 31 among a plurality of pads 31 can include:

[0107] a first insulating layer 102, located on a side of the plurality of data line leads 101 away from the substrate 100, and the first insulating layer 102 includes a first opening 110 exposing at least a part of at least one of the plurality of data line leads 101;

[0108] The first metal layer 1031 is located on a side of the plurality of data line leads 101 away from the substrate 100 and is electrically connected to at least one of the plurality of data line leads 101 through the first opening 110. Among them, the first metal layer 1031 includes a first bottom 1031a and a stepped portion surrounding the first bottom 1031a. The orthographic projection of the first bottom 1031a on the substrate 100 is located within the orthographic projection of the first opening 110 on the substrate 100. The first bottom 1031a is electrically connected to at least one of the plurality of data line leads 101. The stepped portion may include a first stepped portion 1031b on a side of the first insulating layer 102 away from the substrate 100 and a second stepped portion 1031c forming an angle with the first stepped portion 1031b. The second stepped portion 1031c connects the first bottom 1031a and the first stepped portion 1031b. The orthographic projection of the second stepped portion 1031c on the substrate 100 is located within the orthographic projection of the first opening 110 on the substrate 100.

[0109] The second insulating layer 104 is located on a side of the first metal layer 1031 and the first insulating layer 102 away from the substrate 100. Among them, the second insulating layer 104 includes a second opening 120 exposing at least a part of the first bottom 1031a of the first metal layer 1031.

[0110] In some examples, as Figure 4b shown, the driving pad 31 may further include a second metal layer 1032, which is located on a side of the first metal layer 1031 and the second insulating layer 104 away from the substrate 100. Among them, the second metal layer 1032 is electrically connected to the first metal layer 1031 through the second opening 120. The orthographic projection of the second metal layer 1032 on the substrate 100 at least partially overlaps with the orthographic projection of the second opening 120 on the substrate 100.

[0111] In an exemplary embodiment, as Figure 4b shown, the driving pad 31 may further include:

[0112] A third metal layer 1033, which is located on a side of the second metal layer 1032 away from the substrate 100. Among them, the third metal layer 1033 is electrically connected to the second metal layer 1032. The orthographic projection of the third metal layer 1033 on the substrate 100 covers the orthographic projection of the second metal layer 1032 on the substrate 100.

[0113] In an exemplary embodiment, as Figure 4b shown, the display substrate may further include:

[0114] A third insulating layer 106, which is located on a side of the third metal layer 1033 away from the substrate 100. The third insulating layer 106 includes a third opening 130.

[0115] Among them, as Figure 4b shown, the orthographic projection of the third opening 130 on the substrate substrate 100 is within the range of the orthographic projection of the second opening 120 on the substrate substrate 100, and the orthographic projection of the first opening 110 on the substrate substrate 100 is within the range of the orthographic projection of the third opening 130 on the substrate substrate 100.

[0116] In an exemplary embodiment, the third insulating layer 106 may include at least one of an inorganic insulating layer and an organic insulating layer.

[0117] In an exemplary embodiment, as Figure 4b shown, the first metal layer 1031 may further include a second bottom 1031e surrounding the stepped portion. The stepped portion may further include a third stepped portion 1031d forming an angle with the first stepped portion 1031b. The third stepped portion 1031d connects the second bottom 1031e and the first stepped portion 1031b. The orthographic projection of the second insulating layer 104 on the substrate substrate 100 at least partially overlaps with the orthographic projection of the second bottom 1031e on the substrate substrate 100.

[0118] In an exemplary embodiment, as Figure 4b shown, the display substrate may further include:

[0119] A fourth metal layer 108, located on the side of the third metal layer 1033 and the third insulating layer 106 facing away from the substrate substrate 100. Among them, the fourth metal layer 108 may be electrically connected to the third metal layer 1033 through the third opening 130. The orthographic projection of the fourth metal layer 108 on the substrate substrate 100 at least partially overlaps with the orthographic projection of the third metal layer 1033 on the substrate substrate 100. For example, the orthographic projection of the fourth metal layer 108 on the substrate substrate 100 may cover the orthographic projection of the third metal layer 1033 on the substrate substrate 100.

[0120] In an exemplary embodiment, as Figure 4b shown, the display substrate may further include:

[0121] A fourth insulating layer 107. In the direction Z perpendicular to the plane of the substrate substrate 100, the fourth insulating layer 107 may be located between the third insulating layer 106 and the fourth metal layer 108. Among them, the fourth insulating layer 107 may include a fourth opening 140. The orthographic projection of the fourth opening 140 on the substrate substrate 100 is within the orthographic projection of the third opening 130 on the substrate substrate 100. The fourth metal layer 108 may be electrically connected to the third metal layer 1033 through the third opening 130 and the fourth opening 140.

[0122] In an exemplary embodiment, as Figure 2 and 4bAs shown, the first insulating layer 102 may be disposed on the same layer as the interlayer insulating layer 203 and the second gate insulating layer 202, the second insulating layer 104 may be disposed on the same layer as the passivation layer 204, the third insulating layer 106 may be disposed on the same layer as the third planarization layer 207, and the fourth insulating layer 107 may be disposed on the same layer as at least one of the touch interlayer insulating layer 502 and the pixel defining layer 304. Between the substrate and the plurality of data line leads (i.e., the gate metal layer), layers such as a barrier layer, a buffer layer, etc. may also be arranged, as Figure 4b indicated by the film layer 105. The data line lead 101 may be disposed on the same layer as at least one of the first gate metal layer and the second gate metal layer, the first metal layer 1031 may be disposed on the same layer as the first source / drain metal layer, the second metal layer 1032 may be disposed on the same layer as the second source / drain metal layer, the third metal layer 1033 may be disposed on the same layer as the third source / drain metal layer, and the fourth metal layer 108 may be disposed on the same layer as one of the first touch conductive layer and the second touch conductive layer. In an exemplary embodiment, the third insulating layer 106 is not limited to being disposed on the same layer as the third planarization layer 207. For example, the third insulating layer 106 may be disposed on the same layer as the third planarization layer 207, or, in the direction Z perpendicular to the plane of the substrate 100, the third insulating layer 106 may be located between the third planarization layer 207 and the first electrode 301 (i.e., the anode).

[0123] In an exemplary embodiment, Figure 1a Compared with Figure 1b the difference is that Figure 1a the bending region B13 is not provided in Figure 1b so that the signal access region B12 cannot be bent to the back of the display region AA, and the other structures are the same as those in Figure 1a and Figure 1b The schematic diagram of the signal connection between the first signal access region B121 and the second signal access region B122 in Figure 5As shown, a first signal access area B121 is set to be bound and connected to an integrated circuit. Such a structure can be called a COP (Chip on Panel) structure. The integrated circuit can be a driver integrated circuit (abbreviated as DIC). The first signal access area B121 can be called a COP area or a DIC area (driver integrated circuit area). The second signal access area B122 can be called a flexible printed circuit board bonding area (which can be abbreviated as an FPC area). The first signal access area B121 and the second signal access area B122 can be collectively referred to as a pad area (i.e., a PAD area). The bonding test pad 32c in the FPC area can be connected to the drive test pad 31c in the DIC area through a test signal line L11. The bonding test pad 32c can provide a test signal (for testing the contact resistance of the drive pad 31) to the drive test pad 31c through the test signal line L11. The drive test pad 31c can be a drive pad for testing the contact resistance in the first signal access area B121, and the bonding test pad 32c can be a bonding pad for testing the contact resistance in the second signal access area B122. The DIC area can be connected to the FPC area through a connection line L21. The bonding pad 32 in the FPC area can provide a working signal to the drive pad 31 in the DIC area through the connection line L21. The driver integrated circuit (DIC) can also be bonded to the flexible printed circuit board, which can reduce the size of the first border area B1. Such a structure can be called a chip on flexible (COF).

[0124] In the COP structure, the COP area needs to be provided with signals through a flexible printed circuit board (FPC), and the contact resistance of the drive pad 31 (IC Bonding Pad) also needs to be monitored through the FPC. When testing the contact resistance of the drive pad 31, in the case where the length dimension of the test signal line L11 is large and the resistance of the test signal line L11 is high (for example, for a metal material with low conductivity, the resistance will be relatively large), the resistance of the test signal line L11 is usually relatively large, resulting in inaccurate testing of the contact resistance of the drive pad 31. And the contact resistance of the drive pad 31 (i.e., the contact resistance between the drive pad 31 and the pins of the driver integrated circuit) is important for evaluating the performance of the display substrate. In the case where the testing of the contact resistance of the drive pad 31 is inaccurate, the performance testing of the display substrate is also inaccurate.

[0125] Embodiments of the present disclosure provide a display substrate, which may include:

[0126] A substrate, the substrate includes a display area and a first border area located on at least one side of the display area;

[0127] At least one test group, located in the first border area, and a plurality of driving test pads, a plurality of bonding test pads, and a plurality of test signal lines are included in the same test group;

[0128] Wherein, in the same test group: the plurality of bonding test pads are located on a side of the plurality of driving test pads away from the display area, the plurality of bonding test pads correspond to the plurality of test signal lines one by one, one bonding test pad in the plurality of bonding test pads is electrically connected to one driving test pad in the plurality of driving test pads through a corresponding test signal line, the one driving test pad is electrically connected to at least one bonding test pad in the plurality of bonding test pads through at least one test signal line in the plurality of test signal lines, at least two driving test pads in the plurality of driving test pads are electrically connected, and the plurality of driving test pads are located at positions adjacent to the plurality of bonding test pads.

[0129] In the display substrate provided by the embodiments of the present disclosure, a display area and a first border area located on at least one side are included. The first border area includes at least one test group. The test group includes a plurality of driving test pads, a plurality of bonding test pads, and a plurality of test signal lines. In the same test group, the bonding test pads are located on a side of the driving test pads away from the display area. The plurality of bonding test pads correspond to the plurality of test signal lines one by one. One bonding test pad is electrically connected to one of the driving test pads through a corresponding test signal line. One driving test pad is electrically connected to at least one bonding test pad through at least one test signal line. The plurality of driving test pads are located at positions adjacent to the plurality of bonding test pads, which can minimize the length of the test signal lines, reduce the resistance of the test signal lines, and improve the accuracy of the contact resistance of the test driving pads. The drawings of the embodiments of the present disclosure only relate to the structures involved in the embodiments of the present disclosure, and other structures can refer to the general design.

[0130] Such as Figure 1a 、 Figure 1b 、 Figures 6a to 8 shown, Figure 1a 、 Figure 1b is a schematic plan view of the display substrate, Figures 6a to 6b is a schematic structural view of the connection between the driving test pad and the bonding test pad, Figure 7 is Figure 6a an enlarged structural view of the position of R1 in Figure 8 is Figure 6a a schematic structural view of one test group in

[0131] A substrate 100, and the substrate 100 may include a display area AA and a first border area B1 located on at least one side of the display area AA;

[0132] At least one test group C11 is located in the first border area B1. The same test group C11 may include multiple driving test pads 31c, multiple bonding test pads 32c, and multiple test signal lines L11.

[0133] Among them, in the same test group C11, the bonding test pads 32c may be located on the side of the driving test pads 31c away from the display area AA. The multiple bonding test pads 32c may correspond one-to-one to the multiple test signal lines L11. One of the multiple bonding test pads 32c may be electrically connected to one of the multiple driving test pads 31c through the corresponding test signal line L11. One driving test pad 31c may be electrically connected to at least one of the multiple bonding test pads 32c through at least one of the multiple test signal lines L11. At least two of the multiple driving test pads 31c may be electrically connected, and the multiple driving test pads 31c may be located at positions adjacent to the multiple bonding test pads 32c.

[0134] In an exemplary embodiment, in the same test group C11, the multiple driving test pads 31c are located at positions adjacent to the multiple bonding test pads 32c, which can reduce the length of the test signal lines L11, thereby reducing the resistance of the test signal lines L11 and improving the accuracy of the contact resistance of the test driving pads.

[0135] In an exemplary embodiment, as Figures 6a to 8 shown, the display substrate may further include:

[0136] Multiple driving pads 31 are located in the first border area B1. In the first direction X, the multiple driving test pads 31c in the at least one test group C11 may be located on at least one side of the multiple driving pads 31.

[0137] Multiple bonding pads 32 are located in the first border area B1. The multiple bonding pads 32 are located on the side of the multiple driving pads 31 away from the display area AA. In the first direction X, the multiple bonding test pads 32c in the at least one test group C11 may be located on at least one side of the multiple bonding pads 32.

[0138] In the same test group C11, in the first direction X, the multiple driving test pads 31c, the multiple bonding test pads 32c, and the multiple test signal lines L11 are located on the same side of the multiple driving pads 31 and the multiple bonding pads 32.

[0139] In an exemplary embodiment, the contact resistance of the driving test pad 31c refers to the contact resistance between the driving test pad 31c and the pin in the driving integrated circuit.

[0140] In an exemplary embodiment, a plurality of driving test pads 31c in the test group C11 may be prepared and formed together with a plurality of driving pads 31. The structure of the driving test pads 31c is substantially the same as that of the driving pads 31 (for example, they may have the same structure, such as the structure shown in Figure 4b ). The driving test pads 31c in the test group C11 are used to test the contact resistance between the pins in the driving integrated circuit and are not electrically connected to the data lines DL in the display area AA. The detected contact resistance between the driving test pads 31c and the pins in the driving integrated circuit can be regarded as the contact resistance between the driving pads 31 and the pins in the driving integrated circuit.

[0141] In an exemplary embodiment, a plurality of bonding test pads 32c in the test group C11 may be prepared and formed together with a plurality of bonding pads 32. The structure of the bonding test pads 32c may be substantially the same as that of the bonding pads 321 (for example, they may have the same structure). The bonding test pads 32c are used to provide test signals to the driving test pads 31c electrically connected thereto and transfer corresponding electrical signals to the flexible printed circuit board FPC. Corresponding test points are provided on the flexible printed circuit board FPC. The electrical signals are obtained through the test points, and the contact resistance between the driving test pads 31c and the pins in the driving integrated circuit is obtained according to the provided test signals and the obtained electrical signals, so as to obtain the contact resistance between the driving pads 31 and the pins in the driving integrated circuit.

[0142] In an exemplary embodiment, as shown in Figures 6a to 7 , the display substrate may further include a plurality of driving virtual pads 33 and a plurality of bonding virtual pads 34. The driving pads 31, the driving test pads 31c, and the driving virtual pads 33 may be within the range of the first signal access area B121. The bonding pads 32, the bonding test pads 32c, and the bonding virtual pads 34 may be within the range of the second signal access area B122. In the first direction X, the driving test pads 31c may be located on both sides of the plurality of driving pads 31, the bonding test pads 32c may be located on both sides of the plurality of bonding pads 32, the plurality of driving virtual pads 33 may be located on the side of the driving test pads 31c away from the plurality of driving pads 31, and the plurality of bonding virtual pads 34 may be located on the side of the bonding test pads 32c away from the plurality of bonding pads 32. That is, in the first direction X, the driving virtual pads 33 and the bonding virtual pads 34 are located at the outermost edge positions. The driving virtual pads 33 and the bonding virtual pads 34 are not electrically connected to other signal lines and do not transmit signals during the normal operation of the display substrate. The driving virtual pads 33 can protect the driving test pads 31c and the driving pads 31, and the bonding virtual pads 34 can protect the bonding pads 32 and the bonding test pads 32c.

[0143] In an exemplary embodiment, as Figure 1a , Figure 1b and Figure 3 shown, the display substrate may further include:

[0144] A plurality of sub-pixels PX, located on one side of the substrate substrate and within the display area AA;

[0145] A plurality of data lines DL, located within the display area AA and electrically connected to the plurality of sub-pixels PX, the plurality of data lines DL being configured to provide data signals to the plurality of sub-pixels PX;

[0146] Wherein, the plurality of driving pads 31 may include a plurality of first driving pads 311 and a plurality of second driving pads 312, the plurality of second driving pads 312 may be located on a side of the plurality of first driving pads 311 away from the display area AA, and the plurality of first driving pads 311 are electrically connected to the plurality of data lines DL; at least some of the plurality of bonding pads 32 are electrically connected to the plurality of second driving pads 312, and the conductivity of at least part of the structure of the plurality of test signal lines L11 in the at least one test group C11 is consistent with the conductivity of the plurality of data lines DL.

[0147] In an exemplary embodiment, the data line DL generally uses a material with a relatively high conductivity and usually has a relatively low resistance. The conductivity of at least part of the structure of the test signal line L11 is consistent with the conductivity of the data line DL, which may be that at least part of the structure of the test signal line L11 uses the same material as the data line DL, or at least part of the structure of the test signal line L11 uses a material with a conductivity substantially consistent with or the same as that of the data line DL, so that the resistance of the test signal line L11 is relatively low, thereby improving the accuracy of the contact resistance test of the driving pad 31.

[0148] In an exemplary embodiment, as Figure 5 shown, at least some of the bonding pads 32 may be electrically connected to the plurality of second driving pads 312 through a plurality of connection lines L21 respectively, thereby realizing the electrical connection between the DIC area and the FPC area.

[0149] In an exemplary embodiment, as Figure 6b shown, the at least one test group C11 may include at least one first test group C111 and at least one second test group C112;

[0150] In the same first test group C111: It may include a plurality of first driving test pads 31c1, a plurality of first bonding test pads 32c1, and a plurality of first test signal lines L11c1. The plurality of first bonding test pads 32c1 correspond one-to-one with the plurality of first test signal lines L11c1. One of the plurality of first bonding test pads 32c1 is electrically connected to one of the plurality of first driving test pads 31c1 through the corresponding first test signal line L11c1. One of the first driving test pads 31c1 may be electrically connected to at least one of the plurality of first bonding test pads 32c1 through at least one of the plurality of first test signal lines L11c1;

[0151] In the same second test group C112: It may include a plurality of second driving test pads 31c2, a plurality of second bonding test pads 32c2, and a plurality of second test signal lines L11c2. The plurality of second bonding test pads 32c2 correspond one-to-one with the plurality of second test signal lines L11c2. One of the plurality of second bonding test pads 32c2 is electrically connected to one of the plurality of second driving test pads 31c2 through the corresponding second test signal line L11c2. One of the second driving test pads 31c2 may be electrically connected to at least one of the plurality of second bonding test pads 32c2 through at least one of the plurality of second test signal lines L11c2;

[0152] Among them, the plurality of second driving test pads 31c2 may be located on a side of the plurality of first driving test pads 31c1 away from the display area AA. In the first direction X, the plurality of first bonding test pads 32c1 may be located on a side of the plurality of second bonding test pads 32c2 away from the plurality of bonding pads 32.

[0153] In an exemplary embodiment, as Figure 6bAs shown, in the first direction X, multiple first driving test pads 31c1 in the same first test group C111 can be located on one side of multiple first driving pads 311, and multiple second driving test pads 31c2 in the same second test group C112 can be located on one side of multiple second driving pads 312. That is, multiple first driving test pads 31c1 in the first test group C111 and multiple second driving test pads 31c2 in the second test group C112 can be located at the edge position of the first signal access area B121. Similarly, multiple first bonding test pads 32c1 in the first test group C111 and multiple second bonding test pads 32c2 in the second test group C112 can be located at the edge position of the second signal access area B122. That is, in the first direction X, multiple first bonding test pads 32c1 and multiple second bonding test pads 32c2 can be located on one side of multiple bonding pads 32.

[0154] In an exemplary embodiment, the first test group C111 can be used to test the contact resistance between the first driving pad 311 (which can be referred to as a signal output pad) and the driving integrated circuit pin, and the second test group C112 can be used to test the contact resistance between the second driving pad 312 (which can be referred to as a signal input pad) and the driving integrated circuit pin.

[0155] In an exemplary embodiment, as Figure 6a and Figure 8 shown, at least one test signal line L11 among multiple test signal lines L11 can include a first structural portion h1, a second structural portion h2, and a third structural portion h3;

[0156] In the same test signal line L11: One end of the second structural portion h2 is connected to the first structural portion h1, and the other end is connected to the third structural portion h3; The other end of the first structural portion h1 is electrically connected to one of the driving test pads 31c among multiple driving test pads 31c, and the other end of the third structural portion h3 is electrically connected to the corresponding bonding test pad 32c.

[0157] In an exemplary embodiment, as Figure 6a and Figure 8 shown, the first structural portion h1 can be a zigzag or strip-shaped extending along the first direction X, the second structural portion h2 can be a strip-shaped or zigzag extending along the second direction Y, and the third structural portion h3 can be a zigzag extending along the first direction X.

[0158] In an exemplary embodiment, in the direction Z perpendicular to the plane of the substrate, the first structural portion h1 and the third structural portion h3 may be located on the side of the second structural portion h2 closer to the substrate, or the first structural portion h1 and the third structural portion h3 may be located on the side of the second structural portion h2 away from the substrate, or the first structural portion h1 and the third structural portion h3 may be provided on the same layer as the second structural portion h2.

[0159] In an exemplary embodiment, as Figures 1a to 2 shown, the display area AA may include a plurality of sub-pixels PX and a plurality of data lines DL. The plurality of data lines DL may be electrically connected to the plurality of sub-pixels PX, and the plurality of data lines DL are configured to provide data signals to the sub-pixels PX; at least one of the plurality of sub-pixels PX may include a pixel driving circuit, and the pixel driving circuit may include a plurality of transistors and at least one capacitor;

[0160] In the direction Z perpendicular to the plane of the substrate 100, the capacitor may include: a first electrode plate on one side of the substrate 100, and a second electrode plate on the side of the first electrode plate away from the substrate 100; the transistor may include: an active layer, a control electrode, a first electrode, and a second electrode. The active layer may be located between the first electrode plate and the substrate 100, the control electrode may be provided on the same layer as the first electrode plate, the first electrode and the second electrode may be located on the side of the second electrode plate away from the substrate 100, and the data line DL may be located on the side of the first electrode and the second electrode away from the substrate 100;

[0161] The second structural portion h2 may be provided on the same layer as at least one of the first electrode and the second electrode and the data line DL, that is, the conductivity of the second structural portion h2 is substantially the same as that of the data line DL, and the resistance of the test signal line L11 can be reduced; the same conductivity may be the same, or there may be a certain difference, but the difference is not large.

[0162] In an exemplary embodiment, as Figure 2 shown, the first electrode and the second electrode may be located in the first source-drain metal layer, and the data line DL may be located in the second source-drain metal layer or the third source-drain metal layer, that is, the second structural portion h2 may be a single-layer structure or a multi-layer structure in at least one of the first source-drain metal layer, the second source-drain metal layer, and the third source-drain metal layer.

[0163] In an exemplary embodiment, as Figure 6a 、 Figure 7 and Figure 8As shown, the second structural part h2 can be provided on the same layer as the first electrode and the second electrode, but is not limited thereto. For example, the second structural part h2 can be a double-layer structure provided on the same layer as the first electrode, the second electrode, and the data line DL, which can further reduce the resistance of the test signal line L11, thereby improving the accuracy of the contact resistance test of the driving test pad 31c.

[0164] In an exemplary embodiment, as Figure 6a and Figure 8 shown, the first structural part h1 and the third structural part h3 can be provided on the same layer as at least one of the control electrode and the second electrode plate, or the first structural part h1 and the third structural part h3 can be provided on the same layer as at least one of the first electrode, the second electrode, and the data line DL. For example, the first structural part h1 and the third structural part h3 can be provided on the same layer as the control electrode, or the first structural part h1 and the third structural part h3 can be a double-layer structure provided on the same layer as the control electrode and the second electrode plate, or the first structural part h1 and the third structural part h3 can be a double-layer structure provided on the same layer as the first electrode, the second electrode, and the data line DL. The double-layer structure can reduce the resistance of the first structural part h1 and the third structural part h3, thereby reducing the resistance of the test signal line L11 and improving the accuracy of the contact resistance test of the driving test pad 31c.

[0165] In an exemplary embodiment, as Figure 2 shown, the control electrode can be located in the first gate metal layer, and the second electrode plate of the capacitor can be located in the second gate metal layer, that is, the first structural part h1 and the third structural part h3 can be a single-layer structure or a double-layer structure in at least one of the first gate metal layer and the second gate metal layer; or the first structural part h1 and the third structural part h3 can be a single-layer structure or a multi-layer structure in at least one of the first source-drain metal layer, the second source-drain metal layer, and the third source-drain metal layer. In an exemplary embodiment, as Figure 2 shown, at least one sub-pixel PX can further include a light-emitting structure layer 30. The light-emitting structure layer 30 can be located on the side of the data line DL away from the substrate 100. The light-emitting structure layer 30 can include an anode 301, a light-emitting layer 302, and a cathode 303. In the direction Z perpendicular to the plane of the substrate 100, in the same sub-pixel PX, the light-emitting layer 302 can be located between the anode 301 and the cathode 303; the second structural part h2 can be provided on the same layer as at least one of the first electrode, the second electrode, the data line DL, the anode 301, and the cathode 303. For example, the second structural part h2 can be a multi-layer structure provided on the same layer as at least two of the first electrode, the second electrode, the data line DL, the anode 301, and the cathode 303, which can reduce the resistance of the second structural part h2, thereby reducing the resistance of the test signal line L11;

[0166] In a structure where the first structural portion h1 and the third structural portion h3 are located on a side of the second structural portion h2 away from the substrate 100, the first structural portion h1 and the third structural portion h3 can be provided on the same layer as at least one of the anode and the cathode. In a double-layer structure where the first structural portion h1 and the third structural portion h3 are provided on the same layer as the anode and the cathode, the resistance of the first structural portion h1 and the third structural portion h3 can be reduced, thereby reducing the resistance of the test signal line L11, reducing the influence of the test signal line L11 on the contact resistance test, and improving the accuracy of the contact resistance test.

[0167] In an exemplary embodiment, as Figure 2 , Figure 4b , Figure 6a shown, the first structural portion h1 and the third structural portion h3 are relatively close to the driving pad 31. Organic film layers (such as the first planarization layer 205, the second planarization layer 206, and the third planarization layer 207) near the driving pad 31 and the bonding pad 32 (the structure of the bonding pad 32 and the bonding test pad 32c is basically the same as that of the driving pad 31) usually need to be removed, which can avoid poor contact between the driving integrated circuit and the driving pad 31 and can also avoid poor contact between the bonding pad 32 and the flexible printed circuit board FPC. For example, the positions of the driving pad 31 and the test pad 31c need to remove the first planarization layer 205, the second planarization layer 206, and the third planarization layer 207 in the organic insulating layer, and the inorganic film layers (such as the first gate insulating layer 201, the second gate insulating layer 202, the interlayer insulating layer 203, and the passivation layer 204) can be retained. That is, the first planarization layer 205, the second planarization layer 206, and the third planarization layer 207 on the side of the first structural portion h1 and the third structural portion h3 away from the substrate 100 are etched away, and the first structural portion h1 and the third structural portion h3 are provided as a single-layer structure or a double-layer structure in at least one of the first gate metal layer and the second gate metal layer. The first structural portion h1 and the third structural portion h3 also have the interlayer insulating layer 203 and the passivation layer 204 as protective layers on the side away from the substrate 100, and the first structural portion h1 and the third structural portion h3 are not easily etched away during the process of preparing subsequent film layers (such as subsequent film layers may include film layers such as an anode and a cathode); in a structure where the first structural portion h1 and the third structural portion h3 are located in at least one of the first source-drain metal layer, the second source-drain metal layer, and the third source-drain metal layer, there is no protective film layer on the side of the first structural portion h1 and the third structural portion h3 away from the substrate 100, and they are easily etched away during the process of preparing subsequent film layers (such as subsequent film layers may include film layers such as an anode and a cathode).

[0168] In an exemplary embodiment, as Figure 2 , Figure 4b , Figure 6aAs shown, the second structural part h2 is relatively far from the driving pad 31 and the driving test pad 31c, which will not affect the electrical connection between the driving pad 31 and the driving integrated circuit, nor the electrical connection between the bonding pad 32 and the flexible printed circuit board FPC. The organic film layer (the organic film layer may include the first planar layer 205, the second planar layer 206, and the third planar layer 207) on the side of the second structural part h2 away from the substrate 100 will not be etched away. In the structure where the second structural part h2 is located in at least one of the first source-drain metal layer, the second source-drain metal layer, and the third source-drain metal layer, at least one organic film layer is provided on the side of the second structural part h2 away from the substrate 100 as a protective film layer (for example, among the organic film layers of the first planar layer 205, the second planar layer 206, and the third planar layer 207, at least the third planar layer 207 serves as the protective film layer), and it will not be etched away during the process of preparing subsequent film layers (for example, the subsequent prepared film layers may include film layers such as an anode and a cathode).

[0169] In an exemplary embodiment, the first gate metal layer, the second gate metal layer, the first source-drain metal layer, the second source-drain metal layer, and the third source-drain metal layer may adopt a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or an alloy material of the above metals, such as aluminum-ndodium alloy (AlNd) or molybdenum-niobium alloy (MoNb). It may be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo, Ti / Al / Ti, etc.

[0170] In an exemplary embodiment, the first source-drain metal layer, the second source-drain metal layer, and the third source-drain metal layer generally adopt materials with higher conductivity and relatively lower resistance, so that the resistance of the second structural part h2 in the test signal line L11 is lower, which can improve the accuracy of the contact resistance test of the driving pad 31. The conductivity of the first gate metal layer and the second gate metal layer is generally lower than that of the first source-drain metal layer, the second source-drain metal layer, and the third source-drain metal layer, so that the resistance of the first structural part h1 and the third structural part h3 is relatively higher. The length dimensions of the first structural part h1 and the third structural part h3 can be set to be smaller than the length dimension of the second structural part h2 to minimize the length dimensions of the first structural part h1 and the third structural part h3 in the test signal line L11 and reduce the resistance of the test signal line L11.

[0171] In an exemplary embodiment, as Figures 8 to 15 shown, Figure 8 and Figure 9 is Figure 6a a schematic diagram of a test group in Figures 10 to 15Several schematic diagrams of test group C11 are shown. At least two drive test pads 31c, at least two bonding test pads 32c, and at least two test signal lines L11 can be included in the same test group C11. At least two drive test pads 31c can be electrically connected to at least two bonding test pads 32c through at least two test signal lines L11.

[0172] In an exemplary embodiment, as Figures 9 to 15 shown, in the same test group C11, at least two drive test pads 31c can be located adjacent to at least two bonding test pads 32c, which can reduce the length of the test signal lines L11 and the resistance of the test signal lines L11, thereby improving the accuracy of the contact resistance test of the drive test pads 31c.

[0173] In an exemplary embodiment, as Figures 9 to 15 shown, in the same test group C11: the number of test signal lines L11 and the number of drive test pads 31c are both integer multiples of 2, the number of bonding test pads 32c is the same as the number of test signal lines L11, and is not less than the number of drive test pads 31c.

[0174] In an exemplary embodiment, as Figure 14 and Figure 15 shown, in the same test group C11, the number of drive test pads 31c, bonding test pads 32c, and test signal lines L11 are all two. The first ends of the two test signal lines L11 are respectively electrically connected to the two bonding test pads 32c, and the second ends are respectively electrically connected to the two drive test pads 31c. In an exemplary embodiment, Figure 14 and Figure 15 the structure shown in can test the contact resistance by the two-wire method.

[0175] In an exemplary embodiment, the first end of the test signal line L11 is located at one end on the side close to the bonding pad 32 (i.e., far from the display area AA), and the second end of the test signal line L11 can be at one end on the side close to the drive pad 31 (i.e., close to the display area AA).

[0176] In an exemplary embodiment, as Figure 9 and Figure 12 shown, in the same test group C11, the number of drive test pads 31c is two, the number of bonding test pads 32c and the number of test signal lines L11 are both four. The first ends of the four test signal lines L11 are respectively electrically connected to the four bonding test pads 32c. The second ends of two of the test signal lines L11 are electrically connected to one of the drive test pads 31c, and the second ends of the other two test signal lines L11 are electrically connected to the other drive test pad 31c. In an exemplary embodiment, Figure 9 andFigure 12 The structure shown can test the contact resistance by the four-wire method.

[0177] In an exemplary embodiment, as Figure 10 , Figure 11 and Figure 13 shown, in the same test group C11, the number of drive test pads 31c is two, and the number of bond test pads 32c and test signal lines L11 is six each. The first ends of the six test signal lines L11 are electrically connected to the six bond test pads 32c respectively. The second ends of three of the test signal lines L11 are electrically connected to one of the drive test pads 31c, and the second ends of the other three test signal lines L11 are electrically connected to the other drive test pad 31c. In an exemplary embodiment, Figure 10 , Figure 11 and Figure 13 the structure shown can test the contact resistance by combining the four-wire method and the two-wire method.

[0178] In an exemplary embodiment, as Figures 9 to 15 shown, the at least one test group C11 may further include a shorting wire L31. In the same test group C11, the two drive test pads 31c can be electrically connected through the shorting wire L31.

[0179] In an exemplary embodiment, the first test group C111 generally tests the contact resistance by the four-wire method or a combination of the four-wire method and the two-wire method, and the second test group C112 generally tests the contact resistance by the two-wire method, but not limited thereto. For example, both the first test group C111 and the second test group C112 can test the contact resistance by the four-wire method or a combination of the four-wire method and the two-wire method.

[0180] In an exemplary embodiment, in the Figures 9 to 11 shown structure, the second structural part h2 is a low-resistance trace region, Figure 9 and Figure 10 the first structural part h1 and the third structural part h3 in Figure 11 are high-resistance trace regions, Figure 11In the structure shown, the first structural portion h1, the second structural portion h2, and the third structural portion h3 in the test signal line L11 all adopt low-resistance routing regions, which can reduce the resistance of the test signal line L11 and improve the accuracy of contact resistance testing. In an exemplary embodiment, the length dimension of the second structural portion h2 is greater than the length dimension of the first structural portion h1, and the length dimension of the second structural portion h2 is greater than the length dimension of the third structural portion h3. The length dimension of the third structural portion h3 may be greater than the length dimension of the first structural portion h1. The second structural portion h2 generally adopts a low-resistance material. In the structure where the first structural portion h1 and the third structural portion h3 adopt high-resistance materials, the length dimension of the second structural portion h2 is larger, and the length dimensions of the first structural portion h1 and the third structural portion h3 are smaller, which can reduce the resistance of the test signal line L11.

[0181] In an exemplary embodiment, in Figures 9 to 11 the structure shown, the low-resistance routing region is generally provided on the same layer as at least one of the first electrode and the second electrode, and the data line DL. The high-resistance routing region is generally provided on the same layer as at least one of the control electrode of the transistor and the second electrode plate of the capacitor. For example, the low-resistance routing region may be a double-layer structure provided on the same layer as the first electrode and the second electrode, and the data line DL. The high-resistance routing region may be a double-layer structure provided on the same layer as the control electrode (the first electrode plate of the capacitor) of the transistor and the second electrode plate of the capacitor. In an exemplary embodiment, in Figures 9 to 11 the structure shown, the low-resistance routing region may adopt a low-resistance routing material, that is, the low-resistance routing region adopts a material with a higher conductivity, and the resistance is generally relatively low, so that the resistance of the test signal line L11 is low, thereby improving the accuracy rate of the contact resistance test of the driving pad 31.

[0182] In an exemplary embodiment, in Figures 9 to 15 the structure shown, the test group C11 may further include a short connection line L31. In the same test group C11, the number of driving test pads 31c is two, and the two driving test pads 31c can be electrically connected through the short connection line L31.

[0183] In an exemplary embodiment, in Figures 9 to 15 the structure shown, such as Figures 9 to 13As shown, the jumper wire L31 can be located in the pin PAIC of the driving integrated circuit IC. The two pins PAIC in the driving integrated circuit IC corresponding to the two driving test pads 31c are electrically connected through the jumper wire L31. After the driving integrated circuit IC is crimped with the driving test pads 31c, the two driving test pads 31c can be electrically connected through the jumper wire L31; alternatively, a jumper wire L31 is provided between two adjacent pins in the driving integrated circuit. After the driving integrated circuit is crimped with the driving test pads 31c, the jumper wire L31 is electrically connected to the two driving test pads 31c; or, as Figures 14 to 15 shown, the jumper wire L31 connects the two driving test pads 31c, and the structure of the driving test pads 31c can be the same as that of the driving pads 31 as Figure 4b shown. The jumper wire L31 can be arranged in the same layer as at least one of the first metal layer 1031, the second metal layer 1032, the third metal layer 1033, and the fourth metal layer 108 in the driving test pads 31c. For example, the jumper wire L31 can be a structure integrally formed with at least one of the first metal layer 1031, the second metal layer 1032, the third metal layer 1033, and the fourth metal layer 108 in the driving test pads 31c.

[0184] In an exemplary embodiment, the structures of the bonding pads 32, the bonding test pads 32c, and the driving test pads 31c can be substantially the same as the structure of the driving pads 31 as Figure 4b shown. The first structural portion h1 can be arranged in the same layer as the data lead 101 in the driving test pads 31c. For example, the first structural portion h1 can be a structure integrally formed with the data lead 101 in the driving test pads 31c. The data lead 101 of the bonding test pads 32c can be replaced by a third structural portion h3, that is, the third structural portion h3 extends into the corresponding bonding test pads 32c and is electrically connected to the first metal layer 1031. Alternatively, the third structural portion h3 can be electrically connected to the first metal layer 1031 in the bonding test pads 32c through a via; the bonding pads 32 can be not provided with the data lead 101.

[0185] In an exemplary embodiment, in the same test signal line L11, the second structural portion h2 can be electrically connected to the first structural portion h1 and the third structural portion h3 through vias.

[0186] The embodiments of the present disclosure also provide a contact resistance testing method for testing the contact resistance of the driving test pads 31c in the display substrate described in any of the above embodiments, as Figure 1a 、 Figure 1b 、 Figures 6a to 13As shown, the display substrate may include a display area AA and a first border area B1 located on at least one side of the display area AA. The first border area B1 may include at least one test group C11. The same test group C11 may include a plurality of driving test pads 31c, a plurality of bonding test pads 32c, and a plurality of test signal lines L11. In the same test group C11, the plurality of bonding test pads 32c may be located on a side of the driving test pads 31c away from the display area AA. The plurality of bonding test pads 32c may correspond to the plurality of test signal lines L11 one by one. One bonding test pad 32c among the plurality of bonding test pads 32c may be electrically connected to one driving test pad 31c among the plurality of driving test pads 31c through a corresponding test signal line L11. One driving test pad 31c may be electrically connected to at least one bonding test pad 32c among the plurality of bonding test pads 32c through at least one test signal line L11 among the plurality of test signal lines L11. At least two driving test pads 31c among the plurality of driving test pads 31c are electrically connected. The plurality of driving test pads 31c may be located at a position adjacent to the plurality of bonding test pads 32c. The plurality of bonding test pads 32c may include at least one first type of bonding test pad 321 and at least one second type of bonding test pad 322; The method may include:

[0187] Providing a first electrical signal to the first type of bonding test pad 321, testing a second electrical signal of the second type of bonding test pad 322, and obtaining a first contact resistance of the driving test pad 31c according to the first electrical signal and the second electrical signal.

[0188] In an exemplary embodiment, the contact resistance of the driving test pad 31c refers to the contact resistance between the driving test pad 31c and the pin in the driving integrated circuit, and this contact resistance may be regarded as the contact resistance between the driving pad 31 and the pin in the driving integrated circuit.

[0189] In an exemplary embodiment, as Figure 9 and Figure 12 shown, the at least one test group C11 may further include a short circuit wire L31. In the same test group C11: the number of driving test pads 31c is two, and the two driving test pads 31c may be electrically connected through the short circuit wire L31. The plurality of bonding test pads 32c may include two first type of bonding test pads 321 and two second type of bonding test pads 322. The plurality of test signal lines L11 may include two first type of test signal lines L111 and two second type of test signal lines L112. The two first type of bonding test pads 321 may be electrically connected to the two driving test pads 31c respectively through the two first type of test signal lines L111. The two second type of bonding test pads 322 may be electrically connected to the two driving test pads 31c respectively through the two second type of test signal lines L112.

[0190] In an exemplary embodiment, in Figure 12 the shown test group C11, a first electrical signal is provided to the first type of bonding test pad 321, and the second electrical signal of the second type of bonding test pad 322 is tested, which may include: providing a first current signal to one of the first type of bonding test pads 321, providing a ground signal to the other first type of bonding test pad 321, and testing the second voltage signals of the two second type of bonding test pads 322; the first electrical signal may include a first current signal and a ground signal, and the second electrical signal may include a second voltage signal. For example, the first current signal is I1, and the second voltage signals of the two second type of bonding test pads 322 obtained by testing are U2. Since the two second type of bonding test pads 322 are connected by a voltmeter to test the second voltage signal and the internal resistance of the voltmeter is relatively large, it can be considered that the two second type of bonding test pads 322 are open-circuited, and the current I12 flowing through the two second type of bonding test pads 322 can be ignored. The current flowing through the two drive test pads 31c is I11, then I1 = I11 + I12 ≈ I11. When the test signal line L11 is made of a low-resistance material, the resistance of the test signal line L11 can be ignored, and the resistance of the first type of bonding test pad 321 can also be ignored. The voltage is mainly concentrated on the two drive test pads 31c, then U2 ≈ I1 * 2 * R31c, and R31c1 ≈ U2 / (2 * I1). The first contact resistance R31c1 of the drive test pad 31c is basically not affected by the test signal line L11, and the test accuracy of the contact resistance is relatively high.

[0191] In an exemplary embodiment, in Figure 9 and Figure 12 the shown schematic diagram, the two first type of bonding test pads 321 may be located in the middle positions of the two second type of bonding test pads 322.

[0192] In an exemplary embodiment, as shown in 10, Figure 11 and 13 in the same test group C11, the multiple bonding test pads 32c may further include two third type of bonding test pads 323. Figure 10 , Figure 11 , Figure 12 For adding two third type of bonding test pads 323 on the basis of Figure 9 and Figure 12 the multiple test signal lines L11 may further include two third type of test signal lines L113, and the two third type of bonding test pads 323 may be electrically connected to the two drive test pads 31c respectively through the two third type of test signal lines L113;

[0193] Before providing the first electrical signal to the first type of bonding test pad 321, or after obtaining the first contact resistance of the driving test pad 31c based on the first electrical signal and the second electrical signal, it may further include: providing a third electrical signal to the third type of bonding test pad 323, testing the fourth electrical signal of the third type of bonding test pad 323, and obtaining the second contact resistance of the driving test pad 31c based on the third electrical signal and the fourth electrical signal.

[0194] In an exemplary embodiment, the third electrical signal may include a third voltage signal, the fourth electrical signal may include a third current signal, and the second contact resistance R31c2 of the driving test pad 31c is tested according to the third voltage signal and the third current signal.

[0195] In an exemplary embodiment, Figure 10 、 Figure 11 and Figure 13 In the structure shown in, a third voltage signal U3 is provided to two third-type bonding test pads 323, the third current signal I3 of the third-type bonding test pad 323 is tested, the second contact resistance of the driving test pad 31c is R31c2, and the resistance of the third-type test signal line L113 is RL11. Then: I3 * 2 * R31c2 + I3 * 2 * R32c + I3 * 2 * RL11 = U3. Since the resistance R32c of the bonding test pad 32c is small and the resistance of the test signal line L11 is low, I3 * 2 * R31c ≈ U3, and the second contact resistance R31c2 of the driving test pad 31c ≈ U3 / (2 * I3). When the resistance of the test signal line L11 is high, the resistance of the test signal line L11 is RL11. Then: I3 * 2 * R31c2 + I3 * 2 * L11 ≈ U3, and the second contact resistance R31c2 of the driving test pad 31c ≈ (U3 - I3 * 2 * L11) / (2 * I3). The resistance RL11 of the test signal line L11 can be obtained by pre-testing.

[0196] In an exemplary embodiment, the third electrical signal may include a fourth current signal, the fourth signal may include a fourth current signal, and the second contact resistance R31c2 of the driving test pad 31c is tested according to the fourth voltage signal and the fourth current signal.

[0197] In an exemplary embodiment, as Figure 13 shown, the resistance can be measured by providing a voltage signal to the third type of bonding test pad 323, testing the current signal of the third type of bonding test pad 323, and obtaining the second contact resistance R31c2 according to the provided voltage signal and the tested current signal; or the resistance can be measured by providing a current signal to the third type of bonding test pad 323, testing the voltage signal of the third type of bonding test pad 323, and obtaining the second contact resistance R31c2 according to the provided current signal and the tested voltage signal.

[0198] In an exemplary embodiment, the contact resistance R31c of the driving test pad 31c can be obtained by driving the first contact resistance of the test pad 31c to be R31c1 and the second contact resistance to be R31c2. For example, the finally obtained contact resistance R31c of the driving test pad 31c can be the average value of the first contact resistance R31c1 and the second contact resistance R31c2, that is, R31c = (R31c1 + R31c2) / 2.

[0199] In an exemplary embodiment, in Figure 14 and Figure 15 In the structure shown, a test group C11 may include two test signal lines L11, two bonding test pads 32c, and two driving test pads 31c. After connecting the two bonding test pads 32c with a multimeter, the measured resistance is R = 2R32c + 2R31c + 2RL11. The obtained resistance includes the resistance RL11 of the test signal line L11, and the contact resistance test is inaccurate. Since the multimeter has a resistance range, connect the two bonding test pads 32c to the interfaces of the two resistance ranges of the multimeter. For example, the multimeter can provide a current signal I to the bonding test pads 32c and measure the voltage U of the two bonding test pads 32c (these two bonding test pads 32c can be used as the first type of bonding test pads and multiplexed as the second type of bonding test pads). Then U = I*(2R32c + 2R31c + 2RL11), and the contact resistance R31c of the driving test pad 31c = U / (2*I) - R32c - RL11. In Figure 14 and Figure 15 In the structure shown, when the test signal line L11 is made of a low-resistance metal (a metal with a higher conductivity), the resistance of the test signal line can be reduced, and the accuracy of the contact resistance test can be improved.

[0200] In an exemplary embodiment, in Figure 14 and Figure 15 In the structure shown, a voltage U can be provided to the bonding test pads 32c, and the current signal I of the two bonding test pads 32c (these two bonding test pads 32c can be used as the first type of bonding test pads and multiplexed as the second type of bonding test pads) can be measured. The test result of this method is basically the same as the test result of providing a current signal I to the bonding test pads 32c and measuring the voltage U of the two bonding test pads 32c.

[0201] The embodiments of the present disclosure also provide a display device. As Figure 16 shown, the display device may include: a display substrate. The display substrate may be the display substrate provided in any of the foregoing embodiments.

[0202] In an exemplary embodiment, the display device may be a liquid crystal display (LCD), an organic light emitting diode (OLED), or a light emitting diode (LED) display device. The display device may be: a liquid crystal panel, an electronic paper, an OLED panel, an active-matrix organic light emitting diode (AMOLED) panel, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, or any other product or component with a display function.

[0203] The display substrate, display device, and contact resistance testing method provided by the embodiments of the present disclosure. The display substrate includes a display area and a first border area located on at least one side. The first border area includes at least one test group. The test group includes a plurality of driving test pads, a plurality of bonding test pads, and a plurality of test signal lines. In the same test group, the bonding test pads are located on the side away from the display area of the driving test pads. The plurality of bonding test pads correspond to the plurality of test signal lines one by one. One bonding test pad is electrically connected to one of the driving test pads through the corresponding test signal line. One driving test pad is electrically connected to at least one bonding test pad through at least one test signal line. The plurality of driving test pads are located adjacent to the plurality of bonding test pads, which can minimize the length of the test signal lines, reduce the resistance of the test signal lines, and improve the accuracy of testing the contact resistance of the driving test pads. The drawings of the embodiments of the present disclosure only relate to the structures involved in the embodiments of the present disclosure, and other structures can refer to the general design.

[0204] Without conflict, the features in the embodiments of the present disclosure can be combined with each other to obtain new embodiments.

[0205] Although the disclosed embodiments of the present disclosure are as above, the content described is only an embodiment adopted for the convenience of understanding the embodiments of the present disclosure, and is not used to limit the embodiments of the present disclosure. Any person skilled in the art within the scope of the embodiments of the present disclosure can make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed by the embodiments of the present disclosure. However, the scope of patent protection of the embodiments of the present disclosure shall still be subject to the scope defined by the appended claims.

Claims

1. A display substrate, characterized in that: include: A base substrate, the base substrate comprising a display area and a first frame area located on at least one side of the display area; At least one test group is located in the first frame area, and the same test group includes a plurality of drive test pads, a plurality of binding test pads and a plurality of test signal lines; Among them, in the same test group: the multiple binding test pads are located on a side of the multiple driving test pads away from the display area, the multiple binding test pads correspond one-to-one to the multiple test signal lines, one of the multiple binding test pads is electrically connected to one of the multiple driving test pads through the corresponding test signal line, the one driving test pad is electrically connected to at least one of the multiple binding test pads through at least one test signal line among the multiple test signal lines, at least two of the multiple driving test pads are electrically connected, and the multiple driving test pads are located adjacent to the multiple binding test pads.

2. The display substrate according to claim 1, characterized in that: Also includes: A plurality of driving pads are located in the first frame area, and in a first direction, a plurality of driving test pads in the at least one test group are located on at least one side of the plurality of driving pads; A plurality of binding pads are located in the first frame area, the plurality of binding pads are located on a side of the plurality of driving pads away from the display area, and in the first direction, a plurality of binding test pads in the at least one test group are located on at least one side of the plurality of binding pads; In the same test group, in the first direction, the plurality of driving test pads, the plurality of binding test pads, and the plurality of test signal lines are located on the same side of the plurality of driving pads and the plurality of binding pads.

3. The display substrate according to claim 2, characterized in that: Also includes: A plurality of sub-pixels are located on one side of the base substrate and in the display area; a plurality of data lines located in the display area and electrically connected to the plurality of sub-pixels, the plurality of data lines being configured to provide data signals to the plurality of sub-pixels; Among them, the multiple driving pads include multiple first driving pads and multiple second driving pads, the multiple second driving pads are located on a side of the multiple first driving pads away from the display area, and the multiple first driving pads are electrically connected to the multiple data lines; at least part of the multiple binding pads are electrically connected to the multiple second driving pads, and the conductivity of at least part of the structure of the multiple test signal lines in the at least one test group is consistent with the conductivity of the multiple data lines.

4. The display substrate according to claim 3, characterized in that: The at least one test group includes at least one first test group and at least one second test group; In the same first test group: comprising a plurality of first drive test pads, a plurality of first binding test pads, and a plurality of first test signal lines, the plurality of first binding test pads correspond to the plurality of first test signal lines one by one, a first binding test pad among the plurality of first binding test pads is electrically connected to a first drive test pad among the plurality of first drive test pads through a corresponding first test signal line, and the first drive test pad is electrically connected to at least one first binding test pad among the plurality of first binding test pads through at least one first test signal line among the plurality of first test signal lines; In the same second test group: comprising a plurality of second drive test pads, a plurality of second binding test pads, and a plurality of second test signal lines, the plurality of second binding test pads correspond to the plurality of second test signal lines one by one, one of the plurality of second binding test pads is electrically connected to one of the plurality of second drive test pads through the corresponding second test signal line, and the one second drive test pad is electrically connected to at least one second binding test pad of the plurality of second binding test pads through at least one second test signal line of the plurality of second test signal lines; The plurality of second driving test pads are located on a side of the plurality of first driving test pads away from the display area.

5. The display substrate according to claim 1, characterized in that: At least one of the plurality of test signal lines comprises a first structure portion, a second structure portion, and a third structure portion; In the same test signal line: one end of the second structure part is connected to the first structure part, and the other end is connected to the third structure part; the other end of the first structure part is electrically connected to one of the multiple drive test pads, and the other end of the third structure part is electrically connected to the corresponding binding test pad.

6. The display substrate according to claim 5, characterized in that: In a direction perpendicular to the plane where the base substrate is located, the first structure portion and the third structure portion are located on a side of the second structure portion close to the base substrate, or the first structure portion and the third structure portion are located on a side of the second structure portion away from the base substrate, or the first structure portion and the third structure portion are arranged on the same layer as the second structure portion.

7. The display substrate according to claim 5, characterized in that: The display area includes a plurality of sub-pixels and a plurality of data lines, the plurality of data lines are electrically connected to the plurality of sub-pixels, and the plurality of data lines are configured to provide data signals to the plurality of sub-pixels; at least one sub-pixel of the plurality of sub-pixels includes a pixel driving circuit, the pixel driving circuit includes a plurality of transistors and at least one capacitor; In a direction perpendicular to the plane where the substrate is located, the capacitor includes: a first electrode plate located on one side of the substrate, and a second electrode plate located on a side of the first electrode plate away from the substrate; the transistor includes: an active layer, a control electrode, a first electrode, and a second electrode, the active layer is located between the first electrode plate and the substrate, the control electrode is arranged in the same layer as the first electrode plate, the first electrode and the second electrode are located on a side of the second electrode plate away from the substrate, and the data line is located on a side of the first electrode and the second electrode away from the substrate; The second structure portion is provided in the same layer as at least one of the first electrode, the second electrode, and the data line.

8. The display substrate according to claim 7, characterized in that: The first structure portion and the third structure portion are arranged on the same layer as at least one of the control electrode and the second electrode plate, or the first structure portion and the third structure portion are arranged on the same layer as at least one of the first electrode, the second electrode and the data line.

9. The display substrate according to any one of claims 1 to 8, characterized in that: The same test group includes at least two driving test pads, at least two binding test pads, and at least two test signal lines, and the at least two driving test pads are electrically connected to the at least two binding test pads through the at least two test signal lines.

10. The display substrate according to claim 9, characterized in that: In the same test group: the number of the test signal lines and the number of the drive test pads are both integer multiples of 2, the number of the binding test pads is the same as the number of the test signal lines and is not less than the number of the drive test pads.

11. The display substrate according to claim 10, characterized in that: In the same test group, the number of the driving test pads, the binding test pads and the test signal lines are all two, the first ends of the two test signal lines are respectively electrically connected to the two binding test pads, and the second ends are respectively electrically connected to the two driving test pads.

12. The display substrate according to claim 10, characterized in that: In the same test group, the number of the driving test pads is two, the number of the binding test pads and the number of the test signal lines are both four, the first ends of the four test signal lines are electrically connected to the four binding test pads respectively, the second ends of two of the test signal lines are electrically connected to one of the driving test pads, and the second ends of the other two test signal lines are electrically connected to the other driving test pad.

13. The display substrate according to claim 10, characterized in that: In the same test group, the number of the driving test pads is two, the number of the binding test pads and the test signal lines are six each, the first ends of the six test signal lines are electrically connected to the six binding test pads respectively, the second ends of three of the test signal lines are electrically connected to one of the driving test pads, and the second ends of the other three test signal lines are electrically connected to another driving test pad.

14. The display substrate according to any one of claims 1 to 8, characterized in that: The at least one test group further includes a short-circuit wire. In the same test group, the number of the driving test pads is two, and the two driving test pads are electrically connected through the short-circuit wire.

15. A display device, characterized in that: Comprising the display substrate according to any one of claims 1 to 14.

16. A contact resistance testing method, characterized in that: Used to test the contact resistance of the driving test pad in the display substrate according to any one of claims 1 to 14, the display substrate comprises a display area and a first frame area located at least on one side of the display area, the first frame area comprises at least one test group, and the same test group comprises a plurality of driving test pads, a plurality of binding test pads and a plurality of test signal lines; in the same test group, the plurality of binding test pads are located on a side of the plurality of driving test pads away from the display area, the plurality of binding test pads correspond to the plurality of test signal lines one by one, one of the plurality of binding test pads is electrically connected to one of the plurality of driving test pads through a corresponding test signal line, the one driving test pad is electrically connected to at least one of the plurality of binding test pads through at least one test signal line among the plurality of test signal lines, at least two of the plurality of driving test pads are electrically connected, the plurality of driving test pads are located adjacent to the plurality of binding test pads, and the plurality of binding test pads comprise at least one first-type binding test pad and at least one second-type binding test pad; the method comprises: A first electrical signal is provided to the first type binding test pad, a second electrical signal of the second type binding test pad is tested, and a first contact resistance of the driving test pad is obtained according to the first electrical signal and the second electrical signal.

17. The contact resistance testing method according to claim 16, characterized in that: The at least one test group also includes a short-circuit wire; in the same test group: the number of the drive test pads is two, the two drive test pads are electrically connected through the short-circuit wire, the multiple binding test pads include two of the first-type binding test pads and two of the second-type binding test pads, the multiple test signal lines include two of the first-type test signal lines and two of the second-type test signal lines, the two first-type binding test pads are respectively electrically connected to the two drive test pads through the two first-type test signal lines, and the two second-type binding test pads are respectively electrically connected to the two drive test pads through the two second-type test signal lines.

18. The contact resistance testing method according to claim 17, characterized in that: Providing a first electrical signal to the first type of binding test pad and testing the second electrical signal of the second type of binding test pad includes: providing a first current signal to one of the first type of binding test pads, providing a ground signal to another first type of binding test pad, and testing the second voltage signals of two second type of binding test pads; the first electrical signal includes the first current signal and the ground signal, and the second electrical signal includes the second voltage signal.

19. The contact resistance testing method according to any one of claims 17 to 18, characterized in that: In the same test group, the plurality of binding test pads further include two third-type binding test pads, the plurality of test signal lines further include two third-type test signal lines, and the two third-type binding test pads are electrically connected to the two driving test pads respectively through the two third-type test signal lines; Before providing the first electrical signal to the first type binding test pad, or after obtaining the first contact resistance of the driving test pad according to the first electrical signal and the second electrical signal, it also includes: providing a third electrical signal to the third type binding test pad, testing the fourth electrical signal of the third type binding test pad, and obtaining the second contact resistance of the driving test pad according to the third electrical signal and the fourth electrical signal.

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