Coding and decoding device and method

Abstract

The invention provides a coding and decoding device and method, and relates to the technical field of wireless communication. The decoding device can perform decoding in an analog domain, the problems of high operation complexity and performance loss caused by high analog-to-digital conversion power consumption and quantization are avoided, and the storage space of a digital circuit can be saved. The decoding device comprises an analog circuit. The analog circuit is used for acquiring analog signals. The analog signal is determined by the decoding device according to a received coded sequence, the coded sequence is a sequence obtained by coding a sequence to be coded, the length of the sequence to be coded is N, N is equal to 2n, and n is a positive integer. The analog circuit is also used for decoding the analog signal to obtain a decoding result.

Description

Coding and decoding device and method Technical Field

[0001] The present application relates to the field of wireless communication technology, and in particular to a coding device and method. Background Art

[0002] Communication systems mostly transmit signals in the analog domain. After receiving the analog signal, the receiving device quantizes it through an analog-to-digital (AD) conversion module to produce a digital signal, which is then decoded by digital circuits. However, the AD conversion module consumes a lot of power, and the quantization process introduces the complexity of converting floating-point to fixed-point, which can also lead to performance losses and consume a lot of memory in the digital circuits.

[0003] Summary of the Invention

[0004] The present application provides a coding device and method, wherein the decoding device and method can perform decoding in the analog domain, thereby reducing power consumption and computational complexity, and saving storage space.

[0005] In a first aspect, a decoding device is provided, the decoding device comprising an analog circuit. The analog circuit is configured to obtain an analog signal. The analog signal is determined by the decoding device based on a received coded sequence, wherein the coded sequence is a sequence obtained by encoding a sequence to be coded, and the length of the sequence to be coded is N, where N=2. n , n is a positive integer. The analog circuit is also used to decode the analog signal to obtain a decoding result.

[0006] That is to say, after the decoding device obtains the analog signal, it decodes it in the analog domain. There is no problem of high power consumption of analog-to-digital conversion, high computational complexity and performance loss caused by quantization, and it can also save storage space of the digital circuit.

[0007] In one possible design, the sequence to be encoded includes a first information bit and a second information bit. The analog circuit includes a first f operation circuit, a first decoding circuit, a first delay control circuit, a first g operation circuit, and a second decoding circuit. The analog circuit is further configured to decode an analog signal to obtain a decoding result, including: a first f operation circuit configured to perform an f operation on the analog signal; a first decoding circuit configured to decode the result of the first f operation circuit to obtain an estimated value of the first information bit. The result decoded by the first decoding circuit corresponds to a code length of N / 2 and a code rate of A / (N / 2), where A represents the number of first information bits. The first delay control circuit is configured to control the time at which the analog signal is input to the first g operation circuit. The first g operation circuit performs a g operation on the analog signal and a first bit value. The first bit value is an estimated value of the first information bit. The second decoding circuit is configured to decode the result of the first g operation circuit to obtain an estimated value of the second information bit. The result decoded by the second decoding circuit corresponds to a code length of N / 2 and a code rate of B / (N / 2), where B represents the number of second information bits. The decoding result includes an estimated value of the first information bit and an estimated value of the second information bit.

[0008] That is to say, when the first N / 2 bits of the sequence to be encoded include A first information bits and the last N / 2 bits include B second information bits, the analog circuit adopts a nested manner, combining the first decoding circuit with a code length of N / 2 and a code rate of A / (N / 2) and the second decoding circuit with a code length of N / 2 and a code rate of B / (N / 2), and then combining the first f operation circuit, the first g operation circuit and the first delay control circuit to realize the decoding function with a code length of N and a code rate of (A+B) / N.

[0009] In one possible design, the first decoding circuit includes a ninth g operation circuit and a first sub-decoding circuit. The first decoding circuit is configured to decode the result of the first f operation circuit to obtain an estimated value of the first information bit, and includes a ninth g operation circuit configured to perform a g operation on the result of the first f operation circuit. The first sub-decoding circuit is configured to decode the result of the ninth g operation circuit to obtain an estimated value of the first information bit. The result decoded by the first sub-decoding circuit corresponds to a code length of N / 4 and a code rate of A / (N / 4).

[0010] That is to say, the first decoding circuit can also be nested, combining the first sub-decoding circuit for code length N / 4 and code rate A / (N / 4) with the ninth g operation circuit to realize the decoding function with code length N / 2 and code rate A / (N / 2).

[0011] In one possible design, the second decoding circuit includes a second sub-decoding circuit and a third sub-decoding circuit. The second decoding circuit is used to decode the result of the first g operation circuit to obtain an estimated value of the second information bit, including: a second sub-decoding circuit is used to decode the result of the first g operation circuit to obtain estimated values ​​of C first information bits. The code length corresponding to the result decoded by the second sub-decoding circuit is N / 4, and the code rate is C / (N / 4), where C is a positive integer. The third sub-decoding circuit is used to decode the result of the first g operation circuit and the result of the second sub-decoding circuit to obtain estimated values ​​of D first information bits. The code length corresponding to the result decoded by the third sub-decoding circuit is N / 4, and the code rate is D / (N / 4), where D is a positive integer. C+D=B.

[0012] That is to say, the second decoding circuit can also be nested, using a second sub-decoding circuit for a code length of N / 4 and a code rate of C / (N / 4) and a third sub-decoding circuit for a code length of N / 4 and a code rate of D / (N / 4) to implement a decoding function with a code length of N / 2 and a code rate of B / (N / 2).

[0013] In one possible design, a first f-operation circuit includes a first real-to-absolute-value sign RTAS converter, a minimum WTA module, a first multiplier, and a second multiplier. The first f-operation circuit, configured to perform an f-operation on an analog signal, includes: a first RTAS converter configured to receive and process a first signal to obtain the sign and absolute value corresponding to each log-likelihood ratio (LLR) value in the first signal. The first signal includes two LLR values ​​in the analog signal. A WTA module configured to determine the minimum of the absolute values ​​obtained by the first RTAS converter. A first multiplier configured to multiply the signs obtained by the first RTAS converter. A second multiplier configured to multiply the result of the WTA module by the result of the first multiplier. The number of first f-operation circuits is N / 2, and the result of the first f-operation circuit includes the results of N / 2 second multipliers.

[0014] That is, the first f operation circuit implements the f operation function through the first RTAS converter, the WTA module, the first multiplier and the second multiplier.

[0015] In one possible design, the sequence to be encoded includes a second information bit. The analog circuit includes a first g operation circuit and a second decoding circuit. The analog circuit is further configured to decode the analog signal to obtain a decoding result, including: a first g operation circuit configured to perform a g operation on the analog signal and a first bit value. The first bit value is determined based on the first N / 2 LLR values ​​in the analog signal. A second decoding circuit is configured to decode the result of the first g operation circuit to obtain an estimated value of the second information bit. The decoding result of the second decoding circuit corresponds to a code length of N / 2 and a code rate of B / (N / 2), where B represents the number of second information bits. The decoding result includes the estimated value of the second information bit.

[0016] That is to say, when the last N / 2 bits of the sequence to be encoded include B second information bits, the analog circuit adopts a nested manner, combining the second decoding circuit with a code length of N / 2 and a code rate of B / (N / 2) with the first g operation circuit to realize the decoding function with a code length of N and a code rate of B / N.

[0017] In one possible design, a first g operation circuit includes a third multiplier and a first adder. The first g operation circuit, configured to perform a g operation on an analog signal and a first bit value, includes: a third multiplier configured to multiply the first bit value by an LLR value in the first signal. The first signal includes two LLR values ​​in the analog signal. A first adder configured to add the result of the third multiplier to another LLR value in the first signal. The number of first g operation circuits is N / 2, and the result of the first g operation circuit includes the results of N / 2 first adders.

[0018] That is to say, the first g operation circuit implements the g operation function through the third multiplier and the first adder.

[0019] In one possible design, a first g operation circuit includes a second RTAS converter, a fourth multiplier, a fifth multiplier, a second delay control circuit, and a second adder. The first g operation circuit, configured to perform a g operation on an analog signal and a first bit value, includes: a second RTAS converter configured to receive and process an LLR value in the first signal to obtain a first sign and a first absolute value. The first signal includes two LLR values ​​in the analog signal. The fourth multiplier is configured to multiply the first bit value by the first sign. The fifth multiplier is configured to multiply the result of the fourth multiplier by the first absolute value. The second delay control circuit is configured to control the timing at which another LLR value in the first signal is input to the second adder. The second adder is configured to add the result of the fifth multiplier to the LLR value input from the second delay control circuit. The number of first g operation circuits is N / 2, and the result of the first g operation circuit includes the results of N / 2 second adders.

[0020] That is, the first g operation circuit implements the g operation function through the second RTAS converter, the fourth multiplier, the fifth multiplier, the second delay control circuit and the second adder.

[0021] In one possible design, the sequence to be encoded also includes frozen bits. The first decoding circuit includes a first operation circuit and a sign conversion circuit. The first decoding circuit is configured to decode the result of the first f operation circuit to obtain an estimated value of the first information bit. The first decoding circuit includes: a first operation circuit configured to receive the result of the first f operation circuit and perform a g operation on the value of the frozen bits and the result of the first f operation circuit; and a sign conversion circuit configured to perform sign processing on the result of the first operation circuit to obtain an estimated value of the first information bit.

[0022] That is, in the first decoding circuit, the first operation circuit first performs the g operation, and then the sign conversion circuit extracts the sign to obtain the estimated value of the first information bit.

[0023] In one possible design, the sequence to be encoded also includes frozen bits. The first decoding circuit includes a first operation circuit and a path metric circuit. The first decoding circuit is configured to decode the result of the first f operation circuit to obtain an estimated value of the first information bit, and includes: a first operation circuit configured to receive the result of the first f operation circuit and perform a g operation on the value of the frozen bits and the result of the first f operation circuit. The path metric circuit is configured to determine the estimated value of the first information bit based on the first path metric value and the result of the first operation circuit. The first path metric value is a metric value of a first decoding path, and the first decoding path indicates the value of a bit preceding the first information bit.

[0024] That is, in the first decoding circuit, the first operation circuit first performs the g operation, and then the path metric circuit determines the estimated value of the first information bit according to the path metric value.

[0025] In one possible design, candidate values ​​for the first information bit include a first candidate value and a second candidate value. The path metric circuit includes a first processing module, a second processing module, and a comparator. The path metric circuit is configured to determine an estimated value of the first information bit based on the first path metric value and a result of a first operation circuit, and includes: a first processing module configured to receive the first path metric value and the result of the first operation circuit, and determine a second path metric value based on the first candidate value, the first path metric value, and the result of the first operation circuit; a second processing module configured to receive the first path metric value and the result of the first operation circuit, and determine a third path metric value based on the second candidate value, the first path metric value, and the result of the first operation circuit; and a comparator configured to compare the second path metric value with the third path metric value and output an estimated value of the first information bit. The estimated value of the first information bit is the candidate value corresponding to the larger path metric value between the second path metric value and the third path metric value.

[0026] That is, in the path metric circuit, the first processing module first determines the second path metric value, the second processing module determines the third path metric value, and then the comparator determines the larger path metric value to output the candidate value corresponding to the larger path metric value.

[0027] In one possible design, the first processing module includes a third RTAS converter, a sixth multiplier, a first calculation unit, a seventh multiplier, and a third adder. The first processing module is configured to receive the first path metric value and the result of the first operation circuit, and determine the second path metric value based on the first candidate value, the first path metric value, and the result of the first operation circuit. The first processing module includes: a third RTAS converter, configured to receive and process the result of the first operation circuit to output a second sign and a second absolute value; a sixth multiplier, configured to multiply the first candidate value and the second sign; a first calculation unit, configured to receive and process the result of the sixth multiplier; a seventh multiplier, configured to multiply the result of the first calculation unit by the second absolute value; and a third adder, configured to sum the first path metric value and the result of the seventh multiplier to obtain the second path metric value.

[0028] That is, the first processing module implements the calculation function of the second path metric value through the third RTAS converter, the sixth multiplier, the first calculation unit, the seventh multiplier and the third adder.

[0029] In one possible design, the second processing module includes a fourth RTAS converter, an eighth multiplier, a second computation unit, a ninth multiplier, and a fourth adder. The second processing module is configured to receive the first path metric value and the result of the first operation circuit, and determine a third path metric value based on the second candidate value, the first path metric value, and the result of the first operation circuit. The second processing module includes: a fourth RTAS converter configured to receive and process the result of the first operation circuit to output a third sign and a third absolute value; an eighth multiplier configured to multiply the second candidate value by the third sign; a second computation unit configured to receive and process the result of the eighth multiplier; a ninth multiplier configured to multiply the result of the second computation unit by the third absolute value; and a fourth adder configured to sum the first path metric value and the result of the ninth multiplier to obtain a third path metric value.

[0030] That is, the second processing module implements the calculation function of the third path metric value through the fourth RTAS converter, the eighth multiplier, the second calculation unit, the ninth multiplier and the fourth adder.

[0031] In one possible design, the frozen bits include a first frozen bit, a second frozen bit, and a third frozen bit. The result of the first f operation circuit includes a first partial result and a second partial result, wherein the first partial result includes the results of the first N / 4 first f operation circuits, and the second partial result includes the results of the last N / 4 first f operation circuits. The first operation circuit includes a second g operation circuit, a third g operation circuit, and a fourth g operation circuit. The first operation circuit is configured to receive the result of the first f operation circuit and perform a g operation on the value of the frozen bit and the result of the first f operation circuit, including: a second g operation circuit configured to perform a g operation on the value of the first frozen bit and the first partial result; a third g operation circuit configured to perform a g operation on the value of the second frozen bit and the second partial result; and a fourth g operation circuit configured to perform a g operation on the value of the third frozen bit, the result of the first g operation circuit, and the result of the second g operation circuit to obtain the result of the first operation circuit.

[0032] That is, the first operation circuit realizes the function of processing the value of the frozen bit and the result of the first f operation circuit through three g operation circuits (ie, the second g operation circuit, the third g operation circuit, and the fourth g operation circuit).

[0033] In one possible design, the second decoding circuit includes B subcircuits, each of the B subcircuits including an operation unit and a sign conversion circuit. The second decoding circuit, configured to decode the result of the first g operation circuit to obtain an estimated value of the second information bit, includes: an operation unit of the i-th subcircuit, configured to determine a probability distribution of the i-th second information bit among the B second information bits. i is any positive integer less than or equal to B. The i-th subcircuit is the i-th subcircuit among the B subcircuits. The sign conversion circuit of the i-th subcircuit, configured to perform a sign operation on the probability distribution of the i-th second information bit to obtain an estimated value of the i-th second information bit.

[0034] That is, in the B sub-circuits of the second decoding circuit, each sub-circuit calculates an estimated value of a second information bit through an operation unit and a symbol conversion circuit.

[0035] In one possible design, B=3. The bit preceding the first second information bit is a first frozen bit. The second decoding circuit, configured to decode the result of the first g operation circuit to obtain an estimated value of the second information bit, includes: a first operation unit, configured to receive and process the value of the first frozen bit and the result of the first g operation circuit to obtain a probability distribution of the first second information bit. The first operation unit is a operation unit of the first sub-circuit. A first conversion circuit, configured to perform a sign operation on the probability distribution of the first first information bit to obtain an estimated value of the first first information bit. The first conversion circuit is a sign conversion circuit of the first sub-circuit. A second operation unit, configured to receive and process the estimated value of the first second information bit and the result of the first g operation circuit to obtain a probability distribution of the second second information bit. The second operation unit is a operation unit of the second sub-circuit. A second conversion circuit, configured to perform a sign operation on the probability distribution of the second second information bit to obtain an estimated value of the second second information bit. The second conversion circuit is a sign conversion circuit of the second sub-circuit. The third operation unit is configured to receive and process the estimated values ​​of the first and second second information bits and the result of the first g operation circuit to obtain a probability distribution of the third second information bit. The third operation unit is the operation unit of the third sub-circuit. The third conversion circuit is configured to perform a sign operation on the probability distribution of the third second information bit to obtain an estimated value of the third second information bit. The third conversion circuit is the sign conversion circuit of the third sub-circuit.

[0036] That is, in the second decoding circuit, each operation unit and conversion circuit are combined (such as the first operation unit and the first conversion circuit are combined, or the second operation unit and the second conversion circuit are combined, or the third operation unit and the third conversion circuit are combined) to calculate an estimated value of a second information bit.

[0037] In one possible design, the second decoding circuit includes B subcircuits, each of the B subcircuits including an operation unit and a path metric circuit. The second decoding circuit, used to decode the result of the first g operation circuit to obtain an estimated value of the second information bit, includes: an operation unit of the i-th subcircuit, used to determine the probability distribution of the i-th second information bit among the B second information bits. i is any positive integer less than or equal to B. The i-th subcircuit is the i-th subcircuit among the B subcircuits. The path metric circuit of the i-th subcircuit is used to receive the path metric value of the i-th decoding path, and determine the estimated value of the i-th second information bit based on the path metric value of the i-th decoding path and the probability distribution of the i-th second information bit. The i-th decoding path indicates the value of the bit before the i-th second information bit in the encoded sequence.

[0038] That is, in the B sub-circuits of the second decoding circuit, each sub-circuit calculates an estimated value of a second information bit through an operation unit and a path metric circuit.

[0039] In one possible design, B = 3. The bit preceding the first second information bit is a first frozen bit. The second decoding circuit, configured to decode the result of the first g operation circuit to obtain an estimated value of the second information bit, includes: a first operation unit, configured to receive and process the value of the first frozen bit and the result of the first g operation circuit to obtain a probability distribution of the first second information bit. The first operation unit is a operation unit of the first sub-circuit. A first path metric circuit is configured to receive a path metric value of the first decoding path and determine an estimated value of the first second information bit based on the path metric value of the first decoding path and the probability distribution of the first second information bit. The first decoding path indicates the value of the bit preceding the first second information bit. The first path metric circuit is a path metric circuit of the first sub-circuit. A second operation unit is configured to receive and process the estimated value of the first second information bit and the result of the first g operation circuit to obtain a probability distribution of the second second information bit. The second operation unit is a operation unit of the second sub-circuit. The second path metric circuit is configured to receive the path metric value of the second decoding path and determine an estimated value of the second second information bit based on the path metric value of the second decoding path and the probability distribution of the second second information bit. The second decoding path indicates the value of the bit preceding the second second information bit. The second path metric circuit is the path metric circuit of the second sub-circuit. The third operation unit is configured to receive and process the estimated values ​​of the first and second second information bits and the result of the first g operation circuit to obtain the probability distribution of the third second information bit. The third operation unit is the operation unit of the third sub-circuit. The third path metric circuit is configured to receive the path metric value of the third decoding path and determine an estimated value of the third second information bit based on the path metric value of the third decoding path and the probability distribution of the third second information bit. The third decoding path indicates the value of the bit preceding the third second information bit. The third path metric circuit is the path metric circuit of the third sub-circuit.

[0040] That is to say, in the second decoding circuit, each operation unit is combined with a path measurement circuit (such as the first operation unit is combined with a first path measurement circuit, or the second operation unit is combined with a second path measurement circuit, or the third operation unit is combined with a third path measurement circuit) to calculate an estimated value of a second information bit.

[0041] In one possible design, the first operation unit includes a second f operation circuit, a third f operation circuit, and a fifth g operation circuit. The first operation unit, configured to receive and process the value of the first frozen bit and the result of the first g operation circuit, includes: a second f operation circuit configured to receive a second signal and perform an f operation on the second signal. The second signal is a portion of the result of the first g operation circuit. A third f operation circuit configured to receive a third signal and perform an f operation on the second signal. The third signal is a signal in the result of the first g operation circuit other than the second signal. The fifth g operation circuit is further configured to perform a g operation on the value of the first frozen bit, the result of the first f operation circuit, and the result of the second f operation circuit to obtain a processing result of the first operation unit.

[0042] That is to say, the first operation unit implements the processing function of the first operation unit through the second f operation circuit, the third f operation circuit and the fifth g operation circuit.

[0043] In one possible design, the second operation unit includes a sixth g operation circuit, a seventh g operation circuit, and a fourth f operation circuit. The second operation unit, configured to receive and process the estimated value of the first second information bit and the result of the first g operation circuit, includes: a sixth g operation circuit configured to perform a g operation on the estimated value of the first information bit and a second signal. The second signal is a portion of the result of the first g operation circuit. A seventh g operation circuit configured to perform a g operation on the estimated value of the first information bit and a third signal. The third signal is the signal in the result of the first g operation circuit other than the second signal. A fourth f operation circuit configured to perform an f operation on the results of the sixth g operation circuit and the seventh g operation circuit to obtain a processing result of the second operation unit.

[0044] That is to say, the second operation unit implements the processing function of the second operation unit through the sixth g operation circuit, the seventh g operation circuit and the fourth f operation circuit.

[0045] In one possible design, the third operation unit includes a sixth g operation circuit, a seventh g operation circuit, and an eighth g operation circuit. The third operation unit is configured to receive and process the estimated values ​​of both the first and second second information bits and the result of the first g operation circuit, and includes: a sixth g operation circuit configured to perform a g operation on the estimated value of the first first information bit and a second signal. The second signal is a portion of the result of the first g operation circuit. A seventh g operation circuit configured to perform a g operation on the estimated value of the first information bit and a third signal. The third signal is the signal in the result of the first g operation circuit excluding the second signal. An eighth g operation circuit configured to perform a g operation on the estimated value of the second second information bit, the result of the sixth g operation circuit, and the result of the seventh g operation circuit to obtain the processing result of the third operation unit.

[0046] That is to say, the third operation unit implements the processing function of the third operation unit through the sixth g operation circuit, the seventh g operation circuit and the eighth g operation circuit.

[0047] In one possible design, the coded sequence includes a first information bit. The analog circuit includes a first operation circuit and a sign conversion circuit. The analog circuit is further configured to decode the analog signal to obtain a decoding result, and includes: a first operation circuit configured to perform a g operation on the analog signal; and a sign conversion circuit configured to perform sign processing on the result of the first operation circuit to obtain an estimated value of the first information bit.

[0048] That is, in the analog circuit, the first operation circuit first performs the g operation, and then the sign conversion circuit extracts the sign to obtain the estimated value of the first information bit.

[0049] In one possible design, the coded sequence includes a first information bit. The analog circuit includes a first operation circuit and a path metric circuit. The analog circuit is further configured to decode the analog signal to obtain a decoding result, and includes: a first operation circuit configured to perform a g operation on the analog signal; and a path metric circuit configured to determine an estimated value of the first information bit based on the first path metric value and the result of the first operation circuit. The first path metric value is a metric value of a first decoding path, which indicates the value of a bit preceding the first information bit.

[0050] That is, in the analog circuit, the first operation circuit first performs the g operation, and then the path metric circuit determines the estimated value of the first information bit according to the path metric value.

[0051] In one possible design, the frozen bits include a first frozen bit, a second frozen bit, and a third frozen bit. The first operation circuit includes a second g operation circuit, a third g operation circuit, and a fourth g operation circuit. The first operation circuit, configured to perform a g operation on an analog signal, includes: a second g operation circuit configured to perform a g operation on the value of the first frozen bit and the first N / 2 LLR values ​​in the analog signal; a third g operation circuit configured to perform a g operation on the value of the second frozen bit and the last N / 2 LLR values ​​in the analog signal; and a fourth g operation circuit configured to perform a g operation on the value of the third frozen bit, a result of the first g operation circuit, and a result of the second g operation circuit to obtain a result of the first operation circuit. The analog signal includes N LLR values.

[0052] That is, the first operation circuit realizes the function of processing the frozen bit value and the analog signal through three g operation circuits (ie, the second g operation circuit, the third g operation circuit, and the fourth g operation circuit).

[0053] In one possible design, the coding sequence includes B second information bits. The analog circuit includes B subcircuits, each of which includes an operation unit and a sign conversion circuit. The analog circuit is further configured to decode the analog signal to obtain a decoding result, including: an operation unit of the i-th subcircuit, configured to determine the probability distribution of the i-th second information bit among the B second information bits. i is any positive integer less than or equal to B. The i-th subcircuit is the i-th subcircuit among the B subcircuits. The sign conversion circuit of the i-th subcircuit is configured to perform a sign operation on the probability distribution of the i-th second information bit to obtain an estimated value of the i-th second information bit.

[0054] That is, in the B sub-circuits of the analog circuit, each sub-circuit calculates an estimated value of a second information bit through an operation unit and a symbol conversion circuit.

[0055] In one possible design, B=3. The bit preceding the first second information bit is a first frozen bit. The analog circuit is further configured to decode the analog signal to obtain a decoding result, and includes: a first operation unit configured to receive and process the value of the first frozen bit and the analog signal to obtain a probability distribution of the first second information bit. The first operation unit is a operation unit of the first sub-circuit. A first conversion circuit is configured to perform a sign operation on the probability distribution of the first first information bit to obtain an estimated value of the first first information bit. The first conversion circuit is a sign conversion circuit of the first sub-circuit. A second operation unit is configured to receive and process the estimated value of the first second information bit and the analog signal to obtain a probability distribution of the second second information bit. The second operation unit is a operation unit of the second sub-circuit. A second conversion circuit is configured to perform a sign operation on the probability distribution of the second second information bit to obtain an estimated value of the second second information bit. The second conversion circuit is a sign conversion circuit of the second sub-circuit. The third operation unit is configured to receive and process the estimated values ​​of the first and second second information bits and the result of the first g operation circuit to obtain a probability distribution of the third second information bit. The third operation unit is the operation unit of the third sub-circuit. The third conversion circuit is configured to perform a sign operation on the probability distribution of the third second information bit to obtain an estimated value of the third second information bit. The third conversion circuit is the sign conversion circuit of the third sub-circuit.

[0056] That is, in the analog circuit, each operation unit and conversion circuit are combined (such as the first operation unit and the first conversion circuit are combined, or the second operation unit and the second conversion circuit are combined, or the third operation unit and the third conversion circuit are combined) to calculate an estimated value of a second information bit.

[0057] In one possible design, the analog circuit includes B subcircuits, each of the B subcircuits including an operation unit and a path metric circuit. The analog circuit is further configured to decode an analog signal to obtain a decoding result, including: an operation unit of the i-th subcircuit, configured to determine the probability distribution of the i-th second information bit among the B second information bits. i is any positive integer less than or equal to B. The i-th subcircuit is the i-th subcircuit among the B subcircuits. The path metric circuit of the i-th subcircuit is configured to receive a path metric value of the i-th decoding path, and determine an estimated value of the i-th second information bit based on the path metric value of the i-th decoding path and the probability distribution of the i-th second information bit. The i-th decoding path indicates the value of the bit preceding the i-th second information bit in the encoded sequence.

[0058] That is, in the B sub-circuits of the analog circuit, each sub-circuit calculates an estimated value of a second information bit through an operation unit and a path metric circuit.

[0059] In one possible design, B = 3. The bit preceding the first second information bit is a first frozen bit. The analog circuit is further configured to decode the analog signal to obtain a decoding result, and includes a first operation unit configured to receive and process the value of the first frozen bit and the analog signal to obtain a probability distribution of the first second information bit. The first operation unit is a operation unit of the first sub-circuit. A first path metric circuit is configured to receive a path metric value of the first decoding path and determine an estimated value of the first second information bit based on the path metric value of the first decoding path and the probability distribution of the first second information bit. The first decoding path indicates the value of the bit preceding the first second information bit. The first path metric circuit is a path metric circuit of the first sub-circuit. A second operation unit is configured to receive and process the estimated value of the first second information bit and the analog signal to obtain a probability distribution of the second second information bit. The second operation unit is a operation unit of the second sub-circuit. The second path metric circuit is configured to receive the path metric value of the second decoding path and determine an estimated value of the second second information bit based on the path metric value of the second decoding path and the probability distribution of the second second information bit. The second decoding path indicates the value of the bit preceding the second second information bit. The second path metric circuit is the path metric circuit of the second sub-circuit. The third operation unit is configured to receive and process the estimated values ​​and analog signals of both the first and second second information bits to obtain the probability distribution of the third second information bit. The third operation unit is the operation unit of the third sub-circuit. The third path metric circuit is configured to receive the path metric value of the third decoding path and determine an estimated value of the third second information bit based on the path metric value of the third decoding path and the probability distribution of the third second information bit. The third decoding path indicates the value of the bit preceding the third second information bit. The third path metric circuit is the path metric circuit of the third sub-circuit.

[0060] That is to say, in the analog circuit, each operation unit is combined with a path measurement circuit (such as the first operation unit is combined with a first path measurement circuit, or the second operation unit is combined with a second path measurement circuit, or the third operation unit is combined with a third path measurement circuit) to calculate an estimated value of a second information bit.

[0061] In one possible design, the first operation unit includes a second f operation circuit, a third f operation circuit, and a fifth g operation circuit. The first operation unit is configured to receive and process the value of the first frozen bit and the analog signal, and includes: a second f operation circuit configured to receive the second signal and perform an f operation on the second signal. The second signal is a portion of the analog signal. A third f operation circuit is configured to receive the third signal and perform an f operation on the second signal. The third signal is a signal in the analog signal other than the second signal. The fifth g operation circuit is further configured to perform a g operation on the value of the first frozen bit, the result of the first f operation circuit, and the result of the second f operation circuit to obtain a processing result of the first operation unit.

[0062] That is to say, the first operation unit implements the processing function of the first operation unit through the second f operation circuit, the third f operation circuit and the fifth g operation circuit.

[0063] In one possible design, the second operation unit includes a sixth g operation circuit, a seventh g operation circuit, and a fourth f operation circuit. The second operation unit, configured to receive and process an estimated value of the first second information bit and an analog signal, includes: a sixth g operation circuit configured to perform a g operation on the estimated value of the first information bit and the second signal. The second signal is a portion of the analog signal. A seventh g operation circuit configured to perform a g operation on the estimated value of the first information bit and a third signal. The third signal is a signal in the analog signal other than the second signal. A fourth f operation circuit configured to perform an f operation on the result of the sixth g operation circuit and the result of the seventh g operation circuit to obtain a processing result of the second operation unit.

[0064] That is to say, the second operation unit implements the processing function of the second operation unit through the sixth g operation circuit, the seventh g operation circuit and the fourth f operation circuit.

[0065] In one possible design, the third operation unit includes a sixth g operation circuit, a seventh g operation circuit, and an eighth g operation circuit. The third operation unit is configured to receive and process the estimated values ​​of both the first second information bit and the second second information bit and the analog signal, and includes: a sixth g operation circuit configured to perform a g operation on the estimated value of the first first information bit and the second signal. The second signal is a portion of the analog signal. A seventh g operation circuit configured to perform a g operation on the estimated value of the first information bit and the third signal. The third signal is a signal in the analog signal other than the second signal. An eighth g operation circuit configured to perform a g operation on the estimated value of the second second information bit, the result of the sixth g operation circuit, and the result of the seventh g operation circuit to obtain a processing result of the third operation unit.

[0066] That is to say, the third operation unit implements the processing function of the third operation unit through the sixth g operation circuit, the seventh g operation circuit and the eighth g operation circuit.

[0067] In a second aspect, a decoding method is provided, which is applied to a decoding device, wherein the decoding device includes an analog circuit. The method includes: the analog circuit obtains an analog signal. The analog signal is determined by the decoding device based on a received coded sequence, wherein the coded sequence is a sequence obtained by encoding a sequence to be coded, and the length of the sequence to be coded is N, where N=2. n , n is a positive integer. The analog circuit decodes the analog signal to obtain a decoding result.

[0068] In one possible design, a sequence to be encoded includes a first information bit and a second information bit. An analog circuit includes a first f operation circuit, a first decoding circuit, a first delay control circuit, a first g operation circuit, and a second decoding circuit. The analog circuit decodes an analog signal to obtain a decoding result, including: the first f operation circuit performs an f operation on the analog signal. The first decoding circuit decodes the result of the first f operation circuit to obtain an estimated value of the first information bit. The decoding result of the first decoding circuit corresponds to a code length of N / 2 and a code rate of A / (N / 2), where A represents the number of first information bits. The first delay control circuit controls the timing of input of the analog signal into the first g operation circuit. The first g operation circuit performs a g operation on the analog signal and a first bit value. The first bit value is an estimated value of the first information bit. The second decoding circuit decodes the result of the first g operation circuit to obtain an estimated value of the second information bit. The decoding result of the second decoding circuit corresponds to a code length of N / 2 and a code rate of B / (N / 2), where B represents the number of second information bits. The decoding result includes the estimated value of the first information bit and the estimated value of the second information bit.

[0069] In one possible design, the first f-operation circuit includes a first real-to-absolute-value sign RTAS converter, a minimum WTA module, a first multiplier, and a second multiplier. The first f-operation circuit performs an f-operation on an analog signal, including: the first RTAS converter receives and processes the first signal to obtain the sign and absolute value corresponding to each log-likelihood ratio (LLR) value in the first signal. The first signal includes two LLR values ​​in the analog signal. The WTA module determines the minimum of the absolute values ​​obtained by the first RTAS converter. The first multiplier multiplies the signs obtained by the first RTAS converter. The second multiplier multiplies the result of the WTA module by the result of the first multiplier. The number of first f-operation circuits is N / 2, and the result of the first f-operation circuit includes the results of N / 2 second multipliers.

[0070] In one possible design, the sequence to be encoded includes a second information bit. The analog circuit includes a first g operation circuit and a second decoding circuit. The analog circuit decodes the analog signal to obtain a decoding result, including: the first g operation circuit performs a g operation on the analog signal and a first bit value. The first bit value is determined based on the first N / 2 LLR values ​​in the analog signal. The second decoding circuit decodes the result of the first g operation circuit to obtain an estimated value of the second information bit. The decoding result of the second decoding circuit corresponds to a code length of N / 2 and a code rate of B / (N / 2), where B represents the number of second information bits. The decoding result includes the estimated value of the second information bit.

[0071] In one possible design, a first g operation circuit includes a third multiplier and a first adder. The first g operation circuit performs a g operation on an analog signal and a first bit value, including: the third multiplier multiplies the first bit value by an LLR value in the first signal. The first signal includes two LLR values ​​in the analog signal. The first adder adds the result of the third multiplier to another LLR value in the first signal. The number of first g operation circuits is N / 2, and the result of the first g operation circuit includes the results of N / 2 first adders.

[0072] In one possible design, a first g operation circuit includes a second RTAS converter, a fourth multiplier, a fifth multiplier, a second delay control circuit, and a second adder. The first g operation circuit performs a g operation on an analog signal and a first bit value, including: the second RTAS converter receives and processes an LLR value in the first signal to obtain a first sign and a first absolute value. The first signal includes two LLR values ​​in the analog signal. The fourth multiplier multiplies the first bit value by the first sign. The fifth multiplier multiplies the result of the fourth multiplier by the first absolute value. The second delay control circuit controls the timing of inputting another LLR value in the first signal into the second adder. The second adder adds the result of the fifth multiplier and the LLR value input from the second delay control circuit. The number of first g operation circuits is N / 2, and the result of the first g operation circuit includes the results of N / 2 second adders.

[0073] In one possible design, the sequence to be encoded also includes frozen bits. The first decoding circuit includes a first operation circuit and a sign conversion circuit. The first decoding circuit decodes the result of the first f operation circuit to obtain an estimated value of the first information bit, including: the first operation circuit receives the result of the first f operation circuit and performs a g operation on the value of the frozen bits and the result of the first f operation circuit. The sign conversion circuit performs sign processing on the result of the first operation circuit to obtain an estimated value of the first information bit.

[0074] In one possible design, the sequence to be encoded also includes frozen bits. The first decoding circuit includes a first operation circuit and a path metric circuit. The first decoding circuit decodes the result of the first f operation circuit to obtain an estimated value of the first information bit, including: the first operation circuit receives the result of the first f operation circuit and performs a g operation on the value of the frozen bits and the result of the first f operation circuit. The path metric circuit determines the estimated value of the first information bit based on the first path metric value and the result of the first operation circuit. The first path metric value is a metric value of the first decoding path, and the first decoding path indicates the value of the bit preceding the first information bit.

[0075] In one possible design, candidate values ​​for the first information bit include a first candidate value and a second candidate value. The path metric circuit includes a first processing module, a second processing module, and a comparator. The path metric circuit determines an estimated value of the first information bit based on the first path metric value and the result of the first operation circuit, including: the first processing module receives the first path metric value and the result of the first operation circuit, and determines a second path metric value based on the first candidate value, the first path metric value, and the result of the first operation circuit. The second processing module receives the first path metric value and the result of the first operation circuit, and determines a third path metric value based on the second candidate value, the first path metric value, and the result of the first operation circuit. The comparator compares the second path metric value with the third path metric value and outputs an estimated value of the first information bit. The estimated value of the first information bit is the candidate value corresponding to the larger path metric value between the second path metric value and the third path metric value.

[0076] In one possible design, the first processing module includes a third RTAS converter, a sixth multiplier, a first calculation unit, a seventh multiplier, and a third adder. The first processing module receives the first path metric value and the result of the first operation circuit, and determines the second path metric value based on the first candidate value, the first path metric value, and the result of the first operation circuit. The first processing module includes: the third RTAS converter receives and processes the result of the first operation circuit to output a second sign and a second absolute value; the sixth multiplier multiplies the first candidate value and the second sign; the first calculation unit receives and processes the result of the sixth multiplier; the seventh multiplier multiplies the result of the first calculation unit by the second absolute value; and the third adder sums the first path metric value and the result of the seventh multiplier to obtain the second path metric value.

[0077] In one possible design, the second processing module includes a fourth RTAS converter, an eighth multiplier, a second calculation unit, a ninth multiplier, and a fourth adder. The second processing module receives the first path metric value and the result of the first operation circuit, and determines a third path metric value based on the second candidate value, the first path metric value, and the result of the first operation circuit. The second processing module includes: the fourth RTAS converter receives and processes the result of the first operation circuit to output a third sign and a third absolute value; the eighth multiplier multiplies the second candidate value by the third sign; the second calculation unit receives and processes the result of the eighth multiplier; the ninth multiplier multiplies the result of the second calculation unit by the third absolute value; and the fourth adder sums the first path metric value and the result of the ninth multiplier to obtain the third path metric value.

[0078] In one possible design, the frozen bits include a first frozen bit, a second frozen bit, and a third frozen bit. The result of the first f operation circuit includes a first partial result and a second partial result, the first partial result including the results of the first N / 4 first f operation circuits, and the second partial result including the results of the last N / 4 first f operation circuits. The first operation circuit includes a second g operation circuit, a third g operation circuit, and a fourth g operation circuit. The first operation circuit receives the result of the first f operation circuit and performs a g operation on the value of the frozen bit and the result of the first f operation circuit, including: the second g operation circuit performs a g operation on the value of the first frozen bit and the first partial result; the third g operation circuit performs a g operation on the value of the second frozen bit and the second partial result; and the fourth g operation circuit performs a g operation on the value of the third frozen bit, the result of the first g operation circuit, and the result of the second g operation circuit to obtain the result of the first operation circuit.

[0079] In one possible design, the second decoding circuit includes B subcircuits, each of the B subcircuits including an operation unit and a sign conversion circuit. The second decoding circuit decodes the result of the first g operation circuit to obtain an estimated value of the second information bit, including: the operation unit of the i-th subcircuit determines the probability distribution of the i-th second information bit among the B second information bits. i is any positive integer less than or equal to B. The i-th subcircuit is the i-th subcircuit among the B subcircuits. The sign conversion circuit of the i-th subcircuit performs a sign operation on the probability distribution of the i-th second information bit to obtain an estimated value of the i-th second information bit.

[0080] In one possible design, B=3. The bit preceding the first second information bit is a first frozen bit. The second decoding circuit decodes the result of the first g operation circuit to obtain an estimated value of the second information bit, including: a first operation unit receiving and processing the value of the first frozen bit and the result of the first g operation circuit to obtain a probability distribution of the first second information bit. The first operation unit is the operation unit of the first sub-circuit. The first conversion circuit performs a sign operation on the probability distribution of the first first information bit to obtain an estimated value of the first first information bit. The first conversion circuit is the sign conversion circuit of the first sub-circuit. The second operation unit receives and processes the estimated value of the first second information bit and the result of the first g operation circuit to obtain a probability distribution of the second second information bit. The second operation unit is the operation unit of the second sub-circuit. The second conversion circuit performs a sign operation on the probability distribution of the second second information bit to obtain an estimated value of the second second information bit. The second conversion circuit is the sign conversion circuit of the second sub-circuit. The third operation unit receives and processes the estimated values ​​of the first and second second information bits and the result of the first g operation circuit to obtain a probability distribution for the third second information bit. The third operation unit is the operation unit of the third sub-circuit. The third conversion circuit performs a sign operation on the probability distribution of the third second information bit to obtain an estimated value for the third second information bit. The third conversion circuit is the sign conversion circuit of the third sub-circuit.

[0081] In one possible design, the second decoding circuit includes B subcircuits, each of the B subcircuits including an operation unit and a path metric circuit. The second decoding circuit decodes the result of the first g operation circuit to obtain an estimated value of the second information bit, including: the operation unit of the i-th subcircuit determines the probability distribution of the i-th second information bit among the B second information bits. i is any positive integer less than or equal to B. The i-th subcircuit is the i-th subcircuit among the B subcircuits. The path metric circuit of the i-th subcircuit receives the path metric value of the i-th decoding path, and determines the estimated value of the i-th second information bit based on the path metric value of the i-th decoding path and the probability distribution of the i-th second information bit. The i-th decoding path indicates the value of the bit before the i-th second information bit in the encoded sequence.

[0082] In one possible design, B=3. The bit preceding the first second information bit is a first frozen bit. The second decoding circuit decodes the result of the first g operation circuit to obtain an estimated value of the second information bit, including: a first operation unit receiving and processing the value of the first frozen bit and the result of the first g operation circuit to obtain a probability distribution of the first second information bit. The first operation unit is an operation unit of the first sub-circuit. The first path metric circuit receives the path metric value of the first decoding path and determines the estimated value of the first second information bit based on the path metric value of the first decoding path and the probability distribution of the first second information bit. The first decoding path indicates the value of the bit preceding the first second information bit. The first path metric circuit is the path metric circuit of the first sub-circuit. The second operation unit receives and processes the estimated value of the first second information bit and the result of the first g operation circuit to obtain a probability distribution of the second second information bit. The second operation unit is an operation unit of the second sub-circuit. The second path metric circuit receives the path metric value of the second decoding path and determines an estimated value of the second second information bit based on the path metric value of the second decoding path and the probability distribution of the second second information bit. The second decoding path indicates the value of the bit preceding the second second information bit. The second path metric circuit is the path metric circuit of the second sub-circuit. The third operation unit receives and processes the estimated values ​​of the first and second second information bits and the result of the first g operation circuit to obtain the probability distribution of the third second information bit. The third operation unit is the operation unit of the third sub-circuit. The third path metric circuit receives the path metric value of the third decoding path and determines an estimated value of the third second information bit based on the path metric value of the third decoding path and the probability distribution of the third second information bit. The third decoding path indicates the value of the bit preceding the third second information bit. The third path metric circuit is the path metric circuit of the third sub-circuit.

[0083] In one possible design, the first operation unit includes a second f operation circuit, a third f operation circuit, and a fifth g operation circuit. The first operation unit receives and processes the value of the first frozen bit and the result of the first g operation circuit, including: the second f operation circuit receives a second signal and performs an f operation on the second signal. The second signal is a portion of the result of the first g operation circuit. The third f operation circuit receives a third signal and performs an f operation on the second signal. The third signal is the signal in the result of the first g operation circuit other than the second signal. The fifth g operation circuit performs a g operation on the value of the first frozen bit, the result of the first f operation circuit, and the result of the second f operation circuit to obtain a processing result of the first operation unit.

[0084] In one possible design, the second operation unit includes a sixth g operation circuit, a seventh g operation circuit, and a fourth f operation circuit. The second operation unit receives and processes the estimated value of the first second information bit and the result of the first g operation circuit, including: the sixth g operation circuit performs a g operation on the estimated value of the first information bit and a second signal. The second signal is a portion of the result of the first g operation circuit. The seventh g operation circuit performs a g operation on the estimated value of the first information bit and a third signal. The third signal is the signal in the result of the first g operation circuit other than the second signal. The fourth f operation circuit performs an f operation on the results of the sixth g operation circuit and the seventh g operation circuit to obtain the processing result of the second operation unit.

[0085] In one possible design, the third operation unit includes a sixth g operation circuit, a seventh g operation circuit, and an eighth g operation circuit. The third operation unit receives and processes the estimated values ​​of both the first and second second information bits and the result of the first g operation circuit, including: the sixth g operation circuit performs a g operation on the estimated value of the first first information bit and a second signal. The second signal is a portion of the result of the first g operation circuit. The seventh g operation circuit performs a g operation on the estimated value of the first information bit and a third signal. The third signal is the signal in the result of the first g operation circuit excluding the second signal. The eighth g operation circuit performs a g operation on the estimated value of the second second information bit, the result of the sixth g operation circuit, and the result of the seventh g operation circuit to obtain the processing result of the third operation unit.

[0086] In one possible design, the coded sequence includes a first information bit. The analog circuit includes a first operation circuit and a sign conversion circuit. The analog circuit decodes the analog signal to obtain a decoding result, including: the first operation circuit performing a g operation on the analog signal; and the sign conversion circuit performing a sign-removal process on the result of the first operation circuit to obtain an estimated value of the first information bit.

[0087] In one possible design, a coded sequence includes a first information bit. The analog circuit includes a first operation circuit and a path metric circuit. The analog circuit decodes an analog signal to obtain a decoding result, including: the first operation circuit performing a g operation on the analog signal. The path metric circuit determines an estimated value of the first information bit based on the first path metric value and the result of the first operation circuit. The first path metric value is a metric value of a first decoding path, which indicates the value of a bit preceding the first information bit.

[0088] In one possible design, the frozen bits include a first frozen bit, a second frozen bit, and a third frozen bit. The first operation circuit includes a second g operation circuit, a third g operation circuit, and a fourth g operation circuit. The first operation circuit performs a g operation on the analog signal, including: the second g operation circuit performs a g operation on the value of the first frozen bit and the first N / 2 LLR values ​​in the analog signal; the third g operation circuit performs a g operation on the value of the second frozen bit and the last N / 2 LLR values ​​in the analog signal; and the fourth g operation circuit performs a g operation on the value of the third frozen bit, the result of the first g operation circuit, and the result of the second g operation circuit to obtain a result of the first operation circuit. The analog signal includes N LLR values.

[0089] In one possible design, the coding sequence includes B second information bits. The analog circuit includes B subcircuits, each of which includes an operation unit and a sign conversion circuit. The analog circuit decodes the analog signal to obtain a decoding result, including: the operation unit of the i-th subcircuit determines the probability distribution of the i-th second information bit among the B second information bits. i is any positive integer less than or equal to B. The i-th subcircuit is the i-th subcircuit among the B subcircuits. The sign conversion circuit of the i-th subcircuit performs a sign operation on the probability distribution of the i-th second information bit to obtain an estimated value of the i-th second information bit.

[0090] In one possible design, B=3. The bit preceding the first second information bit is a first frozen bit. The analog circuit decodes the analog signal to obtain a decoding result, including: a first operation unit receiving and processing the value of the first frozen bit and the analog signal to obtain a probability distribution of the first second information bit. The first operation unit is the operation unit of the first sub-circuit. The first conversion circuit performs a sign operation on the probability distribution of the first first information bit to obtain an estimated value of the first first information bit. The first conversion circuit is the sign conversion circuit of the first sub-circuit. The second operation unit receives and processes the estimated value of the first second information bit and the analog signal to obtain a probability distribution of the second second information bit. The second operation unit is the operation unit of the second sub-circuit. The second conversion circuit performs a sign operation on the probability distribution of the second second information bit to obtain an estimated value of the second second information bit. The second conversion circuit is the sign conversion circuit of the second sub-circuit. The third operation unit receives and processes the estimated values ​​of the first and second second information bits and the result of the first g operation circuit to obtain a probability distribution for the third second information bit. The third operation unit is the operation unit of the third sub-circuit. The third conversion circuit performs a sign operation on the probability distribution of the third second information bit to obtain an estimated value for the third second information bit. The third conversion circuit is the sign conversion circuit of the third sub-circuit.

[0091] In one possible design, the analog circuit includes B subcircuits, each of the B subcircuits including an arithmetic unit and a path metric circuit. The analog circuit decodes an analog signal to obtain a decoding result, including: the arithmetic unit of the i-th subcircuit determines the probability distribution of the i-th second information bit among the B second information bits. i is any positive integer less than or equal to B. The i-th subcircuit is the i-th subcircuit among the B subcircuits. The path metric circuit of the i-th subcircuit receives a path metric value of the i-th decoding path, and determines an estimated value of the i-th second information bit based on the path metric value of the i-th decoding path and the probability distribution of the i-th second information bit. The i-th decoding path indicates the value of the bit preceding the i-th second information bit in the encoded sequence.

[0092] In one possible design, B=3. The bit preceding the first second information bit is a first frozen bit. The analog circuit decodes the analog signal to obtain a decoding result, including: a first operation unit receiving and processing the value of the first frozen bit and the analog signal to obtain a probability distribution of the first second information bit. The first operation unit is an operation unit of the first sub-circuit. A first path metric circuit receives a path metric value of the first decoding path and determines an estimated value of the first second information bit based on the path metric value of the first decoding path and the probability distribution of the first second information bit. The first decoding path indicates the value of the bit preceding the first second information bit. The first path metric circuit is a path metric circuit of the first sub-circuit. A second operation unit receives and processes the estimated value of the first second information bit and the analog signal to obtain a probability distribution of the second second information bit. The second operation unit is an operation unit of the second sub-circuit. A second path metric circuit receives a path metric value of the second decoding path and determines an estimated value of the second second information bit based on the path metric value of the second decoding path and the probability distribution of the second second information bit. The second decoding path indicates the value of the bit preceding the second second information bit. The second path metric circuit is the path metric circuit of the second sub-circuit. The third operation unit receives and processes the estimated values ​​and analog signals of both the first and second second information bits to obtain a probability distribution of the third second information bit. The third operation unit is the operation unit of the third sub-circuit. The third path metric circuit receives the path metric value of the third decoding path and determines the estimated value of the third second information bit based on the path metric value of the third decoding path and the probability distribution of the third second information bit. The third decoding path indicates the value of the bit preceding the third second information bit. The third path metric circuit is the path metric circuit of the third sub-circuit.

[0093] In one possible design, the first operation unit includes a second f operation circuit, a third f operation circuit, and a fifth g operation circuit. The first operation unit receives and processes the value of the first frozen bit and the analog signal, including: the second f operation circuit receives the second signal and performs an f operation on the second signal. The second signal is a portion of the analog signal. The third f operation circuit receives the third signal and performs an f operation on the second signal. The third signal is a signal in the analog signal other than the second signal. The fifth g operation circuit performs a g operation on the value of the first frozen bit, the result of the first f operation circuit, and the result of the second f operation circuit to obtain a processing result of the first operation unit.

[0094] In one possible design, the second operation unit includes a sixth g operation circuit, a seventh g operation circuit, and a fourth f operation circuit. The second operation unit receives and processes the estimated value of the first second information bit and the analog signal, including: the sixth g operation circuit performing a g operation on the estimated value of the first information bit and the second signal. The second signal is a portion of the analog signal. The seventh g operation circuit performs a g operation on the estimated value of the first information bit and a third signal. The third signal is a signal in the analog signal other than the second signal. The fourth f operation circuit performs an f operation on the results of the sixth g operation circuit and the seventh g operation circuit to obtain a processing result of the second operation unit.

[0095] In one possible design, the third operation unit includes a sixth g operation circuit, a seventh g operation circuit, and an eighth g operation circuit. The third operation unit receives and processes the estimated values ​​of both the first and second second information bits and the analog signal, including: the sixth g operation circuit performs a g operation on the estimated value of the first first information bit and the second signal. The second signal is a portion of the analog signal. The seventh g operation circuit performs a g operation on the estimated value of the first information bit and the third signal. The third signal is the analog signal excluding the second signal. The eighth g operation circuit performs a g operation on the estimated value of the second second information bit, the result of the sixth g operation circuit, and the result of the seventh g operation circuit to obtain a processing result of the third operation unit.

[0096] According to a third aspect, a coding device is provided, comprising a processing module and a transceiver module. The processing module is configured to encode a sequence to be coded to obtain a coded sequence. The sequence to be coded includes at least one subblock, wherein the at least one subblock includes a first subblock. Each bit corresponding to the first subblock is a frozen bit, or each bit corresponding to the first subblock is an information bit. The transceiver module is configured to transmit the coded sequence.

[0097] In a fourth aspect, a coding method is provided. The coding method is applied to a coding device, and the method includes the coding device encoding a sequence to be coded to obtain a coded sequence. The coded sequence includes at least one subblock, and the at least one subblock includes a first subblock. Each bit corresponding to the first subblock is a frozen bit, or each bit corresponding to the first subblock is an information bit. The coding device transmits the coded sequence.

[0098] In a fifth aspect, a computer-readable storage medium is provided, wherein a program is stored in the computer-readable storage medium. When the program is called by a processor, the method of the second aspect or any one of the second aspects is executed. For example, when the program is called by the processor, the analog circuit in the decoding device performs the following steps: the analog circuit obtains an analog signal. The analog signal is determined by the decoding device based on the received coded sequence, and the coded sequence is the sequence after the sequence to be coded is coded, and the length of the sequence to be coded is N, where N=2 n , n is a positive integer. The analog circuit decodes the analog signal to obtain a decoding result. Alternatively, when the program is called by the processor, the method of the fourth aspect or any one of the fourth aspects is executed.

[0099] In a sixth aspect, a computer program product comprising instructions is provided. When the computer program product is called by a processor, the method of the second aspect or any one of the second aspects is executed. For example, when the program is called by the processor, the analog circuit in the decoding device performs the following steps: the analog circuit obtains an analog signal. The analog signal is determined by the decoding device based on the received coded sequence. The coded sequence is the sequence after the sequence to be coded is coded. The length of the sequence to be coded is N, where N=2 n , n is a positive integer. The analog circuit decodes the analog signal to obtain a decoding result. Alternatively, when the program is called by the processor, the method of the fourth aspect or any one of the fourth aspects is executed.

[0100] Among them, the technical effects brought about by any design in the second to sixth aspects can refer to the beneficial effects of the corresponding methods provided above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0101] FIG1 is a schematic diagram of the architecture of a communication system provided in an embodiment of the present application;

[0102] FIG2 is a schematic diagram of a basic flow of wireless communication provided by an embodiment of the present application;

[0103] FIG3 is a schematic diagram of an encoding process provided in an embodiment of the present application;

[0104] FIG4 is a schematic structural diagram of a decoding device provided in an embodiment of the present application;

[0105] FIG5 is a schematic structural diagram of an f operation circuit provided in an embodiment of the present application;

[0106] FIG6 is a schematic diagram of the structure of a g operation circuit provided in an embodiment of the present application;

[0107] FIG7 is a schematic structural diagram of another g operation circuit provided in an embodiment of the present application;

[0108] FIG8 is a schematic diagram of the structure of a path metric circuit provided in an embodiment of the present application;

[0109] FIG9 is a schematic diagram of the structure of another path metric circuit provided in an embodiment of the present application;

[0110] FIG10a is a schematic diagram of a decoding process of a polar code provided in an embodiment of the present application;

[0111] FIG10 b is a schematic structural diagram of an analog circuit provided in an embodiment of the present application;

[0112] FIG10c is a schematic structural diagram of another analog circuit provided in an embodiment of the present application;

[0113] FIG11a is a schematic diagram of a decoding process of another polar code provided in an embodiment of the present application;

[0114] FIG11b is a schematic structural diagram of another analog circuit provided in an embodiment of the present application;

[0115] FIG11c is a schematic structural diagram of another analog circuit provided in an embodiment of the present application;

[0116] FIG12a is a schematic diagram of a decoding process of another polar code provided in an embodiment of the present application;

[0117] FIG12b is a schematic structural diagram of another analog circuit provided in an embodiment of the present application;

[0118] FIG12c is a schematic structural diagram of another analog circuit provided in an embodiment of the present application;

[0119] FIG13a is a schematic diagram of a decoding process of another polar code provided in an embodiment of the present application;

[0120] FIG13b is a schematic structural diagram of another analog circuit provided in an embodiment of the present application;

[0121] FIG14 is a schematic diagram of a flow chart of a coding method provided in an embodiment of the present application;

[0122] FIG15 is a first structural diagram of an encoding device provided in an embodiment of the present application;

[0123] FIG16 is a second structural diagram of the encoding device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0124] FIG1 is a schematic diagram of the architecture of a communication system 1000 used in an embodiment of the present application. As shown in FIG1 , the communication system 1000 includes at least one network device (such as 110a and 110b in FIG1 ) and at least one terminal device (such as 120a-120j in FIG1 ). The terminal device is connected to the network device wirelessly. FIG1 is only a schematic diagram, and the communication system may also include other network devices, such as wireless relay devices and wireless backhaul devices, which are not shown in FIG1 .

[0125] A network device may be a base station, an evolved NodeB (eNodeB), a transmission reception point (TRP), a next-generation NodeB (gNB) in a fifth-generation (5G) mobile communication system, a next-generation base station in a sixth-generation (6G) mobile communication system, a base station in a future mobile communication system, or an access node in a wireless fidelity (WiFi) system. It may also be a module or unit that performs some of the functions of a base station, for example, a centralized unit (CU) or a distributed unit (DU). The CU here completes the functions of the radio resource control (RRC) protocol and the packet data convergence protocol (PDCP) of the base station, and can also complete the function of the service data adaptation protocol (SDAP); the DU completes the functions of the radio link control (RLC) layer and the medium access control (MAC) layer of the base station, and can also complete the functions of part of the physical layer or all of the physical layer. For the specific description of the above-mentioned various protocol layers, please refer to the relevant technical specifications of the 3rd Generation Partnership Project (3GPP). The network device can be a macro base station (such as 110a in Figure 1), a micro base station or an indoor station (such as 110b in Figure 1), or a relay node or a donor node, etc. The embodiments of the present application do not limit the specific technology and specific device form adopted by the network device. For the convenience of description, the following description is taken as an example.

[0126] Terminal devices may also be referred to as terminals, user equipment (UE), mobile stations, mobile terminals, etc. Terminal devices can be widely used in various scenarios, for example, device-to-device (D2D), vehicle-to-everything (V2X) communication, machine-type communication (MTC), Internet of Things (IOT), virtual reality, augmented reality, industrial control, autonomous driving, telemedicine, smart grid, smart furniture, smart office, smart wearable, smart transportation, smart city, etc. Terminal devices may be mobile phones, tablet computers, computers with wireless transceiver functions, wearable devices, vehicles, drones, helicopters, airplanes, ships, robots, robotic arms, smart home devices, etc. The embodiments of the present application do not limit the specific technology and specific device form adopted by the terminal devices.

[0127] Network devices and terminal devices can be fixed or mobile. They can be deployed on land, including indoors or outdoors, handheld or vehicle-mounted; on water; and in the air on aircraft, balloons, and satellites. The embodiments of this application do not limit the application scenarios of network devices and terminal devices.

[0128] The roles of network devices and terminal devices can be relative. For example, the helicopter or drone 120i in Figure 1 can be configured as a mobile base station. To terminal devices 120j accessing the wireless access network via 120i, terminal device 120i is a network device. However, to network device 110a, 120i is a terminal device, meaning that communication between 110a and 120i occurs via a wireless air interface protocol. Of course, communication between 110a and 120i can also occur via a base station-to-base station interface protocol. In this case, 120i is also a network device relative to 110a. Therefore, both network devices and terminal devices can be collectively referred to as communication devices. 110a and 110b in Figure 1 can be referred to as communication devices with network device functionality, while 120a-120j in Figure 1 can be referred to as communication devices with terminal device functionality.

[0129] Network devices and terminal devices, network devices and network devices, and terminal devices and terminal devices can communicate through authorized spectrum, unauthorized spectrum, or both; can communicate through spectrum below 6 gigahertz (GHz), spectrum above 6 GHz, or spectrum below 6 GHz and spectrum above 6 GHz simultaneously. The embodiments of the present application do not limit the spectrum resources used for wireless communications.

[0130] In the embodiments of the present application, the functions of the network device may also be performed by a module (such as a chip) in the network device, or by a control subsystem that includes the network device functions. The control subsystem that includes the network device functions here may be a control center in the above-mentioned application scenarios such as smart grid, industrial control, smart transportation, and smart city. The functions of the terminal device may also be performed by a module (such as a chip or a modem) in the terminal device, or by a device that includes the terminal device functions.

[0131] Next, the basic process of wireless communication is introduced.

[0132] Figure 2 illustrates a basic wireless communication process. At the transmitting device, a signal undergoes source coding, channel coding, and modulation before being transmitted over a channel to the receiving device. At the receiving device, the signal undergoes demodulation, channel decoding, and source decoding, and is then output to the destination. It's easy to understand that in uplink transmission, the transmitting device is the terminal device in Figure 1, and the receiving device is the network device in Figure 1. In downlink transmission, the transmitting device is the network device in Figure 1, and the receiving device is the terminal device in Figure 1.

[0133] It should be understood that the basic process of wireless communication also includes additional processes, such as precoding and interleaving. Since these additional processes are common knowledge to those skilled in the art, they are not listed one by one.

[0134] It should be understood that the encoding and decoding apparatus and method of the embodiments of the present application can be applied to both the source encoding and decoding process and the channel encoding and decoding process. In the source encoding and decoding scenario, the source coding can be performed using a Hadamard transform. In the channel encoding and decoding scenario, the channel coding can be performed using a Hadamard transform, and in addition to the Hadamard transform, other techniques are still required to complete the channel coding.

[0135] To facilitate understanding of the embodiments of the present application, the following briefly describes the technologies involved in the embodiments of the present application. It should be understood that these descriptions are only for facilitating understanding of the embodiments of the present application and should not constitute any limitation on the present application.

[0136] Polar codes

[0137] Polar code is a channel coding scheme that can be rigorously proven to asymptotically reach the Shannon capacity of a binary input channel. It has the characteristics of good performance and low complexity.

[0138] See Figure 3, which is a typical schematic diagram of 8X8 polar code encoding. In Figure 3, the sequence to be encoded includes Based on the reliability of each bit, the bits in the sequence to be encoded are divided into frozen bits and information (data) bits. Generally, bits with higher reliability are set as information bits, while bits with lower reliability are set as frozen bits. The value of the frozen bits is usually set to 0 and is known to both the transmitting and receiving devices. As shown in Figure 3, u7, u6, u5, and u3 are the four bits with the highest reliability and are set as information bits. u4, u2, u1, and u0 are the four bits with the lowest reliability and are set as frozen bits.

[0139] Polar codes are primarily decoded using the continuous erasure decoding algorithm. This algorithm decodes each bit based on the inherent temporal order of the polar code. Currently, the main continuous erasure decoding algorithms include successive cancellation (SC) decoding and successive cancellation list (SCL) decoding.

[0140] Currently, most communication systems transmit signals in the analog domain. Specifically, a transmitting device converts digital signals into analog signals for transmission via a digital-to-analog (DA) conversion module. Correspondingly, a receiving device receives the analog signals and quantizes them using an analog-to-digital (AD) conversion module to obtain digital signals. These signals are then decoded using digital circuits.

[0141] In the above-mentioned digital-to-analog conversion or analog-to-digital conversion process, there are two main ways to utilize ultra-bandwidth:

[0142] Method 1 divides the entire bandwidth into narrower sub-bands and uses parallel low-speed converters. However, this method requires a large number of low-speed converters and local oscillator circuits to ensure timing and bandwidth matching.

[0143] The second approach utilizes a single digital-to-analog converter (DAC) / analog-to-digital converter (DAC) across the entire ultra-wideband. However, the power consumption of this type of DAC / ADC is linearly proportional to the input signal bandwidth; the greater the bandwidth, the greater the DAC / ADC's power consumption. Furthermore, the power consumption of this type of DAC / ADC increases exponentially with accuracy; the higher the accuracy, the greater the power consumption.

[0144] In addition, the quantization process of analog-to-digital conversion introduces the quantization complexity of floating-point to fixed-point, which may also lead to performance loss and large storage capacity of digital circuits.

[0145] In view of this, an embodiment of the present application provides a coding and decoding device, wherein the coding device can encode a sequence to be coded, and the decoding device can decode in an analog domain.

[0146] Next, the decoding device 400 proposed in the embodiment of the present application is described in detail with reference to FIG. 4 to FIG. 12 c :

[0147] As shown in FIG4 , the decoding device 400 includes an analog circuit 401 and a transceiver 402. The analog circuit 401 is used to receive an analog signal from the transceiver 402. The analog signal is determined by the decoding device 400 based on the received coded sequence. The coded sequence is the sequence after the sequence to be coded is coded, and the length of the sequence to be coded is N, where N=2. n , n is a positive integer. Analog circuit 401 is further configured to decode the analog signal to obtain a decoding result. That is, after decoding device 400 acquires the analog signal, it decodes it in the analog domain, eliminating the need for analog-to-digital conversion. This eliminates the issues of high power consumption, high computational complexity, and performance loss associated with quantization, and also saves storage space in the digital circuit.

[0148] In the embodiment of the present application, when the length of the sequence to be encoded is different and the code rate is different, the circuit structure of the analog circuit 401 is also different.

[0149] To more clearly describe the circuit structure of analog circuit 401, the structures of the f operation circuit, the g operation circuit, and the path metric circuit are first described.

[0150] 1. Structure of f operation circuit

[0151] Referring to Figure 5 , a schematic diagram of an f-operation circuit is shown. In Figure 5 , the f-operation circuit includes a real to absolute value and sign (RTAS) converter 501, a sign multiplier (SM) 502, a minimum winner-take-all (WTA) module 503, and an absolute value and sign to real (ASTR) converter 504. The functions of each component are described below:

[0152] In Figure 5, RTAS converter 501 is used to convert real values ​​into signs and absolute values. That is, the input of RTAS converter 501 includes one or more real values, and the output of RTAS converter 501 includes the absolute value and sign of each real value.

[0153] For example, using FIG5 as an example, the inputs of RTAS converter 501 include real value Lin1 and real value Lin2. The outputs of RTAS converter 501 include: the absolute value |Lin1| corresponding to real value Lin1, the sign sign1 corresponding to real value Lin1; the absolute value |Lin2| corresponding to real value Lin2, and the sign sign2 corresponding to real value Lin2.

[0154] It is easy to understand that in the embodiment of the present application, the symbol refers to the analog domain symbol, and the two can be replaced with each other. For the sake of simplicity, the embodiment of the present application takes the symbol as an example for introduction. When the frozen bit is 1, the value of the symbol corresponding to the frozen bit is +1. Conversely, when the frozen bit is 0, the value of the symbol corresponding to the frozen bit is -1. During the XOR operation of the symbols, if the XOR symbols are the same, the result of the XOR operation is the symbol of the frozen bit. If the XOR symbols are different, the result of the XOR operation is another symbol of the frozen bit. For example, referring to Table 1, Table 1 shows the following four XOR operation situations:

[0155] When the frozen bit X is 1 and the information bit Y is 1, the values ​​of the symbols are both +1, and the frozen result of the XOR operation of the two symbols is +1.

[0156] When the frozen bit X is 0 and the information bit Y is 0, the values ​​of the symbols are both -1, and the frozen result of the XOR operation of the two symbols is -1.

[0157] When the frozen bit X is 0 and the information bit Y is 1, the value of the symbol corresponding to the frozen bit is -1, and the value of the symbol corresponding to the information bit is +1. The XOR operation of these two symbols results in a frozen result of +1.

[0158] When the frozen bit X is 1 and the information bit Y is 0, the value of the symbol corresponding to the frozen bit is +1, and the value of the symbol corresponding to the information bit is -1. The XOR operation of these two symbols results in a frozen result of -1. This is explained here and will not be repeated in the following text.

[0159] Table 1

[0160]

[0161] 5 , SM 502 is used to multiply at least two symbols. That is, the input of SM 502 includes two or more symbols, and the output of SM 502 includes one symbol, which is the symbol obtained by multiplying the input symbols of SM 502.

[0162] For example, taking FIG5 as an example, the input of SM502 includes a symbol sign1 and a symbol sign2. The output of SM502 includes: a symbol, which is a symbol obtained by multiplying the symbol sign1 and the symbol sign2.

[0163] In Figure 5 , the WTA module 503 is used to obtain the minimum value among multiple absolute values. That is, the input of the WTA module 503 includes two or more absolute values, and the output of the WTA module 503 includes an absolute value that is the minimum of the multiple absolute values ​​input to the WTA module 503.

[0164] For example, taking FIG5 as an example, the input of the WTA module 503 includes an absolute value |Lin1| and an absolute value |Lin2|. The output of the WTA module 503 includes: an absolute value |Lin1| i |, and the absolute value |L i | is the smaller of the absolute value |Lin1| and the absolute value |Lin2|.

[0165] 5 , the ASTR converter 504 is used to multiply an absolute value and a sign. That is, the input of the ASTR converter 504 includes an absolute value and a sign, and the output of the ASTR converter 504 includes a real value, which is the product of the absolute value and the sign of the input of the ASTR converter 504.

[0166] For example, taking FIG5 as an example, the input of the ASTR converter 504 includes the absolute value |L i | and the sign output by SM502. The output of ASTR converter 504 includes: a real value, which is composed of the absolute value |L i The result is obtained by multiplying the sign output by SM502. In Figure 5, it is denoted as f(Lin1, Lin2).

[0167] As shown in the description of Figure 5 above, the circuit structure shown in Figure 5 can implement the function of the f operation. The formula for the f operation is f(Lin1, Lin2) = sign(Lin1)sign(Lin2)min(|Lin1|,|Lin2|). This means that the inputs to the f operation are two real values ​​(i.e., the real value Lin1 and the real value Lin2), and the output of the f operation is a real value (i.e., the real value sign(lin1)sign(Lin2)min(|Lin1|,|Lin2|)).

[0168] It is easy to understand that FIG5 exemplifies the analog circuit structure of the f operation circuit and should not be understood as limiting the embodiments of the present application. Of course, if there are other analog circuit structures that can implement the f operation function, they also fall within the scope of protection of the embodiments of the present application.

[0169] It is easy to understand that in the embodiments of the present application, the f operation circuit involved can refer to the circuit structure shown in Figure 5, which is uniformly explained here and will not be repeated in the following text.

[0170] 2. Structure of g operation circuit

[0171] Referring to FIG6 , FIG6 shows a schematic diagram of a g operation circuit structure. In FIG6 , the g operation circuit includes a sign and real multiplier (SRM) 601 and a real adder (RA) 602. The functions of each component are described as follows:

[0172] In Figure 6, SRM 601 is used to multiply a real value and a sign. That is, the input of SRM 601 includes a real value and a sign, and the output of SRM 601 includes a real value that is the product of the real value and the sign input to SRM 601.

[0173] 6 , the input of SRM 601 includes a real value Lin2 and a symbol b. The output of SRM 601 includes the product of the real value Lin2 and the symbol b.

[0174] 6 , RA602 is used to add at least two real values. That is, the input of RA602 includes two or more real values, and the output of RA602 includes a real value obtained by adding the real values ​​input to RA602.

[0175] For example, using FIG6 as an example, the input of RA602 includes the real value Lin1 and the real value output by SRM601. The output of RA602 includes a real value, which is the sum of the real value Lin1 and the real value output by SRM601. In FIG6, this is denoted as g(Lin1, Lin2, b).

[0176] As can be seen from the above description of FIG6 , the circuit structure shown in FIG6 can realize the function of g operation.

[0177] Referring to FIG7 , FIG7 shows a schematic diagram of a g operation circuit structure. In FIG7 , the g operation circuit includes an RTAS converter 701, an SM 702, an ASTR converter 703, an RA 704, and a delay control circuit 705. The functions of each component are described as follows:

[0178] In Figure 7, RTAS converter 701 is used to convert real values ​​into signs and absolute values. That is, the input of RTAS converter 701 includes one or more real values, and the output of RTAS converter 701 includes the absolute value and analog domain sign of each real value.

[0179] 7 , the input of the RTAS converter 701 includes the real value Lin2 , and the output of the RTAS converter 701 includes: the absolute value |Lin2| corresponding to the real value Lin2 , and the analog domain symbol sign2 corresponding to the real value Lin2 .

[0180] In Figure 7, SM702 is used to multiply at least two symbols. That is, the input of SM702 includes two or more symbols, and the output of SM702 includes one symbol obtained by multiplying the symbols input to SM702.

[0181] 7 , the input of SM 702 includes symbol b and the symbol output by RTAS converter 701 . The output of SM 702 includes a symbol obtained by multiplying symbol b and the symbol output by RTAS converter 701 .

[0182] In Figure 7, the ASTR converter 703 is used to multiply the absolute value and the sign. That is, the input of the ASTR converter 703 includes an absolute value and a sign, and the output of the ASTR converter 703 includes a real value, which is the product of the absolute value and the sign input to the ASTR converter 703.

[0183] 7 , the input of ASTR converter 703 includes the absolute value |Lin2| and the sign output by SM 702. The output of ASTR converter 703 includes a real value obtained by multiplying the absolute value |Lin2| and the sign output by SM 702.

[0184] 7 , RA704 is used to add at least two real values. That is, the input of RA704 includes two or more real values, and the output of RA704 includes a real value obtained by adding the real values ​​input by RA704.

[0185] For example, using FIG7 as an example, the input of RA704 includes the real value Lin1 and the real value output by ASTR converter 703. The output of RA704 includes a real value obtained by adding the real value Lin1 and the real value output by ASTR converter 703. In FIG7 , this is denoted as g(Lin1, Lin2, b).

[0186] In FIG7 , the delay control circuit 705 is used to delay the input signal.

[0187] Exemplarily, taking FIG. 7 as an example, the delay control circuit 705 is used to delay the input of the real value Lin1.

[0188] As can be seen from the above description of FIG. 7 , the circuit structure shown in FIG. 7 can realize the function of g operation.

[0189] It is easy to understand that Figures 6 and 7 illustrate the analog circuit structure of the g operation circuit and should not be understood as limiting the embodiments of the present application. Of course, if there are other analog circuit structures that can implement the g operation function, they also fall within the scope of protection of the embodiments of the present application.

[0190] It is easy to understand that in the embodiments of the present application, the g operation circuit involved can refer to the circuit structure shown in Figure 6 or Figure 7, which is uniformly explained here and will not be repeated in the following text.

[0191] 3. Structure of path metric circuit

[0192] First, let's introduce the formula that path metrics satisfy:

[0193]

[0194] in, represents the path metric value of the i-th decoding path, Indicates the path metric value of the i-1th decoding path. express The absolute value of Represents a log-likelihood-ration (LLR), and the LLR represents the logarithm of the ratio of the probability that the value of the i-th bit is 0 to the probability that the value of the i-th bit is 1. The LLR is based on and Sure, represents an N-bit value, and is a value determined by the decoding device based on the received coded sequence, The i-th decoding path indicates the estimated value of the first i bits, and the i-1-th decoding path indicates the estimated value of the first i bits.

[0195] In formula (1), the first segment indicates that u i is an information bit or a correct frozen bit, and That is to say, in u i is an information bit or a correct frozen bit, and In the case of

[0196] In formula (1), the second segment indicates that u i is an information bit or a correct frozen bit, and That is to say, in u i is an information bit or a correct frozen bit, and In the case of

[0197] In formula (1), the third segment indicates that u i is a frozen bit and has an incorrect value. In this case,

[0198] FIG8 shows a schematic diagram of the structure of a path metric circuit. The path metric circuit includes an RTAS converter 801, an SM 802, a calculation unit 803, a real multiplier 804, and an RA 805. The functions of each component are described as follows:

[0199] In Figure 8, RTAS converter 801 is used to convert real values ​​into signs and absolute values. That is, the input of RTAS converter 801 includes one or more real values, and the output of RTAS converter 801 includes the absolute value and analog domain sign of each real value.

[0200] 8 , the input of the RTAS converter 801 includes a real value L. The output of the RTAS converter 801 includes: an absolute value |L| corresponding to the real value L, and an analog domain symbol sign(L) corresponding to the real value L.

[0201] In Figure 8, SM802 is used to multiply at least two symbols. That is, the input of SM802 includes two or more symbols, and the output of SM802 includes one symbol, which is the symbol obtained by multiplying the symbols input to SM802.

[0202] For example, taking FIG8 as an example, the input of SM802 includes the symbol u i =-1 and symbol sign(L). The output of SM802 includes: a symbol, which is symbol u i = -1 and the symbol sign (L) multiplied together. Specifically, in u i =-1 and the sign (L) is negative, the output of SM802 is +1. i When L = -1 and the sign (L) is positive, the output of SM802 is -1.

[0203] In FIG8 , the calculation unit 803 is used to perform the calculation of 0.5x-0.5.

[0204] For example, when the output of SM802 is +1, it means that the value of x in "05x-0.5" is +1. Accordingly, the value output by calculation unit 803 is 0. When the output of SM802 is -1, it means that the value of x in "05x-0.5" is -1. Accordingly, the value output by calculation unit 803 is -1.

[0205] In Figure 8, real number multiplier 804 is used to multiply at least two real numbers. That is, the input of real number multiplier 804 includes two or more real numbers, and the output of real number multiplier 804 includes a real number obtained by multiplying the real numbers input to real number multiplier 804.

[0206] For example, using FIG8 as an example, the input of real number multiplier 804 includes the absolute value |L| and the value output by calculation unit 803. The output of real number multiplier 804 includes a real number, which is obtained by multiplying the absolute value |L| and the value output by calculation unit 803. Specifically, when the value output by calculation unit 803 is -1, the value output by real number multiplier 804 is -|L|. When the value output by calculation unit 803 is 0, the value output by real number multiplier 804 is 0.

[0207] In FIG8 , RA805 is used to add at least two real values. That is, the input of RA805 includes two or more real values, and the output of RA805 includes a real value obtained by adding the real values ​​input to RA805.

[0208] For example, taking Figure 8 as an example, the input of RA805 includes and the value output by the real multiplier 804. The output of RA805 includes: a real value, which is Specifically, when the value output by the real number multiplier 804 is 0, the result output by RA805 is When the value output by the real multiplier 804 is -|L|, the result output by RA805 is

[0209] It is easy to understand that for u i For the correct frozen bit scenario, In this case, the circuit shown in FIG8 can realize the functions of the first segment and the second segment in formula (1).

[0210] It is easy to understand that for u i For frozen bits and incorrect values, The path metric circuit does not output the decoding result. The circuit shown in Figure 8 does not take this situation into consideration.

[0211] In the embodiment of the present application, the path metric circuit for freezing bits involved can refer to the circuit structure shown in FIG8 , which is uniformly explained here and will not be described in detail below.

[0212] Referring to FIG9 , FIG9 shows a schematic diagram of the structure of another path metric circuit. The path metric circuit includes a first processing module 901, a second processing module 902, and a compare converter (CC) 903. The functions of each component are described as follows:

[0213] In FIG9 , the first processing module 901 is used to determine u i =1 corresponds to a path metric value of 1.

[0214] For example, the circuit structure of the first processing module 901 can be seen in FIG8 , which will not be described in detail here.

[0215] Among them, the u input by the first processing module 901 i =1, which means that the i-th bit u i Possible value is 1.

[0216] Among them, the path metric value 1 can be recorded as

[0217] In FIG9 , the second processing module 902 is used to determine u i = -1 corresponds to a path metric value of 2.

[0218] For example, the circuit structure of the second processing module 902 can be seen in FIG8 , which will not be described in detail here.

[0219] Among them, the u input by the second processing module 902 i =-1, which means that the i-th bit u i Possible value is -1.

[0220] Among them, the path metric value 1 can be recorded as

[0221] In FIG9 , CC903 is used to compare the path metric value 1 and the path metric value 2 to output the larger path metric value and the u corresponding to the larger path metric value. i Specifically, when the path metric value 1 is large, the CC903 outputs is the path metric value 1, and u output by CC903 i = 1. When the path metric value 2 is large, the CC903 outputs is the path metric value 2, u output by CC903 i =-1.

[0222] Among them, the u output by CC903 i is the i-th bit u i Specifically, when CC903 outputs u i =1, it means that the i-th bit u i The estimated value is 1. i = -1, which means that the i-th bit u i The estimated value of is -1.

[0223] It is easy to understand that for u i For information bits, In this case, the circuit shown in FIG9 can realize the functions of the first segment and the second segment in formula (1).

[0224] It is easy to understand that Figures 8 and 9 illustrate the analog circuit structure of the path metric circuit and should not be understood as limiting the embodiments of the present application. Of course, if there are other analog circuit structures that can implement the path metric calculation function, they also fall within the scope of protection of the embodiments of the present application.

[0225] In the embodiment of the present application, the path metric circuit of the information bit involved can refer to the circuit structure shown in Figure 9, which is uniformly explained here and will not be repeated in the following text.

[0226] Next, the analog circuit 401 is introduced by taking different code lengths N and code rates R as examples:

[0227] Example 1:

[0228] Taking Figure 10a as an example, the code length N = 4 and the code rate R = 1 / 4. In Figure 10a, b1, b2, and b3 are frozen bits, and b4 is the information bit. The symbol value of the frozen bit forward feedback is fixed. Therefore, it is not necessary to perform f and g operations on each bit; the operation on the fourth bit (i.e., b4) can be performed. The analog signal includes z1, z2, z3, and z4. The analog signal is determined by the decoding device 400 based on the received coded sequence, such as the LLR of the received coded sequence determined by the decoding device 400. The above z1, z2, z3, and z4 are the LLR values ​​determined by the decoding device 400. z1 represents the LLR value of the first bit, z2 represents the LLR value of the second bit, z3 represents the LLR value of the third bit, and z4 represents the LLR value of the fourth bit.

[0229] In some embodiments, taking FIG10b as an example, the analog circuit 401 includes a g operation circuit 1001 and a sign conversion circuit 1002. The description of each circuit part is as follows:

[0230] The g operation circuit 1001 includes the following functions: receiving the value of the frozen bit, acquiring the analog signal, and performing the g operation on the value of the frozen bit and the analog signal.

[0231] Taking FIG10b as an example, the g operation circuit 1001 includes a g operation circuit A, a g operation circuit B, and a g operation circuit C. The three g operation circuits are described as follows:

[0232] The functions of the g operation circuit A include:

[0233] The g operation circuit A is used to receive the value of the first frozen bit, such as b1 = -1.

[0234] The g operation circuit A is used to obtain the value of the first portion of bits in the analog signal, wherein the first portion of bits includes a portion of bits in the encoded sequence, such as z1=-1, z2=-1.

[0235] The g operation circuit A is used to perform a g operation on the value of the first frozen bit and the value of the first part of bits. In FIG10 b , the processing of the g operation circuit A is denoted as g1 (z1, z2, b1).

[0236] The functions of the g operation circuit B include:

[0237] The g operation circuit B is used to receive the value of the second frozen bit, such as b2=-1.

[0238] The g operation circuit B is used to receive the value of the second portion of bits. The second portion of bits includes the bits in the encoded sequence except the first portion of bits, such as z3=-1, z4=-1.

[0239] The g operation circuit B is used to perform a g operation on the value of the second frozen bit and the value of the second part of the bits. In Figure 10b, the processing of the g operation circuit B is recorded as g2(z3,z4,b2).

[0240] The functions of the g operation circuit C include:

[0241] The g operation circuit C is used to receive the value of the third frozen bit, such as b3 = -1.

[0242] The g operation circuit C is used to receive the result of the g operation circuit A and the result of the g operation circuit B. In FIG10 b , the result of the g operation circuit A is denoted as g1 , and the result of the g operation circuit B is denoted as g2 .

[0243] The g operation circuit C is used to perform a g operation on the value of the third frozen bit, the result of the g operation circuit A, and the result of the g operation circuit B. In Figure 10b, the processing of the g operation circuit C is denoted as g3 (g1, g2, b3).

[0244] That is, in the g operation circuit 1001, the conditional probability of the information bit is determined by the g operation circuit A, the g operation circuit B, and the g operation circuit C.

[0245] The function of the sign conversion circuit 1002 includes: performing sign processing on the result of the g operation circuit 1001 to obtain an estimated value of the information bit.

[0246] Taking FIG10b as an example, the sign conversion circuit 1002 is used to perform sign processing (such as inversion) on the result of the g operation circuit C to obtain an estimated value of the information bit, that is, an estimated value of b4.

[0247] In this way, for some decoding methods of polar codes, such as SC decoding, the receiving device can decode the analog signal through the g operation circuit 1001 and the symbol conversion circuit 1002 without calculating the path metric.

[0248] In some other embodiments, taking FIG. 10c as an example, the analog circuit 401 includes a g operation circuit 1001 and a path metric circuit 1003. The description of each circuit part is as follows:

[0249] The g operation circuit 1001 can be referred to the introduction of FIG10 b and will not be described again here.

[0250] The functions of the path metric circuit 1003 include:

[0251] The path metric circuit 1003 is configured to receive a first path metric value, wherein the first path metric value is a metric value of a first decoding path, and the first decoding path indicates a value of a frozen bit.

[0252] Taking Figure 10c as an example, the first path metric value can be recorded as That is, the first decoding path indicates the values ​​of three frozen bits (ie, b1, b2, and b3).

[0253] The path metric circuit 1003 is configured to determine an estimated value of the information bit according to the first path metric value and a result of the g operation circuit 1001 .

[0254] The path metric circuit 1003 can be described in detail in FIG9 and will not be described in detail here.

[0255] Taking FIG. 10 c as an example, the path metric circuit 1003 is configured to determine an estimated value of the information bit, ie, an estimated value of b4, according to the first path metric value and the result of the g operation circuit C.

[0256] In this way, for some decoding methods of polar codes, such as SCL decoding, path metrics need to be calculated. The receiving device can decode the analog signal through the g operation circuit 1001 and the path metric circuit 1003.

[0257] It is easy to understand that in Figures 10b and 10c, the timing at which the analog currents of frozen bits b1 and b2 enter the circuit is controlled to perform two g operations in parallel (i.e., the g operation performed by g operation circuit A and the g operation performed by g operation circuit B). After these two g operations are completed, the timing at which frozen bit b3 enters the circuit is controlled to complete the g operation performed by g operation circuit C. In Figures 10b and 10c, the forward feedback symbols are all frozen bit symbols. The entire decoding process is completed by controlling the timing at which the frozen bit symbols enter analog circuit 401. No delay control is required between g operation circuits A and B, i.e., no delay control circuit is required.

[0258] Example 2:

[0259] Taking Figure 11a as an example, the code length N = 4 and the code rate R = 3 / 4. In Figure 11a, b1 is a frozen bit, and b2, b3, and b4 are information bits. The symbol value of the frozen bit forward feedback is fixed. Therefore, it is not necessary to perform f and g operations on each bit; operations on the second, third, and fourth bits (i.e., b2, b3, and b4) can be performed. Similarly, the analog signal includes z1, z2, z3, and z4. The analog signal is determined by the decoding device 400 based on the received coded sequence, such as the LLR of the received coded sequence determined by the decoding device 400. The above z1, z2, z3, and z4 are the LLR values ​​determined by the decoding device 400. z1 represents the LLR value of the first bit, z2 represents the LLR value of the second bit, z3 represents the LLR value of the third bit, and z4 represents the LLR value of the fourth bit.

[0260] In the second embodiment, the analog signal is divided into two parts, which are respectively recorded as the first signal and the second signal. For example, the first signal includes z1 = -1, z3 = -1, and the second signal includes z2 = -1, z4 = -1.

[0261] In some embodiments, taking FIG. 11b as an example, the encoded sequence includes K bits. The first bit of the K bits is a frozen bit, and the second bit to the Kth bit of the K bits are information bits, where K is a positive integer equal to N. When the code length N = 4 and the code rate R = 3 / 4, K = 4.

[0262] Analog circuit 401 includes K-1 subcircuits. Each of the K-1 subcircuits includes an operation unit and a sign conversion circuit. The operation unit of the i-th subcircuit is configured to determine the probability distribution of the i+1th bit among the K bits. i is a positive integer less than K, and the i-th subcircuit is the i-th subcircuit among the K-1 subcircuits. The sign conversion circuit of the i-th subcircuit is configured to perform a sign operation on the probability distribution of the i+1th bit to obtain an estimated value of the i+1th bit.

[0263] Specifically, taking Figure 11b as an example, the operation unit of the first subcircuit is denoted as the first operation unit 1101, and the sign conversion circuit of the first subcircuit is denoted as the first conversion circuit 1104. The operation unit of the second subcircuit is denoted as the second operation unit 1102, and the sign conversion circuit of the second subcircuit is denoted as the second conversion circuit 1105. The operation unit of the third subcircuit is denoted as the third operation unit 1103, and the sign conversion circuit of the third subcircuit is denoted as the third conversion circuit 1106. The description of each circuit is as follows:

[0264] The first operation unit 1101 is configured to receive the value of the first frozen bit and the target signal, and perform an operation on the value of the first frozen bit and the target signal to determine the probability distribution of the first information bit. In the case where the code length N=4 and the code rate R=3 / 4, the target signal is an analog signal.

[0265] Taking FIG. 11 b as an example, the first operation unit 1101 includes an f operation circuit 1 , an f operation circuit 2 , and a g operation circuit 1 .

[0266] In FIG11 b , the f operation circuit 1 is used to receive a first signal and perform an f operation on the first signal, wherein the first signal is a part of the target signal.

[0267] Exemplarily, in FIG. 11 b , the first signal includes z1 = -1, z3 = -1.

[0268] In FIG11 b , the f operation circuit 2 is configured to receive a second signal and perform an f operation on the second signal, wherein the second signal is a signal in the target signal other than the first signal.

[0269] Exemplarily, in FIG. 11 b , the second signal includes z2 = -1, z4 = -1.

[0270] In Figure 11b, the g operation circuit 1 is also used to receive the value of the first frozen bit, and perform the g operation on the value of the first frozen bit, the result of the f operation circuit 1, and the result of the f operation circuit 2 to obtain the processing result of the first operation unit (i.e., the probability distribution of the first information bit).

[0271] Exemplarily, the value of the first frozen bit is recorded as b1=-1, the result of f operation circuit 1 is recorded as f1, the result of f operation circuit 2 is recorded as f2, and the processing result of the first operation unit is recorded as g1(f1, f2, b1).

[0272] That is, the first operation unit 1101 determines the conditional probability of the information bit b2 through the f operation circuit and the g operation circuit.

[0273] The first conversion circuit 1104 is configured to perform a sign operation on the processing result of the first operation unit 1101 to obtain an estimated value of the first information bit.

[0274] The first conversion circuit 1104 can be described in detail in the introduction to the symbol conversion circuit in FIG10 b , which will not be described again here.

[0275] Exemplarily, the processing result of the first operation unit 1101 is g1(f1, f2, b1). The first information bit is information bit b2. Accordingly, the first conversion circuit 1104 inputs g1(f1, f2, b1) to obtain an estimated value of information bit b2.

[0276] The second operation unit 1102 is used to receive the estimated value of the first information bit and the target signal, and perform an operation on the estimated value of the first information bit and the target signal to obtain the probability distribution of the second information bit.

[0277] Taking FIG. 11 b as an example, the second operation unit 1102 includes an f operation circuit 3 , a g operation circuit 2 , and a g operation circuit 3 .

[0278] The g operation circuit 2 is configured to receive the estimated value of the first information bit and the first signal, and perform a g operation on the estimated value of the first information bit and the first signal. The first signal is a portion of the target signal. For details, see the description of the f operation circuit 1 in FIG11 b, which will not be repeated here.

[0279] The g operation circuit 3 is configured to receive the estimated value of the first information bit and the second signal, and perform the g operation on the estimated value of the first information bit and the second signal. The second signal is a signal in the target signal other than the first signal. For details, see the description of the f operation circuit 2 in FIG11 b, which will not be repeated here.

[0280] The f operation circuit 3 is used to process the results of the g operation circuit 2 and the g operation circuit 3 to obtain the processing result of the second operation unit (that is, the probability distribution of the second information bit).

[0281] Exemplarily, the result of g operation circuit 2 is recorded as g2, and the result of g operation circuit 3 is recorded as g3. The processing result of the second operation unit is recorded as f3 (g2, g3). The second information bit is b3.

[0282] That is, the second operation unit 1102 can determine the conditional probability of the information bit b3 through the f operation circuit and the g operation circuit.

[0283] The second conversion circuit 1105 is configured to perform a sign operation on the processing result of the second operation unit to obtain an estimated value of the second information bit.

[0284] The second conversion circuit 1105 can be described in detail in the description of the symbol conversion circuit in FIG10 b , which will not be described again here.

[0285] Exemplarily, the processing result of the second operation unit 1102 is f3(g2, g3). The second information bit is information bit b3. Accordingly, the second conversion circuit 1105 inputs f3(g2, g3) to obtain an estimated value of information bit b3.

[0286] The third operation unit 1103 is used to receive and process the estimated value of the first information bit, the estimated value of the second information bit and the target signal to obtain the probability distribution of the third information bit.

[0287] Taking FIG11b as an example, the third operation unit 1103 includes g operation circuit 2, g operation circuit 3 and g operation circuit 4. For g operation circuit 2 and g operation circuit 3, refer to the introduction of the second operation unit 1102 and will not be repeated here.

[0288] The g operation circuit 4 is used to receive the estimated value of the second information bit, the result of the g operation circuit 2 and the result of the g operation circuit 3, and perform the g operation on the estimated value of the second information bit, the result of the g operation circuit 2 and the result of the g operation circuit 3 to obtain the processing result of the third operation unit 1103 (that is, the probability distribution of the third information bit).

[0289] Exemplarily, the second information bit is b3, the result of g operation circuit 2 is recorded as g2, and the result of g operation circuit 3 is recorded as g3. The processing result of the third operation unit is recorded as g4 (g2, g3, b3). The third information bit is b4.

[0290] That is, the third operation unit 1103 can determine the conditional probability of the information bit b4 through the g operation circuit.

[0291] The third conversion circuit 1106 is configured to perform a sign operation on the processing result of the third operation unit to obtain an estimated value of the third information bit.

[0292] The third conversion circuit 1106 can be described in the introduction of the symbol conversion circuit in FIG10 b , which will not be described again here.

[0293] Illustratively, the processing result of the third operation unit 1103 is g4(g2, g3, b3). The third information bit is b4. Accordingly, the third conversion circuit 1106 inputs g4(g2, g3, b3) to obtain an estimated value of the information bit b4.

[0294] It is easy to understand that when the code length N=4 and the code rate R=3 / 4, the analog circuit 401 obtains the estimated values ​​of the information bits b2, b3, and b4, which means that the analog circuit 401 determines the decoding result.

[0295] This eliminates the need to calculate path metrics for some polar code decoding methods, such as SC decoding. When the code length N = 4 and the code rate R = 3 / 4, the receiving device can decode the analog signal using the arithmetic unit and symbol conversion circuit.

[0296] In other embodiments, taking FIG. 11c as an example, the encoded sequence includes K bits. The first bit of the K bits is a frozen bit, and the second bit through the K bits of the K bits are information bits, where K is a positive integer equal to N. When the code length N = 4 and the code rate R = 3 / 4, K = 4.

[0297] Analog circuit 401 includes K-1 subcircuits. Each of the K-1 subcircuits includes an operation unit and a path metric circuit. The operation unit of the i-th subcircuit is configured to determine the probability distribution of the i+1th bit of the K bits. i is a positive integer less than K. The i-th subcircuit is the i-th subcircuit of the K-1 subcircuits. The path metric circuit of the i-th subcircuit is configured to receive the path metric value of the i-th decoding path and determine an estimated value of the i+1th bit based on the path metric value of the i-th decoding path and the probability distribution of the i+1th bit. The i-th decoding path indicates the values ​​of the first i bits of the K bits.

[0298] Specifically, taking Figure 11c as an example, the operation unit of the first sub-circuit is denoted as first operation unit 1101, and the path metric circuit of the first sub-circuit is denoted as first path metric circuit 1107. The operation unit of the second sub-circuit is denoted as second operation unit 1102, and the path metric circuit of the second sub-circuit is denoted as second path metric circuit 1108. The operation unit of the third sub-circuit is denoted as third operation unit 1103, and the path metric circuit of the third sub-circuit is denoted as third path metric circuit 1109. The description of each circuit is as follows:

[0299] The first operation unit 1101 , the second operation unit 1102 and the third operation unit 1103 can be referred to the introduction of FIG11 b and will not be described again here.

[0300] The first path metric circuit 1107 is configured to receive a path metric value of a first decoding path and determine an estimated value of the first information bit based on the path metric value of the first decoding path and a probability distribution of the first information bit, wherein the first decoding path indicates a value of the first frozen bit.

[0301] Taking Figure 11c as an example, the first frozen bit is b1. The first decoding path indicates the value of the frozen bit b1. The path metric value of the first decoding path is recorded as The first information bit is b2, and the probability distribution of the first information bit is g1(f1, f2, b1). The estimated value of information bit b2 is determined by summing g1(f1, f2, b1). The first path metric circuit 1107 can be described in detail in FIG9 and will not be described again here.

[0302] The second path metric circuit 1108 is configured to receive a path metric value of a second decoding path and determine an estimated value of the second information bit based on the path metric value of the second decoding path and the probability distribution of the second information bit, wherein the second decoding path indicates the value of the first frozen bit and the estimated value of the first information bit.

[0303] Taking Figure 11c as an example, the first frozen bit is b1, the first information bit is b2, and the second decoding path indicates the value of the frozen bit b1 and the estimated value of the information bit b2. The path metric value of the second decoding path is recorded as The second information bit is b3, and the probability distribution of the second information bit is recorded as f3(g2, g3). The estimated value of information bit b3 is determined by summing f3(g2, g3). The second path metric circuit 1108 can be described in detail in FIG9 and will not be described again here.

[0304] The third path metric circuit 1109 is configured to receive a path metric value of the third decoding path and determine an estimated value of the third information bit based on the path metric value of the third decoding path and a probability distribution of the third information bit. The third decoding path indicates the value of the first frozen bit, the estimated value of the first information bit, and the estimated value of the second information bit.

[0305] Taking Figure 11c as an example, the first frozen bit is b1, the first information bit is b2, and the second information bit is b3. The third decoding path indicates the value of the frozen bit b1, the estimated value of the information bit b2, and the estimated value of the information bit b3. The path metric value of the third decoding path is recorded as The third information bit is b4, and the probability distribution of the third information bit is g4(g2, g3, b3). The estimated value of information bit b4 is determined by summing g4(g2, g3, b3). The third path metric circuit 1109 can be described in detail in FIG9 and will not be described again here.

[0306] It is easy to understand that when the code length N=4 and the code rate R=3 / 4, the analog circuit 401 obtains the estimated values ​​of the information bits b2, b3, and b4, which means that the analog circuit 401 determines the decoding result.

[0307] Therefore, some polar code decoding methods, such as SCL decoding, require path metric calculation. When the code length N = 4 and the code rate R = 3 / 4, the receiving device can decode the analog signal through the calculation unit and the path metric circuit.

[0308] It is easy to understand that in Figure 11b and Figure 11c, after z1, z2, z3, and z4 enter the f operation circuit 1 and the f operation circuit 2, two f operations (i.e., the f operations performed by the f operation circuit 1 and the f operation circuit 2) are performed in parallel, and z1, z2, z3, and z4 entering the g operation circuit 2 and the g operation circuit 3 are all delayed until the estimated value of the information bit b2 is obtained.

[0309] Then, after the results of g operation circuit 2 and g operation circuit 3 enter f operation circuit 3, f operation (i.e., f operation performed by f operation circuit 3) is performed, and the results of g operation circuit 2 and g operation circuit 3 are delayed until the estimated value of information bit b3 is obtained.

[0310] In addition, the analog circuit for information bit b3 and the analog circuit for information bit b3 are delayed until the estimated value of information bit b4 is obtained. The analog circuit 401 outputs the estimated values ​​of information bits b2, b3, and b4 together as the decoding result.

[0311] Example 3:

[0312] Taking Figure 12a as an example, the code length N = 8 and the code rate R = 3 / 8. In Figure 12a, b1, b2, b3, b4, and b5 are frozen bits, and b6, b7, and b8 are information bits. The symbol value of the frozen bits fed back forward is fixed. Therefore, there is no need to perform f and g operations on each bit; operations on the 6th, 7th, and 8th bits (i.e., b6, b7, and b8) are sufficient. Similarly, the analog signal includes z1, z2, z3, z4, z5, z6, z7, and z8. The analog signal is determined by the decoding device 400 based on the received coded sequence, such as the LLR of the received coded sequence determined by the decoding device 400. The above z1, z2, z3, z4, z5, z6, z7, and z8 are the LLR values ​​determined by the decoding device 400. z1 represents the LLR value of the first bit, z2 represents the LLR value of the second bit, z3 represents the LLR value of the third bit, z4 represents the LLR value of the fourth bit, and the rest can be deduced by analogy and will not be repeated here.

[0313] In the third embodiment, the analog signal is divided into four parts, which are respectively recorded as the third signal, the fourth signal, the fifth signal and the sixth signal. For example, the third signal includes z1 and z5, the fourth signal includes z2 and z6, the fifth signal includes z3 and z7, and the sixth signal includes z4 and z8.

[0314] In some embodiments, using Figure 12b or Figure 12c as an example, the encoded sequence includes K bits. The first bit of the K bits is a frozen bit, and the second to Kth bits of the K bits are information bits, where K is a positive integer less than N. In addition to the K bits, the encoded sequence also includes L frozen bits, which precede the K bits. L is a positive integer less than N. When the code length N = 8 and the code rate R = 3 / 4, K = L = 4.

[0315] Analog circuit 401 includes K-1 subcircuits. Each of the K-1 subcircuits includes an arithmetic unit and a sign conversion circuit. Each of the K-1 subcircuits can be described in detail in FIG. 11b or FIG. 11c and will not be described in detail here. In addition to the K-1 subcircuits, the analog circuit also includes g arithmetic circuit 5, g arithmetic circuit 6, g arithmetic circuit 7, and g arithmetic circuit 8. The descriptions of g arithmetic circuits 5 to 8 are as follows:

[0316] The g operation circuit 5 is configured to perform a g operation on the estimated value of the first target bit and the third signal, wherein the first target bit is one of the L frozen bits and the third signal is a portion of the analog signal.

[0317] Taking FIG12b (or FIG12c) as an example, the first target bit is the frozen bit b4. The third signal includes z1 and z5. The result of the g operation circuit 5 can be recorded as g5 (z1, z5, b4).

[0318] The g operation circuit 6 is configured to perform a g operation on the estimated value of the first target bit and the fourth signal, wherein the fourth signal is another part of the analog signal, and the third signal is different from the fourth signal.

[0319] Taking FIG12b (or FIG12c) as an example, the first target bit is the frozen bit b4. The fourth signal includes z2 and z6. The result of the g operation circuit 6 can be recorded as g6(z2, z6, b4).

[0320] The g operation circuit 7 is used to perform a g operation on the estimated value of the first target bit and the fifth signal, wherein the fifth signal is another part of the analog signal, and the third signal, the fourth signal and the fifth signal are different from each other.

[0321] Taking FIG12b (or FIG12c) as an example, the first target bit is the frozen bit b4. The fifth signal includes z3 and z7. The result of the g operation circuit 7 can be recorded as g7(z3, z7, b4).

[0322] The g operation circuit 8 is used to perform a g operation on the estimated value of the first target bit and the sixth signal, wherein the sixth signal is another part of the analog signal, and the third signal, the fourth signal, the fifth signal and the sixth signal are different from each other.

[0323] Taking FIG12b (or FIG12c) as an example, the first target bit is the frozen bit b4. The sixth signal includes z4 and z8. The result of the g operation circuit 8 can be recorded as g8 (z4, z8, b4).

[0324] It's easy to understand that in Figure 12b (or Figure 12c), for f operation circuit 1, f operation circuit 2, g operation circuit 2, and g operation circuit 3, the target signals are determined based on the analog signals. Specifically, the first target signal includes the results of g operation circuit 5 and g operation circuit 7. The second target signal includes the results of g operation circuit 6 and g operation circuit 8. In other words, the result of g operation circuit 5 in Figure 12b (or Figure 12c) is equivalent to z1 in Figure 11b (or Figure 11c). The result of g operation circuit 6 in Figure 12b (or Figure 12c) is equivalent to z2 in Figure 11b (or Figure 11c). The result of g operation circuit 7 in Figure 12b (or Figure 12c) is equivalent to z3 in Figure 11b (or Figure 11c). The result of g operation circuit 8 in Figure 12b (or Figure 12c) is equivalent to z4 in Figure 11b (or Figure 11c).

[0325] In summary, Figure 12b shows an analog circuit structure that does not require path metric calculation. This is true for some polar code decoding schemes, such as SC decoding. For code length N = 8 and code rate R = 3 / 4, the receiving device can decode the analog signal using the arithmetic unit, symbol conversion circuit, g arithmetic circuit 5, g arithmetic circuit 6, g arithmetic circuit 7, and g arithmetic circuit 8.

[0326] Figure 12c shows the analog circuit structure that requires path metric calculation, which is required for some polar code decoding methods, such as SCL decoding. For code length N = 8 and code rate R = 3 / 4, the receiving device can decode the analog signal using the arithmetic unit, symbol conversion circuit, g arithmetic circuit 5, g arithmetic circuit 6, g arithmetic circuit 7, and g arithmetic circuit 8.

[0327] It's easy to understand that in Figures 12b and 12c, z1, z2, z3, z4, z5, z6, z7, and z8, along with frozen bit b4, are controlled to enter the circuit simultaneously, executing four g operations (i.e., the g operations performed by g operation circuits 5-8) in parallel. For other details, refer to the description of Figures 11b and 11c, and will not be repeated here. In Figures 12b and 12c, the forward feedback symbols are all frozen bit symbols. The entire decoding process is completed by controlling the timing at which the frozen bit symbols enter analog circuit 401. No delay control is required before g operation circuits 5-8, meaning no delay control circuit is required.

[0328] Example 4:

[0329] Taking Figure 13a as an example, the code length N = 8 and the code rate R = 1 / 2. In Figure 13a, b1, b2, b3, and b4 are frozen bits, and b5, b6, b7, and b8 are information bits. The symbol value of the frozen bits in the forward feedback is fixed. Therefore, there is no need to perform f and g operations on each bit; operations on the 5th, 6th, 7th, and 8th bits (i.e., b5, b6, b7, and b8) are sufficient. Similarly, the analog signal includes z1, z2, z3, z4, z5, z6, z7, and z8. The analog signal is determined by the decoding device 400 based on the received coded sequence, such as the LLR of the received coded sequence determined by the decoding device 400. The above z1, z2, z3, z4, z5, z6, z7, and z8 are the LLR values ​​determined by the decoding device 400. z1 represents the LLR value of the first bit, z2 represents the LLR value of the second bit, z3 represents the LLR value of the third bit, z4 represents the LLR value of the fourth bit, and the rest can be deduced by analogy and will not be repeated here.

[0330] In the fourth embodiment, the analog signal is still divided into four parts, which are respectively recorded as the third signal, the fourth signal, the fifth signal and the sixth signal. For example, the third signal includes z1 and z5, the fourth signal includes z2 and z6, the fifth signal includes z3 and z7, and the sixth signal includes z4 and z8.

[0331] In some embodiments, taking Figure 13b as an example, the encoded sequence includes K bits. The first bit of the K bits is a frozen bit, and the second to Kth bits of the K bits are information bits, where K is a positive integer less than N. In addition to the K bits, the encoded sequence also includes M bits, where the M bits precede the K bits. The M bits include one information bit and M-1 frozen bits. M is a positive integer less than N. When the code length N = 8 and the code rate R = 1 / 2, K = M = 4.

[0332] The analog circuit 401 includes K-1 sub-circuits, g operation circuit 5, g operation circuit 6, g operation circuit 7, and g operation circuit 8. Each of the K-1 sub-circuits includes an operation unit and a sign conversion circuit, as described in FIG11b or FIG11c. For g operation circuits 5 to 8, see FIG12b or FIG12c for details, which will not be described in detail here. In addition to these (i.e., K-1 sub-circuits and g operation circuits 5 to 8), the analog circuit also includes f operation circuit 4, f operation circuit 5, f operation circuit 6, f operation circuit 7, a first operation circuit, and a fourth conversion circuit. The descriptions of each circuit are as follows:

[0333] The f operation circuit 4 is used to perform an f operation on the third signal.

[0334] Taking FIG13b as an example, the third signal includes z1 and z5. The result of the f operation circuit 4 can be recorded as f4(z1, z5).

[0335] The f operation circuit 5 is used to perform an f operation on the fourth signal.

[0336] Taking FIG13b as an example, the fourth signal includes z2 and z6. The result of the f operation circuit 5 can be recorded as f5(z2,z6).

[0337] The f operation circuit 6 is used to perform an f operation on the fifth signal.

[0338] Taking FIG13b as an example, the fifth signal includes z3 and z7. The result of the f operation circuit 6 can be recorded as f6(z3,z7).

[0339] The f operation circuit 7 is used to perform an f operation on the sixth signal.

[0340] Taking FIG13b as an example, the sixth signal includes z4 and z8. The result of the f operation circuit 7 can be recorded as f7(z4,z8).

[0341] The first operation circuit 1301 is configured to receive and process the values ​​of M-1 frozen bits, the result of the f operation circuit 4 , the result of the f operation circuit 5 , the result of the f operation circuit 6 , and the result of the f operation circuit 7 .

[0342] Taking FIG13b as an example, the first operation circuit 1301 includes a g operation circuit A, a g operation circuit B and a g operation circuit C. For details, please refer to the introduction of FIG10b, which will not be repeated here.

[0343] The M-1 frozen bits include frozen bits b1, b2, and b3. The result of the first operation circuit 1301 is recorded as g11 (g9, g10, b3). The specific operation process can be found in the introduction of Figure 10b and will not be repeated here.

[0344] The fourth conversion circuit 1302 is configured to perform sign processing on the result of the first operation circuit 1301 to obtain an estimated value of the information bit in the M bits.

[0345] Taking Figure 13b as an example, the fourth conversion circuit 1302 can be described with reference to the description of the symbol conversion circuit 1002 in Figure 10b and will not be further described here. The M bits include bits b1, b2, b3, and b4, the frozen bits include bits b1, b2, and b3, and the information bits include bit b4. The fourth conversion circuit 1302 performs a sign extraction process on g11 (g9, g10, and b3) to obtain an estimated value for information bit b4.

[0346] It is easy to understand that in Figure 13b, for g operation circuit A and g operation circuit B, the result of f operation circuit 4 in Figure 13b is equivalent to z1 in Figure 10b (or Figure 10c). The result of f operation circuit 5 in Figure 13b is equivalent to z2 in Figure 10b (or Figure 10c). The result of f operation circuit 6 in Figure 13b is equivalent to z3 in Figure 10b (or Figure 10c). The result of f operation circuit 7 in Figure 13b is equivalent to z4 in Figure 10b (or Figure 10c).

[0347] In summary, Figure 13b shows an analog circuit structure that does not require path metric calculation. For some polar code decoding schemes, such as SC decoding, path metric calculation is not required. When the code length N = 8 and the code rate R = 1 / 2, the receiving device can decode the analog signal through the operation unit, symbol conversion circuit, g operation circuit 5, g operation circuit 6, g operation circuit 7, g operation circuit 8, f operation circuit 4, f operation circuit 5, f operation circuit 6, f operation circuit 7, the first operation circuit, and the fourth conversion circuit.

[0348] In addition, some polar code decoding methods, such as SCL decoding, require path metric calculation. When the code length N = 8 and the code rate R = 1 / 2, the receiving device can decode the analog signal through the operation unit, symbol conversion circuit, g operation circuit 5, g operation circuit 6, g operation circuit 7, g operation circuit 8, f operation circuit 4, f operation circuit 5, f operation circuit 6, f operation circuit 7, the first operation circuit, and the fourth conversion circuit.

[0349] It is easy to understand that in the embodiment of the present application, in the notation of LLR, taking four LLRs as an example, they are recorded as z1, z2, z3, and z4. The subscripts are used to distinguish different LLRs. The positions of the four LLR input analog circuit 401 can be replaced with each other. Taking Figure 10b (or Figure 10c, or Figure 11b, or Figure 11c) as an example, z2 and z3 can be replaced with each other. In the notation of the symbols corresponding to the frozen bits, taking three symbols as an example, they are recorded as b1, b2, and b3. The subscripts are used to distinguish different symbols. The positions of the three symbols input analog circuit 401 can be replaced with each other. Taking Figure 10b (or Figure 10c) as an example, b2 and b3 can be replaced with each other, which should not be understood as a limitation on the embodiment of the present application.

[0350] Similarly, taking eight LLRs as an example, they are recorded as z1, z2, z3, z4, z5, z6, z7, and z8. The subscripts are used to distinguish different LLRs. The positions of the eight LLR input analog circuit 401 can be replaced with each other. Taking Figure 12b (or Figure 12c) as an example, z2 and z3 can be replaced with each other. In the notation of frozen bit corresponding symbols, taking two symbols as an example, they are recorded as b4 and b5. The subscripts are used to distinguish different symbols. The positions of the two symbols input analog circuit 401 can be replaced with each other. Taking Figure 12b (or Figure 12c) as an example, b4 and b5 can be replaced with each other, which should not be understood as a limitation on the embodiments of the present application.

[0351] The embodiment of the present application also provides a coding method 1400. The method is applicable to the communication system shown in Figures 1 and 2. As shown in Figure 14, the decoding method 1400 includes the following steps:

[0352] S1401. The encoding device encodes a sequence to be encoded to obtain an encoded sequence.

[0353] The encoding device may be located at the transmitting device side. Exemplarily, the encoding device uses Hadamard transform to encode the sequence to be encoded to obtain an encoded sequence.

[0354] Among them, the length of the sequence to be encoded is N, N=2 n , n is a positive integer. Exemplarily, the length of the sequence to be encoded is 4, as shown in FIG10a. Alternatively, the length of the sequence to be encoded is 8, as shown in FIG12a.

[0355] The sequence to be encoded includes at least one sub-block. The at least one sub-block includes a first sub-block. Each bit corresponding to the first sub-block is a frozen bit, or each bit corresponding to the first sub-block is an information bit.

[0356] For example, taking FIG10a as an example, the encoded sequence includes two sub-blocks. The first sub-block includes b1 and b2, and the second sub-block includes b3 and b4. Each bit corresponding to the first sub-block is a frozen bit.

[0357] For example, taking FIG11a as an example, the encoded sequence includes two sub-blocks. The first sub-block includes b1 and b2, and the second sub-block includes b3 and b4. Each bit corresponding to the second sub-block is an information bit.

[0358] For example, taking Figure 12a as an example, the encoded sequence includes two subblocks. The first subblock includes b1 to b4, and the second subblock includes b5 to b8. Each bit corresponding to the first subblock is a frozen bit. Alternatively, the encoded sequence includes four subblocks. The first subblock includes b1 and b2, the second subblock includes b3 and b4, the third subblock includes b5 and b6, and the fourth subblock includes b7 and b8. Each bit corresponding to the first and second subblocks is a frozen bit, and each bit corresponding to the fourth subblock is an information bit.

[0359] For example, using Figure 13a as an example, the encoded sequence includes four sub-blocks. The first sub-block includes b1 and b2, the second sub-block includes b3 and b4, the third sub-block includes b5 and b6, and the fourth sub-block includes b7 and b8. Each bit corresponding to the first sub-block is a frozen bit, and each bit corresponding to the fourth sub-block is an information bit.

[0360] S1402: The encoding device sends an encoded sequence, and the decoding device receives the encoded sequence accordingly.

[0361] Exemplarily, the encoding device transmits the encoded sequence via a transmitter, and correspondingly, the decoding device receives the encoded sequence via a receiver.

[0362] It is easy to understand that the processing that the coded sequence undergoes before transmission over the channel, such as rate matching, precoding, interleaving, modulation, etc., is common knowledge to those skilled in the art and will not be listed one by one. In the embodiments of this application, the transmission of the coded sequence is used as an example for description, which should not be construed as limiting the embodiments of this application.

[0363] S1403: The decoding device obtains an analog signal according to the encoded sequence.

[0364] Exemplarily, the analog circuit in the decoding device obtains an analog signal according to the encoded sequence, such as determining N LLRs. The structure of the analog circuit can be seen in the introduction of FIG. 4 to FIG. 13 b , which will not be described in detail here.

[0365] S1404: The decoding device analog circuit decodes the analog signal to obtain a decoding result.

[0366] Exemplarily, the analog circuit of the decoding device decodes the analog signal to obtain a decoding result. The process of the analog circuit determining the decoding result can be seen in the introduction of Figures 4 to 13b, which will not be repeated here.

[0367] The method provided by the embodiment of the present application is described in detail above in conjunction with Figure 14. The following describes in detail an encoding device for executing the method provided by the embodiment of the present application in conjunction with Figures 15 and 16.

[0368] For example, Figure 15 is a schematic diagram of the structure of the encoding device provided in an embodiment of the present application. As shown in Figure 15, the encoding device 1500 includes: a processing module 1501 and a transceiver module 1502. For ease of description, Figure 15 only shows the main components of the encoding device 1500.

[0369] In some embodiments, the encoding device 1500 may be applicable to the communication system shown in FIG1 and perform the functions of the encoding device in the method shown in FIG14.

[0370] Processing module 1501 is configured to encode a sequence to be encoded to obtain an encoded sequence. The sequence to be encoded includes at least one sub-block, and the at least one sub-block includes a first sub-block. Each bit corresponding to the first sub-block is a frozen bit, or each bit corresponding to the first sub-block is an information bit.

[0371] The transceiver module 1502 is configured to send the encoded sequence.

[0372] Optionally, the transceiver module 1502 may include a receiving module and a sending module (not shown in FIG15 ). The transceiver module 1502 is used to implement the sending function and the receiving function of the encoding device 1500 .

[0373] Optionally, the encoding device 1500 may further include a storage module (not shown in FIG15 ) that stores a program or instruction. When the processing module 1501 executes the program or instruction, the encoding device 1500 may perform the functions of the encoding device in the method shown in FIG14 .

[0374] It should be understood that the processing module 1501 involved in the encoding device 1500 can be implemented by a processor or a processor-related circuit component, which can be a processor or a processing module; the transceiver module 1502 can be implemented by a transceiver or a transceiver-related circuit component, which can be a transceiver or a transceiver unit.

[0375] In addition, the technical effects of the encoding device 1500 can refer to the technical effects of the method shown in Figure 14, and will not be repeated here.

[0376] For example, FIG16 is a second structural diagram of an encoding device provided in an embodiment of the present application. As shown in FIG16 , encoding device 1600 may include a processor 1601. Optionally, encoding device 1600 may further include a memory 1602 and / or a transceiver 1603. Processor 1601 is coupled to memory 1602 and transceiver 1603, for example, via a communication bus.

[0377] The following is a detailed introduction to the various components of the encoding device 1600 in conjunction with FIG16 :

[0378] The processor 1601 is the control center of the encoding device 1600 and can be a single processor or a collective term for multiple processing elements. For example, the processor 1601 can be one or more central processing units (CPUs), an application specific integrated circuit (ASIC), or one or more integrated circuits configured to implement the embodiments of the present application, such as one or more digital signal processors (DSPs) or one or more field programmable gate arrays (FPGAs).

[0379] Optionally, the processor 1601 may execute various functions of the encoding device 1600 by running or executing a software program stored in the memory 1602 and calling data stored in the memory 1602 .

[0380] In a specific implementation, as an embodiment, the processor 1601 may include one or more CPUs, such as CPU0 and CPU1 shown in FIG16 .

[0381] In a specific implementation, as an embodiment, the encoding device 1600 may also include multiple processors, such as the processor 1601 and the processor 1604 shown in FIG16 . Each of these processors may be a single-core processor (single-CPU) or a multi-core processor (multi-CPU). The processor herein may refer to one or more devices, circuits, and / or processing cores for processing data (e.g., computer program instructions).

[0382] Among them, the memory 1602 is used to store the software program for executing the solution of this application, and the execution is controlled by the processor 1601. The specific implementation method can refer to the above method embodiment and will not be repeated here.

[0383] Alternatively, the memory 1602 may be a read-only memory (ROM) or other type of static storage device that can store static information and instructions, a random access memory (RAM) or other type of dynamic storage device that can store information and instructions, or an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other optical disc storage, an optical disc storage (including a compact disc, laser disc, optical disc, digital versatile disc, Blu-ray disc, etc.), a magnetic disk storage medium or other magnetic storage device, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and can be accessed by a computer, but is not limited thereto. The memory 1602 may be integrated with the processor 1601 or exist independently and be coupled to the processor 1601 through an interface circuit (not shown in FIG16 ) of the encoding device 1600, which is not specifically limited in this embodiment of the present application.

[0384] The transceiver 1603 is used for communication with other devices. For example, if the encoding device 1600 is a transmitting device, the transceiver 1603 can be used for communication with a receiving device.

[0385] Optionally, the transceiver 1603 may include a receiver and a transmitter (not shown separately in FIG16 ), wherein the receiver is used to implement a receiving function, and the transmitter is used to implement a sending function.

[0386] Optionally, the transceiver 1603 can be integrated with the processor 1601, or can exist independently and be coupled to the processor 1601 through the interface circuit of the encoding device 1600 (not shown in Figure 16), which is not specifically limited in this embodiment of the present application.

[0387] It is easy to understand that the structure of the encoding device 1600 shown in Figure 16 does not constitute a limitation on the encoding device. The actual encoding device may include more or fewer components than shown in the figure, or combine certain components, or arrange the components differently.

[0388] In addition, the technical effects of the encoding device 1600 can refer to the technical effects of the methods described in the above method embodiments, and will not be repeated here.

[0389] It should be understood that the processor in the embodiments of the present application may be a central processing unit (CPU), and the processor may also be other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or any conventional processor, etc.

[0390] It should also be understood that the memory in the embodiments of the present application may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of random access memory (RAM) are available, such as static RAM (SRAM), dynamic random access memory (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), and direct rambus RAM (DR RAM).

[0391] Optionally, an embodiment of the present application further provides a computer program product carrying computer instructions, which, when executed on a processor, causes an analog circuit in a decoding device to execute the following steps: the analog circuit acquires an analog signal. The analog signal is determined by the decoding device based on a received coded sequence, the coded sequence being a sequence after the sequence to be coded is coded, and the length of the sequence to be coded is N, where N=2 n , n is a positive integer. The analog circuit decodes the analog signal to obtain a decoding result.

[0392] Alternatively, when the computer instructions are executed on a processor, the encoding device performs the following steps: the encoding device encodes a sequence to be encoded to obtain an encoded sequence. The sequence to be encoded includes at least one subblock, and the at least one subblock includes a first subblock. Each bit corresponding to the first subblock is a frozen bit, or each bit corresponding to the first subblock is an information bit. The encoding device transmits the encoded sequence.

[0393] Optionally, an embodiment of the present application further provides a computer-readable storage medium storing computer instructions. When the computer instructions are executed on a processor, the analog circuit in the decoding device executes the following steps: the analog circuit obtains an analog signal. The analog signal is determined by the decoding device based on the received coded sequence. The coded sequence is the sequence after the sequence to be coded is coded. The length of the sequence to be coded is N, where N=2 n , n is a positive integer. The analog circuit decodes the analog signal to obtain a decoding result.

[0394] Alternatively, when the computer instructions are executed on a processor, the encoding device performs the following steps: the encoding device encodes a sequence to be encoded to obtain an encoded sequence. The sequence to be encoded includes at least one subblock, and the at least one subblock includes a first subblock. Each bit corresponding to the first subblock is a frozen bit, or each bit corresponding to the first subblock is an information bit. The encoding device transmits the encoded sequence.

[0395] Optionally, an embodiment of the present application further provides a chip including an analog circuit. The analog circuit is used to obtain an analog signal. The analog signal is determined by the decoding device based on the received coded sequence, the coded sequence is the sequence after the sequence to be coded is coded, and the length of the sequence to be coded is N, where N=2 n , n is a positive integer. The analog circuit is also used to decode the analog signal to obtain a decoding result.

[0396] Alternatively, the chip includes processing circuitry and an input / output interface. The input / output interface is used to communicate with modules outside the chip. For example, the chip may perform the following steps to implement the above: encoding the sequence to be encoded to obtain an encoded sequence, and transmitting the encoded sequence. The sequence to be encoded includes at least one sub-block, and the at least one sub-block includes a first sub-block. Each bit corresponding to the first sub-block is a frozen bit, or each bit corresponding to the first sub-block is an information bit.

[0397] The above embodiments can be implemented in whole or in part by software, hardware (such as circuits), firmware or any other combination. When implemented using software, the above embodiments can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions or computer programs. When the computer instructions or computer program are loaded or executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from one website, computer, server or data center to another website, computer, server or data center via a wired (such as infrared, wireless, microwave, etc.) method. The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server or data center that contains one or more available media sets. The available medium can be a magnetic medium (for example, a floppy disk, a hard disk, a tape), an optical medium (for example, a DVD), or a semiconductor medium. The semiconductor medium can be a solid-state drive.

[0398] It should be understood that the term "and / or" as used herein simply describes a relationship between associated objects, indicating that three possible relationships exist. For example, "A and / or B" can represent: A alone, A and B together, or B alone. A and B can be singular or plural. Furthermore, the character " / " as used herein generally indicates an "or" relationship between the associated objects, but it may also indicate an "and / or" relationship. For specific understanding, please refer to the context.

[0399] In this application, "at least one" means one or more, and "plurality" means two or more. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can mean: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or plural.

[0400] It should be understood that in the various embodiments of the present application, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0401] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0402] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0403] In the several embodiments provided in this application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of the units is merely a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0404] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0405] In addition, each functional unit in each embodiment of the present application may be integrated into one processing module, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0406] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, server, or communication device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0407] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. A decoding device, characterized in that: include: Analog circuit; wherein, The analog circuit is used to obtain an analog signal; the analog signal is determined by the decoding device according to the received coded sequence, the coded sequence is the sequence after the sequence to be coded is coded, and the length of the sequence to be coded is N, N=2 n , n is a positive integer; The analog circuit is further used to decode the analog signal to obtain a decoding result.

2. The device according to claim 1, characterized in that The sequence to be encoded includes a first information bit and a second information bit; the analog circuit includes a first f operation circuit, a first decoding circuit, a first delay control circuit, a first g operation circuit and a second decoding circuit; The analog circuit is further configured to decode the analog signal to obtain a decoding result, including: The first f operation circuit is used to perform f operation on the analog signal; The first decoding circuit is configured to decode a result of the first f operation circuit to obtain an estimated value of the first information bit; the result decoded by the first decoding circuit corresponds to a code length of N / 2 and a code rate of A / (N / 2), where A represents the number of the first information bits; The first delay control circuit is used to control the time when the analog signal is input into the first g operation circuit; The first g operation circuit is configured to perform a g operation on the analog signal and a first bit value, wherein the first bit value is an estimated value of the first information bit; the second decoding circuit being configured to decode a result of the first g operation circuit to obtain an estimated value of the second information bit; the result decoded by the second decoding circuit corresponds to a code length of N / 2 and a code rate of B / (N / 2), where B represents the number of the second information bits; The decoding result includes an estimated value of the first information bit and an estimated value of the second information bit.

3. The device according to claim 2, characterized in that The first f operation circuit includes a first real number to absolute value sign RTAS converter, a minimum WTA module, a first multiplier and a second multiplier; The first f operation circuit is used to perform an f operation on the analog signal, including: The first RTAS converter is configured to receive and process a first signal to obtain a sign and an absolute value corresponding to each log-likelihood ratio (LLR) value in the first signal; the first signal includes two LLR values ​​in the analog signal; The WTA module is configured to determine a minimum value among the absolute values ​​obtained by the first RTAS converter; The first multiplier is configured to multiply the symbols obtained by the first RTAS converter; the second multiplier is configured to multiply a result of the WTA module by a result of the first multiplier; The number of the first f operation circuits is N / 2, and the result of the first f operation circuit includes the results of N / 2 second multipliers.

4. The device according to claim 1, characterized in that The sequence to be encoded includes a second information bit; the analog circuit includes a first g operation circuit and a second decoding circuit; The analog circuit is further configured to decode the analog signal to obtain a decoding result, including: The first g operation circuit is configured to perform a g operation on the analog signal and a first bit value, wherein the first bit value is determined based on first N / 2 LLR values ​​in the analog signal; the second decoding circuit being configured to decode a result of the first g operation circuit to obtain an estimated value of the second information bit; the result decoded by the second decoding circuit corresponds to a code length of N / 2 and a code rate of B / (N / 2), where B represents the number of the second information bits; The decoding result includes an estimated value of the second information bit.

5. The device according to any one of claims 2 to 4, characterized in that: The first g operation circuit includes a third multiplier and a first adder; The first g operation circuit is configured to perform a g operation on the analog signal and the first bit value, including: The third multiplier is configured to multiply the first bit value and an LLR value in a first signal; the first signal includes two LLR values ​​in the analog signal; The first adder is configured to add a result of the third multiplier and another LLR value in the first signal; The number of the first g operation circuits is N / 2, and the result of the first g operation circuit includes the results of N / 2 first adders.

6. The device according to any one of claims 2 to 4, characterized in that: The first g operation circuit includes a second RTAS converter, a fourth multiplier, a fifth multiplier, a second delay control circuit, and a second adder; the first g operation circuit is used to perform a g operation on the analog signal and the first bit value, including: The second RTAS converter is configured to receive and process an LLR value in a first signal to obtain a first sign and a first absolute value; the first signal includes two LLR values ​​in the analog signal; the fourth multiplier is configured to multiply the first bit value and the first symbol; the fifth multiplier is configured to multiply the result of the fourth multiplier by the first absolute value; The second delay control circuit is used to control the time when another LLR value in the first signal is input into the second adder; the second adder is configured to add a result of the fifth multiplier and the LLR value input by the second delay control circuit; The number of the first g operation circuits is N / 2, and the result of the first g operation circuit includes the results of N / 2 second adders.

7. The device according to claim 2 or 3, characterized in that The sequence to be encoded further includes frozen bits; the first decoding circuit includes a first operation circuit and a symbol conversion circuit; the first decoding circuit is configured to decode a result of the first operation circuit to obtain an estimated value of the first information bit, including: The first operation circuit is configured to receive a result of the first f operation circuit and perform a g operation on the value of the frozen bit and the result of the first f operation circuit; The sign conversion circuit is used to perform sign processing on the result of the first operation circuit to obtain an estimated value of the first information bit.

8. The device according to claim 2 or 3, characterized in that The sequence to be encoded further includes frozen bits; the first decoding circuit includes a first operation circuit and a path metric circuit; The first decoding circuit is used to decode the result of the first f operation circuit to obtain an estimated value of the first information bit, including: The first operation circuit is configured to receive a result of the first f operation circuit and perform a g operation on the value of the frozen bit and the result of the first f operation circuit; The path metric circuit is used to determine an estimated value of the first information bit based on a first path metric value and a result of the first operation circuit; the first path metric value is a metric value of a first decoding path, and the first decoding path indicates a value of a bit preceding the first information bit.

9. The device according to claim 8, characterized in that The candidate values ​​of the first information bit include a first candidate value and a second candidate value; the path metric circuit includes a first processing module, a second processing module and a comparator; The path metric circuit is configured to determine an estimated value of the first information bit according to the first path metric value and a result of the first operation circuit, including: The first processing module is configured to receive the first path metric value and a result of the first operation circuit, and determine a second path metric value according to the first candidate value, the first path metric value, and the result of the first operation circuit; the second processing module is configured to receive the first path metric value and a result of the first operation circuit, and determine a third path metric value according to the second candidate value, the first path metric value, and the result of the first operation circuit; The comparator is used to compare the second path metric value and the third path metric value and output an estimated value of the first information bit; the estimated value of the first information bit is a candidate value corresponding to the larger path metric value between the second path metric value and the third path metric value.

10. The device according to claim 9, characterized in that The first processing module includes a third RTAS converter, a sixth multiplier, a first calculation unit, a seventh multiplier, and a third adder; the first processing module is configured to receive the first path metric value and a result of the first operation circuit, and determine a second path metric value based on the first candidate value, the first path metric value, and the result of the first operation circuit, including: The third RTAS converter is configured to receive and process the result of the first operation circuit to output a second sign and a second absolute value; the sixth multiplier is configured to multiply the first candidate value and the second symbol; The first computing unit is configured to receive and process a result of the sixth multiplier; The seventh multiplier is configured to multiply the result of the first calculation unit and the second absolute value; The third adder is used to add the first path metric value and the result of the seventh multiplier to obtain the second path metric value.

11. The device according to claim 9, characterized in that The second processing module includes a fourth RTAS converter, an eighth multiplier, a second calculation unit, a ninth multiplier, and a fourth adder. The second processing module is configured to receive the first path metric value and a result of the first operation circuit, and determine a third path metric value based on the second candidate value, the first path metric value, and the result of the first operation circuit, including: the fourth RTAS converter is configured to receive and process a result of the first operation circuit to output a third sign and a third absolute value; the eighth multiplier is configured to multiply the second candidate value and the third symbol; The second computing unit is configured to receive and process a result of the eighth multiplier; The ninth multiplier is configured to multiply the result of the second calculation unit by the third absolute value; The fourth adder is used to add the first path metric value and the result of the ninth multiplier to obtain the third path metric value.

12. The device according to any one of claims 7 to 11, characterized in that: The frozen bits include a first frozen bit, a second frozen bit, and a third frozen bit; the result of the first f operation circuit includes a first partial result and a second partial result, the first partial result includes the results of the first N / 4 first f operation circuits, and the second partial result includes the results of the last N / 4 first f operation circuits; The first operation circuit includes a second g operation circuit, a third g operation circuit and a fourth g operation circuit; The first operation circuit is configured to receive a result of the first f operation circuit and perform a g operation on the value of the frozen bit and the result of the first f operation circuit, including: The second g operation circuit is configured to perform a g operation on the value of the first frozen bit and the first partial result; The third g operation circuit is used to perform a g operation on the value of the second frozen bit and the second partial result; The fourth g operation circuit is configured to perform a g operation on the value of the third frozen bit, the result of the first g operation circuit, and the result of the second g operation circuit to obtain the result of the first operation circuit.

13. The device according to any one of claims 2 to 7, characterized in that: The second decoding circuit includes B sub-circuits, each of the B sub-circuits includes an operation unit and a symbol conversion circuit; the second decoding circuit is used to decode the result of the first g operation circuit to obtain an estimated value of the second information bit, including: The operation unit of the i-th sub-circuit is used to determine the probability distribution of the i-th second information bit among the B second information bits; the i-th sub-circuit is the i-th sub-circuit among the B sub-circuits; The sign conversion circuit of the i-th sub-circuit is configured to perform a sign operation on the probability distribution of the i-th second information bit to obtain an estimated value of the i-th second information bit; Wherein, i is any positive integer less than or equal to B.

14. The device according to claim 13, characterized in that B=3; the bit preceding the first second information bit is a first frozen bit; the second decoding circuit is used to decode the result of the first g operation circuit to obtain an estimated value of the second information bit, including: a first operation unit, configured to receive and process the value of the first frozen bit and the result of the first g operation circuit to obtain a probability distribution of the first second information bit; the first operation unit is an operation unit of the first sub-circuit; a first conversion circuit, configured to perform a sign operation on the probability distribution of the first first information bit to obtain an estimated value of the first first information bit; the first conversion circuit being a sign conversion circuit of the first sub-circuit; a second operation unit, configured to receive and process the estimated value of the first second information bit and the result of the first g operation circuit to obtain a probability distribution of the second second information bit; the second operation unit is an operation unit of the second sub-circuit; a second conversion circuit, configured to perform a sign operation on the probability distribution of the second second information bit to obtain an estimated value of the second second information bit; the second conversion circuit being a sign conversion circuit of the second sub-circuit; a third operation unit, configured to receive and process the estimated values ​​of the first second information bit and the second second information bit and the result of the first g operation circuit to obtain a probability distribution of the third second information bit; the third operation unit is an operation unit of the third sub-circuit; The third conversion circuit is used to perform a sign operation on the probability distribution of the third second information bit to obtain an estimated value of the third second information bit; the third conversion circuit is the sign conversion circuit of the third sub-circuit.

15. The device according to any one of claims 2 to 7, characterized in that: The second decoding circuit includes B sub-circuits, each of the B sub-circuits includes an operation unit and a path metric circuit; The second decoding circuit is configured to decode a result of the first g operation circuit to obtain an estimated value of the second information bit, including: The operation unit of the i-th sub-circuit is used to determine the probability distribution of the i-th second information bit among the B second information bits; the i-th sub-circuit is the i-th sub-circuit among the B sub-circuits; The path metric circuit of the i-th sub-circuit is configured to receive a path metric value of an i-th decoding path, and determine an estimated value of the i-th second information bit based on the path metric value of the i-th decoding path and a probability distribution of the i-th second information bit; the i-th decoding path indicates a value of a bit preceding the i-th second information bit in the encoded sequence; Wherein, i is any positive integer less than or equal to B.

16. The device according to claim 15, characterized in that B=3; the bit preceding the first second information bit is a first frozen bit; the second decoding circuit is used to decode the result of the first g operation circuit to obtain an estimated value of the second information bit, including: a first operation unit, configured to receive and process the value of the first frozen bit and the result of the first g operation circuit to obtain a probability distribution of the first second information bit; the first operation unit is an operation unit of the first sub-circuit; a first path metric circuit, configured to receive a path metric value of a first decoding path, and determine an estimated value of the first second information bit based on the path metric value of the first decoding path and a probability distribution of the first second information bit; the first decoding path indicates a value of a bit preceding the first second information bit; the first path metric circuit is a path metric circuit of the first sub-circuit; a second operation unit, configured to receive and process the estimated value of the first second information bit and the result of the first g operation circuit to obtain a probability distribution of the second second information bit; the second operation unit is an operation unit of the second sub-circuit; a second path metric circuit, configured to receive a path metric value of a second decoding path, and determine an estimated value of the second second information bit based on the path metric value of the second decoding path and a probability distribution of the second second information bit; the second decoding path indicates a value of a bit preceding the second second information bit; the second path metric circuit is the path metric circuit of the second sub-circuit; a third operation unit, configured to receive and process the estimated values ​​of the first second information bit and the second second information bit and the result of the first g operation circuit to obtain a probability distribution of the third second information bit; the third operation unit is an operation unit of the third sub-circuit; A third path metric circuit is configured to receive a path metric value of a third decoding path, and determine an estimated value of the third second information bit based on the path metric value of the third decoding path and the probability distribution of the third second information bit; the third decoding path indicates the value of the bit preceding the third second information bit; the third path metric circuit is the path metric circuit of the third sub-circuit.

17. The device according to claim 14 or 16, characterized in that The first operation unit includes a second f operation circuit, a third f operation circuit, and a fifth g operation circuit; the first operation unit is configured to receive and process the value of the first frozen bit and the result of the first g operation circuit, including: The second f operation circuit is configured to receive a second signal and perform an f operation on the second signal; the second signal is a part of the result of the first g operation circuit; The third f operation circuit is configured to receive a third signal and perform an f operation on the second signal; the third signal is a signal other than the second signal in the result of the first g operation circuit; The fifth g operation circuit is further configured to perform a g operation on the value of the first frozen bit, the result of the first f operation circuit, and the result of the second f operation circuit to obtain a processing result of the first operation unit.

18. The device according to claim 14 or 16, characterized in that The second operation unit includes a sixth g operation circuit, a seventh g operation circuit, and a fourth f operation circuit; the second operation unit is configured to receive and process the estimated value of the first second information bit and the result of the first g operation circuit, including: The sixth g operation circuit is configured to perform a g operation on the estimated value of the first information bit and a second signal; the second signal is a part of the result of the first g operation circuit; The seventh g operation circuit is configured to perform a g operation on the estimated value of the first information bit and a third signal; the third signal is a signal other than the second signal in the result of the first g operation circuit; The fourth f operation circuit is used to perform f operation on the result of the sixth g operation circuit and the result of the seventh g operation circuit to obtain the processing result of the second operation unit.

19. The device according to claim 14 or 16, characterized in that The third operation unit includes a sixth g operation circuit, a seventh g operation circuit and an eighth g operation circuit; The third operation unit is configured to receive and process the estimated values ​​of the first second information bit and the second second information bit and the result of the first g operation circuit, including: The sixth g operation circuit is configured to perform a g operation on the estimated value of the first information bit and a second signal; the second signal is a portion of a result of the first g operation circuit; The seventh g operation circuit is configured to perform a g operation on the estimated value of the first information bit and a third signal; the third signal is a signal other than the second signal in the result of the first g operation circuit; The eighth g operation circuit is used to perform a g operation on the estimated value of the second second information bit, the result of the sixth g operation circuit and the result of the seventh g operation circuit to obtain the processing result of the third operation unit.

20. An encoding device, characterized in that: include: a processing module, configured to encode a sequence to be encoded to obtain an encoded sequence; wherein the sequence to be encoded includes at least one sub-block, and the at least one sub-block includes a first sub-block; each bit corresponding to the first sub-block is a frozen bit, or each bit corresponding to the first sub-block is an information bit; The transceiver module is used to send the encoded sequence.

21. A decoding method, characterized in that: include: Analog circuit; wherein, The analog circuit obtains an analog signal; the analog signal is determined by the decoding device according to the received coded sequence, the coded sequence is the sequence after the sequence to be coded is coded, and the length of the sequence to be coded is N, N=2 n , n is a positive integer; The analog circuit decodes the analog signal to obtain a decoding result.

22. A coding method, characterized in that include: The encoding device encodes a sequence to be encoded to obtain an encoded sequence; wherein the sequence to be encoded includes at least one sub-block, and the at least one sub-block includes a first sub-block; each bit corresponding to the first sub-block is a frozen bit, or each bit corresponding to the first sub-block is an information bit; The encoding device sends the encoded sequence.

23. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a program, and when the program is called by the processor, the decoding device executes the method according to claim 21, or the encoding device executes the method according to claim 22.

24. A computer program product comprising instructions, characterized in that When the computer program product is called by a processor, the decoding device executes the method according to claim 21, or the encoding device executes the method according to claim 22.

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