Display panel and display device

Abstract

The invention relates to the technical field of display, and discloses a display panel and a display device.An array substrate of the display panel comprises a first substrate, a semiconductor layer, a first metal layer and a second metal layer; each sub-pixel comprises a thin film transistor and a pixel electrode; the active part of the thin film transistor is electrically connected with the first electrode of the thin film transistor through the first via hole, and the first electrode of the thin film transistor is electrically connected with the data line; the third metal layer between the first substrate and the semiconductor layer comprises a plurality of first shading parts; at the first via hole, the orthographic projection of the first via hole on the first substrate is at least located in the orthographic projection range of the first shading part on the first substrate, the orthographic projection of the first via hole on the first substrate is a first projection, the orthographic projection of the first shading part on the first substrate is a second projection, and the edge of the second projection half surrounds the edge of the first projection. The display device comprises the display panel. According to the invention, the requirements of high transmittance and high contrast can be considered, and the overall display effect is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of display technologies, and particularly to a display panel and a display device. Background Art

[0002] Liquid Crystal Displays (LCDs) have been increasingly widely used in the display field due to advantages such as low power consumption, miniaturization, and lightness and thinness. With the development of human-computer interaction technologies, display devices with touch functions have been favored by consumers, such as mobile phones, tablet computers, and laptop computers with touch functions. In existing LCD display devices, thin-film transistors (TFTs) are generally used as switching devices in pixel units to control the opening and closing of pixel electrodes. The source and drain electrodes in the TFT are connected through vias. However, due to reasons such as metal diffraction and scattering, there will be light leakage at the via positions in the metal material layer. Especially with the increasing maturity of technologies such as in-vehicle displays, customers' specifications for contrast are becoming more and more stringent. To improve the contrast, it is necessary to increase the white state brightness or reduce the dark state brightness.

[0003] The prior art cannot balance the requirements of high transmittance and high contrast. If the panel design compresses the device and the light-shielding black matrix to increase the aperture ratio, once the alignment ability between the color filter substrate and the array substrate is poor, it is easy to shift, resulting in the metal on the array substrate side being exposed in the opening area defined by the black matrix on the color filter substrate. The black matrix layer cannot completely block the metal light leakage at the via, resulting in serious metal light leakage in the dark state, and then the contrast cannot meet the high requirements of customers. If, in order to improve the contrast, the light-shielding area of the black matrix is increased, that is, the metal light leakage phenomenon is improved at the expense of the aperture ratio, it will affect the transmittance of the display device.

[0004] Therefore, providing a display panel and a display device that can compress the area of the light-shielding black matrix as much as possible, achieve high transmittance, and effectively reduce light leakage in the dark state and improve the product contrast is a technical problem that needs to be urgently solved by those skilled in the art. Summary of the Invention

[0005] To solve the above technical problems, the present disclosure provides a display panel and a display device to solve the problem that high transmittance and high contrast in existing display devices cannot be well balanced, affecting the display effect.

[0006] The present disclosure provides a display panel, including an array substrate and a counter substrate disposed opposite to each other; the array substrate includes a first substrate and a semiconductor layer, a first metal layer, and a second metal layer located on a side of the first substrate facing the counter substrate;

[0007] The display panel includes a plurality of sub-pixels, a plurality of scan lines, and a plurality of data lines. The scan lines and the data lines cross and insulate from each other to define the area where the sub-pixels are located;

[0008] The sub-pixel includes a thin-film transistor and a pixel electrode that are electrically connected; the scan line is located in the first metal layer, the active part of the thin-film transistor is located in the semiconductor layer, and the first and second electrodes of the thin-film transistor and the data line are located in the second metal layer;

[0009] The active part of the thin-film transistor is electrically connected to the first electrode of the thin-film transistor through a first via hole. The first electrode of the thin-film transistor is electrically connected to the data line, and the second electrode of the thin-film transistor is electrically connected to the pixel electrode;

[0010] A third metal layer is further included between the first substrate and the semiconductor layer. The third metal layer includes a plurality of first light-shielding parts; at the first via hole, the orthographic projection of the first via hole on the first substrate is at least within the orthographic projection range of the first light-shielding part on the first substrate;

[0011] The orthographic projection of the first via hole on the first substrate is the first projection, and the orthographic projection of the first light-shielding part on the first substrate is the second projection. The edge of the second projection semi-surrounds the edge of the first projection.

[0012] Based on the same inventive concept, the present disclosure also provides a display device, which includes the above display panel.

[0013] The technical solution provided by the embodiments of the present disclosure has the following advantages compared with the prior art:

[0014] The display panel of the present disclosure is provided with a third metal layer between the first substrate and the semiconductor layer. The third metal layer includes a plurality of first light-shielding portions. The first light-shielding portion is provided at the first via where metal light leakage is serious in the dark state display. The orthographic projection of the first via on the first substrate is the first projection, and the orthographic projection of the first light-shielding portion on the first substrate is the second projection. The edge of the second projection semi-surrounds the edge of the first projection, that is, the second projection does not completely surround the first projection. Instead, only part of the entire edge of the second projection surrounds the outer circle of the edge of the first projection, and the other part of the entire edge of the second projection coincides or is similar to coincide with part of the edge of the first projection. It can not only block the metal light leakage at the first via through the first light-shielding portion, ensure the light-shielding effect, and improve the contrast in the dark state display as much as possible. Moreover, the edge of the second projection formed by the first light-shielding portion only semi-surrounds the edge of the first projection formed by the first via. Compared with the light-shielding structure in the prior art, in order to ensure the light-shielding performance, it generally completely covers the via and completely surrounds the periphery of the via. The present disclosure not only does not need to widen the light-shielding width of the black matrix layer on the counter substrate side, nor does it need to greatly increase the area of the first light-shielding portion at the first via, which can minimize the area of the opening region sacrificed by the sub-pixels, and thus can improve the dark state metal light leakage phenomenon. And because the pixel density in the existing liquid crystal display panel is relatively high, the opening area of a single sub-pixel is relatively small. Therefore, the present disclosure sacrifices as little area of the opening region of the sub-pixels as possible to solve the metal light leakage problem at the first via, so that the sub-pixels in the display panel can still maintain a relatively high aperture ratio, making it have better display performance, and can balance the requirements of high transmittance and high contrast, and improve the overall display effect of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The drawings here are incorporated into the specification and constitute a part of this specification, showing embodiments consistent with the present disclosure, and are used together with the specification to explain the principles of the present disclosure.

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, for those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0017] Figure 1 It is a schematic plan view of a display panel provided by an embodiment of the present disclosure;

[0018] Figure 2 is Figure 1 a partial enlarged view of the J1 region in

[0019] Figure 3 is Figure 2A partial enlarged schematic diagram of region J2 in

[0020] Figure 4 is Figure 2 A schematic cross-sectional structure diagram in the A-A' direction in

[0021] Figure 5 is Figure 2 A schematic cross-sectional structure diagram in the B-B' direction in

[0022] Figure 6 A display simulation diagram after increasing the light-shielding area of the black matrix layer on the counter substrate side in a certain prior art project;

[0023] Figure 7 A display simulation diagram after compressing the light-shielding area of the black matrix layer on the counter substrate side in a certain prior art project;

[0024] Figure 8 is Figure 2 and Figure 3 A schematic diagram of the orthographic projection of the first via hole and the first light-shielding part on the plane of the first substrate;

[0025] Figure 9 is Figure 2 and Figure 3 Another schematic diagram of the orthographic projection of the first via hole and the first light-shielding part on the plane of the first substrate;

[0026] Figure 10 is Figure 2 and Figure 3 Another schematic diagram of the orthographic projection of the first via hole and the first light-shielding part on the plane of the first substrate;

[0027] Figure 11 is Figure 2 and Figure 3 Another schematic diagram of the orthographic projection of the first via hole and the first light-shielding part on the plane of the first substrate;

[0028] Figure 12 is Figure 2 and Figure 3 Another schematic diagram of the orthographic projection of the first via hole and the first light-shielding part on the plane of the first substrate;

[0029] Figure 13 is Figure 2 and Figure 3 Another schematic diagram of the orthographic projection of the first via hole and the first light-shielding part on the plane of the first substrate;

[0030] Figure 14 is Figure 2 Another partial enlarged schematic diagram of region J2 in

[0031] Figure 15 is Figure 2 Another partial enlarged schematic diagram of region J2 in

[0032] Figure 16 is Figure 2 Another partial enlarged schematic diagram of region J2 in

[0033] Figure 17 is Figure 2 Another partial enlarged schematic diagram of region J2 in

[0034] Figure 18 is Figure 1 Another partial enlarged schematic diagram of region J1 in

[0035] Figure 19 is Figure 18 A schematic diagram of a sectional structure in the C-C' direction in

[0036] Figure 20 is Figure 1 Another partial enlarged schematic diagram of region J1 in

[0037] Figure 21 is Figure 20 A partial enlarged schematic diagram of region J3 in

[0038] Figure 22 is Figure 20 A schematic diagram of a sectional structure in the D-D' direction in

[0039] Figure 23 is Figure 20 A schematic diagram of a sectional structure in the E-E' direction in

[0040] Figure 24 is Figure 20 A schematic diagram of the orthographic projection of the first via hole, the first light-shielding portion, the second via hole, and the second light-shielding portion on the plane where the first substrate is located in

[0041] Figure 25 is Figure 1 Another partial enlarged schematic diagram of region J1 in

[0042] Figure 26 is Figure 25 A schematic diagram of a sectional structure in the F-F' direction in

[0043] Figure 27 is Figure 18 Another schematic diagram of a sectional structure in the C-C' direction in

[0044] Figure 28 is Figure 25 Another schematic diagram of a sectional structure in the F-F' direction in

[0045] Figure 29 It is a display simulation diagram under dark state display of a product in a certain prior art project;

[0046] Figure 30 It is a display simulation diagram under dark state display of a product in another prior art project;

[0047] Figure 31 It is Figure 1 Another partial enlarged schematic diagram of region J1 in

[0048] Figure 32 It is Figure 1 Another partial enlarged schematic diagram of region J1 in

[0049] Figure 33 It is a planar structure schematic diagram of the display device provided by an embodiment of the present disclosure. Detailed implementation manners

[0050] In order to more clearly understand the above objects, features and advantages of the present disclosure, the solutions of the present disclosure will be further described below. It should be noted that, without conflict, the embodiments of the present disclosure and the features in the embodiments may be combined with each other.

[0051] Many specific details are set forth in the following description in order to provide a thorough understanding of the present disclosure, but the present disclosure may be implemented in other ways different from those described herein; obviously, the embodiments in the specification are only a part of the embodiments of the present disclosure, rather than all the embodiments.

[0052] Please refer to Figures 1 - 5 , Figure 1 It is a planar structure schematic diagram of the display panel provided by an embodiment of the present disclosure, Figure 2 It is Figure 1 A partial enlarged schematic diagram of region J1 in Figure 3 It is Figure 2 A partial enlarged schematic diagram of region J2 in Figure 4 It is Figure 2 A cross-sectional structure schematic diagram in the A-A' direction in Figure 5 It is Figure 2 A cross-sectional structure schematic diagram in the B-B' direction in (it can be understood that, for clearly showing the structure of this embodiment, Figure 2 and Figure 3 are filled with transparency), the display panel 000 provided by this embodiment includes an array substrate 10 and a counter substrate 20 which are oppositely arranged; the array substrate 10 includes a first substrate 101 and a semiconductor layer 102, a first metal layer 103 and a second metal layer 104 located on one side of the first substrate 101 facing the counter substrate 20. The first substrate 101 is not filled in the figure;

[0053] The display panel 000 includes a plurality of sub-pixels 00, a plurality of scan lines G, and a plurality of data lines S. The scan lines G and the data lines S cross and insulate each other to define the area where the sub-pixels 00 are located;

[0054] The sub-pixel 00 includes a thin-film transistor 00T and a pixel electrode 00P that are electrically connected; the scan line G is located in the first metal layer 103, the active part 00TP of the thin-film transistor 00T is located in the semiconductor layer 102, the first pole 00TS and the second pole 00TD of the thin-film transistor 00T, and the data line S are located in the second metal layer 104;

[0055] The active part 00TP of the thin-film transistor 00T is electrically connected to the first pole 00TS of the thin-film transistor 00T through a first via K1. The first pole 00TS of the thin-film transistor 00T is electrically connected to the data line S, and the second pole 00TD of the thin-film transistor 00T is electrically connected to the pixel electrode 00P;

[0056] A third metal layer 105 is further included between the first substrate 101 and the semiconductor layer 102. The third metal layer 105 includes a plurality of first light-shielding parts 1051; at the first via K1, the orthographic projection of the first via K1 on the first substrate 101 is at least within the orthographic projection range of the first light-shielding part 1051 on the first substrate 101;

[0057] The orthographic projection of the first via K1 on the first substrate 101 is the first projection, and the orthographic projection of the first light-shielding part 1051 on the first substrate 101 is the second projection. The edge of the second projection semi-surrounds the edge of the first projection.

[0058] Specifically, the display panel 000 provided in this embodiment may be a liquid crystal display panel. The display panel 000 includes an array substrate 10 and a counter substrate 20 that are disposed opposite to each other. The array substrate 10 may be a substrate provided with structures such as thin-film transistors, pixel electrodes, and common electrodes. The counter substrate 20 may be a substrate provided with color filters and a black matrix layer. A liquid crystal layer 30 may be provided between the array substrate 10 and the counter substrate 20 (as Figure 4 shown). In some other alternative embodiments, the color filters and the black matrix layer may also be both disposed on one side of the array substrate 10. The counter substrate 20 may be a glass cover plate structure. The structure of the counter substrate 20 is not limited in this embodiment. During specific implementation, it can be selected according to actual needs. This embodiment and subsequent embodiments will take the counter substrate 20 as a substrate provided with color filters and a black matrix layer as an example for illustration.

[0059] As Figure 4As shown in the figure, the array substrate 10 of this embodiment includes a first substrate 101, a semiconductor layer 102, a first metal layer 103, and a second metal layer 104 located on the side of the first substrate 101 facing the counter substrate 20. Among them, the first substrate 101 is used as a carrier substrate for arranging other structures of the array substrate 10. The first substrate 101 can be made of hard materials such as glass or ceramics, and this embodiment does not limit this. The display panel 000 includes a plurality of sub-pixels 00, a plurality of scan lines G, and a plurality of data lines S. Optionally, as Figure 1 shown, in the display panel 000 of this embodiment, the scan lines G extend integrally along the first direction X, and the data lines S extend integrally along the second direction Y. The two cross and insulate to define the area where the sub-pixels 00 are located. It can be understood that the scan lines G extending integrally along the first direction X and the data lines S extending integrally along the second direction Y mean that the scan lines G and the data lines S can be curved or bent traces, but the overall extension direction of the scan lines G is the first direction X, and the overall extension direction of the data lines S is the second direction Y. The first direction X and the second direction Y are perpendicular to each other in the plane parallel to the first substrate 101. In subsequent embodiments, referring to the above explanations, the extension direction of the scan lines G is the first direction X and the extension direction of the data lines S is the second direction Y as an example, and no further description will be given. Each sub-pixel 00 includes a thin-film transistor 00T and a pixel electrode 00P connected electrically. The thin-film transistor 00T is used as a switching element of the sub-pixel 00. The semiconductor layer 102 of the array substrate 10 is used to arrange the active part 00TP of the thin-film transistor 00T; the first metal layer 103 of the array substrate 10 is located on the side of the semiconductor layer 102 away from the first substrate 101. The first metal layer 103 is used to arrange the scan lines G, and the first metal layer 103 can also be used to arrange the gate 00TG of the thin-film transistor 00T. At least part of the scan lines G can be reused as the gate 00TG of the thin-film transistor 00T (as Figure 4 shown), it can be understood that generally, a light-shielding structure matching the shape of the channel region is provided in the overlapping region between the gate and the active part of the thin-film transistor (as Figure 3A light-shielding structure is provided in the overlapping region between the gate 00TG of the thin-film transistor 00T and the active portion 00TP. This light-shielding structure (not labeled) is used to block the backlight rays in the channel region. In a liquid crystal display device, a backlight module needs to be provided on the side of the first substrate 101 of the display panel 000 away from the counter substrate 20 to provide a backlight source, that is, to block the light from the backlight module and prevent the light from irradiating within the channel region of the thin-film transistor 00T, reducing the photo-generated carriers in the active portion 00TP of the thin-film transistor 00T, thereby reducing the light leakage current of the thin-film transistor 00T, improving the conductivity of the thin-film transistor 00T, improving the display crosstalk phenomenon, and being beneficial to improving the display quality. The second metal layer 104 of the array substrate 10 is located on the side of the first metal layer 103 away from the first substrate 101. The second metal layer 104 is used to form the first electrode 00TS and the second electrode 00TD of the thin-film transistor 00T, and the data line S is located on the second metal layer 104. It can be understood that the first electrode 00TS of the thin-film transistor 00T can be one of the source electrode or the drain electrode, and the second electrode 00TD can be the other of the source electrode or the drain electrode. In this embodiment, an example is given where the first electrode 00TS is the source electrode of the thin-film transistor 00T and the second electrode 00TD is the drain electrode of the thin-film transistor 00T. The active portion 00TP (source electrode connection region of the active portion 00TP) of the thin-film transistor 00T is electrically connected to the first electrode 00TS of the thin-film transistor 00T through the first via K1, and the first electrode 00TS of the thin-film transistor 00T is electrically connected to the data line S. The active portion 00TP (drain electrode connection region of the active portion 00TP) of the thin-film transistor 00T can also be electrically connected to the second electrode 00TD of the thin-film transistor 00T, and the second electrode 00TD of the thin-film transistor 00T is electrically connected to the pixel electrode 00P. In this embodiment, a gate insulating layer 01 is included between the semiconductor layer 102 and the first metal layer 103. The gate insulating layer 01 can be made of a silicon nitride (SiNx) material or a silicon oxide (SiOx) material. An interlayer insulating layer 02 is provided between the first metal layer 103 and the second metal layer 104. The interlayer insulating layer 02 can be a multi-layer structure, that is, a nitride layer SIN containing silicon nitride (SiNx) and an oxide layer SIO containing silicon oxide (SiOx) can be alternately stacked. The active portion 00TP (source electrode connection region of the active portion 00TP) of the thin-film transistor 00T in the semiconductor layer 102 is electrically connected to the first electrode 00TS of the thin-film transistor 00T in the second metal layer 104 through the first via K1. The first via K1 can be understood as a via provided in the interlayer insulating layer 02.

[0060] It can be understood that in this embodiment Figure 2 the shape of the pixel electrode 00P is only schematic, and in actual implementation, it can be designed according to actual requirements. This embodiment does not limit this. Figure 2The layout shape, etc. of each sub-pixel 00 is only an example and does not represent the only layout structure during actual setting. During specific implementation, it can be set according to actual requirements and the layout structure of the liquid crystal display panel in related technologies, which will not be elaborated in this embodiment.

[0061] When the display panel 000 drives the display, after the thin film transistor 00T of the sub-pixel 00 is turned on under the control of the scan signal transmitted by the scan line G, the voltage on the data line S is transmitted to the second pole 00TD of the thin film transistor 00T through the first pole 00TS of the thin film transistor 00T to drive the pixel electrode 00P. The electric field formed by the voltage difference between the pixel electrode 00P and the common electrode 00C (as Figure 4 shown Figure 4 not filled in) can control the deflection of the liquid crystal in the liquid crystal layer 30 of each sub-pixel 00 region, thereby realizing the display of the picture of the display panel 000. It should be noted that the display principle of the display panel 000 will not be elaborated in this embodiment, and specific understanding can be referred to the driving and display principles of the liquid crystal display panel in related technologies.

[0062] It can be understood that in this embodiment Figure 4 the film layer where the common electrode 00C is located is on the side close to the first substrate 101 of the film layer where the pixel electrode 00P is located. During specific implementation, the film layer where the common electrode 00C is located can also be on the side away from the first substrate 101 of the film layer where the pixel electrode 00P is located, which is not limited in this embodiment.

[0063] In the prior art, in order to improve the contrast, conventionally, by increasing the light-shielding area (i.e., the light-shielding width) of the black matrix layer on the counter substrate side, that is, improving the metal light leakage phenomenon at the expense of the aperture ratio, as Figure 6 shown Figure 6 is a display simulation diagram after increasing the light-shielding area of the black matrix layer on the counter substrate side in a certain project of the prior art. Although the contrast has been improved, the transmittance of the display panel has decreased (the light transmittance is not high), that is, it has an impact on the transmittance of the display panel and affects the display effect. It can be understood that the transmittance mentioned in this embodiment is the light transmittance, which is a key index to measure the light penetration ability of the liquid crystal display, usually expressed in percentage. The higher its value, the more excellent the brightness and color expressiveness of the display. In the prior art, in order to improve the transmittance, usually, the light-shielding area (i.e., the light-shielding width) of the black matrix layer on the counter substrate side is compressed, as Figure 7 shown Figure 7It is a display simulation diagram after compressing the light-shielding area of the black matrix layer on the counter substrate side in a certain prior art project. Although the transmittance has been improved, once the alignment ability between the array substrate and the counter substrate is poor and alignment deviation occurs, the metal on the array substrate side is easily exposed in the opening area defined by the black matrix layer on the counter substrate. Especially, the black matrix layer cannot completely block the metal leakage at the via hole ( Figure 7 The LG positions marked in the regions of different color sub-pixels such as the red sub-pixel R, the green sub-pixel G, and the blue sub-pixel B of Figure 7 , that is, the light leakage positions are referred to Figures 2 - 4 the position of the first via hole K1 in Figures 2 - 4 ), resulting in serious metal leakage in the dark state and a significant decrease in contrast, which cannot meet the high requirements of customers and affects the display quality.

[0064] To solve the above problems, in this embodiment, the display panel 000 is further provided with a third metal layer 105, and the third metal layer 105 is located between the first substrate 101 and the semiconductor layer 102. The third metal layer 105 includes a plurality of first light-shielding portions 1051. At the first via hole K1, the orthographic projection of the first via hole K1 on the first substrate 101 is at least within the orthographic projection range of the first light-shielding portion 1051 on the first substrate 101, that is, the orthographic projection of the first light-shielding portion 1051 on the first substrate 101 covers the orthographic projection of the first via hole K1 on the first substrate 101. In this embodiment, the first light-shielding portion 1051 is only provided at the first via hole K1 where the metal leakage is serious in the dark state display. The orthographic projection of the first via hole K1 on the first substrate 101 is the first projection K1T, and the orthographic projection of the first light-shielding portion 1051 on the first substrate 101 is the second projection 1051T. The edge of the second projection 1051T semi-surrounds the edge of the first projection K1T, that is, the second projection 1051T does not completely surround the first projection K1T. Instead, only part of the edges of the entire edge of the second projection 1051T are surrounded by the outer edge of the first projection K1T, and the other part of the edges of the entire edge of the second projection 1051T coincides or is similar to coincide with part of the edges of the first projection K1T (theoretically coincide, but due to process differences, there may be process errors that do not completely coincide). As Figure 3 and Figure 8 shown, Figure 8 is Figure 2 and Figure 3 a schematic structural diagram of the orthographic projection of the first via hole and the first light-shielding portion 1051 on the plane where the first substrate 101 is located (for clear illustration, Figure 8Other structures are omitted, and only the front projection of the first light-shielding portion 1051 and the first via hole on the plane where the first substrate 101 is located is shown, and transparency filling is performed). Taking the shapes of the first projection K1T and the second projection 1051T as quadrilaterals as an example, the three side edges of the second projection 1051T are outside the edge of the first projection K1T, and the other edge of the second projection 1051T almost coincides with one edge of the first projection K1T. Optionally, the edge of the second projection 1051T surrounding the first projection K1T may include at least one of the left and right edges in the first direction X of the second projection 1051T. Since the positions where metal light leakage is likely to occur at the first via hole K1 are generally on the left and right sides of the first via hole K1 (the two sides along the first direction X are understood as the left and right sides), and there are black matrix layers provided on the side of the counter substrate 20 on both the upper and lower sides of the first via hole K1 (the two sides along the second direction Y are understood as the upper and lower sides), even if there is a slight offset in the position after the array substrate 10 and the counter substrate 20 are bonded, the light shielding of the black matrix layer in the second direction Y is not affected.

[0065] Therefore, in this embodiment, a first light-shielding portion 1051 is provided at the first via hole K1 where metal light leakage is serious under dark state display. The front projection of the first light-shielding portion 1051 on the first substrate 101 covers the front projection of the first via hole K1 on the first substrate 101, and the front projection of the first via hole K1 on the first substrate 101 is the first projection K1T, and the front projection of the first light-shielding portion 1051 on the first substrate 101 is the second projection 1051T. The edge of the second projection 1051T only semi-surrounds the edge of the first projection K1T. It can not only block the metal light leakage at the first via hole K1 through the first light-shielding portion 1051 to ensure the light-shielding effect and improve the contrast under dark state display as much as possible, but also the edge of the second projection 1051T formed by the first light-shielding portion 1051 only semi-surrounds the edge of the first projection K1T formed by the first via hole K1. Compared with the prior art light-shielding structure that generally completely covers the via hole and completely surrounds the periphery of the via hole to ensure the light-shielding performance, in this embodiment, it is not necessary to widen the light-shielding width of the black matrix layer on the side of the counter substrate 20, nor is it necessary to greatly increase the area of the first light-shielding portion 1051 at the first via hole K1. The edge of the second projection 1051T only semi-surrounds the edge of the first projection K1T, which can minimize the sacrificed aperture area of the sub-pixel 00, thereby improving the dark state metal light leakage phenomenon. And because the pixel density in the existing liquid crystal display panel is relatively high, the aperture area of a single sub-pixel 00 is already small. Therefore, in this embodiment, by sacrificing as little as possible the aperture area of the sub-pixel 00, the metal light leakage problem at the first via hole K1 is solved, so that the sub-pixel 00 in the display panel 000 can still maintain a relatively high aperture ratio, making it have better display performance, meeting the requirements of high transmittance and high contrast, and improving the overall display effect of the display panel 000.

[0066] It should be noted that the structure of the display panel is only exemplarily drawn in the figures of this embodiment. In actual implementation, the specific structure of the display panel includes but is not limited to this, and may also include other structures that can implement display functions or other functions such as touch functions. This embodiment will not elaborate here, and specific reference can be made to the structure of the liquid crystal display panel in the related art for understanding.

[0067] Optionally, in this embodiment, the third metal layer 105 is located between the semiconductor layer 102 and the first substrate 101. The third metal layer 105 may include other light-shielding structures, such as a light-shielding structure corresponding to the channel region of the thin-film transistor 00T (the region where the gate and the active part of the thin-film transistor overlap). This light-shielding structure is used to block the backlight light in the channel region (in a liquid crystal display device, a backlight module needs to be provided on the side of the first substrate 101 of the display panel 000 away from the counter substrate 20 to provide a backlight source), that is, to block the light from the backlight module and prevent the light from irradiating within the channel region of the thin-film transistor 00T, reducing the photo-generated carriers in the active part 00TP of the thin-film transistor 00T, thereby reducing the light leakage current of the thin-film transistor 00T, improving the conductivity of the thin-film transistor 00T, improving the display crosstalk phenomenon, and being beneficial to improving the display quality.

[0068] Optionally, in this embodiment, the first light-shielding portion 1051 is disposed on the third metal layer 105 that the display panel 000 generally includes. That is, in order to improve the conductivity of the thin-film transistor 00T, a metal light-shielding layer such as the third metal layer 105 of this embodiment is generally provided between the first substrate 101 and the semiconductor layer 102 in the display panel 000. Therefore, the first light-shielding portion 1051 of this embodiment is made by reusing the third metal layer 105 included in the display panel 000 itself. Without adding other film layers to the film layer structure of the array substrate 10 of the display panel 000, the improvement of the metal light leakage problem can be achieved, which is beneficial to improving the display quality while realizing the thin-type design of the overall panel.

[0069] In some alternative embodiments, please refer to Figures 1 - 5 、 Figure 8 and Figure 9 , Figure 9 is Figure 2 and Figure 3 Another schematic structural diagram of the orthographic projection of the first via hole and the first light-shielding portion on the plane of the first substrate (for clear illustration, Figure 9Other structures are omitted, and only the orthographic projection of the first light-shielding portion and the first via hole on the plane where the first substrate is located is shown, and transparency filling is performed). In this embodiment, along the extension direction of the scanning line G, that is, along the first direction X, the first projection K1T includes opposite first edge K1T1 and second edge K1T2. The first edge K1T1 faces the second pole 00TD of the thin film transistor 00T, and the second edge K1T2 is located on the side of the first edge K1T1 away from the second pole 00TD of the thin film transistor 00T; the second projection 1051T includes opposite third edge 1051T1 and fourth edge 1051T2. The third edge 1051T1 faces the second pole 00TD of the thin film transistor 00T, and the fourth edge 1051T2 is located on the side of the third edge 1051T1 away from the second pole 00TD of the thin film transistor 00T;

[0070] The maximum distance between the first edge K1T1 and the second edge K1T2 is D1, and the minimum distance between the third edge 1051T1 and the fourth edge 1051T2 is D2; wherein, D2 > D1.

[0071] In this embodiment, it is explained that the shape of the first projection K1T can be a square, or it can be a circle, a rectangle, an irregular shape, etc. The shape of the second projection 1051T can also be a square, or it can be a circle, a rectangle, an irregular shape, etc. This embodiment does not limit this. However, regardless of the shape of the orthographic projection of the first via K1 on the first substrate 101 and the orthographic projection of the first light-shielding portion 1051 on the first substrate 101, it is necessary to satisfy that the second projection 1051T formed by the first light-shielding portion 1051 covers the first projection K1T formed by the first via K1, and at the same time, the edge of the second projection 1051T formed by the first light-shielding portion 1051 only semi-surrounds the edge of the first projection K1T formed by the first via K1. Specifically, along the first direction X, which is the overall extension direction of the scan line G, regardless of the shape of the first projection K1T, it includes a first edge K1T1 facing the second pole 00TD of the thin film transistor 00T, and a second edge K1T2 located on the side of the first edge K1T1 away from the second pole 00TD of the thin film transistor 00T. Regardless of the shape of the second projection 1051T, it includes a third edge 1051T1 facing the second pole 00TD of the thin film transistor 00T, and a fourth edge 1051T2 located on the side of the third edge 1051T1 away from the second pole 00TD of the thin film transistor 00T. The maximum distance between the first edge K1T1 and the second edge K1T2 is D1. In the first direction X, the maximum distance between the first edge K1T1 and the second edge K1T2 refers to the distance between the point on the first edge K1T1 that is farthest from the second edge K1T2 and the point on the second edge K1T2 that is farthest from the first edge K1T1, which is D1; similarly, the minimum distance between the third edge 1051T1 and the fourth edge 1051T2 is D2. In the first direction X, the minimum distance between the third edge 1051T1 and the fourth edge 1051T2 refers to the distance between the point on the third edge 1051T1 that is closest to the fourth edge 1051T2 and the point on the fourth edge 1051T2 that is closest to the third edge 1051T1, which is D2 (as Figure 9 shown, taking the shapes of the first projection K1T and the second projection 1051T as non-square or non-rectangular as an example), and D2 is greater than D1. Thus, regardless of the shapes of the first projection K1T and the second projection 1051T, it can be ensured that in the first direction X, the minimum width of the first light-shielding portion 1051 is greater than the maximum width of the first via K1, thereby ensuring the light-shielding effect of the first light-shielding portion 1051 on the metal light leakage at the first via K1, and further improving the contrast and display quality in the dark state display.

[0072] Optionally, as Figures 1 - 5 、 Figure 8 and Figure 10 , Figure 10 is Figure 2 and Figure 3Another schematic structural diagram of the orthographic projection of the first via hole and the first light-shielding portion on the plane of the first substrate (for clear illustration, Figure 10 other structures are omitted in, and only the orthographic projection of the first light-shielding portion and the first via hole on the plane of the first substrate is shown and transparency filling is performed). In this embodiment, the maximum distance D1 between the first edge K1T1 and the second edge K1T2 is less than the minimum distance D2 between the third edge 1051T1 and the fourth edge 1051T2. Then, the third edge 1051T1 can be located on the side of the first edge K1T1 away from the second edge K1T2, and the fourth edge 1051T2 is flush with the second edge K1T2. Thus, while the second projection 1051T formed by the first light-shielding portion 1051 covers the first projection K1T formed by the first via hole K1, and the edge of the second projection 1051T formed by the first light-shielding portion 1051 only semi-surrounds the edge of the first projection K1T formed by the first via hole K1.

[0073] Further optionally, as Figures 1 - 5 、 Figure 8 and Figure 11 , Figure 11 is Figure 2 and Figure 3 Another schematic structural diagram of the orthographic projection of the first via hole K1 and the first light-shielding portion 1051 on the plane of the first substrate (for clear illustration, Figure 11 other structures are omitted in, and only the orthographic projection of the first light-shielding portion and the first via hole on the plane of the first substrate is shown and transparency filling is performed). As Figure 11 shown, since the counter substrate 20 of the display panel 000 generally includes a black matrix layer ( Figure 11 not shown in, reference can be made to Figure 5(Cross-sectional view of the side of the counter substrate 20), which is used to block the metal traces on the side of the array substrate 10. Therefore, along the second direction Y, at the corresponding position above the data line S, a black matrix layer extending along the second direction Y is generally provided in the counter substrate 20 to block the reflected light of the data line S. Therefore, even if the edges of the second projection 1051T are flush or substantially flush with the edges of the first projection K1T on both sides of the first via K1 in the second direction Y, the black matrix layer on the side of the counter substrate 20 can be used to block the possible light leakage on both sides of the first via K1 in the second direction Y. Therefore, in this embodiment, the third edge 1051T1 is located on the side of the first edge K1T1 away from the second edge K1T2, and the fourth edge 1051T2 is flush with the second edge K1T2. Thus, while satisfying that the second projection 1051 formed by the first light-shielding portion 1051 covers the first projection K1T formed by the first via K1, the edges of the second projection 1051T other than the third edge 1051T1 can be set to be substantially flush or substantially coincident with the edges of the first projection K1T other than the first edge K1T1. Thereby, the manufacturing material of the first light-shielding portion 1051 can be saved, the cost can be reduced, and the sub-pixels 00 in the display panel 000 can still maintain a relatively high aperture ratio. It can also prevent the edges of the first light-shielding portion 1051 on both sides of the first via K1 in the second direction Y from exceeding the edges of the first via K1 and affecting the transmittance of this area, which is beneficial to improving the display performance.

[0074] Reference Figure 7 As shown, the applicant found according to the simulation results that the metal light leakage phenomenon generally occurring at the first via K1 is manifested as unilateral light leakage. Therefore, the implementation manner as shown in Figure 11 can not only solve the problem of metal light leakage at the first via K1, but also save the manufacturing material of the first light-shielding portion 1051, reduce the cost, and the sub-pixels 00 in the display panel 000 can still maintain a relatively high aperture ratio. It can also prevent the edges of the first light-shielding portion 1051 on both sides of the first via K1 in the second direction Y from exceeding the edges of the first via K1 and affecting the transmittance of this area, which is beneficial to improving the transmittance of the sub-pixel 00 area and meeting the requirements of both high transmittance and high contrast, and enhancing the overall display effect of the display panel 000.

[0075] Optionally, as shown in Figures 1 - 5 and Figure 8As shown, in this embodiment, the maximum distance D1 between the first edge K1T1 and the second edge K1T2 is less than the minimum distance D2 between the third edge 1051T1 and the fourth edge 1051T2. Then, the fourth edge 1051T2 can be located on the side of the second edge K1T2 away from the first edge K1T1, and the third edge 1051T1 is flush with the first edge K1T1. Thus, it can also meet the requirement that the second projection 1051T formed by the first light-shielding portion 1051 covers the first projection K1T formed by the first via K1, and at the same time, the edge of the second projection 1051T formed by the first light-shielding portion 1051 only semi-surrounds the edge of the first projection K1T formed by the first via K1.

[0076] Further optionally, as Figures 1 - 5 , Figure 8 and Figure 12 , Figure 12 is Figure 2 and Figure 3 Another schematic structural diagram of the orthographic projection of the first via and the first light-shielding portion on the plane of the first substrate (for clear illustration, Figure 12 other structures are omitted in Figure 12 , and only the orthographic projection of the first light-shielding portion and the first via on the plane of the first substrate is shown and transparency filling is performed), as Figure 12 shown, since the counter substrate 20 of the display panel 000 generally includes a black matrix layer ( Figure 5(Cross-sectional view of the side of the counter substrate 20), which is used to block the metal traces on the side of the array substrate 10. Therefore, along the second direction Y, at the corresponding position above the data line S, a black matrix layer extending along the second direction Y is generally provided in the counter substrate 20 to block the reflected light of the data line S. Therefore, even if the edges of the second projection 1051T are flush or substantially flush with the edges of the first projection K1T on both sides of the first via K1 in the second direction Y, the black matrix layer on the side of the counter substrate 20 can be used to block the possible light leakage on both sides of the first via K1 in the second direction Y. Therefore, in this embodiment, the fourth edge 1051T2 can be located on the side of the second edge K1T2 away from the first edge K1T1, and the third edge 1051T1 is flush with the first edge K1T1. Thus, while satisfying that the second projection 1051 formed by the first light-shielding portion 1051 covers the first projection K1T formed by the first via K1, the edges of the second projection 1051 except the fourth edge 1051T2 and the edges of the first projection K1T except the second edge K1T2 can be set to be substantially flush or substantially coincident. Thereby, the manufacturing material of the first light-shielding portion 1051 can be saved, the cost can be saved, and the sub-pixels 00 in the display panel 000 can still maintain a relatively high aperture ratio. It can avoid the edges of the first light-shielding portion 1051 on both sides of the first via K1 in the second direction Y exceeding the edges of the first via K1 and affecting the transmittance of this area, which is beneficial to improving the display performance.

[0077] Reference Figure 7 As shown, the applicant found according to the simulation results that the metal light leakage phenomenon occurring at the first via K1 generally shows unilateral light leakage. Therefore, the embodiment as shown in Figure 12 can not only solve the problem of metal light leakage at the first via K1, but also save the manufacturing material of the first light-shielding portion 1051, save costs, and the sub-pixels 00 in the display panel 000 can still maintain a relatively high aperture ratio. It can avoid the edges of the first light-shielding portion 1051 on both sides of the first via K1 in the second direction Y exceeding the edges of the first via K1 and affecting the transmittance of this area, which is beneficial to improving the transmittance of the sub-pixel 00 area and meeting the requirements of both high transmittance and high contrast, and improving the overall display effect of the display panel 000.

[0078] Optionally, as shown in Figures 1 - 5 , Figure 8 and Figure 13 , Figure 13 is Figure 2 and Figure 3 Another schematic structural view of the front projection of the first via and the first light-shielding portion on the plane of the first substrate (for clear illustration, Figure 13Other structures are omitted, and only the orthographic projection of the first light-shielding portion and the first via hole on the plane of the first substrate is shown, and transparency filling is performed). In this embodiment, the maximum distance D1 between the first edge K1T1 and the second edge K1T2 is less than the minimum distance D2 between the third edge 1051T1 and the fourth edge 1051T2. Then, the third edge 1051T1 is located on the side of the first edge K1T1 away from the second edge K1T2, and the fourth edge 1051T2 is located on the side of the second edge K1T2 away from the first edge K1T1. At this time, it can be satisfied that the second projection 1051T formed by the first light-shielding portion 1051 covers the first projection K1T formed by the first via hole K1. And in order to make the edge of the second projection 1051T formed by the first light-shielding portion 1051 only semi-surround the edge of the first projection K1T formed by the first via hole K1, it can be set that the edges of the second projection 1051T other than the third edge 1051T1 and the fourth edge 1051T2 are substantially flush or substantially coincident with the edges of the first projection K1T other than the first edge K1T1 and the second edge K1T2. As Figure 13 shown, since the counter substrate 20 of the display panel 000 generally includes a black matrix layer ( Figure 13 not shown, reference can be made to Figure 5(Cross-sectional view of the side of the counter substrate 20), which is used to block the metal traces on the side of the array substrate 10. Therefore, along the second direction Y, at the corresponding position above the data line S, a black matrix layer extending along the second direction Y is generally provided in the counter substrate 20 to block the reflected light of the data line S. Therefore, even if the edges of the second projection 1051T are flush or substantially flush with the edges of the first projection K1T on both sides of the first via K1 in the second direction Y, the black matrix layer on the side of the counter substrate 20 can be used to block the possible light leakage on both sides of the first via K1 in the second direction Y. In this embodiment, the third edge 1051T1 is located on the side of the first edge K1T1 away from the second edge K1T2, and the fourth edge 1051T2 is located on the side of the second edge K1T2 away from the first edge K1T1, which can satisfy that the second projection 1051T formed by the first light-shielding portion 1051 covers the first projection K1T formed by the first via K1. At the same time, in order to make the edges of the second projection 1051T formed by the first light-shielding portion 1051 only semi-surround the edges of the first projection K1T formed by the first via K1, it can be set that the edges of the second projection 1051T other than the third edge 1051T1 and the fourth edge 1051T2 are substantially flush or substantially coincident with the edges of the first projection K1T other than the first edge K1T1 and the second edge K1T2. Thus, the manufacturing material of the first light-shielding portion 1051 can be saved, and while saving costs, the sub-pixels 00 in the display panel 000 can still maintain a relatively high aperture ratio, avoiding the edges of the first light-shielding portion 1051 on both sides of the first via K1 in the second direction Y from exceeding the edges of the first via K1 and affecting the transmittance of this area, which is beneficial to improving the display performance, and further solving the problem of metal light leakage at the first via K1, meeting the requirements of both high transmittance and high contrast, and improving the overall display effect of the display panel 000.

[0079] Optionally, as Figures 1 - 2 , Figure 14 shown, Figure 14 is Figure 2 another partial enlarged schematic diagram of the J2 area in Figure 2 (it can be understood that in order to clearly show the structure of this embodiment, Figure 14 the black matrix layer is not shown in Figure 14 and transparency filling is performed). In this embodiment, one side of the counter substrate 20 further includes a black matrix layer 201. The black matrix layer 201 includes a plurality of first light-shielding strips 2011 of the same layer and a plurality of second light-shielding strips (not shown in the figure). The first light-shielding strips 2011 and the second light-shielding strips are arranged crosswise to form a mesh structure. The extending direction of the first light-shielding strips 2011 is the same as the extending direction of the data line S, that is, it can be understood that the overall extending direction of the first light-shielding strips 2011 is the second direction Y, and the overall extending direction of the second light-shielding strips is the first direction X. As Figure 14As shown, even if the edges of the second projection 1051T on both sides of the first via K1 in the second direction Y are flush or substantially flush with the edges of the first projection K1T, the first light-shielding strip 2011 of the black matrix layer 201 on the side of the counter substrate 20 can be used to block the possible light leakage on both sides of the first via K1 in the second direction Y. Therefore, the first light-shielding portion 1051 only needs to consider the light-shielding effect on both sides of the first via K1 in the first direction X.

[0080] Optionally, as Figures 1 - 2 , Figure 15 shown, Figure 15 is Figure 2 another partial enlarged schematic diagram of the J2 region in Figure 2 (it can be understood that, for the sake of clearly showing the structure of this embodiment, Figure 15 the black matrix layer is not shown in

[0081] This embodiment explains that the second projection 1051T formed by the first light-shielding portion 1051 covers the first projection K1T formed by the first via K1 to ensure the improvement of the metal light leakage problem at the first via K1. At the same time, in order to make the edge of the second projection 1051T formed by the first light-shielding portion 1051 only semi-surround the edge of the first projection K1T formed by the first via K1 and improve the transmittance, it can be set that the second projection 1051T formed by the first light-shielding portion 1051 is only a single-sided outward expansion structure compared with the first projection K1T formed by the first via K1, that is, along the first direction X, the third edge 1051T1 of the second projection 1051T extends beyond the first edge K1T1 of the first projection K1T, while the other edges of the second projection 1051T are substantially flush or substantially coincident with the other edges of the first projection K1T. At this time, in order to ensure the light-shielding effect of the first light-shielding portion 1051 at the first via K1, it can be set that along the first direction X, the minimum distance D5 between the third edge 1051T1 and the edge of the data line S is 2 - 2.2 μm, that is, along the first direction X, the distance between the third edge 1051T1 and its nearest data line S edge is between 2 - 2.2 μm. Even when the array substrate 10 and the counter substrate 20 are aligned and packaged, and there is a slight misalignment in the first direction X, the two sides of the first light-shielding strip 2011 in the first direction X cannot provide good light shielding for the two sides of the first via K1, it can still ensure the light-shielding effect of the first light-shielding portion 1051 on the first via K1 in the first direction X. And the distance between the third edge 1051T1 and its nearest data line S edge is 2 - 2.2 μm along the first direction X, which can ensure that the outward expansion width of the first light-shielding portion 1051 in the first direction X is not too large to affect the transmittance of the display panel 000, and thus can balance the display effects of high transmittance and high contrast.

[0082] In some alternative embodiments, please refer to Figures 1 - 2 and Figure 16 as shown. Figure 16 It is Figure 2 another partial enlarged schematic diagram of the J2 region in Figure 2 (it can be understood that, for the sake of clearly showing the structure of this embodiment, Figure 16 the black matrix layer is not shown in

[0083] and transparency filling is performed). In this embodiment, one side of the counter substrate 20 further includes a black matrix layer 201. The black matrix layer 201 includes a plurality of first light-shielding strips 2011 of the same layer and a plurality of second light-shielding strips (not shown in the figure). The first light-shielding strips 2011 and the second light-shielding strips are cross-arranged to form a mesh structure. The extending direction of the first light-shielding strips 2011 is the same as the extending direction of the data lines S. That is, it can be understood that the overall extending direction of the first light-shielding strips 2011 is the second direction Y, and the overall extending direction of the second light-shielding strips is the first direction X.

[0084] This embodiment explains that the first light-shielding strips 2011 of the black matrix layer 201 can be understood as a structure having the same extending direction as the data lines S. That is, the first light-shielding strips 2011 can be understood as being disposed above the data lines S to block the reflection of the metal material of the data lines S and prevent the reflected light of the metal data lines S from affecting the display quality. Further, in this embodiment, at the position corresponding to the first via K1, the first light-shielding strip 2011 is provided with a first protrusion 20111 such that the orthographic projection of the first light-shielding portion 1051 on the first substrate 101 is within the orthographic projection range of the first protrusion 20111 on the first substrate 101. Since the first light-shielding portion 1051 is made of the third metal layer 105, that is, the first light-shielding portion 1051 also belongs to the metal material, the first light-shielding portion 1051 will be exposed outside the shielding range of the black matrix layer 201 after expanding outward in the first direction X. Therefore, in this embodiment, at the position corresponding to the first via K1, the first light-shielding strip 2011 is provided with a first protrusion 20111, that is, the first light-shielding strip 2011 also expands outward to a certain extent in the first direction X at the position of the first light-shielding portion 1051, that is, at the position of the first via K1, to form the first protrusion 20111, and the orthographic projection of the first light-shielding portion 1051 on the first substrate 101 is within the orthographic projection range of the first protrusion 20111 on the first substrate 101, so as to block the influence of the metal reflection of the first light-shielding portion 1051 on the display effect.

[0085] Optionally, at the position of the first via K1, the orthographic projection of the first light-shielding portion 1051 on the first substrate 101 is within the orthographic projection range of the first protruding portion 20111 on the first substrate 101. It may be that the orthographic projection of the first protruding portion 20111 on the first substrate 101 covers the orthographic projection of the first light-shielding portion 1051 on the first substrate 101, and the area of the orthographic projection of the first protruding portion 20111 on the first substrate 101 is larger than the area of the orthographic projection of the first light-shielding portion 1051 on the first substrate 101 (as Figure 16 shown), thereby ensuring the shielding effect of the first protruding portion 20111 of the first light-shielding strip 2011 on the reflected light of the first light-shielding portion 1051.

[0086] Alternatively, as Figures 1 - 2 , Figure 17 shown, Figure 17 is Figure 2 another partial enlarged schematic diagram of the J2 region in Figure 2 (it can be understood that, for the sake of clearly showing the structure of this embodiment, Figure 17 the black matrix layer is not shown in Figure 17 and transparency filling is performed). In some other alternative embodiments, it may be set that the orthographic projection of the first light-shielding portion 1051 on the first substrate 101 coincides with the orthographic projection of the first protruding portion 20111 on the first substrate 101, that is, the orthographic projection of the first protruding portion 20111 on the first substrate 101 covers the orthographic projection of the first light-shielding portion 1051 on the first substrate 101, and the area of the orthographic projection of the first protruding portion 20111 on the first substrate 101 is equal to the area of the orthographic projection of the first light-shielding portion 1051 on the first substrate 101 (as

[0087] shown). Thereby, while ensuring the shielding effect of the first protruding portion 20111 of the first light-shielding strip 2011 on the reflected light of the first light-shielding portion 1051, the layout area of the first light-shielding strip 2011, that is, the black matrix layer 201, can be reduced, which is beneficial to improving the transmittance of the display panel 000. Figure 16 and Figure 17 in this embodiment only show the setting structure of the first protruding portion 20111 of the first light-shielding strip 2011 when the first light-shielding portion 1051 extends outward unilaterally on the right side in the first direction X. In specific implementation, if the first light-shielding portion 1051 extends outward bilaterally on both the left and right sides in the first direction X, the setting structure of the first protruding portion 20111 of the first light-shielding strip 2011 can also change with the shape of the first light-shielding portion 1051, as long as it satisfies that at the position of the first via K1, the orthographic projection of the first light-shielding portion 1051 on the first substrate 101 is within the orthographic projection range of the first protruding portion 20111 on the first substrate 101, and the metal reflection effect of the first light-shielding portion 1051 can be blocked.

[0088] In some alternative embodiments, please continue to refer toFigure 1 , Figure 18 and Figure 19 , Figure 18 is Figure 1 Another partial enlarged schematic view of region J1 in Figure 19 is Figure 18 A schematic cross-sectional structure view in the C-C' direction in (It can be understood that, for clearly showing the structure of this embodiment, Figure 18 transparency filling is performed). In this embodiment, the shape of the orthographic projection of the active portion 00TP of the thin film transistor 00T on the first substrate 101 is L-shaped. It can be understood that, in this embodiment, the shape of the orthographic projection of the active portion 00TP of the thin film transistor 00T on the first substrate 101 may be that the overall shape of the active portion 00TP presents an L-shape, and it does not mean that the shape of the orthographic projection of the active portion 00TP of the thin film transistor 00T on the first substrate 101 is a standard L-shape (as Figure 2 shown).

[0089] Optionally, the active portion 00TP of the thin film transistor 00T is electrically connected to the second pole 00TD of the thin film transistor 00T through a second via K2;

[0090] The third metal layer 105 further includes a plurality of second light-shielding portions 1052 and a plurality of third light-shielding portions 1053;

[0091] At the second via K2, the orthographic projection of the second via K2 on the first substrate 101 is at least located within the orthographic projection range of the second light-shielding portion 1052 on the first substrate 101;

[0092] The orthographic projection of the third light-shielding portion 1053 on the first substrate 101 covers the orthographic projection of the channel region of the thin film transistor 00T on the first substrate 101;

[0093] The first light-shielding portion 1051, the second light-shielding portion 1052, and the third light-shielding portion 1053 are respectively independent structures.

[0094] This embodiment explains that the third metal layer 105 is located between the semiconductor layer 102 and the first substrate 101. The third metal layer 105 may include other light-shielding structures, such as a third light-shielding portion 1053 corresponding to the channel region of the thin-film transistor 00T (the region formed by the overlap of the gate and the active portion of the thin-film transistor). The third light-shielding portion 1053 is used to block the backlight light of the channel region (in a liquid crystal display device, a backlight module needs to be provided on the side of the first substrate 101 of the display panel 000 away from the counter substrate 20 to provide a backlight source), that is, to block the light from the backlight module and prevent the light from irradiating within the channel region of the thin-film transistor 00T, reducing the photo-generated carriers of the active portion 00TP of the thin-film transistor 00T. Thus, the light leakage current of the thin-film transistor 00T due to light irradiation can be reduced, the conductivity of the thin-film transistor 00T can be improved, the display crosstalk phenomenon can be improved, and it is beneficial to improve the display quality. The third metal layer 105 may further include other light-shielding structures. For example, at the second via K2, the positive projection of the second light-shielding portion 1052 on the first substrate 101 covers the positive projection of the second via K2 on the first substrate 101. By providing the second light-shielding portion 1052, the metal light leakage problem at the second via K2 can be improved, and further, it is beneficial to further improve the display contrast.

[0095] Since the shape of the positive projection of the active portion 00TP of the thin-film transistor 00T in this embodiment on the first substrate 101 as a whole presents an L shape, the layout positions of the first via K1, the channel region of the thin-film transistor 00T, and the second via K2 are relatively scattered in the direction parallel to the plane where the display panel 000 is located. Therefore, for the region where the same sub-pixel 00 is located, the first light-shielding portion 1051, the second light-shielding portion 1052, and the third light-shielding portion 1053 provided by the third metal layer 105 can be independent structures, avoiding the problem that the integrated first light-shielding portion 1051, second light-shielding portion 1052, and third light-shielding portion 1053 cause too large a metal light-shielding area and affecting the aperture ratio of the sub-pixel 00. Further, it is beneficial to improve the overall transmittance of the panel and ensure the display quality.

[0096] It can be understood that in the drawings of this embodiment and the above embodiments, the shape of the positive projection of the active portion 00TP of the thin-film transistor 00T on the first substrate 101 as a whole presents an L shape as an example for illustration. In actual implementation, the shape of the positive projection of the active portion 00TP of the thin-film transistor 00T on the first substrate 101 may also present other shapes as a whole, such as a large U shape or a small U shape, etc. This embodiment does not limit this, and in actual implementation, it can be set according to the actual requirements of the display panel 000.

[0097] In some alternative embodiments, please refer to Figure 1 、 Figures 20 - 23 , Figure 20 is Figure 1Another partial enlarged schematic diagram of region J1 in the middle Figure 21 is Figure 20 A partial enlarged schematic diagram of region J3 in the middle Figure 22 is Figure 20 A schematic cross-sectional structure diagram in the D-D' direction in the middle Figure 23 is Figure 20 A schematic cross-sectional structure diagram in the E-E' direction in the middle (it can be understood that, for clearly showing the structure of this embodiment, Figure 20 and Figure 21 transparency filling is performed). In this embodiment, the shape of the orthographic projection of the active part 00TP of the thin film transistor 00T on the first substrate 101 is U-shaped.

[0098] This embodiment explains that the design of the thin film transistor 00T provided on the array substrate 10 side in the display panel 000 can be that the shape of the orthographic projection of the active part 00TP of the thin film transistor 00T on the first substrate 101 is U-shaped. The thin film transistor 00T has two gate electrodes 00TG. The thin film transistor 00T has the advantages of high input impedance, low voltage-controlled power consumption, simple control circuit, high voltage resistance, large current-carrying capacity, etc. Moreover, since the shape of the orthographic projection of the active part 00TP of the thin film transistor 00T on the first substrate 101 is U-shaped, the entire structure of the thin film transistor 00T can be compressed to the maximum extent in the sub-pixel 00 region, so that the layout positions of the first via hole K1, the channel region of the thin film transistor 00T, and the second via hole K2 are relatively concentrated in the direction parallel to the plane where the display panel 000 is located, which is beneficial to improving the transmittance of the display panel 000.

[0099] It can be understood that this embodiment does not limit the shape of the orthographic projection of the active part 00TP of the thin film transistor 00T on the first substrate 101. And no matter what shape it is, it satisfies that at the first via hole K1, the orthographic projection of the first via hole K1 on the first substrate 101 is at least located within the orthographic projection range of the first light-shielding part 1051 on the first substrate 101. And the orthographic projection of the first via hole K1 on the first substrate 101 is the first projection, and the orthographic projection of the first light-shielding part 1051 on the first substrate 101 is the second projection. The edge of the second projection semi-surrounds the edge of the first projection, meeting the requirements of both high transmittance and high contrast, and improving the overall display effect of the display panel 000. When the shape of the orthographic projection of the active part 00TP of the thin film transistor 00T on the first substrate 101 is U-shaped, the setting of the first light-shielding part 1051 can be understood and set with reference to any of the above embodiments, and this embodiment will not elaborate here.

[0100] Optionally, as Figure 1 、 Figures 20 - 23 、 Figure 24 shown, Figure 24 is Figure 20A schematic diagram of the orthographic projection of the first via hole and the first light-shielding portion, the second via hole and the second light-shielding portion on the plane where the first substrate is located (it can be understood that, for the sake of clearly showing the structure of this embodiment, Figure 20 the black matrix layer is not shown in the figure, Figure 24 transparency filling is performed, Figure 24 other structures are omitted in the figure, and only the orthographic projection of the first light-shielding portion and the first via hole on the plane where the first substrate is located, and the orthographic projection of the second light-shielding portion and the second via hole on the plane where the first substrate is located are shown). In this embodiment, the third metal layer 105 further includes a plurality of second light-shielding portions 1052;

[0101] The active portion 00TP of the thin-film transistor 00T is electrically connected to the second pole 00TD of the thin-film transistor 00T through the second via hole K2, and the orthographic projection of the second via hole K2 on the first substrate 101 is within the orthographic projection range of the second light-shielding portion 1052 on the first substrate 101;

[0102] The orthographic projection of the second via hole K2 on the first substrate 101 is the third projection K2T, and the orthographic projection of the second light-shielding portion 1052 on the first substrate 101 is the fourth projection 1052T;

[0103] Along the extension direction of the scan line G, that is, along the first direction X, the first projection K1T includes a fifth edge K1T3 on the side away from the third projection K2T, the third projection K2T includes a sixth edge K2T1 on the side away from the first projection K1T, the second projection 1051T includes a seventh edge 1051T3 on the side away from the fourth projection 1052T, and the fourth projection 1052T includes an eighth edge 1052T1 on the side away from the second projection 1051T;

[0104] The maximum distance between the fifth edge K1T3 and the sixth edge K2T1 is D3, and the minimum distance between the seventh edge 1051T3 and the eighth edge 1052T1 is D4; among them, D4 > D3.

[0105] Further optionally, D4 - D3 ≤ 1 μm.

[0106] This embodiment explains that the active portion 00TP of the thin-film transistor 00T is electrically connected to the second pole 00TD of the thin-film transistor 00T through the second via hole K2, and metal light leakage may also occur at the second via hole K2. Therefore, a second light-shielding portion 1052 can be further provided in the third metal layer 105, so that the orthographic projection of the second via hole K2 on the first substrate 101 is within the orthographic projection range of the second light-shielding portion 1052 on the first substrate 101, and the problem of metal light leakage at the second via hole K2 is improved through the second light-shielding portion 1052.

[0107] In this embodiment, it is also set that if the orthographic projection of the second via K2 on the first substrate 101 is named the third projection K2T, and the orthographic projection of the second light-shielding portion 1052 on the first substrate 101 is named the fourth projection 1052T, then along the extension direction of the scan line G, that is, along the first direction X, the first projection K1T includes a fifth edge K1T3 on the side away from the third projection K2T, the third projection K2T includes a sixth edge K2T1 on the side away from the first projection K1T, the second projection 1051T includes a seventh edge 1051T3 on the side away from the fourth projection 1052T, the fourth projection 1052T includes an eighth edge 1052T1 on the side away from the second projection 1051T, and the maximum distance D3 between the fifth edge K1T3 and the sixth edge K2T1 is less than the minimum distance D4 between the seventh edge 1051T3 and the eighth edge 1052T1;

[0108] In the first direction X, the maximum distance between the fifth edge K1T3 and the sixth edge K2T1 refers to the distance D3 between the point on the fifth edge K1T3 that is farthest from the sixth edge K2T1 and the point on the sixth edge K2T1 that is farthest from the fifth edge K1T3; similarly, in the first direction X, the minimum distance between the seventh edge 1051T3 and the eighth edge 1052T1 refers to the distance D4 between the point on the seventh edge 1051T3 that is closest to the eighth edge 1052T1 and the point on the eighth edge 1052T1 that is closest to the seventh edge 1051T3 (as Figure 24 shown, taking the shapes of the first projection K1T, the second projection 1051T, the third projection K2T, and the fourth projection 1052T as squares as an example), and D4 is greater than D3. Thus, regardless of the shapes of the first projection K1T, the second projection 1051T, the third projection K2T, and the fourth projection 1052T, it can be ensured that in the first direction X, the minimum width of the first light-shielding portion 1051 is greater than the maximum width of the first via K1, and the minimum width of the second light-shielding portion 1052 is greater than the maximum width of the second via K2. Furthermore, the light-shielding effect of the first light-shielding portion 1051 on the metal light leakage at the first via K1 and the light-shielding effect of the second light-shielding portion 1052 on the metal light leakage at the second via K2 can be guaranteed, further improving the contrast and display quality in the dark state display.

[0109] Further optionally, as Figure 1 、 Figures 20 - 23 、 Figure 24As shown, along the first direction X, the first projection K1T includes a fifth edge K1T3 on a side away from the third projection K2T, the third projection K2T includes a sixth edge K2T1 on a side away from the first projection K1T, the second projection 1051T includes a seventh edge 1051T3 on a side away from the fourth projection 1052T, the fourth projection 1052T includes an eighth edge 1052T1 on a side away from the second projection 1051T. The maximum distance D3 between the fifth edge K1T3 and the sixth edge K2T1 is less than the minimum distance D4 between the seventh edge 1051T3 and the eighth edge 1052T1, and D4 - D3 ≤ 1 μm. Thus, while ensuring the light-shielding effect of the first light-shielding portion 1051 at the first via K1 and the light-shielding effect of the second light-shielding portion 1052 at the second via K2, it is also possible to prevent the widths of the first light-shielding portion 1051 and the second light-shielding portion 1052 in the first direction X from being too large and affecting the transmittance of the display panel 000, thereby achieving a display performance that takes into account both high contrast and high transmittance.

[0110] In some alternative embodiments, please continue to refer to Figure 1 、 Figures 20 - 23 , in this embodiment, the third metal layer 105 further includes a plurality of third light-shielding portions 1053;

[0111] The orthographic projection of the channel region of the thin-film transistor 00T on the first substrate 101 is within the orthographic projection range of the third light-shielding portion 1053 on the first substrate 101.

[0112] The third light-shielding portion 1053 is used to block the backlight light of the channel region (in a liquid crystal display device, a backlight module needs to be provided on a side of the first substrate 101 of the display panel 000 away from the counter substrate 20 to provide a backlight source), that is, to block the light from the backlight module and prevent the light from irradiating within the channel region range of the thin-film transistor 00T, reducing the photo-generated carriers of the active portion 00TP of the thin-film transistor 00T. Thus, the light leakage current of the thin-film transistor 00T can be reduced, the conductivity of the thin-film transistor 00T can be improved, the display crosstalk phenomenon can be improved, and it is beneficial to improve the display quality.

[0113] Optionally, as shown in Figure 20 and Figure 22 , the first light-shielding portion 1051, the second light-shielding portion 1052, and the third light-shielding portion 1053 are respectively independent structures, so that the layout area of the third metal layer 105 can be minimized to the greatest extent, the transmittance of the display panel 000 can be maximally improved, and the display quality can be ensured.

[0114] Optionally, as shown in Figure 1 、 Figure 25 and Figure 26 , Figure 25 is Figure 1 Another partial enlarged schematic diagram of the J1 region inFigure 26 Yes Figure 25 It is a schematic cross-sectional structure diagram in the F-F' direction in Figure 25 (it can be understood that in order to clearly show the structure of this embodiment, Figure 25 transparency filling is performed). In this embodiment, the first light-shielding portion 1051, the second light-shielding portion 1052, and the third light-shielding portion 1053 are of an integral structure.

[0115] This embodiment explains that in the display panel 000, the shape of the orthographic projection of the active portion 00TP of the thin-film transistor 00T on the first substrate 101 is U-shaped, which can compress the entire structure of the thin-film transistor 00T to the maximum extent in the sub-pixel 00 region, so that the first via hole K1, the channel region of the thin-film transistor 00T, and the second via hole K2 are relatively concentrated in the direction parallel to the plane where the display panel 000 is located, which is beneficial to improving the transmittance of the display panel 000. At this time, the first light-shielding portion 1051 correspondingly provided at the first via hole K1, the second light-shielding portion 1052 correspondingly provided at the second via hole K2, and the third light-shielding portion 1053 correspondingly provided at the channel region of the thin-film transistor 00T can be an integral overall structure, that is, it can be understood that for a single sub-pixel 00, the first light-shielding portion 1051, the second light-shielding portion 1052, and the third light-shielding portion 1053 are an entire structure. Since the shape of the orthographic projection of the active portion 00TP of the thin-film transistor 00T on the first substrate 101 is designed as U-shaped, the positions of the first via hole K1, the channel region of the thin-film transistor 00T, and the second via hole K2 in the direction parallel to the plane where the display panel 000 is located are relatively concentrated, that is, the space size occupied by the entire thin-film transistor 00T is relatively small. Therefore, the first light-shielding portion 1051, the second light-shielding portion 1052, and the third light-shielding portion 1053 can be integrally provided for light shielding, which is beneficial to simplifying the manufacturing process steps, reducing the manufacturing process difficulty, and improving the manufacturing process efficiency.

[0116] In some alternative embodiments, please refer to Figures 1 - 5 , Figure 18 , Figures 20 - 26 and Figure 27 , Figure 28 . Figure 27 Yes Figure 18 It is another schematic cross-sectional structure diagram in the C-C' direction in Figure 18 , Figure 28 Yes Figure 25 It is another schematic cross-sectional structure diagram in the F-F' direction in Figure 25 . In this embodiment, the display panel 000 further includes a first conductive portion 00D1, and the first conductive portion 00D1 is in direct contact with the active portion 00TP of the thin-film transistor 00T within the first via hole K1. Optionally, the display panel 000 further includes a second conductive portion 00D2 made of the same material as the first conductive portion 00D1, and the second conductive portion 00D2 is in direct contact with the active portion 00TP of the thin-film transistor 00T within the second via hole K2.

[0117] This embodiment explains that the first pole 00TS of the thin film transistor 00T is electrically connected to the active part 00TP (source connection area of the active part 00TP) of the thin film transistor 00T through the first via K1, and the second pole 00TD of the thin film transistor 00T is electrically connected to the active part 00TP (drain connection area of the active part 00TP) of the thin film transistor 00T through the second via K2. To avoid the problem that due to the process reasons of the first via K1 and the second via K2, the contact area between the first pole 00TS of the thin film transistor 00T and the active part 00TP of the thin film transistor 00T in the first via K1 is too small, resulting in poor electrical performance transmission, and the contact area between the second pole 00TD of the thin film transistor 00T and the active part 00TP of the thin film transistor 00T in the second via K2 is too small, resulting in poor electrical performance transmission, this embodiment sets that the display panel 000 further includes a first conductive part 00D1, and the first conductive part 00D1 is in direct contact with the active part 00TP of the thin film transistor 00T in the first via K1. Optionally, the display panel 000 further includes a second conductive part 00D2 made of the same material as the first conductive part 00D1, and the second conductive part 00D2 is in direct contact with the active part 00TP of the thin film transistor 00T in the second via K2. Along the first direction X, the first conductive part 00D1 can be slightly wider than the width of the data line S, and the width of the second conductive part 00D2 can be slightly wider than the width of the second via K2 in the first direction X. By setting the first conductive part 00D1 and the second conductive part 00D2, the contact areas between the first pole 00TS and the second pole 00TD of the thin film transistor 00T and the active part 00TP of the thin film transistor 00T can be increased respectively, thereby ensuring the charging performance of the thin film transistor 00T and being beneficial to improving the product yield.

[0118] It can be understood that the settings of the first conductive part 00D1 and the second conductive part 00D2 in this embodiment can be set according to the charging requirements of the display panel 000 itself. The shape of the orthographic projection of the active part 00TP of the thin film transistor 00T on the first substrate 101 as a whole presents an L shape or a U shape, and the first conductive part 00D1 and the second conductive part 00D2 can be set. The first conductive part 00D1 and the second conductive part 00D2 can be made of a metal material of the same material as the data line S. The manufacturing process of this embodiment will not be elaborated, and specific understanding can be referred to the manufacturing process of the panel in the related technology.

[0119] Optionally, as Figure 27 and Figure 28 shown, at the first via K1, the orthographic projection of the first via K1 on the first substrate 101 is within the orthographic projection range of the first conductive part 00D1 on the first substrate 101, and the orthographic projection of the first conductive part 00D1 on the first substrate 101 is within the orthographic projection range of the first light-shielding part 1051 on the first substrate 101.

[0120] This embodiment is provided at the first via K1. The orthographic projection of the first via K1 on the first substrate 101 is within the orthographic projection range of the first conductive portion 00D1 on the first substrate 101, that is, the orthographic projection of the first conductive portion 00D1 on the first substrate 101 at least covers the orthographic projection position of the first via K1 on the first substrate 101. The orthographic projection area of the first conductive portion 00D1 on the first substrate 101 is relatively large and is in direct contact with the active portion 00TP of the thin-film transistor 00T. Therefore, good contact conductivity can be ensured. And the orthographic projection of the first conductive portion 00D1 on the first substrate 101 is within the orthographic projection range of the first light-shielding portion 1051 on the first substrate 101, which can ensure the light-shielding effect of the first light-shielding portion 1051 on the metal material of the first conductive portion 00D1, effectively avoid metal light leakage at the first via K1, and better improve the display contrast of the display panel 000. Similarly, at the second via K2, the orthographic projection of the second via K2 on the first substrate 101 is within the orthographic projection range of the second conductive portion 00D2 on the first substrate 101, that is, the orthographic projection of the second conductive portion 00D2 on the first substrate 101 at least covers the orthographic projection position of the second via K2 on the first substrate 101. The orthographic projection area of the second conductive portion 00D2 on the first substrate 101 is relatively large and is in direct contact with the active portion 00TP of the thin-film transistor 00T. Therefore, good contact conductivity can be ensured. And the orthographic projection of the second conductive portion 00D2 on the first substrate 101 is within the orthographic projection range of the second light-shielding portion 1052 on the first substrate 101, which can ensure the light-shielding effect of the second light-shielding portion 1052 on the metal material of the second conductive portion 00D2, effectively avoid metal light leakage at the second via K2, and better improve the display contrast of the display panel 000.

[0121] As Figure 29 and Figure 30 shown, Figure 29 is a display simulation diagram of a product in the dark state display in a certain project of the prior art. Figure 30 is a display simulation diagram of a product in the dark state display in another project of the prior art. From Figure 29 and Figure 30 the schematic display simulation diagrams of the dark state display of the existing products, it can be seen that there are metal light leakage problems at the vias in different sub-pixel regions of the display panel. Among them, in the visible light band, the transmittance of green light is higher than that of red light and blue light. Therefore, from the Figure 29 and Figure 30 dark state light leakage diagrams of the actual products, it can be seen that compared with the green sub-pixel G, the red sub-pixel R, and the blue sub-pixel B, the light leakage of the green sub-pixel G is the most obvious, that is, the dark state light leakage of the green sub-pixel G is more deteriorated.

[0122] Therefore, in some alternative embodiments, as Figure 1 and Figure 31 shown, Figure 31 isFigure 1 Another partial enlarged schematic diagram of the J1 region in Figure 32 is Figure 1 Another partial enlarged schematic diagram of the J1 region in (it can be understood that, for clearly showing the structure of this embodiment, Figure 31 and Figure 32 transparency filling is performed). To solve the above problems in this embodiment, when the display panel 000 includes multiple sub-pixels 00 including red sub-pixels 00R, blue sub-pixels 00B, and green sub-pixels 00G, it can be set that the region where the green sub-pixels 00G are located includes the first light-shielding portion 1051, and the regions of the red sub-pixels 00R and blue sub-pixels 00B do not include the first light-shielding portion 1051, that is, to improve the light leakage problem in the most obvious region and optimize the dark state display effect. The regions of the red sub-pixels 00R and blue sub-pixels 00B can only be provided with the third light-shielding portion 1053 corresponding to the channel region of the thin-film transistor 00T, and the corresponding positions of the remaining vias can not use the structure of the third metal layer 105 for light shielding, thereby effectively improving the transmittance of the display panel 000 and better taking into account the display performance of high contrast and high transmittance.

[0123] It can be understood that for the embodiment in which the shape of the positive projection of the active portion 00TP of the thin-film transistor 00T in the display panel 000 on the first substrate 101 is overall in an L shape, the first light-shielding portion 1051 of the third metal layer 105 can be provided at the first via K1 of the green sub-pixels 00G, the second light-shielding portion 1052 of the third metal layer 105 can be provided at the second via K2 of the green sub-pixels 00G, and the third light-shielding portion corresponding to the channel region of the thin-film transistor 00T of the green sub-pixels 00G is provided at the corresponding position of the third metal layer 105, while the red sub-pixels 00R and blue sub-pixels 00B only provide the third light-shielding portion 1053 corresponding to the channel region of the thin-film transistor 00T at the corresponding position to achieve light shielding of the channel region (as Figure 31 shown). For the embodiment in which the shape of the positive projection of the active portion 00TP of the thin-film transistor 00T in the display panel 000 on the first substrate 101 is overall in a U shape, the overall first light-shielding portion 1051, second light-shielding portion 1052, and third light-shielding portion 1053 can be provided in the region of the green sub-pixels 00G to cover and shield the first via K1, second via K2, and the channel region of the thin-film transistor 00T in the region of the green sub-pixels 00G, while the red sub-pixels 00R and blue sub-pixels 00B only provide the third light-shielding portion 1053 corresponding to the channel region of the thin-film transistor 00T at the corresponding position, without the need to expand outward to form the first light-shielding portion and the second light-shielding portion, thereby effectively improving the transmittance of the display panel 000 (as Figure 32 shown).

[0124] In some alternative embodiments, please refer to Figure 33 , Figure 33It is a schematic plan view of a display device provided by an embodiment of the present disclosure. The display device 111 provided by this embodiment includes the display panel 000 provided by the above-mentioned embodiment of the present invention. Figure 33 Taking a mobile phone as an example only, the display device 111 is described. It can be understood that the display device 111 provided by the embodiments of the present disclosure can be other display devices 111 with display functions such as computers, televisions, in-vehicle display devices, etc. The present invention does not make specific limitations thereto. The display device 111 provided by the embodiments of the present disclosure has the beneficial effects of the display panel 000 provided by the embodiments of the present invention. For specific descriptions of the display panel 000, reference can be made to the above-mentioned embodiments, and details will not be repeated in this embodiment.

[0125] It should be noted that in this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements not only includes those elements, but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. Without further limitations, an element defined by the statement "comprising one..." does not exclude the existence of additional identical elements in the process, method, article or device comprising the said element.

[0126] The above are only specific embodiments of the present disclosure, enabling those skilled in the art to understand or implement the present disclosure. Various modifications to these embodiments will be obvious to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure will not be limited to the embodiments described herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A display panel, characterized in that: It comprises an array substrate and an opposing substrate which are arranged opposite to each other; the array substrate comprises a first substrate and a semiconductor layer, a first metal layer and a second metal layer which are located on a side of the first substrate facing the opposing substrate; The display panel includes a plurality of sub-pixels, a plurality of scan lines and a plurality of data lines, wherein the scan lines and the data lines are cross-insulated and define the area where the sub-pixels are located; The sub-pixel includes a thin film transistor and a pixel electrode that are electrically connected; The scan line is located in the first metal layer, the active part of the thin film transistor is located in the semiconductor layer, the first electrode and the second electrode of the thin film transistor and the data line are located in the second metal layer; The active portion of the thin film transistor is electrically connected to the first electrode of the thin film transistor through a first via hole, the first electrode of the thin film transistor is electrically connected to the data line, and the second electrode of the thin film transistor is electrically connected to the pixel electrode; A third metal layer is further included between the first substrate and the semiconductor layer, and the third metal layer includes a plurality of first light shielding portions; At the first via hole, an orthographic projection of the first via hole on the first substrate is at least located within the orthographic projection range of the first light shielding portion on the first substrate; The orthographic projection of the first via hole on the first substrate is a first projection, the orthographic projection of the first light shielding portion on the first substrate is a second projection, and an edge of the second projection half surrounds an edge of the first projection.

2. The display panel according to claim 1, characterized in that: Along the extension direction of the scan line, the first projection includes a first edge and a second edge opposite to each other, the first edge faces the second pole of the thin film transistor, and the second edge is located on a side of the first edge away from the second pole of the thin film transistor; the second projection includes a third edge and a fourth edge opposite to each other, the third edge faces the second pole of the thin film transistor, and the fourth edge is located on a side of the third edge away from the second pole of the thin film transistor; The maximum distance between the first edge and the second edge is D1, and the minimum distance between the third edge and the fourth edge is D2; wherein D2>D1.

3. The display panel according to claim 2, characterized in that: The third edge is located at a side of the first edge away from the second edge, and the fourth edge is flush with the second edge.

4. The display panel according to claim 2, characterized in that: The fourth edge is located at a side of the second edge away from the first edge, and the third edge is flush with the first edge.

5. The display panel according to claim 2, characterized in that: The third edge is located on a side of the first edge away from the second edge, and the fourth edge is located on a side of the second edge away from the first edge.

6. The display panel according to claim 2, characterized in that: Along the extending direction of the scan line, the minimum distance that the third edge exceeds the edge of the data line is 2-2.2 μm.

7. The display panel according to claim 2, characterized in that: The display panel further includes a black matrix layer, the black matrix layer includes a plurality of first light shielding strips and a plurality of second light shielding strips in the same layer, the first light shielding strips and the second light shielding strips are cross-arranged to form a mesh structure, and the extension direction of the first light shielding strips is the same as the extension direction of the data lines; The first light-shielding strip includes a first protruding portion, and an orthographic projection of the first light-shielding portion on the first substrate is located within a range of an orthographic projection of the first protruding portion on the first substrate.

8. The display panel according to claim 7, characterized in that: An orthographic projection of the first light shielding portion on the first substrate coincides with an orthographic projection of the first protruding portion on the first substrate.

9. The display panel according to claim 2, characterized in that: The active portion of the thin film transistor has an L-shape as an orthographic projection on the first substrate.

10. The display panel according to claim 9, characterized in that: The active portion of the thin film transistor is electrically connected to the second electrode of the thin film transistor through a second via hole; The third metal layer further includes a plurality of second light shielding portions and a plurality of third light shielding portions; At the second via hole, an orthographic projection of the second via hole on the first substrate is at least located within the orthographic projection range of the second light shielding portion on the first substrate; The orthographic projection of the third light shielding portion on the first substrate covers the orthographic projection of the channel region of the thin film transistor on the first substrate; The first light shielding portion, the second light shielding portion, and the third light shielding portion are independent structures respectively.

11. The display panel according to claim 1, characterized in that: The active portion of the thin film transistor has an orthographic projection on the first substrate in a U shape.

12. The display panel according to claim 11, characterized in that: The third metal layer further includes a plurality of second light shielding portions; The active portion of the thin film transistor is electrically connected to the second electrode of the thin film transistor through a second via hole, and the orthographic projection of the second via hole on the first substrate is located within the orthographic projection range of the second light shielding portion on the first substrate; The orthographic projection of the second via hole on the first substrate is a third projection, and the orthographic projection of the second light shielding portion on the first substrate is a fourth projection; Along the extension direction of the scan line, the first projection includes a fifth edge away from the third projection, the third projection includes a sixth edge away from the first projection, the second projection includes a seventh edge away from the fourth projection, and the fourth projection includes an eighth edge away from the second projection; The maximum distance between the fifth edge and the sixth edge is D3, and the minimum distance between the seventh edge and the eighth edge is D4; wherein D4>D3.

13. The display panel according to claim 12, characterized in that: D4-D3≤1μm.

14. The display panel according to claim 12, characterized in that: The third metal layer further includes a plurality of third light shielding portions; The orthographic projection of the channel region of the thin film transistor on the first substrate is located within the orthographic projection range of the third light shielding portion on the first substrate.

15. The display panel according to claim 14, characterized in that: The first light shielding portion, the second light shielding portion, and the third light shielding portion are independent structures respectively.

16. The display panel according to claim 14, characterized in that: The first light shielding portion, the second light shielding portion, and the third light shielding portion are an integrated structure.

17. The display panel according to claim 1, characterized in that: The display panel further includes a first conductive portion, which is in direct contact with an active portion of the thin film transistor in the first via hole.

18. The display panel according to claim 17, characterized in that: At the first via hole, the orthographic projection of the first via hole on the first substrate is located within the orthographic projection range of the first conductive portion on the first substrate, and the orthographic projection of the first conductive portion on the first substrate is located within the orthographic projection range of the first light shielding portion on the first substrate.

19. The display panel according to claim 1, characterized in that: The plurality of sub-pixels include a red sub-pixel, a blue sub-pixel and a green sub-pixel; The region where the green sub-pixel is located includes the first light shielding portion, while the regions where the red sub-pixel and the blue sub-pixel are located do not include the first light shielding portion.

20. A display device, characterized in that: A display panel comprising any one of claims 1-19.

Images