Smart card data rapid processing architecture and method based on COS system
By designing a data rapid processing architecture based on COS system in smart cards and optimizing data transmission mode and processing mechanism, the bottleneck problem of data processing performance of smart cards under traditional communication mechanisms is solved, and more efficient data processing is achieved.
Patent Information
- Application Number
- CN202510108229.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-23
- Publication Date
- 2025-06-03
AI Technical Summary
The traditional "one send and one receive" communication mechanism and data transmission mode of smart cards between the host business system and smart cards have become a bottleneck in data processing performance.
Design a smart card data rapid processing architecture based on COS system. Through the integrated controller and communication bus controller, the data transmission mode and processing mechanism are optimized, and the data reception and transmission FIFO is adopted with a ping-pong structure, and the data is sent directly to the processor, reducing the cache and forwarding process of RAM memory.
By optimizing the data transmission and processing mechanism, the data transmission delay is significantly shortened, the data processing efficiency of smart cards is improved, and the performance bottleneck caused by traditional communication mechanisms and data transmission delay is solved.
Smart Images
Figure CN120085828A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of data processing, and in particular, to a fast intelligent card data processing architecture and method based on a COS system. Background Art
[0002] In the field of intelligent card applications, as the services of its host system continue to increase, the frequency of service requests for intelligent cards has also increased significantly. This requires the intelligent card to be able to process data quickly and return a response result to its host service system, so as to ensure that the service system can quickly execute various service requests of users.
[0003] Currently, the communication between the host service system and the intelligent card is a "one - send - one - receive" mechanism. That is, after the communication bus controller receives the data sent by the host, it stores the data in its own first - in - first - out queue (FIFO) and generates an interrupt (in the t1 time period), then the COS system copies the data to the RAM (in the t2 time period). After command parsing (in the t3 time period), the data in the RAM is sent to the cryptographic chip (in the t4 time period), then the processor performs arithmetic processing on the service request (in the t5 time period), and finally the arithmetic result is returned to the host service system through the COS system (in the t6, t7, and t8 time periods). The traditional data transmission and processing process between the host service system and the intelligent card is as Figure 3 shown.
[0004] Currently, the working frequency of the intelligent card processor core is continuously increasing, and it already has the ability of high - speed operation. Compared with the processor operation delay, the data transmission delay and processing mechanism between the host service system and the intelligent card have become the performance bottleneck of data fast processing.
[0005] Therefore, aiming at the problem of the intelligent card data processing performance bottleneck, it is necessary to optimize the data transmission mode and data processing mechanism in the COS system environment, so as to improve the data processing performance of the intelligent card and reduce the service request delay of the host service system. Summary of the Invention
[0006] The purpose of the present invention is to overcome the deficiencies of the prior art and propose a fast intelligent card data processing architecture and method based on a COS system, which can change the traditional "one - send - one - receive" communication mechanism and data transmission mode between the host service system and the intelligent card, and solve the data processing performance bottleneck problem caused by high - delay data transmission.
[0007] The present invention solves its technical problems by adopting the following technical solutions:
[0008] An intelligent card data rapid processing architecture based on a COS system, comprising a communication bus controller, an integrated controller, a RAM memory, a FLASH, and a processor core. Among them, the integrated controller is respectively connected to the RAM memory and the processor core through an internal interface, the processor core is respectively connected to the RAM memory and the FLASH, and the communication bus controller is respectively connected to the RAM memory and the processor core;
[0009] The communication bus controller is used to implement the communication link between the host service system and the intelligent card; the integrated controller is used for intelligent card initialization, host system command parsing, packet length training and negotiation, resource preprocessing, and data receiving and sending FIFO status monitoring; the RAM memory provides a data cache space for the processor; the FLASH stores data information such as the program code and related resources of the intelligent card for the processor to read; the processor core is used for data operation and returns the operation result to the host service system.
[0010] Moreover, the integrated controller includes a command parsing module, a packet length training and negotiation module, and a status monitoring module. Among them, the command parsing module is used to analyze the service request commands issued by the host service system; the packet length training and negotiation module is used to determine the packet length of a single DMA data transfer between the host service system and the intelligent card; the status monitoring module is used to monitor the status of the data receiving FIFO and the data sending FIFO in the communication bus controller, and save the empty / full status information of the FIFO in its own status register, providing a status indication for the host service system and the processor core to operate the data FIFO.
[0011] Moreover, the communication bus controller includes a data receiving FIFO and a data sending FIFO.
[0012] Moreover, the receiving FIFO includes a first data receiving FIFO, a second data receiving FIFO, and a third data receiving FIFO. The first data receiving FIFO only receives the command data packets issued by the host service system, which are analyzed by the command parsing module in the integrated controller, and the intelligent card processor is notified to execute the corresponding command operations; the second data receiving FIFO and the third data receiving FIFO are organized in a ping-pong structure to receive the large packet length data to be processed issued by the host service system. The host service system writes data to the second data receiving FIFO, and after it is full, it starts to write data to the third data receiving FIFO. At the same time, the intelligent card processor starts to read data after the second data receiving FIFO is full. After the data reading is completed, the operation processing starts. After the data processing is completed, it starts to read the data to be processed in the third data receiving FIFO and perform data operation processing. Subsequently, it alternately reads the data in the second data receiving FIFO and the third data receiving FIFO in turn.
[0013] Moreover, the data transmission FIFO includes a first FIFO, a second data transmission FIFO, and a third data transmission FIFO. The first data transmission FIFO only receives the return messages of general command types sent by the smart card processor and returns them to the host service system. The second and third data transmission FIFOs are organized in a ping-pong structure and receive the operation results of large packet-length data sent by the smart card processor. The smart card processor writes data to the second data transmission FIFO. After it is full, it starts writing data to the third data transmission FIFO. At the same time, the host service system starts reading data after the second data transmission FIFO is full. After the data reading is completed, it starts reading the data in the third data transmission FIFO, and then alternately reads the data in the second and third data transmission FIFOs in sequence.
[0014] A processing method for a smart card data fast processing architecture based on a COS system includes an initialization process and a normal working process.
[0015] Moreover, the initialization stage includes the following steps:
[0016] Step 1: The host service system sends a packet length training and negotiation command to the smart card;
[0017] Step 2: The command parsing module in the smart card integrated controller parses the command. After confirming the command, it notifies the processor to move the relevant resources in the FLASH memory to the RAM memory and starts packet length training;
[0018] Step 3: The smart card processor calculates the operation performance in different packet length cases, determines the data packet length corresponding to the highest operation performance of the processor, and returns the data packet length information to the host service system;
[0019] Step 4: After receiving the trained data packet length information, the host service system negotiates and determines the data packet length for DMA operation between the host service system and the smart card according to the actual hardware conditions.
[0020] Moreover, the normal working process includes the following steps:
[0021] Step 1: The host service system sends a service request command to the smart card;
[0022] Step 2: The smart card receives the service request command through the typical mode and analyzes the command through the command parsing module in the integrated controller;
[0023] Step 3: If it is a configuration and query general command type, the smart card processes it according to the typical mode. After the command is executed, it sends a response to the host business system. If it is a large data volume operation processing start command, after the relevant resources of the smart card are prepared, it notifies the host business system that it can start a large data transfer operation and switches to the direct mode;
[0024] Step 4: After receiving the feedback information from the smart card, the host business system performs DMA operations with the packet length negotiated in the initialization phase;
[0025] Step 5: In the direct mode, the smart card directly sends the data in the data reception FIFO to the processor without copying it to the RAM memory and then forwarding it to the processor, reducing the data transfer time;
[0026] Step 6: After the processor finishes the operation, it directly sends the operation result to the data transmission FIFO of the communication bus controller without passing through the RAM memory;
[0027] Step 7: The data transmission FIFO sends the operation result to the host business system to complete a large packet length data operation processing operation.
[0028] The advantages and positive effects of the present invention are:
[0029] The present invention includes a communication bus controller, an integrated controller, a RAM memory, a FLASH, and a processor core. Among them, the integrated controller is respectively connected to the RAM memory and the processor core through an internal interface, the processor core is respectively connected to the RAM memory and the FLASH, and the communication bus controller is respectively connected to the RAM memory and the processor core. Among them, the integrated controller determines the packet length of a DMA data transfer between the host business system and the smart card through a packet length training and negotiation module, enabling the smart card to exert the best operation performance of the processor in the case of a large amount of operations; designing a dedicated data transceiver FIFO and a dedicated path for large packet data transfer reduces the data transfer delay between the host business system and the smart card processor and improves the data processing efficiency of the smart card. The present invention can optimize the operation performance of the smart card processor and can solve the data operation processing performance bottleneck problem caused by the original communication mechanism and data transfer delay between the host business system and the smart card. BRIEF DESCRIPTION OF THE DRAWINGS
[0030] Figure 1 It is a smart card data fast processing architecture diagram based on the COS system of the present invention;
[0031] Figure 2 It is a working flow diagram of the smart card command parsing module of the present invention;
[0032] Figure 3 It is a traditional data transfer processing flow chart. Detailed implementation manners
[0033] The present invention will be further described in detail below with reference to the accompanying drawings.
[0034] An intelligent card data fast processing architecture based on a COS system, as Figure 1 shown, includes a communication bus controller, a comprehensive controller, a RAM memory, a FLASH, and a processor core. Among them, the comprehensive controller is respectively connected to the RAM memory and the processor core through an internal interface, the processor core is respectively connected to the RAM memory and the FLASH, and the communication bus controller is respectively connected to the RAM memory and the processor core;
[0035] The communication bus controller is used to implement the communication link between the host service system and the intelligent card; the comprehensive controller is used for intelligent card initialization, host system command parsing, packet length training and negotiation, resource preprocessing, and data reception and transmission FIFO status monitoring; the RAM memory provides a data cache space for the processor; the FLASH stores data information such as program codes and related resources of the intelligent card for the processor to read; the processor core is used for data operation and returns the operation result to the host service system.
[0036] The comprehensive controller includes a command parsing module, a packet length training and negotiation module, and a status monitoring module. Among them, the command parsing module is used to analyze the service request commands issued by the host service system; the packet length training and negotiation module is used to determine the packet length of a single DMA data transmission between the host service system and the intelligent card; the status monitoring module is used to monitor the status of the data reception FIFO and the data transmission FIFO in the communication bus controller, and save the empty / full status information of the FIFO in its own status register, providing a status indication for the host service system and the processor core to operate the data FIFO.
[0037] The function of the command parsing module is to analyze the service request commands issued by the host service system. The service request commands of the host service system can be divided into the following two categories:
[0038] 1. General command types such as initialization, configuration, and query. The intelligent card operates in the default typical mode and notifies the intelligent card processor to complete corresponding operations according to the service request commands;
[0039] 2. Special commands for starting large data volume operation processing, notifying the intelligent card processor to cache relevant resources required for subsequent operation processing from the FLASH memory to the RAM in advance, shortening the access time to relevant resources during the data operation process, and switching to the direct mode, notifying the host service system that it can start a large amount of data transmission operations.
[0040] As Figure 2 shown is the working flow chart of the intelligent card command parsing module;
[0041] Step S1: The host business system issues a command;
[0042] Step S2: Command parsing;
[0043] Step S3: Determine whether the command is of the general command type. If so, proceed to Step S4; otherwise, proceed to Step S5;
[0044] Step S4: Run in the typical mode; execute the corresponding command operation and proceed to Step S6;
[0045] Step S5: The command is of the special command type. Cache the relevant resources to the RAM memory, switch to the direct mode, and proceed to Step S6;
[0046] Step S6: Send a response to the host business system.
[0047] The packet length training and negotiation module is responsible for determining the packet length of a single DMA data transfer between the host business system and the smart card, enabling the smart card to exert the best computing performance of the processor under the condition of a large amount of operations.
[0048] Affected by resource call operations, the characteristics of the processor itself, etc., as the length of the data packet increases, the computing performance of the processor improves. When the length of the data packet is greater than a certain length, the computing performance of the processor begins to decline. Therefore, it is necessary to confirm the data packet length at the best computing performance of the smart card through data packet length training operations. The process of packet length training and negotiation is as follows:
[0049] 1. The smart card creates a series of data packets with different lengths from small to large within a certain range, sends them to the processor for operations respectively, calculates the computing performance in different packet length cases, determines the data packet length corresponding to the highest computing performance of the processor, and returns the data packet length information to the host business system;
[0050] 2. After receiving the trained data packet length information, the host business system determines whether it supports DMA operations with this data packet length between the host business system and the smart card. If it supports DMA operations with this data packet length, the host business system and the smart card perform DMA operations with this data packet length; otherwise, perform DMA operations with the maximum data packet length between the host business system and the smart card.
[0051] The function of the status monitoring module is to monitor the status of the data reception FIFO and the data transmission FIFO in the communication bus controller, and save the empty / full status information of the above-mentioned multiple FIFOs in its own status register, providing a status indication for the host business system and the processor core to operate the data FIFO.
[0052] In traditional smart cards, a single-data FIFO design is adopted in the communication bus controller, and the same data FIFO is shared for receiving and sending data. Since traditional smart cards adopt a "one-send-one-receive" data transmission and processing mechanism, the host service system will only send the next packet of data to the smart card after receiving the result of the previous service request. Using a single-data FIFO design will not cause problems such as data overwriting or loss. However, the single-data FIFO structure will result in very low data transmission efficiency between the host service system and the smart card. Therefore, to improve the data transmission efficiency between the host service system and the smart card, the present invention designs a data reception FIFO and a data transmission FIFO based on a ping-pong structure, and the detailed design is as follows.
[0053] The reception FIFO includes a first data reception FIFO, a second data reception FIFO, and a third data reception FIFO. The first data reception FIFO only receives the command data packets sent by the host service system, which are analyzed by the command parsing module in the comprehensive controller, and the smart card processor is notified to execute the corresponding command operations; the second data reception FIFO and the third data reception FIFO are organized in a ping-pong structure to receive the large packet-length data to be processed sent by the host service system. The host service system writes data to the second data reception FIFO, and after it is full, it starts writing data to the third data reception FIFO. At the same time, the smart card processor starts reading data after the second data reception FIFO is full. After the data reading is completed, arithmetic processing is started. After the data processing is completed, it starts reading the data to be processed in the third data reception FIFO and performs data arithmetic processing. Subsequently, the data in the second data reception FIFO and the third data reception FIFO are alternately read in sequence.
[0054] The transmission FIFO includes a first FIFO, a second data transmission FIFO, and a third data transmission FIFO. The first transmission FIFO only receives the return messages of general command types sent by the smart card processor and returns them to the host service system; the second data transmission FIFO and the third data transmission FIFO are organized in a ping-pong structure to receive the large packet-length data arithmetic results sent by the smart card processor. The smart card processor writes data to the second data transmission FIFO, and after it is full, it starts writing data to the third data transmission FIFO. At the same time, the host service system starts reading data after the second data transmission FIFO is full. After the data reading is completed, it starts reading the data in the third data transmission FIFO. Subsequently, the data in the second data transmission FIFO and the third data transmission FIFO are alternately read in sequence.
[0055] Figure 1The traditional data transmission and processing flow between the host business system and the smart card is given. Taking a service request for a large amount of data operation and processing at one time as an example, from the host business system issuing the service request to the smart card returning the operation result to the host business system, it can be divided into 8 time periods, namely t1 to t8.
[0056] Similarly, taking a service request for a large amount of data operation and processing at one time as an example, from the host business system issuing the service request to the smart card returning the operation result to the host business system, it can be divided into 5 time periods, namely T1 to T5.
[0057] The comparative analysis of each stage of data transmission is as follows:
[0058] For the communication bus transmission time, through the design of the data receiving FIFO and the data sending FIFO in the data fast processing architecture proposed by the present invention, data transmission can be carried out alternately between the host business system and the smart card, and it can be obtained that T1 < t1, T5 < t8. Generally
[0059] For the transmission time between the communication bus controller data FIFO and the processor core, in the traditional data processing flow, the transmission time from the communication bus controller data FIFO to the processor core is t2 + t3 + t4, and the transmission time from the processor core to the communication bus controller data FIFO is t6 + t7; in the data fast processing architecture proposed by the present invention, the transmission time from the communication bus controller data FIFO to the processor core is T2, and the transmission time from the processor core to the communication bus controller data FIFO is T4. Thus, it can be seen that the cache forwarding link of the RAM memory is omitted in the data fast processing architecture proposed by the present invention. Generally
[0060] For the operation time of the smart card processor, there is a packet length training and negotiation module in the data fast processing architecture proposed by the present invention, which can negotiate the optimal DMA data packet length with the host business system, so that the smart card processor works under the best performance conditions. Compared with the traditional smart card architecture, the operation performance of the processor can be greatly improved, and it can be obtained that T3 < t5.
[0061] By comparing with the traditional smart card data processing architecture, to complete a service request for a large amount of data operation and processing at one time, the smart card data fast processing architecture proposed by the present invention can shorten the time used in each stage of data transmission and processing, and greatly improve the data transmission and processing performance of the smart card.
[0062] A processing method for a smart card data fast processing architecture based on the COS system realizes the fast processing of the host business system service request from the following two aspects:
[0063] 1. Determine the packet length of a single DMA data transfer between the host service system and the smart card through the packet length training and negotiation module, so that the smart card can exert the best computing performance of the processor under the condition of performing a large number of operations;
[0064] 2. By designing a data transceiver FIFO and a dedicated path for large packet data transfer, reduce the data transfer delay between the host service system and the smart card processor, and improve the data processing efficiency of the smart card.
[0065] For the designs in the above two aspects, adopting the data fast processing architecture proposed by the present invention, the working process of the smart card is divided into two stages, one is the initialization stage, and the other is the normal working stage.
[0066] The initialization stage includes the following steps:
[0067] Step 1: The host service system sends a packet length training and negotiation command to the smart card;
[0068] Step 2: The command parsing module in the smart card integrated controller parses the command. After confirming the command, it notifies the processor to move the relevant resources in the FLASH memory to the RAM memory and start packet length training;
[0069] Step 3: The smart card processor calculates the computing performance under different packet lengths, determines the data packet length corresponding to the highest computing performance of the processor, and returns the data packet length information to the host service system;
[0070] Step 4: After receiving the trained data packet length information, the host service system negotiates and determines the data packet length for DMA operation between the host service system and the smart card according to the actual hardware conditions.
[0071] The normal working process includes the following steps:
[0072] Step 1: The host service system sends a service request command to the smart card;
[0073] Step 2: The smart card receives the service request command through the typical mode and analyzes the command through the command parsing module in the integrated controller;
[0074] Step 3: If it is a configuration and query general command type, the smart card processes it according to the typical mode. After the command is executed, it sends a response to the host service system; if it is a large data volume operation processing start command, after the relevant resources are prepared, the smart card notifies the host service system that it can start a large data transfer operation and switches to the direct mode;
[0075] Step 4: After receiving the feedback information from the smart card, the host service system performs DMA operation with the data packet length negotiated in the initialization stage;
[0076] Step 5: In the direct access mode, the smart card directly sends the data in the data reception FIFO to the processor without copying it to the RAM memory and then forwarding it to the processor, thus reducing the data transmission time.
[0077] Step 6: After the processor finishes the operation, it directly sends the operation result to the data transmission FIFO of the communication bus controller without passing through the RAM memory either.
[0078] Step 7: The data transmission FIFO sends the operation result to the host service system, completing an operation process for large packet length data.
[0079] In the above initialization stage and normal operation stage, through the packet length training of the smart card and negotiation with the host service system, the packet length of a single DMA data transmission between the host service system and the smart card is determined, enabling the smart card processor to achieve the best operation performance. Secondly, a data reception and transmission FIFO and a dedicated path for large packet data transmission are designed to reduce the data transmission delay between the host service system and the smart card processor, further improving the data processing efficiency of the smart card.
[0080] It should be emphasized that the embodiments described in the present invention are illustrative rather than restrictive. Therefore, the present invention includes, but is not limited to, the embodiments described in the specific implementation manners. Any other implementation manners obtained by those skilled in the art according to the technical solutions of the present invention also fall within the scope of protection of the present invention.
Claims
1. A smart card data fast processing architecture based on COS system, characterized by: It includes a communication bus controller, an integrated controller, a RAM memory, a FLASH and a processor core, wherein the integrated controller is connected to the RAM memory and the processor core through internal interfaces, the processor core is connected to the RAM memory and the FLASH, and the communication bus controller is connected to the RAM memory and the processor core; The communication bus controller is used to realize the communication link between the host business system and the smart card; the integrated controller is used for smart card initialization, host system command parsing, data packet length training and negotiation, resource preprocessing and data transmission and reception FIFO status monitoring; RAM memory provides data cache space for the processor; FLASH stores the program code, related resources and other data information of the smart card for the processor to read; the processor core is used for data calculation and returns the calculation results to the host business system.
2. The COS-based smart card data rapid processing architecture according to claim 1, characterized in that: The integrated controller includes a command parsing module, a packet length training and negotiation module, and a status monitoring module, wherein the command parsing module is used to analyze the service request command issued by the host business system; the packet length training and negotiation module is used to determine the packet length of a DMA data transmission between the host business system and the smart card; the status monitoring module is used to monitor the status of the data receiving FIFO and the data sending FIFO in the communication bus controller, and save the empty and full status information of the FIFO in its own status register, providing a status indication function for the host business system and the processor core to operate the data FIFO.
3. The COS-based smart card data rapid processing architecture according to claim 1, characterized in that: The communication bus controller includes a data receiving FIFO and a data sending FIFO.
4. The COS-based smart card data rapid processing architecture according to claim 3, characterized in that: The receiving FIFO includes a first data receiving FIFO, a second data receiving FIFO and a third data receiving FIFO. The first data receiving FIFO only receives command data packets sent by the host service system, which are analyzed by the command parsing module in the integrated controller and notify the smart card processor to execute the corresponding command operation; The second data receiving FIFO and the third data receiving FIFO are organized in a ping-pong structure to receive large packets of long data to be processed sent by the host business system. The host business system writes data to the second data receiving FIFO, and starts writing data to the third data receiving FIFO after it is full. At the same time, the smart card processor starts reading data after the second data receiving FIFO is full, and starts performing calculations after the data is read. After the data is processed, it starts reading the data to be processed in the third data receiving FIFO and performs data calculations. Subsequently, the data in the second data receiving FIFO and the third data receiving FIFO are read alternately.
5. The COS-based smart card data rapid processing architecture according to claim 3, characterized in that: The data sending FIFO includes a first FIFO, a second data sending FIFO and a third data sending FIFO. The first data sending FIFO only receives return messages of general command types sent by the smart card processor and returns them to the host business system; the second data sending FIFO and the third data sending FIFO are organized in a ping-pong structure to receive large packet length data calculation results sent by the smart card processor. The smart card processor writes data to the second data sending FIFO, and starts writing data to the third data sending FIFO after it is full. At the same time, the host business system starts reading data after the second data sending FIFO is full. After the data reading is completed, it starts reading data in the third data sending FIFO, and subsequently reads data in the second data sending FIFO and the third data sending FIFO alternately.
6. A processing method for a smart card data fast processing architecture based on a COS system according to any one of claims 1 to 5, characterized in that: Including initialization process and normal working process.
7. The method for processing smart card data fast processing architecture based on COS system according to claim 6, characterized in that: The initialization phase includes the following steps: Step 1: The host service system sends a packet length training and negotiation command to the smart card; Step 2: The command parsing module in the smart card integrated controller parses the command, and after confirming the command, notifies the processor to move the relevant resources in the FLASH memory to the RAM memory, and starts packet length training; Step 3: The smart card processor calculates the computing performance under different packet lengths, determines the data packet length corresponding to the processor's highest computing performance, and returns the data packet length information to the host service system; Step 4: After receiving the trained data packet length information, the host service system negotiates and determines the data packet length for DMA operation between the host service system and the smart card according to actual hardware conditions.
8. The method for processing smart card data fast processing architecture based on COS system according to claim 6, characterized in that: The normal working process includes the following steps: Step 1: The host service system sends a service request command to the smart card; Step 2: The smart card receives the service request command through a typical mode, and performs command analysis through a command parsing module in the integrated controller; Step 3: If it is a general command type for configuration and query, the smart card processes it in a typical mode and sends a response to the host business system after the command is executed; if it is a large data volume operation and processing start command, the smart card notifies the host business system that it can start a large amount of data transmission operation after the relevant resources are prepared, and switches to the direct mode; Step 4: After receiving the feedback information from the smart card, the host service system performs DMA operation with the data packet length negotiated in the initialization phase; Step 5: In direct mode, the smart card sends the data in the data receiving FIFO directly to the processor, and no longer copies it to the RAM memory and then forwards it to the processor, thereby reducing the data transmission time; Step 6: After the processor completes the operation, the operation result is directly sent to the data transmission FIFO of the communication bus controller without passing through the RAM memory; Step 7: The data transmission FIFO sends the calculation result to the host service system, completing a large packet length data calculation and processing operation.