A Deadlock Prevention Method and Device Based on AXI Bus Data Reordering

Abstract

The present invention relates to an anti-deadlock method and device based on AXI bus data reordering. This method, by introducing data caching, reordering, and virtual handshaking mechanisms during data transmission, ensures that communications between multiple master devices and multiple slave devices avoid deadlocks caused by out-of-order transmission. By dynamically adjusting the data transmission and response sequences, the present invention effectively improves the system's data transmission efficiency and ensures the stability and reliability of the AXI bus in complex multi-master, multi-slave systems.

Description

Technical Field

[0001] The present invention belongs to the field of chip technology, and in particular relates to an anti-deadlock method and device based on AXI bus data reordering. Background Art

[0002] The Advanced eXtensible Interface (AXI) protocol, designed by ARM, offers high flexibility and scalability, supporting concurrent data transmission between multiple masters and slaves. It is widely used in modern systems requiring efficient data exchange. Address and data control are separated, with a total of five channels: read address channel (AR channel), read data channel (R channel), write address channel (AW channel), write data channel (W channel), and write response channel (B channel). Its core design concept is to improve data transmission efficiency through multiple independent channels, creating a full-duplex operation mechanism.

[0003] The AXI 4.0 protocol is a variant of the Advanced Microcontroller Bus Architecture (AMBA) protocol proposed by ARM. This protocol uses ID tags to control the order of data transmission. For data transmission, the AW channel carries the ID tag AWID for the current write request, while the AR channel carries the ID tag ARID for the current read request. Data transmission between a slave device and a master device can be accomplished through multiple responses with ID tags. These responses carry requests with ID tags. The R channel carries the read data ID tag RID for read requests, and the B channel carries the write completion ID tag BID for write requests.

[0004] The Outstanding mechanism in the AXI protocol allows the host to initiate multiple read and write requests without receiving a response. This mechanism allows the host to continue sending new requests while waiting for a response, thereby improving data transmission efficiency. Without the Outstanding mechanism, the bus master's behavior for read operations is to send a read address command through the AR channel and wait for the read data to be returned through the R channel. For write operations, it sends a write address command through the AW channel, then sends the write data through the W channel, and finally waits for the write response to be returned through the B channel. If the Outstanding mechanism is supported, the bus master can continuously issue multiple read or write commands without receiving a response, then wait for each command to be returned. For read operations, the bus master sends multiple read address commands through the AR channel and waits for the read data to be returned through the R channel for multiple read requests. For write operations, the bus master sends multiple write address commands through the AW channel and, after preparing the data, sends the write data for multiple write requests through the W channel, finally waiting for the B channel to respond that the data for multiple write commands has been written.

[0005] One use of IDs in the AXI protocol is to disrupt the order of data transmission. In a complex SoC system, different types of slave space addresses exist, with some corresponding to faster-responding memories and others to slower ones. For example, a read request from a slower-responding memory will arrive at the bus master later than a faster-responding memory. If the bus master issues a read request for the slower memory before sending a read request for the faster memory, the master will be stuck waiting for the slower memory to respond, degrading bus performance. The AXI bus's out-of-order transmission mechanism is designed to address this issue. This is based on the out-of-order mechanism. In this out-of-order read implementation, the bus master can issue multiple read commands with the same ARID. Read data for read requests with the same ARID must be sent back in the order in which the master sent the read address commands. However, for read requests with different ARIDs, the read data can be sent back to the bus master out of the order in which the read address commands were sent. For write disorder, AXI4 has cancelled the use of the WID signal of the W channel and no longer supports write disorder. That is, the write data sent by the W channel is sent completely in the order of the write address command of the AW channel, but the B channel still supports disorderly transmission. If the Slave device completes all writing of the write data, the device with the fastest response can first transmit the write response to the bus Master without having to respond in the order in which the write address commands were sent.

[0006] Although the AXI protocol provides an efficient data transmission mechanism and supports parallel operation, deadlock can occur in complex multi-master, multi-slave systems. Deadlock is often caused by circular dependencies between multiple masters and slaves. For example, in a two-bus master read-accessing two slaves, if Master1 sends read requests with ARIDs of 0 to Slave1 and Slave2, and Master2 also sends read requests with ARIDs of 0 to Slave2 and Slave1, the interconnect structure design allows the slaves to add bits to the ARIDs of different sources to distinguish between different masters. For example, the ARID sent by Master1 changes from 0 to 10 across the interconnect structure, while the ARID sent by Master2 changes from 0 to 20 across the interconnect structure. To the slaves, these appear to be different ARID numbers, allowing for out-of-order transmission. However, for the two masters, data with the same ARID should be transmitted in the order in which the read address commands were sent. Master1 can only accept data from Slave1 before Slave2, and Master2 can only accept data from Slave2 before Slave1. There is only one correct response order. Due to out-of-order transmission, Slave1 and Slave2 have two correct response orders: responding to Master1 first or Master2 first. If Slave1 responds to Master2 first, and Slave2 responds to Master1 first, this violates the principle that data with the same ID must be transmitted in the order in which the read address commands are sent. This causes both masters and slaves to wait, leading to a system deadlock. This is how out-of-order transmission of read requests can cause deadlock.

[0007] The AXI protocol's Outstanding transfer access mechanism allows a bus master to issue the next Write Data Address command without waiting for the previous Write Data Address command to complete. Although a master can initiate multiple commands simultaneously on the AW channel to negotiate access to multiple slaves, within a transfer cycle, a slave can only exchange data on the W channel with the only master granted access. Due to this mechanism, multi-master, multi-slave data exchange carries a risk of deadlock caused by the Outstanding mechanism. For example, if two bus masters are accessing two slaves for write access, Master1 initially issues two Write Address commands to Slave2 and Slave1, sequentially and consecutively. Then, Master2 issues two Write Address commands to Slave1 and Slave2, sequentially and consecutively. Because the path delay between Slave1 and Master1 is shorter than the path delay between Slave2 and Master1, the write address command sent by Master1 to Slave1 arrives first, reaching Slave1 before the write address command sent by Master2 to Slave1. Slave1 then gains access to Slave1. At this point, Slave1 opens the W channel and waits for Master1 to write data. Similarly, because the path delay between Slave2 and Master2 is shorter than the path delay between Slave2 and Master1, the write address command sent by Master2 to Slave2 arrives first, reaching Slave2 before the write address command sent by Master1 to Slave2. Slave2 then gains access to Slave2. At this point, Slave2 opens the W channel and waits for Master2 to write data. For the Master, write data must be transmitted in the order in which the write address commands were sent. Master1 must send data to Slave2 first, and Master2 must send data to Slave1 first. However, Slave1 is waiting for Master1's data and will not accept Master2's data. Slave2 is now waiting for Master2's data and will not accept Master1's data. This creates a waiting cycle and deadlocks the bus. This is why using the Outstanding mechanism for write requests can cause deadlocks.

[0008] Because the AXI protocol allows out-of-order transmission and transmission path delays, when data does not match the request, the master and slave devices will be deadlocked. When one master and slave device affects multiple master and slave devices, the system bus will be deadlocked.

[0009] To avoid deadlock in the AXI protocol, there are two main existing solutions: the Single Slave method and the Single Slave Per ID method. The Single Slave method, if the read / write address commands sent via the Outstanding mechanism are destined for different slave devices, suspends the continuous transmission of subsequent read / write address commands, ensuring that the current read / write address request is completed before the next request is sent, thus preventing deadlock. This method is simple to understand and implement, but its main drawback is that it reduces data bandwidth. The master device cannot initiate a new request while waiting for the previous request to complete, resulting in data transmission delays. Only the Outstanding transmission mechanism can be implemented for the same device.

[0010] Single Slave Per ID is more flexible than the Single Slave mechanism. If the corresponding IDs of read and write address commands sent through the Outstanding mechanism are inconsistent, or if the IDs are the same but sent to the same slave device, the Outstanding mechanism continues to be supported. If the IDs are the same but sent to different slave devices, the subsequent read and write address commands are suspended to ensure that the current read and write address request is completed before the next request is sent, preventing deadlock. This method is more supportive of out-of-order read request transmission, but it cannot solve the deadlock problem encountered when writing data. Summary of the Invention

[0011] The object of the present invention is to address the deficiencies of existing methods and provide an anti-deadlock method and device based on AXI bus data reordering.

[0012] To achieve the above object, the present invention adopts the following technical solutions:

[0013] An anti-deadlock method based on AXI bus data reordering, the method comprising:

[0014] Monitor the response time of master-slave device interactions;

[0015] When the response time exceeds a preset threshold, a virtual handshake signal is constructed to complete the response to the master device or the slave device, and the write data from the master device or the read data from the slave device transmitted by the bus is read;

[0016] storing the write data or read data in a cache module;

[0017] After reordering the data in the cache module according to the address sequence of the read request command or the write request command, the data is sent to the master device or the slave device in sequence.

[0018] As a preferred embodiment, monitoring the response time of the master-slave device interaction includes monitoring the response time of the master device to the slave device sending write data, and monitoring the response time of the slave device to the master device returning read data.

[0019] As a preferred implementation, the method of monitoring the response time of the master-slave device interaction is:

[0020] Monitor the time for which the DATA and VAILD signals of the R and W channels remain valid. If the time for which the signals remain valid exceeds the preset threshold, perform subsequent processing to construct a virtual handshake signal.

[0021] As a preferred embodiment, when the master device sends a read request command or a write request command, the cache module sequentially caches the sending address of the read request command or the sending address of the write request command as a tag;

[0022] The write data from the master device or the read data from the slave device is stored under the corresponding tag.

[0023] As a preferred embodiment, the virtual handshake signal includes a slave device handshake signal simulating a response mechanism of the slave device, and a master device handshake signal simulating a response mechanism of the master device;

[0024] According to the deadlocked device, the corresponding virtual handshake signal is triggered to release the deadlock state of the device.

[0025] A second object of the present invention is to provide an anti-deadlock device based on AXI bus data reordering, the device comprising:

[0026] A deadlock monitoring unit, which monitors the response time of the interaction between the master and slave devices and activates the virtual handshake unit when the response time exceeds a preset threshold;

[0027] A data cache unit sequentially caches the sending addresses of read request commands or write request commands as tags;

[0028] The virtual handshake unit includes a host handshake unit, a slave handshake unit and a bus channel judgment module; the host handshake unit or the slave handshake unit sends a simulated response signal to the master device or the slave device according to the deadlocked channel and receives data from the bus; the bus channel judgment module judges the channel ID of the data received from the bus according to the bus interconnection channel information, stores it in the address tag corresponding to the data buffer module, and sends the data to the master device or the slave device in the order of the address tags.

[0029] As a preferred embodiment, the anti-deadlock device is integrated into the AXI bus interface between the bus interconnection channel and the master device or the slave device.

[0030] As a preferred implementation, the data cache unit uses BRAM to cache data.

[0031] A third object of the present invention is to provide a computer device comprising a memory, a processor and a computer program stored in the memory, wherein the processor executes the computer program to implement the steps of the above method.

[0032] A fourth object of the present invention is to provide a computer-readable storage medium having a computer program / instruction stored thereon, which implements the steps of the above method when the computer program / instruction is executed by a processor.

[0033] A fifth object of the present invention is to provide a computer program product comprising a computer program / instruction, which implements the steps of the above method when the computer program / instruction is executed by a processor.

[0034] The present invention has the following beneficial effects:

[0035] (1) The method of the present invention ensures that data is transmitted in the correct order by introducing data caching, reordering, and virtual handshaking mechanisms during data transmission, thereby avoiding deadlock while maintaining high system throughput and flexibility as much as possible. By dynamically adjusting the data transmission and response sequences, the present invention can effectively improve the system's data transmission efficiency and ensure the stability and reliability of the AXI bus in complex multi-master and multi-slave systems.

[0036] (2) The device of the present invention is suitable for master devices with high real-time requirements and low tolerance for bus delays, such as high-frame-rate LCD devices. By combining a data cache unit, a virtual handshake unit, and a deadlock monitoring unit, the device effectively solves the deadlock problem caused by bus delays or out-of-order transmission, ensuring the data transmission stability and real-time performance of high-frame-rate display devices. At the same time, the device of the present invention can maintain a high throughput in a complex multi-master and multi-slave environment, meeting the stringent requirements for high performance and low latency in similar scenarios.

[0037] (3) Different from the deadlock resolution method of abandoning the outstanding feature of the AXI bus by suspending the request, the present invention can configure the data depth of the data cache unit according to the device's delay requirements, thereby restoring the transmission capability of the outstanding transmission mechanism of the bus to a certain extent. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 Schematic diagram of data transmission in different situations when reading data.

[0039] Figure 2 Schematic diagram of data transmission in different situations in the data writing state.

[0040] Figure 3 Schematic diagram of the structure of the device of the present invention.

[0041] Figure 4 Schematic diagram of the device of the present invention connected to an AXI interconnect device.

[0042] Figure 5 Flowchart of the method of the present invention. DETAILED DESCRIPTION

[0043] In order to make the purpose, technical solutions and advantages of this application more clear, the following further describes this application in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0044] Figure 1 、 Figure 2 The data transmission situations in different situations when reading and writing data in the present invention and the prior art are explained to illustrate the working mechanism of the method of the present invention.

[0045] In the case of read deadlock, multiple master devices initiate read requests to multiple slave devices. When the AR channel ID is the same, the master device expects to receive responses in the order of the addresses in which the requests were issued. However, due to the out-of-order transmission of the slave devices or the delay of the transmission path, the master device cannot receive the data responses in the order in which the transmission addresses were sent, resulting in a deadlock. This causes multiple master devices to wait for multiple slave devices, causing the system to deadlock. The data reordering mechanism can receive the read data from the bus and reorder it when the response data of multiple read requests do not arrive in the order of the read address commands, causing a deadlock. The reordered data is sent to the master device to ensure that the data is received in the correct order of the read address commands, thus avoiding the occurrence of deadlock. Figure 1 shown.

[0046] In the case of write deadlock, multiple master devices initiate write requests to multiple slave devices. Due to path delays, register insertion to relieve timing tensions, or other hardware factors, the write requests received by the slave device may not arrive in the order of the write address commands sent by the master device, thereby incorrectly opening the write data channel to the master device. The master device needs to send write data according to the write address command, but the write data sent does not conform to the order in which the slave device receives the write address command, which will cause a write deadlock in a single master-slave device, thereby causing multiple master-slave devices to wait for each other, causing the system to deadlock. When the master device sends write data and the slave device does not accept it, the data reordering mechanism accepts the write data uploaded from the bus and reorders it, and sends the sorted data to the slave device to ensure that the data is received in the order of the write address commands received by the slave device to avoid deadlock. Figure 2 shown.

[0047] Based on the above principle, the present invention designs an anti-deadlock device based on AXI bus data reordering, such as Figure 3 As shown in FIG, the device has three modules: a data cache unit, a virtual handshake unit, and a deadlock monitoring unit. The anti-deadlock device is integrated into the bus interface of the master and slave devices, such as Figure 4 shown.

[0048] The deadlock monitoring unit monitors the response time of the interaction between the master and slave devices, and starts the virtual handshake unit when the response time exceeds a preset threshold.

[0049] The data cache unit sequentially caches the sending addresses of the read address command or the write address command as tags;

[0050] The virtual handshake unit includes a host handshake unit, a slave handshake unit and a bus channel judgment module; the host handshake unit or the slave handshake unit sends a simulated response signal to the master device or the slave device according to the channel where the deadlock occurs, and receives data from the bus. The bus channel judgment module judges the address corresponding to the channel of the data received from the bus according to the bus interconnection channel information, stores it in the address tag corresponding to the data buffer module, and sends the data to the master device / slave device in the order of the address tags.

[0051] In one embodiment, the deadlock monitoring unit monitors whether the current master and slave devices have entered a deadlock state. If, when data arrives, the master device or the slave device does not respond to the data, and the response time exceeds the monitoring judgment threshold, it is determined that a deadlock has occurred, and the data is no longer sent to the corresponding master and slave devices, and the virtual handshake unit receives the data.

[0052] In one embodiment, the deadlock monitoring unit monitors the responses of the R and W channels. Specifically, when a deadlock occurs, the data in the DATA channel and the data validity flags in the VAILD channel (RDATA and RVALID for the R channel, and WDATA and WVALID for the W channel) are maintained. In this embodiment, an upper time threshold is set to determine whether the validity flag of the data is maintained for a normal period of time. If the upper limit of the normal retention period is exceeded, a deadlock is determined. The virtual handshake unit is then activated to respond and resolve the deadlock.

[0053] During a read, the master responds to read requests and returns data via the R channel. On the R channel, if the master cannot accept the read data, neither RRESP nor RREADY will be valid. On the R channel, the slave's RDATA and RVALID will always contain valid data and the data will be valid, leading to deadlock.

[0054] During a write, the master sends write data to the slave via the W channel. If the slave cannot accept the write data, WREADY will not be valid. While the master is on the W channel, WDATA and WVALID will always contain valid data and the data is valid, leading to a deadlock.

[0055] Based on the above deadlock formation mechanism, we monitor the response of the R channel and the W channel to determine whether a deadlock occurs.

[0056] In one embodiment, the data cache unit uses BRAM to store address tags and read and write data. The BRAM is configured into multiple independent storage blocks according to the data depth, and the number of blocks is determined by the data cache depth. Figure 3 As shown, the contents cached by the data cache unit include address tags (ADDR1, ARRD2...ADDRN) and BURST transmission data packets under the corresponding address tags.

[0057] For read deadlock, the data cache unit caches the address of the read request command sent by the master device as a label, and reorders the data returned by different slave devices from different AXI channels according to this label. The final result can meet the requirement that the read data returned by the master device under the same ID must be consistent with the order of the read request commands sent.

[0058] In the case of write deadlock, the data cache unit caches the address of the write request command sent by the master device as a label, and caches the master device data sent to different AXI channels but trapped in write deadlock according to this label. If the write data is sent to the slave device in the order of the cached addresses, it cannot comply with the write request address order received by the slave device, because the order of the write data in the cache unit is the address order of the write request sent by the master device. Due to other hardware reasons such as path delays and register insertion beats, the order of write requests received by the slave device is unknown to the master device, so the data in the data cache unit can only be reordered and sent to see if it complies with the order of the slave device's received addresses (in this patent, the cached write data under the next address label in the data cache unit is selected, and the virtual handshake unit simulates the master device to send the write data to the slave device under the corresponding address label again to see if the slave device receives it).

[0059] Specifically, when reading data, the data cache unit sequentially caches the sending addresses of read address commands as tags. This storage method starts with the last block of the BRAM. When the next read address command is sent, the tag previously stored in the last storage block is moved to the previous storage block, and the new read command address is stored in the last storage block, and so on. When a read command address has already been moved to the first storage block and a new read address command is sent, the address of the first storage block is moved out and the new read address command is stored in the last storage block. If a read deadlock occurs, the bus interconnect channel determines the address of the slave module that responds to the read request and sends back the read data. The read data is then stored in the corresponding tag of the data cache unit, and the read data is reordered. In the event of a read deadlock, because the read data does not conform to the read address sequence initiated by the master device and cannot be accepted by the master device, the virtual handshake unit responds to the slave device's handshake and accepts the read data. Based on the bus interconnect channel information, the data is stored in the data cache unit under the corresponding tag, completing the reordering. When the address sequence of the master device initiating a read request is met, the virtual handshake unit simulates the slave device sending read data that meets the address sequence.

[0060] In the case of writing data, the data cache unit caches the sending address of the write address command in sequence as a label. The storage method is the same as that in the case of reading data. If a write deadlock occurs, the address of the slave module that has not responded to the write request to write the write data is determined through the bus interconnection channel, and the write data is stored under the corresponding label of the data cache unit for subsequent selection of the W channel. In the case of write deadlock, since the write data does not conform to the write address command sequence accepted by the slave device, the slave device cannot accept it. The virtual handshake unit responds to the handshake of the master device and accepts the write data, and stores it in the data cache unit under the corresponding label according to the bus interconnection channel information. The virtual handshake unit can simulate the master device sending write data to the slave device. If no response is detected from the slave device, the cached write data under the next address label in the data cache unit is selected, and the virtual handshake unit simulates the master device to send the write data to the slave device again.

[0061] In one embodiment, the execution process of each unit of the virtual handshake unit is described as follows:

[0062] The virtual handshake unit includes a host handshake unit, a slave handshake unit and a bus channel judgment module.

[0063] The host handshake unit is used to imitate the response mechanism of the slave device to release the deadlock state of the master device, or to send sorted read data to the master device. Its execution process is as follows:

[0064] (1) Releasing the master device deadlock: The master device is in a deadlock state because write data cannot be written to the slave device. On the W channel, WDATA and WVALID will always maintain valid data and the data validity bit. The host handshake unit is responsible for pulling WREADY high to transmit to the master device a signal that the slave device is ready to receive write data. After receiving the WREADY signal, the master device starts to update WDATA until the last batch of data and pulls WLAST high. After detecting that WLAST is pulled high, WREADY is restored and BRESP and BVAILD of the B channel are pulled high. When the BREADY signal of the master device is detected, BRESP and BVAILD of the B channel are restored, and the master device deadlock is released.

[0065] (2) Sending data to the master device: During the data reading process, if the ID is the same, the master device needs to receive the data sent by the slave device in the order in which the master device sends the read address. On the R channel, the host handshake unit sends data at RDATA and pulls RVAILD high. When it detects that RREADY and RRESP are pulled high at the same time, it sends the next batch of data until the last batch of data is sent. When the last batch of data is sent, RLAST is pulled high, and then the RDATA, RVAILD and RLAST signals are restored.

[0066] The slave handshake unit is used to imitate the response mechanism of the master device to release the deadlock state of the slave device, or to send sorted write data to the slave device. Its execution process is as follows:

[0067] (1) Releasing the slave device deadlock: The slave device is deadlocked because the read data cannot be written to the master device. On the R channel, RDATA and RVALID will always maintain valid data and the valid bit of the data. The slave handshake unit is responsible for pulling up RREADY and RRESP to signal to the slave device that the master device is ready to receive read data. After receiving the RREADY and RRESP signals, the slave device starts to update RDATA until the last batch of data is received and pulls up RLAST. After detecting that RLAST is pulled high, the WREADY and RRESP signals are restored, and the slave device deadlock is released.

[0068] (2) Sending data to the slave device: The reason for sending data to the slave device is that during the data writing process, the slave device needs to receive the data sent by the master device in the order in which the slave device receives the write address. On the W channel, the slave handshake unit sends data at WDATA and pulls up WVAILD. When it detects that WREADY is pulled high, it sends the next batch of data until the last batch of data is sent. When the last batch of data is sent, it pulls up WLAST, then restores WDATA and WVAILD signals and pulls up the BREADY signal of the B channel. When the BRESP and BVAILD signals of the slave device are detected, the BREADY signal of the B channel is restored.

[0069] The bus channel judgment module judges the high-order address information of the AXI channel according to the data transmitted by the bus interconnection channel, and stores the transmitted data in the corresponding address tag of the data cache unit.

[0070] Specifically, in the case of read deadlock, since the slave device will not transmit data out of order when receiving a read request from the same master device with the same ID, but will transmit the read data in the order of receiving the request, the bus channel judgment module will judge the high-order address information of the read data sent by the slave device based on the channel through which the read data is transmitted in the bus interconnection channel, and then cache it in the order of the address tags already cached in the data cache unit.

[0071] In the case of write deadlock, the master device sends write data in the order of the addresses in which it sends write requests. The bus channel judgment module reads the high-order address information of the write data sent by the master device based on the channel through which the write data is transmitted in the bus interconnection channel, and then caches it in the order of the address tags already cached in the data cache unit.

[0072] Based on the process shown above, in the case of read deadlock, the slave handshake unit simulates the master device's response to release the slave device's deadlock state, and the master handshake unit sends the sorted read data to the master device. In the case of write deadlock, the master handshake unit simulates the slave device's response to release the master device's deadlock state, and the slave handshake unit sends the sorted write data to the slave device.

[0073] When in use, the anti-deadlock device is connected to the bus interface of the master-slave device.

[0074] In one embodiment, the anti-deadlock device is connected to the bus interface of the master and slave devices, such as Figure 4 Due to the instability of the slave device, in this embodiment, the anti-deadlock device is integrated into the master device.

[0075] In one embodiment, the execution process of each module in the anti-deadlock device is as follows: Figure 5 As shown, the process includes the following:

[0076] Step 1: When the deadlock monitoring unit monitors the data interaction between the master and slave devices, whether the situation occurs when the detection judgment threshold is exceeded but no response occurs, and if so, the virtual handshake unit is started.

[0077] Step 2: The host handshake unit or the slave handshake unit of the virtual handshake unit simulates the response of the slave device or the master device, and accepts the read data from the slave device or the write data from the master device.

[0078] Step 3: The bus channel judgment module receives the data and determines the address information corresponding to the transmitted data according to the information of the bus interconnection channel, and stores the data under the corresponding address tag in the data cache unit. Each data entering the unit has an address tag for data identification.

[0079] Step 4: The host handshake unit or the slave handshake unit simulates the master device sending data to the slave device, or simulates the slave device sending data to the master device to solve the deadlock problem.

Claims

1. An anti-deadlock method based on AXI bus data reordering, characterized in that: The method comprises: Monitor the response time of master-slave device interactions; When the response time exceeds a preset threshold, a virtual handshake signal is constructed to complete the response to the master device or the slave device, and the write data from the master device or the read data from the slave device transmitted by the bus is read; The write data or the read data is stored in a cache module; wherein, when the master device sends a read request command or a write request command, the cache module sequentially caches the sending address of the read request command or the sending address of the write request command as a tag; the write data from the master device or the read data from the slave device is stored under the corresponding tag; After reordering the data in the cache module according to the address sequence of the read request command or the write request command, the data is sent to the master device or the slave device in sequence.

2. The method according to claim 1, characterized in that Monitoring the response time of the interaction between the master and slave devices includes monitoring the response time of the master device to the write data sent by the slave device, and monitoring the response time of the slave device to the read data returned by the master device.

3. The method according to claim 1, characterized in that The method of monitoring the response time of the master-slave device interaction is: Monitor the time for which the DATA and VAILD signals of the R and W channels remain valid. If the time for which the signals remain valid exceeds the preset threshold, perform subsequent processing to construct a virtual handshake signal.

4. The method according to claim 1, wherein The virtual handshake signal includes a slave device handshake signal simulating a response mechanism of the slave device, and a master device handshake signal simulating a response mechanism of the master device; According to the deadlocked device, the corresponding virtual handshake signal is triggered to release the deadlock state of the device.

5. An anti-deadlock device based on AXI bus data reordering, characterized in that: The device comprises: A deadlock monitoring unit, which monitors the response time of the interaction between the master and slave devices and activates the virtual handshake unit when the response time exceeds a preset threshold; A data cache unit, when the master device sends a read request command or a write request command, sequentially caches the sending addresses of the read request command or the write request command as tags, and stores the write data from the master device or the read data from the slave device under the corresponding tags; The virtual handshake unit includes a host handshake unit, a slave handshake unit and a bus channel judgment module; the host handshake unit or the slave handshake unit sends a simulated response signal to the master device or the slave device according to the deadlocked channel and receives data from the bus; the bus channel judgment module judges the channel ID of the data received from the bus according to the bus interconnection channel information, stores it in the address tag corresponding to the data buffer module, and sends the data to the master device or the slave device in the order of the address tags.

6. The anti-deadlock device according to claim 5, characterized in that: The anti-deadlock device is integrated into the bus interconnection channel and the AXI bus interface of the master device or the slave device.

7. A computer device comprising a memory, a processor, and a computer program stored in the memory, characterized in that: The processor executes the computer program to implement the steps of the method according to any one of claims 1 to 4.

8. A computer-readable storage medium having a computer program / instruction stored thereon, characterized in that: When the computer program / instruction is executed by a processor, the steps of the method according to any one of claims 1 to 4 are implemented.

9. A computer program product comprising a computer program / instructions, characterized in that When the computer program / instruction is executed by a processor, the steps of the method according to any one of claims 1 to 4 are implemented.

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