Network-on-chip construction method and device, medium and product

Abstract

The invention discloses a network-on-chip construction method and device, a medium and a product, and relates to the technical field of network-on-chip design, and the method comprises the steps: building a bottom layer cellular network based on a cellular topological structure, each node in the bottom layer network comprises a router and a processing unit, and carries out the data interaction with an adjacent node; the method comprises the following steps of: symmetrically dividing a network into a plurality of geometric sectors with the same coverage angle by taking a center node of a bottom-layer network as an original point, and selecting at least one node from each sector as a cross-layer node; and connecting the cross-layer nodes to corresponding nodes in the top-layer switched network through additional channels, wherein the top-layer network nodes only comprise routers and realize full interconnection through the additional channels. According to the invention, the long-distance communication is transferred to the top switching network through a hierarchical structure, the data transmission hop count and signal delay are effectively reduced, the hardware resource consumption is reduced, and the network expansibility and the communication efficiency are improved.

Description

Technical Field

[0001] The present application relates to the technical field of on-chip network design, and particularly to an on-chip network construction method, device, medium and product. Background Art

[0002] With the improvement of chip integration, traditional two-dimensional on-chip networks (NoCs) are difficult to meet the requirements of large-scale integrated circuits due to physical wire length and signal delay problems. In the prior art, although three-dimensional NoCs shorten the network diameter, there are through-silicon via (TSV) communication bottlenecks and structural complexity problems; hierarchical interconnect structures optimize long-distance communication by introducing a top-level switching network, but the Mesh network nodes have a high connection degree, resulting in large link overhead and routing complexity. Cellular topology networks have received attention because of their low node connection degree and low hardware resource consumption, but traditional cellular networks lack hierarchical design and it is difficult to balance local communication efficiency and global transmission performance.

[0003] Therefore, there is an urgent need for an improved on-chip network construction method to solve the problems of large hardware overhead, high routing complexity and insufficient scalability in traditional solutions. Summary of the Invention

[0004] The present application provides an on-chip network construction method, device, medium and product to solve the problems of large hardware overhead, high routing complexity and insufficient scalability in traditional solutions.

[0005] The present application provides an on-chip network construction method, which includes: Establishing a bottom-layer cellular network based on a cellular topology structure; each node in the bottom-layer cellular network includes a router and a processing unit, and each node in the bottom-layer cellular network exchanges data with adjacent nodes; Selecting at least one node as a cross-layer node from each area of the bottom-layer cellular network; each area is a geometric sector obtained by symmetrically dividing the bottom-layer cellular network with the central node of the bottom-layer cellular network as the origin, and the coverage angle of each sector is the same; Connecting the cross-layer nodes to the corresponding nodes in the top-level switching network through additional channels to obtain a hierarchical cellular on-chip network; each node in the top-level switching network includes a router and is fully interconnected through additional channels.

[0006] The present application also provides an electronic device, including: a memory for storing a computer program; a processor for implementing the steps of any of the above on-chip network construction methods when executing the computer program.

[0007] The present application also provides a computer-readable storage medium storing a computer program, wherein the computer program implements the steps of any of the above on-chip network construction methods when executed by a processor.

[0008] The present application also provides a computer program product, including a computer program, which implements the steps of any of the above-mentioned on-chip network construction methods when executed by a processor.

[0009] Through the present application, a bottom-layer network is established based on a cellular topology structure. Cross-layer nodes are selected by symmetrically dividing geometric sectors and connected to a fully interconnected top-layer switching network through additional channels, forming a hierarchical communication architecture. The bottom-layer cellular network adopts a hexagonal cellular topology structure, and each node only needs to be connected to 3 adjacent nodes (compared with the 4-degree connection of the traditional two-dimensional Mesh network), significantly reducing the number of physical links, greatly reducing the wiring area and power consumption. At the same time, the symmetrically divided geometric sectors ensure the uniform distribution of cross-layer nodes in the bottom-layer network, avoiding the wiring congestion problem caused by excessive node density in local areas and improving the overall link utilization rate. The cross-layer nodes are directly connected to the fully interconnected top-layer switching network through additional channels to build a high-speed transmission channel, so that cross-sector and long-distance data packets do not need to traverse the bottom-layer cellular nodes hop by hop, but directly reach the target area through the top-layer network. The geometric symmetry of the bottom-layer cellular topology is closely combined with the sector division rule, supporting the flexible expansion of the network. New nodes only need to expand outward in a hexagonal ring layer and follow the symmetric sector layout, without the need to redesign the routing logic or adjust the top-layer architecture. In addition, the division of labor between the bottom layer and the top layer in the hierarchical architecture (the bottom layer is responsible for adjacent communication, and the top layer is responsible for cross-region transmission) is compatible with existing on-chip network protocols, reducing the integration and migration costs with traditional Mesh or NoC systems. The symmetric sector division ensures the uniform distribution of cross-layer nodes in the bottom-layer network. Combined with the path diversity of the fully interconnected top-layer network, the communication traffic can be dynamically allocated to different sectors and top-layer links, avoiding the congestion problem caused by a single path for edge nodes in the traditional Mesh network. At the same time, the fully interconnected feature of the top-layer network provides redundant channels for critical paths and can automatically switch the routing in case of local link failures, improving the system reliability. The present application solves the trade-off problem between scalability, latency, and resource overhead of traditional on-chip networks by complementing the hardware efficiency advantages of the cellular topology with the global transmission capabilities of the hierarchical architecture. Description of the Drawings

[0010] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following will briefly introduce the drawings required for the description of the specific embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0011] Figure 1 Schematic diagram of the conversion process from a Mesh network to a cellular network provided by an embodiment of the present application; Figure 2 Schematic flow chart of a method for constructing a network - on - chip provided by an embodiment of the present application; Figure 3 Schematic diagram of a two - dimensional HM4 honeycomb topology network provided by an embodiment of the present application; Figure 4 Schematic diagram of the coordinate system of the HM3 honeycomb network provided by an embodiment of the present application; Figure 5 Schematic diagram of the area division of the HM3 honeycomb network provided by an embodiment of the present application; Figure 6 Schematic diagram of cross - layer nodes in the HM3 honeycomb network provided by an embodiment of the present application; Figure 7 Schematic diagram of the construction of type one in the hierarchical HM2 network topology provided by an embodiment of the present application; Figure 8 Schematic diagram of the construction of type one in the hierarchical HM3 network topology provided by an embodiment of the present application; Figure 9 Schematic diagram of the construction of type one in the hierarchical HM4 network topology provided by an embodiment of the present application; Figure 10 Schematic diagram of the construction of type two in the hierarchical HM2 network topology provided by an embodiment of the present application; Figure 11 Schematic diagram of the construction of type two in the hierarchical HM3 network topology provided by an embodiment of the present application; Figure 12 Schematic diagram of the construction of type two in the hierarchical HM4 network topology provided by an embodiment of the present application; Figure 13 Schematic diagram of the structure of a network - on - chip construction device provided by an embodiment of the present application; Figure 14 Schematic diagram of the structure of a computer device provided by an embodiment of the present application. Detailed implementation manners

[0012] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without making creative efforts belong to the protection scope of the present application.

[0013] It should be noted that in the description of this application, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed, or elements inherent to such process, method, article or device. The terms "first", "second", etc. in this application are used to distinguish similar objects, rather than to describe a specific order or sequence.

[0014] To enable those skilled in the art of this technology to better understand the solution of this application, the following further details this application in conjunction with the accompanying drawings and specific embodiments.

[0015] Combined with the specific application environment architecture or specific hardware architecture on which the execution of the on-chip network construction method depends, the specific application environment architecture or specific hardware architecture is described herein.

[0016] On-chip network (NoC) is a brand-new on-chip interconnection architecture that transmits data packets through the network on the NoC chip. Although NoC optimizes issues such as the scalability and parallel operation of SoC, it does not solve the problems of shortening physical connections and resulting signal delays. With the further improvement of chip integration, limited by the two-dimensional layout conditions, 2D NoC is difficult to ensure that key components are adjacent, difficult to shorten the critical path length and reduce signal delays. Although the three-dimensional network solves the problems existing in the two-dimensional on-chip network, shortens the network diameter, and increases path diversity, with good scalability, the three-dimensional structure has high complexity and there is a TSV communication bottleneck.

[0017] Since the Mesh structure is simple, with high regularity, symmetry and scalability, most current hierarchical on-chip networks are based on the Mesh network, retaining the advantages of the Mesh network while reducing network latency.

[0018] The honeycomb mesh network (referred to as the honeycomb network for short) has a topological structure similar to that of the Mesh network. The Mesh network can be transformed into a honeycomb network through appropriate changes, and the transformation process is shown in Figure 1. Since the connection degree of the honeycomb mesh nodes is only 3, which is 1 less than the node degree of the Mesh network, the hardware overhead of the honeycomb mesh is 25% less than that of the Mesh network, which is superior to the two-dimensional Mesh network. Since the honeycomb network has a topological structure and properties similar to those of the Mesh network, it can have a good foundation for studying the honeycomb mesh based on the research of the Mesh network, and can also greatly reduce the network cost compared to the Mesh network.

[0019] Therefore, the embodiments of this application provide an on-chip network construction method, and the method is described in detail in combination with the execution process of the on-chip network construction method.

[0020] First, introduce the terms involved in this application.

[0021] NoC: Network on Chip, on-chip network; SoC: System on Chip, system on chip; HM: Honeycomb Mesh, honeycomb mesh network; AHC: additional highway connections, additional high-speed path interconnection; TSV: Through Silicon Via, through-silicon via technology; PE: Processing Element, processing unit.

[0022] An embodiment of this application provides a method for constructing an on-chip network. The specific process of this method is as Figure 2 shown and specifically includes the following steps.

[0023] S201. Establish a bottom-layer honeycomb network based on a honeycomb topology; each node in the bottom-layer honeycomb network includes a router and a processing unit, and each node in the bottom-layer honeycomb network exchanges data with adjacent nodes.

[0024] Specifically, the bottom-layer network adopts a honeycomb topology, that is, a two-dimensional network formed by periodically arranging multiple regular hexagonal units. Each hexagonal vertex is a network node, and the nodes are connected by edges to form a honeycomb-like grid. Each node includes a router (responsible for packet forwarding) and a processing unit (PE) (performing computing tasks), and the two are connected by an internal bus. Each node only communicates directly with 3 adjacent nodes, and data exchange is realized through physical links.

[0025] S202. Select at least one node from each area of the bottom-layer honeycomb network as a cross-layer node.

[0026] Specifically, each area is a geometric sector obtained by symmetrically dividing the bottom-layer honeycomb network with the central node of the bottom-layer honeycomb network as the origin, and the coverage angle of each sector is the same. For example, when divided into six sectors, each sector covers 60°. At least one node is selected as a cross-layer node in each sector (area), and the selection criteria need to be met: the number of cross-layer nodes selected in each sector is equal and distributed along the central symmetry axis. The cross-layer nodes need to cover all the ring layers of the bottom-layer network.

[0027] S203. Connect the cross-layer nodes to the corresponding nodes in the top-layer switching network through additional channels to obtain a hierarchical honeycomb on-chip network.

[0028] Specifically, each node in the top-level switching network contains a router and is fully interconnected through additional channels. The additional channels are dedicated physical links, independent of the local communication links of the underlying cellular network, and are used to connect cross-layer nodes to the top-level switching network. Each cross-layer node is connected to a designated node in the top-level network one-to-one or one-to-many through additional channels. For example, cross-layer nodes in the same sector may share a top-level node.

[0029] The method for constructing an on-chip network in this embodiment is based on a cellular topology to establish the underlying network, selects cross-layer nodes by symmetrically dividing geometric sectors, and uses additional channels to connect to a fully interconnected top-level switching network to form a hierarchical communication architecture. The underlying cellular network adopts a hexagonal cellular topology, and each node only needs to be connected to 3 adjacent nodes (compared with the 4-degree connection of the traditional two-dimensional Mesh network), significantly reducing the number of physical links, greatly reducing the wiring area and power consumption; at the same time, the symmetrically divided geometric sectors ensure the uniform distribution of cross-layer nodes in the underlying network, avoiding wiring congestion problems caused by excessive node density in local areas and improving the overall link utilization rate. By directly connecting cross-layer nodes to the fully interconnected top-level switching network through additional channels, a high-speed transmission channel is constructed, enabling cross-sector and long-distance data packets to directly reach the target area through the top-level network without having to hop through the underlying cellular nodes one by one. The geometric symmetry of the underlying cellular topology is closely combined with the sector division rule, supporting the flexible expansion of the network. New nodes only need to expand outward in a hexagonal ring layer and follow the symmetric sector layout without having to redesign the routing logic or adjust the top-level architecture; in addition, the division of labor between the underlying and top-level in the hierarchical architecture (the underlying is responsible for adjacent communication, and the top-level is responsible for cross-region transmission) is compatible with existing on-chip network protocols, reducing the integration and migration costs with traditional Mesh or NoC systems. The symmetric sector division ensures the uniform distribution of cross-layer nodes in the underlying network. Combining the path diversity of the fully interconnected top-level network, the communication traffic can be dynamically allocated to different sectors and top-level links, avoiding congestion problems caused by a single path for edge nodes in traditional Mesh networks; at the same time, the fully interconnected feature of the top-level network provides redundant channels for critical paths and can automatically switch routes in case of local link failures, improving system reliability. This application solves the trade-off problem between scalability, latency, and resource overhead in traditional on-chip networks by complementing the hardware efficiency advantages of the cellular topology with the global transmission capabilities of the hierarchical architecture.

[0030] In an alternative embodiment, each node in the underlying cellular network has a data interaction interface for data interaction within and between nodes. The data interaction interface includes a processing unit interface and a routing interface. The processing unit interface is used for local data interaction between the processing units and routers of each node in the underlying cellular network. The routing interface is used for data interaction between adjacent nodes in the underlying cellular network. By configuring a data interaction interface for each node, the communication paths within the node (between the processing unit and the router) and between nodes (between adjacent routers) are clearly distinguished, avoiding resource competition caused by mixed data streams. The physical isolation of the interface (such as an independent bus or channel) enables parallel execution of local computing and network transmission, improving the utilization rate of the processing unit (PE) within the node and reducing the waiting latency of cross-node communication. By separating the data interaction interface into a processing unit interface and a routing interface, that is, the processing unit interface is directly connected to the PE and the router, the local data access path is shortened (such as the distance from the register to the router), reducing the single-hop transmission delay. The routing interface independently occupies physical link resources to ensure that data forwarding between adjacent nodes is not interfered by local computing tasks, improving network throughput. The interface separation avoids arbitration delay caused by the simultaneous access of the PE and the router to the same bus, meeting the parallel communication requirements of multi-core chips.

[0031] In an alternative embodiment, the cellular topology is a two-dimensional cellular network composed of multiple hexagonal rings; the additional channel is a bidirectional high-speed link. Using a two-dimensional cellular network (instead of a three-dimensional stack) avoids the complexity of the TSV process, is compatible with the existing chip manufacturing process, and reduces the implementation cost. The bidirectional high-speed link as an additional channel improves the signal transmission rate by increasing the line width or using a low-impedance metal layer, compensating for the physical distance disadvantage of the cross-layer link, and ensuring that the single-hop latency of the top-layer network is lower than the sum of the multi-hop latencies of the bottom layer. In addition, the underlying cellular network includes multiple ring layers. The distribution of the ring layers includes: expanding outward from the hexagonal ring at the center of the two-dimensional cellular network according to the size of the underlying cellular network, and sequentially numbering the hexagonal rings. Through the hexagonal ring layer numbering mechanism (such as ring 1 to ring t), the number of ring layers (t value) can be selected according to the computing requirements (such as the number of cores) to ensure that the network scale matches the computing load. The ring layer numbering provides a logical basis for cross-layer node selection, making the distribution of cross-layer nodes consistent with the network expansion direction and reducing the hop count fluctuation of long-distance communication.

[0032] In an alternative embodiment, the size of the underlying cellular network is an integer greater than 1. Defining the network size t≥2 (such as HM2 to HM6) ensures that the cellular network has practical application value. When t = 1 (single hexagon), a hierarchical structure cannot be formed. When t≥2, the hierarchical communication ability of the network is forced. When t≥2, the symmetric region division and cross-layer node selection rules can be effectively executed, avoiding the path redundancy problem of the single-ring network.

[0033] In an alternative embodiment, the number of cross-layer nodes is determined by the size of the underlying cellular network; and the spacing between cross-layer nodes in the same ring layer is equal, and the cross-layer nodes in different ring layers are aligned along the cellular symmetry axis. Through the equal-spacing and symmetry-axis alignment rules, the cross-layer nodes in the same ring layer are evenly distributed, avoiding bandwidth contention caused by dense cross-layer nodes in local areas; the nodes in different ring layers are aligned along the symmetry axis, making the additional channel (AHC) present a straight-line or periodic broken-line layout in the chip layout, reducing routing conflicts and improving the utilization rate of routing resources.

[0034] In an alternative embodiment, the selection of cross-layer nodes includes: Taking the center point of the underlying cellular network as the origin, three coordinate axes with an included angle of 120 degrees with each other are set, and the underlying cellular network is divided into six regions; along the positive direction of each coordinate axis, a series of parallel lines perpendicular to the coordinate axis are made, and each parallel line passes through the nodes of the underlying cellular network to form a positive-direction sawtooth chain; starting from the origin, the coordinate values of all nodes on the first sawtooth chain perpendicular to the positive direction of the coordinate axis are 1, the second is 2, and so on in sequence; along the negative direction of each coordinate axis, a series of parallel lines perpendicular to the coordinate axis are made, and each parallel line passes through the nodes of the underlying cellular network to form a negative-direction sawtooth chain; starting from the origin, the coordinate values of the nodes on the first negative-direction vertical chain are 0, the second is -1, and so on in sequence; according to the serial numbers of the sawtooth chains in the coordinate axis direction where each node in the underlying cellular network is located, the coordinate values of each node are determined; for any region in the underlying cellular network, the nodes with coordinate values equal to the ring layer number are used as cross-layer nodes.

[0035] Through the coordinate axis division and sawtooth chain coordinate rules, accurate cross-layer node positioning is achieved. The six regions divided by the three 120-degree coordinate axes cover the entire network, ensuring no blind spots in the selection of cross-layer nodes; the sawtooth chain coordinate values (such as the ring layer number) provide a unique selection criterion for cross-layer nodes, avoiding layout deviations caused by manual intervention or random selection; the cross-layer node coordinate values are consistent with the ring layer number, ensuring that the physical path of the cross-layer link (AHC) is consistent with the network expansion direction and shortening the average length of the additional channel.

[0036] In an alternative embodiment, the nodes of the top-level switching network do not have data interaction interfaces; the number of nodes in the top-level switching network is equal to the total number of ring layers of the underlying cellular network. The top-level nodes are not connected to data interaction interfaces (such as PEs or memories), only for data forwarding, avoiding the competition of computing tasks and communication tasks for router resources and improving the throughput of the top-level network; the number of top-level nodes is equal to the number of underlying ring layers (such as HM4 corresponding to 4 top-level nodes), ensuring that each ring layer's cross-layer nodes have exclusive top-level routing resources and avoiding congestion caused by shared nodes in multiple ring layers.

[0037] In an alternative embodiment, connecting the cross-layer nodes to the corresponding nodes in the top-level switching network through an additional channel includes: Connect the cross-layer nodes in the same hexagonal ring to the same node in the top-layer switching network through additional channels; or, connect the cross-layer nodes in adjacent regions to the same node in the top-layer switching network.

[0038] Connecting the cross-layer nodes in the same hexagonal ring to the same node in the top-layer switching network includes: Based on the total number of ring layers in the underlying cellular network, confirm the number of nodes in the top-layer switching network; connect all cross-layer nodes in the same hexagonal ring layer in the underlying cellular network to a single corresponding node in the top-layer switching network through additional channels. Divide the six regions of the underlying cellular network into three groups of cross-region node clusters; the number of nodes in the top-layer switching network is equal to the number of clusters; connect the cross-layer nodes of each cluster to the same node in the top-layer switching network through additional channels.

[0039] Provide two alternative cross-layer connection strategies to adapt to different design requirements. Type one is the same-ring connection, where cross-layer nodes in the same ring layer share the top-layer nodes, reducing the scale of the top-layer network (number of nodes = number of ring layers) and the wiring complexity; type two is the cross-region connection, where cross-layer nodes in adjacent regions share the top-layer nodes (such as three pairs of regions), further reducing the top-layer nodes to 3, which is suitable for chip designs with limited area. Through one-to-one mapping between the ring layer and the top-layer nodes, the cross-layer communication of each ring layer is processed by an independent top-layer node, avoiding cross-interference of data flows across ring layers; the failure of a top-layer node in a single ring layer only affects the communication of that ring layer, improving the network fault tolerance. Through regional clustering connection, only 3 top-layer nodes are needed to cover the entire network, greatly reducing the number of top-layer routers and the area overhead; the three clusters are symmetrically distributed along the coordinate axes, making the wiring path of the additional channels (AHC) exhibit 120-degree rotational symmetry and simplifying the physical design rules.

[0040] In addition, in the above steps, during the selection process of the cross-layer nodes, the selection of the cross-layer nodes further includes: real-time monitoring of the link utilization rate of the underlying cellular network, and when the link utilization rate of any sector exceeds the preset threshold, switching the connection mode of the cross-layer nodes to the same-ring layer aggregation connection mode; when the link utilization rates of all sectors are lower than the threshold, switching to the cross-region cluster connection mode. The bandwidth of the additional channels is dynamically allocated according to the ring layer number where the cross-layer nodes are located. The bandwidth of the additional channel connecting the cross-layer nodes with the ring layer number n is n times the baseband bandwidth, where n ≥ 1; when selecting the routing path of the data packet, preferentially transmit the data packet with the largest cross-ring layer number through the additional channel with the highest bandwidth. When a cross-layer link failure is detected, perform the following steps: according to the coordinate difference of the failed link, map the target path to the mirror sector symmetric to the current sector to generate a redundant communication path; update the routing priority table of the corresponding node in the top-layer switching network and raise the priority of the redundant path to the highest level.

[0041] In summary, the on-chip network construction method provided by the embodiments of the present application constructs an efficient, low-power, and scalable on-chip interconnection system through the collaborative design of a cellular topology structure, symmetric sector division, cross-layer node dynamic selection rules, and a fully interconnected top-layer switching network. The deep correlation and complementary effects among its technical features significantly optimize the network performance and resource utilization rate. The underlying network based on the cellular topology adopts a hexagonal ring layer expansion structure, and each node only needs to be connected to 3 adjacent nodes. Compared with the 4-degree connection of the traditional Mesh network, the number of hardware links is significantly reduced. At the same time, the geometric symmetry of the hexagon provides a physical basis for subsequent cross-layer node selection and sector division. The nodes in the underlying network achieve isolated communication between the local processing unit (PE) and the router through a modular data interaction interface, avoiding data flow conflicts. The standardized design of the interface is further seamlessly compatible with the additional channels of the top-layer switching network, ensuring protocol consistency during cross-layer data transmission and reducing the logical overhead of heterogeneous network integration. The underlying network is symmetrically divided into six 60-degree sectors through a three-axis coordinate system, and cross-layer nodes are accurately located based on the zigzag chain coordinate values, so that the cross-layer nodes are evenly distributed along the cellular symmetry axis and expand layer by layer outward in combination with the ring layer numbering rule, forming a node selection framework with clear logic. This design not only ensures the regularity of the physical layout of cross-layer nodes (for example, the node spacing in the same ring layer is equal, and different ring layers are aligned along the symmetry axis), but also is deeply coupled with the fully interconnected architecture of the top-layer switching network: when cross-layer nodes are connected to the top layer through additional channels, two connection modes can be selected according to the network scale. In Mode 1, the cross-layer nodes in the same hexagonal ring layer are aggregated to a single top-layer node, and the network diameter is compressed to the lowest through the top-layer direct path; in Mode 2, the cross-layer node clusters in adjacent sectors are connected to 3 top-layer nodes, simplifying the wiring complexity by reducing the number of top-layer nodes, while retaining the natural support of the cellular symmetry for load balancing. The two modes can be dynamically adapted to different scenario requirements. For example, in high-performance computing scenarios, Mode 1 is preferably used to minimize latency, while area-sensitive chips can choose Mode 2 to reduce the wiring density. The fully interconnected characteristics of the top-layer switching network and the low connectivity of the underlying cellular network are complementary: the top-layer nodes only contain routers and are not connected to processing units, focusing on the high-speed relay of cross-region data, while the underlying nodes efficiently process adjacent communications through local interfaces, forming a division of labor system of "fine-grained local processing at the bottom layer and high-speed global processing at the top layer". This hierarchical architecture transfers long-distance communication traffic to the top layer through additional channels, significantly reducing the number of hops at the bottom layer. At the same time, the symmetric scalability of the cellular topology supports flexible expansion from HM2 to HM6 scale. New nodes only need to extend outward according to the hexagonal ring layer rule, without reconstructing the routing logic or adjusting the top-layer mapping relationship, greatly improving the scalability of the network.In addition, the symmetric distribution of cross-layer nodes combined with the path diversity of the fully interconnected top layer enables dynamic traffic allocation to different ring layers and sectors, avoiding congestion problems at edge nodes in traditional Mesh networks. The redundant paths in the top-layer network further enhance the fault tolerance ability, allowing for rapid routing switching through mirror-symmetric sectors in case of local link failures, thus improving system reliability. Through the close linkage of geometric rules, hierarchical division of labor, and dynamic adaptation mechanisms, each technical feature achieves multi-dimensional performance breakthroughs. At the hardware level, the low cellular connectivity and modular interface design reduce the wiring area, and the bi-directional high-speed characteristics of the additional channels improve the top-layer throughput. At the performance level, the hierarchical architecture significantly compresses the maximum end-to-end hop count, reducing the average latency and achieving load balancing through symmetric sector and ring layer rules. At the scalability level, the hexagonal ring layer expansion and coordinate system support seamless scale expansion, and the two top-layer connection modes provide flexible choices for different application scenarios. This method fundamentally solves the contradiction among scalability, latency, and resource overhead in traditional on-chip networks.

[0042] Based on the on-chip network construction method provided in the above embodiments, a specific example will be used for detailed description below.

[0043] This embodiment also provides a hierarchical cellular on-chip network topology structure based on the on-chip network construction method of the above embodiments. The bottom layer of the proposed hierarchical cellular interconnected on-chip network is a two-dimensional cellular topology network, and its top layer is a switching network interconnected using additional high-speed channels (AHC). This structure enables long-distance and multi-hop data packets in the on-chip network to be directly transmitted through the top-layer fast channels, effectively reducing the hop count and network latency of network transmission. There are two different types of connection methods between the bottom-layer network and the top-layer network of the hierarchical cellular network proposed in this example. Type one has a smaller network diameter, and type two is easier to implement in hardware in terms of wiring layout. The hierarchical cellular interconnected topology network proposed in this example is superior to hierarchical Mesh networks (CMesh and CHMesh), with advantages such as a small network diameter, small network latency, good network scalability, low structural complexity, small link overhead, and strong load capacity.

[0044] The bottom-layer network of the hierarchical cellular on-chip network topology structure in this example is constructed based on the cellular topology structure. The cellular topology structure consists of many hexagons. The definition of the cellular network is as follows: For the cellular grid topology, the network consists of one hexagon with a size of 1, denoted as HM1. Add a hexagonal ring (i.e., 6 hexagons) to the boundary (six sides) of HM1 to obtain a cellular network with a size of 2, denoted as HM2. Similarly, add a hexagonal ring to the boundary of HM(t - 1) to obtain a cellular network with a size of t, denoted as HMt. A typical cellular topology network can be referred to Figure 3 , Figure 3 as a two-dimensional HM4 cellular topology network, Figure 3It includes ordinary routing nodes and bidirectional links in the underlying cellular network.

[0045] Based on the method for constructing a network-on-chip according to the above embodiments, the hierarchical cellular network-on-chip topology structure of this example needs to use the coordinate system of the cellular network for area division. This example uses the coordinate system as shown in Figure 4 shown, Figure 4 which is the HM3 cellular network coordinate system, Figure 4 and includes ordinary routing nodes and bidirectional links. The coordinate axes , , intersect at the center point of the cellular network. The positive semi-axes of the three coordinate axes divide the cellular network evenly into three parts. On a certain coordinate axis ( , or ), nodes with the same coordinates form a zigzag chain perpendicular to this axis. If the node coordinates need to be determined, first determine the coordinates of the node, find a straight line passing through the center point of the cellular network and perpendicular to the axis, denoted as (as shown by the dashed line in Figure 4 ). Taking this straight line as the boundary, along the positive direction, the coordinate values of all nodes on the first zigzag chain perpendicular to the axis and parallel to are 1, and the coordinate values of all nodes on the second zigzag chain perpendicular to the axis and parallel to are 2, and so on to obtain the coordinate values of the positive semi-axis of the axis; along the negative direction, the coordinate values of all nodes on the first zigzag chain perpendicular to the axis and parallel to are 0, and the coordinate values of all nodes on the second zigzag chain perpendicular to the axis and parallel to are -1, and so on to obtain the coordinate values of the negative semi-axis of the axis. Similarly, the and coordinate values of the node are obtained.

[0046] Based on the above Figure 3 cellular topology structure and Figure 4 cellular network coordinate system, the specific construction of the hierarchical cellular network-on-chip topology structure of this example is as follows.

[0047] This example is based on cellular networks with sizes ranging from 2 to 6, namely HM2, HM3, HM4, HM5, and HM6. The hierarchical cellular interconnected on-chip network proposed in the present invention has a two-dimensional cellular network at the bottom layer, which is mainly responsible for communication between adjacent points. Each node consists of a router and a PE unit, and each node is connected to a port. The top layer network is connected using a fully interconnected method and is a switching network that uses additional highway connections (AHC). The nodes in the network only contain routers, which are mainly responsible for communication, and each node is not connected to a port. The nodes in the bottom layer network that are connected to the top layer network through additional high-speed channels are defined as cross-layer nodes, and the additional high-speed channels between the two layers are cross-layer links.

[0048] The specific design process of the hierarchical cellular network is as follows.

[0049] First, it is necessary to determine the scale of the bottom layer cellular network.

[0050] To determine the scale of the bottom layer network of the cellular hierarchical network, it is required that the size of the cellular network HMt is greater than 1, that is . Taking HM3 as an example for illustration, as Figure 5 shown. According to the straight line , , the entire cellular network is divided into 6 regions, which are sequentially denoted as Region I, Region II, Region III, Region IV, Region V, and Region VI in a clockwise direction. From the center of the cellular network outwards, the hexagonal rings are sequentially denoted as Ring 1, Ring 2, Ring 3, and so on.

[0051] Next, it is necessary to determine the cross-layer nodes in each region.

[0052] The cross-layer nodes in the HM3 network are as Figure 6 shown. The nodes in the bottom layer network that are connected to the top layer network through additional high-speed channels are defined as cross-layer nodes. The cross-layer nodes in each region are as follows: In Region I, the nodes on Ring are cross-layer nodes; In Region II, the nodes on Ring are cross-layer nodes; In Region III, the nodes on Ring are cross-layer nodes; In Region IV, the nodes on Ring are cross-layer nodes; In Region V, the nodes on Ring is a cross-layer node; In Region VI, the nodes on the ring are cross-layer nodes.

[0053] Figure 6 The cross-layer nodes in the cellular network are marked, including the ordinary routing nodes, two-way links, cross-layer nodes in Ring 1, and cross-layer nodes in Ring 2 in the underlying cellular network.

[0054] Finally, the top-level network needs to be constructed.

[0055] The construction of the top-level network includes two types.

[0056] Type 1 is to connect the cross-layer nodes in the same hexagonal ring in the underlying cellular network to the same node in the top-level network. The number of routing nodes in the top-level network is determined by the size of the underlying HMt network. That is, for the underlying HMt network, its top-level network has nodes, and the connection method of these nodes is fully interconnected.

[0057] The construction of Type 1 in the hierarchical HM2 network topology is as Figure 7 shown, Figure 7 which includes ordinary routing nodes, cross-layer nodes, nodes in the top-level network, two-way links, and additional high-speed channels, where the additional high-speed channels are also two-way transmission.

[0058] The construction of Type 1 in the hierarchical HM3 network topology is as Figure 8 shown. In Figure 8 it includes ordinary routing nodes, cross-layer nodes in Ring 1, nodes in the top-level network connected to the cross-layer nodes in Ring 1, cross-layer nodes in Ring 2, nodes in the top-level network connected to the cross-layer nodes in Ring 2, two-way links, and additional high-speed channels.

[0059] The construction of Type 1 in the hierarchical HM4 network topology is as Figure 9 shown, Figure 9 which includes ordinary routing nodes, cross-layer nodes in Ring 1, nodes in the top-level network connected to the cross-layer nodes in Ring 1, cross-layer nodes in Ring 2, nodes in the top-level network connected to the cross-layer nodes in Ring 2, cross-layer nodes in Ring 3, nodes in the top-level network connected to the cross-layer nodes in Ring 3, two-way links, and additional high-speed channels.

[0060] Type 2 is to connect the cross-layer nodes in the underlying network regions I and II to the same node in the top-layer network through additional high-speed paths; connect the cross-layer nodes in the underlying network regions III and IV to the same node in the top-layer network through additional high-speed paths; connect the cross-layer nodes in the underlying network regions V and VI to the same node in the top-layer network through additional high-speed paths. Therefore, there are 3 nodes in the top-layer network, and these 3 nodes are fully interconnected.

[0061] Figure 10 is the construction of Type 2 in the hierarchical HM2 network topology, Figure 11 is the construction of Type 2 in the hierarchical HM3 network topology, Figure 12 is the construction of Type 2 in the hierarchical HM4 network topology. Figure 10 、 Figure 11 and Figure 12 all contain ordinary routing nodes, cross-layer nodes in regions I and II, nodes in the top-layer network connected to the cross-layer nodes in regions I and II, cross-layer nodes in regions III and IV, nodes in the top-layer network connected to the cross-layer nodes in regions III and IV, cross-layer nodes in regions V and VI, nodes in the top-layer network connected to the cross-layer nodes in regions V and VI, bidirectional links, and additional high-speed channels.

[0062] Through the above three steps, a hierarchical cellular on-chip network topology is constructed. Compared with other networks, the comparison results are shown in Table 1. From the comparison of the Mesh network and the hierarchical Mesh network, as well as the HM network and the hierarchical HM network in Table 1, it can be seen that the hierarchical structure can effectively reduce the network diameter, thereby reducing the number of hops and network latency of transmission. The network diameter refers to the maximum value of the shortest distance between all node pairs in the network, and the network diameter largely affects the network latency.

[0063] As can be seen from Table 1, when the number of network nodes is the same, the top-layer node connectivity of the CMesh network and the hierarchical cellular network is not much different, but the number of top-layer nodes and the diameter of the hierarchical cellular network proposed in the present invention are both smaller than those of the CMesh network, which indicates that the hierarchical cellular network has smaller resource overhead and latency.

[0064] As can be seen from Table 1, when the number of network nodes is the same, the number of top-layer nodes and the top-layer node connectivity of the CHMesh network and the hierarchical cellular network are not much different, but the diameter of the hierarchical cellular network proposed in the present invention is smaller than that of the CHMesh network, which indicates that the hierarchical cellular network has smaller latency.

[0065] The complexity of the interconnection network topology is related to the connectivity and the number of links. The Mesh network is widely used in the on-chip network due to its simple structure. As can be seen from Table 1, when the number of nodes is not much different, the number of links in the hierarchical cellular network is between that of the CMesh network and the CHMesh network, and the connectivity of the network nodes is not much different. Therefore, the hierarchical cellular interconnection network proposed by the present invention is easy to be implemented in hardware and has broad application prospects.

[0066] In summary, the performance of the hierarchical cellular on-chip network topology proposed in this example is superior to the four network topologies in Table 1, and has the advantages of small network delay, good network scalability, simple structure, easy hardware implementation, etc. The bottom layer of the proposed hierarchical cellular interconnected on-chip network is a two-dimensional cellular topology network, and its top layer is a switching network using additional high-speed channel interconnection (AHC). This structure can enable long-distance and multi-hop data packets in the on-chip network to be directly transmitted through the top-layer fast channel, effectively reducing the number of hops and network delay of network transmission. There are two different types of connection methods between the bottom-layer network and the top-layer network of the hierarchical cellular network proposed by the present invention. Type one has a smaller network diameter, and type two is easier to be implemented in hardware in terms of wiring layout. In short, the hierarchical cellular interconnection topology network proposed by the present invention is superior to the hierarchical Mesh network (CMesh and CHMesh), and has the advantages of small network diameter, small network delay, good network scalability, low structural complexity, small link overhead, strong load capacity, etc., and has broader application prospects.

[0067] Table 1

[0068] Through the description of the above embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be implemented by means of software plus a necessary general hardware platform. Of course, it can also be implemented by hardware, but in many cases, the former is a better implementation method.

[0069] The embodiment of the present application also provides an on-chip network construction device, and the structure of the device is as Figure 13 shown, including: A bottom-layer network construction module 1301, configured to establish a bottom-layer cellular network based on a cellular topology structure; each node in the bottom-layer cellular network includes a router and a processing unit, and each node in the bottom-layer cellular network exchanges data with adjacent nodes; A cross-layer node selection module 1302, configured to select at least one node as a cross-layer node from each area of the bottom-layer cellular network; each area is a geometric sector obtained by symmetrically dividing the bottom-layer cellular network with the central node of the bottom-layer cellular network as the origin, and the coverage angle of each sector is the same; A connection module 1303, configured to connect cross-layer nodes to corresponding nodes in a top-layer switching network through additional channels, thereby obtaining a hierarchical cellular network-on-chip; each node in the top-layer switching network includes a router and is fully interconnected through the additional channels.

[0070] In an alternative embodiment, the cross-layer node selection module 1302 is specifically configured to: Taking the center point of the underlying cellular network as the origin, three coordinate axes with an angle of 120 degrees to each other are set, and the underlying cellular network is divided into six regions; Along the positive direction of each coordinate axis, a series of parallel lines perpendicular to the coordinate axis are made, and each parallel line passes through the nodes of the underlying cellular network to form a positive-direction sawtooth chain; starting from the origin, the coordinate values of all nodes on the first sawtooth chain perpendicular to the positive direction of the coordinate axis are 1, the second is 2, and so on incrementally; Along the negative direction of each coordinate axis, a series of parallel lines perpendicular to the coordinate axis are made, and each parallel line passes through the nodes of the underlying cellular network to form a negative-direction sawtooth chain; starting from the origin, the coordinate values of the nodes on the first negative-direction perpendicular chain are 0, the second is -1, and so on decrementally; Determine the coordinate values of each node according to the serial numbers of the sawtooth chains in the coordinate axis directions where the nodes in the underlying cellular network are located; For any region in the underlying cellular network, the nodes with coordinate values equal to the ring layer number are used as cross-layer nodes.

[0071] In an alternative embodiment, the connection module 1303 is specifically configured to: Connect the cross-layer nodes located in the same hexagonal ring to the same node in the top-layer switching network through additional channels; or connect the cross-layer nodes in adjacent regions to the same node in the top-layer switching network.

[0072] In an alternative embodiment, the connection module 1303 is further configured to: Based on the total number of ring layers of the underlying cellular network, confirm the number of nodes in the top-layer switching network; Connect all the cross-layer nodes located in the same hexagonal ring layer in the underlying cellular network to a single corresponding node in the top-layer switching network through additional channels.

[0073] In an alternative embodiment, the connection module 1303 is further configured to: Divide the six regions of the underlying cellular network into three groups of cross-region node clusters; the number of nodes in the top-layer switching network is equal to the number of clusters; Connect the cross-layer nodes of each cluster to the same node in the top-layer switching network through additional channels.

[0074] For the description of the features in the corresponding embodiments of the on-chip network construction device, reference can be made to the relevant descriptions in the corresponding embodiments of the on-chip network construction method, which will not be elaborated here one by one.

[0075] An embodiment of the present application further provides an electronic device, such as Figure 14 as shown, including a memory 14 and a processor 20. A computer program is stored in the memory 10, and the processor 20 is configured to run the computer program to execute the steps in any of the above embodiments of the on-chip network construction method.

[0076] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored. The computer program is configured to execute the steps in any of the above embodiments of the on-chip network construction method when running.

[0077] In an exemplary embodiment, the above computer-readable storage medium may include, but is not limited to: USB flash drives, read-only memories (ROMs), random access memories (RAMs), mobile hard disks, magnetic disks, or optical discs, etc., all kinds of media that can store computer programs.

[0078] An embodiment of the present application further provides a computer program product. The above computer program product includes a computer program, and when the computer program is executed by a processor, it implements the steps in any of the above embodiments of the on-chip network construction method.

[0079] An embodiment of the present application further provides another computer program product, including a non-volatile computer-readable storage medium. The non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, it implements the steps in any of the above embodiments of the on-chip network construction method.

[0080] Those skilled in the art can further realize that the units and algorithm steps of each example described in combination with the embodiments disclosed in this article can be implemented by electronic hardware, computer software, or a combination of the two. To clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described according to functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present application.

[0081] The above has introduced in detail a method, system, device, equipment and storage medium for constructing a network-on-chip provided by the present application. Specific examples are used in this article to elaborate on the principle and implementation manner of the present application. The description of the above embodiments is only used to help understand the method and its core idea of the present application. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the protection scope of the claims of the present application.

Claims

1. A method for constructing a network on chip, characterized in that: The method comprises: An underlying cellular network is established based on a cellular topology structure; each node in the underlying cellular network includes a router and a processing unit, and each node in the underlying cellular network interacts with adjacent nodes for data; Selecting at least one node from each area of ​​the underlying cellular network as a cross-layer node; each area is a geometric sector obtained by symmetrically dividing the underlying cellular network with a central node of the underlying cellular network as an origin, and each sector has the same coverage angle; The cross-layer nodes are connected to corresponding nodes in the top-level switching network through additional channels to obtain a hierarchical cellular network on chip; each node in the top-level switching network includes a router and is fully interconnected through the additional channels.

2. The method according to claim 1, characterized in that Each node in the underlying cellular network has a data interaction interface, and the data interaction interface is used for data interaction within the node and between nodes.

3. The method according to claim 2, characterized in that The data interaction interface includes a processing unit interface and a routing interface; The processing unit interface is used for local data interaction between the processing unit of each node in the underlying cellular network and the router; The routing interface is used for data interaction between adjacent nodes in the underlying cellular network.

4. The method according to claim 3, characterized in that The cellular topology structure is a two-dimensional cellular network, which is composed of a plurality of hexagonal rings; the additional channel is a bidirectional high-speed link.

5. The method according to claim 4, characterized in that The underlying cellular network includes a plurality of ring layers; the distribution of the ring layers includes: According to the size of the underlying cellular network, the hexagonal ring at the center of the two-dimensional cellular network is expanded outward, and the hexagonal rings are numbered in sequence.

6. The method according to claim 5, characterized in that The size of the underlying cellular network is an integer greater than 1.

7. The method according to claim 6, characterized in that The number of cross-layer nodes is determined by the size of the underlying cellular network; and the cross-layer nodes of the same ring layer are spaced equally, and the cross-layer nodes of different ring layers are aligned along the cellular symmetry axis.

8. The method according to any one of claims 1 to 7, characterized in that: The selection of cross-layer nodes includes: Taking the center point of the underlying cellular network as the origin, three coordinate axes are set with an angle of 120 degrees to each other to divide the underlying cellular network into six areas; Along the positive direction of each coordinate axis, draw a series of parallel lines perpendicular to the coordinate axis. Each parallel line passes through the underlying cellular network nodes to form a positive direction sawtooth chain. Starting from the origin, the coordinate values ​​of all nodes on the first sawtooth chain perpendicular to the positive direction of the coordinate axis are 1, and the second are 2, and so on. Along the negative direction of each coordinate axis, draw a series of parallel lines perpendicular to the coordinate axis. Each parallel line passes through the underlying cellular network nodes to form a negative direction sawtooth chain. Starting from the origin, the coordinate value of the node on the first negative direction vertical chain is 0, the second is -1, and so on. Determine the coordinate value of each node according to the sawtooth chain sequence number of the coordinate axis direction of each node in the underlying cellular network; For any area in the underlying cellular network, nodes whose node coordinate values ​​are equal to the ring layer number are regarded as cross-layer nodes.

9. The method according to claim 8, characterized in that The nodes of the top-level switching network do not have a data interaction interface; the number of nodes of the top-level switching network is equal to the total number of ring layers of the bottom-level cellular network.

10. The method according to claim 9, characterized in that The step of connecting the cross-layer node to a corresponding node in the top-level switching network through an additional channel includes: Cross-layer nodes in the same hexagonal ring are connected to the same node in the top-level switching network through an additional channel; or, cross-layer nodes in adjacent areas are connected to the same node in the top-level switching network.

11. The method according to claim 10, characterized in that The method of connecting the cross-layer nodes located in the same hexagonal ring to the same node in the top-layer switching network through an additional channel includes: Determining the number of nodes of the top switching network based on the total number of ring layers of the bottom cellular network; All cross-layer nodes in the same hexagonal ring layer in the bottom cellular network are connected to a single corresponding node in the top switching network through additional channels.

12. The method according to claim 10, characterized in that The step of connecting the cross-layer nodes in adjacent areas to the same node in the top-level switching network includes: The six regions of the bottom cellular network are divided into three groups of cross-region node clusters; the number of nodes in the top switching network is equal to the number of clusters; Connect the cross-layer nodes of each cluster to the same node in the top-level switching network through additional channels.

13. An electronic device, characterized in that: include: Memory for storing computer programs; A processor, configured to implement the steps of the on-chip network construction method as claimed in any one of claims 1 to 12 when executing the computer program.

14. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, wherein the computer program, when executed by a processor, implements the steps of the on-chip network construction method according to any one of claims 1 to 12.

15. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the on-chip network construction method according to any one of claims 1 to 12 are implemented.

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