Memory and control method thereof, memory system and storage medium

Abstract

The embodiment of the invention provides a memory and a control method thereof, a memory system and a storage medium. The memory includes: a counting circuit including a plurality of counters and configured to receive an address of a current access line, map the address of the current access line onto at least one counter by using a logical algorithm, and generate a first count value; the first count value is the visited frequency of the current visited line; the determination circuit is connected with the counting circuit and is configured to compare the first counting value with a second counting value stored in the determination circuit and determine an attack row address according to a comparison result; the second count value is the access times corresponding to the access line with the most access times recorded by the counting circuit before the counting circuit receives the address of the current access line.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and relates to, but is not limited to, a memory and its control method, a memory system, and a storage medium. Background Art

[0002] A memory, such as a Dynamic Random Access Memory (DRAM), is a commonly used semiconductor device in a computer, and it can store data by storing charges in a capacitor of a storage cell. Since the charges stored in the capacitor will leak over time, the dynamic random access memory needs to periodically perform a normal Refresh operation. In some cases, in addition to the normal refresh, an additional row hammer refresh operation needs to be performed to prevent the occurrence of the Row Hammer Effect.

[0003] However, in the related art, there are still many problems to be solved in the process of performing the above refresh operation. Summary of the Invention

[0004] In view of this, embodiments of the present disclosure provide a memory, including: a counting circuit, including a plurality of counters, and configured to receive an address of a currently accessed row, map the address of the currently accessed row to at least one of the counters by using a logical algorithm, and generate a first count value; the first count value is the number of times the currently accessed row has been accessed; a determination circuit, connected to the counting circuit, and configured to compare the first count value with a second count value stored in the determination circuit, and determine an attack row address according to the comparison result; the second count value is the number of times of the access row that has been accessed the most times recorded by the counting circuit before receiving the address of the currently accessed row.

[0005] In some embodiments, the counting circuit includes: a Bloom filter; the Bloom filter is configured to: be combined with the plurality of counters, and map the address of the currently accessed row to at least one of the counters by using at least one hash function through a hash algorithm.

[0006] In some embodiments, when the address of the currently accessed row is mapped to a plurality of counters by a plurality of the hash functions, the first count value is the smallest count value recorded in the plurality of counters.

[0007] In some embodiments, the memory further includes: a register, connected to the determination circuit, and configured to: store the attack row address; wherein, when the first count value is greater than the second count value, the attack row address is the address of the currently accessed row.

[0008] In some embodiments, the memory further includes: an address converter and a refresh circuit; wherein, the address conversion circuit is connected to the register and is configured to: determine a victim row address according to the attacked row address; the victim row is at least one memory row physically located above and below the attacked row; the refresh circuit, connected to the address conversion circuit, is configured to: perform a refresh operation on the victim row.

[0009] In some embodiments, the memory further includes: a control circuit; the control circuit, connected to the refresh circuit, is configured to: provide a refresh command; wherein, the refresh circuit performs a refresh operation on the victim row based on the refresh command.

[0010] In some embodiments, the counting circuit is further configured to: clear the first count value after performing a refresh operation on the victim row.

[0011] Embodiments of the present disclosure further provide a memory system, including one or more memories as described in the above embodiments of the present disclosure; and a memory controller, coupled to the memory, for controlling the memory.

[0012] Embodiments of the present disclosure further provide a control method for a memory, the memory including: a counting circuit and a determination circuit; wherein, the counting circuit includes a plurality of counters; the control method includes:

[0013] The counting circuit receives the address of the currently accessed row, maps the address of the currently accessed row to at least one of the counters by using a logical algorithm, and generates a first count value; the first count value is the number of times the currently accessed row has been accessed; the determination circuit compares the first count value with a second count value stored in the determination circuit, and determines the attacked row address according to the comparison result; the second count value is the number of times of the access row with the most accessed times recorded by the counting circuit before receiving the currently accessed row.

[0014] In some embodiments, the counting circuit includes: a Bloom filter; the mapping the address of the currently accessed row to at least one of the counters by using a logical algorithm includes: combining the Bloom filter and a plurality of the counters, and mapping the address of the currently accessed row to at least one of the counters by using at least one hash function through a hash algorithm.

[0015] In some embodiments, when the address of the currently accessed row is mapped to a plurality of counters by a plurality of the hash functions, the first count value is the count value corresponding to the counter with the smallest value.

[0016] In some embodiments, the memory further includes: a register; and the control method further includes: storing the attacked row address in the register; wherein, when the first count value is greater than the second count value, the attacked row address is the address of the currently accessed row.

[0017] In some embodiments, the memory further includes: an address converter and a refresh circuit; wherein, the control method further includes: the address conversion circuit determines a victim row address according to the attacked row address; the victim row is at least one memory row physically located above and below the attacked row; and the refresh circuit performs a refresh operation on the victim row.

[0018] In some embodiments, the memory further includes: a control circuit; the control method further includes: the control circuit provides a refresh command; and performing the refresh operation on the victim row includes: using the refresh circuit and based on the refresh command, performing a refresh operation on the victim row.

[0019] In some embodiments, the control method further includes: after performing the refresh operation on the victim row, clearing the first count value.

[0020] An embodiment of the present disclosure further provides a storage medium, on which executable instructions are stored, and when the executable instructions are executed by a memory controller, the steps of the control method as described in the above embodiments of the present disclosure can be implemented.

[0021] The memory provided in each embodiment of the present disclosure includes a counting circuit. The counting circuit includes a plurality of counters and is configured to receive the address of the currently accessed row, map the address of the currently accessed row to at least one counter by using a logical algorithm, and generate a first count value; the first count value is the number of times the currently accessed row has been accessed; a determination circuit, connected to the counting circuit, is configured to compare the first count value with a second count value stored in the determination circuit, and determine the attacked row address according to the comparison result; the second count value is the number of times the most frequently accessed row has been accessed before the counting circuit receives the address of the currently accessed row. In the embodiments of the present disclosure, the counting circuit maps the received address of the currently accessed row to at least one counter by using a logical algorithm and generates a first count value. Thus, compared with directly storing the accessed address in the memory, the embodiments of the present disclosure can reduce the storage space occupied by the address of the accessed row; on the other hand, by mapping the addresses of all accessed rows to obtain counters and generating count values for recording the number of times the accessed rows have been accessed, each accessed row can be tracked and monitored, reducing the risk of omission of the addresses of the accessed rows, thereby reducing the row hammer effect on the adjacent rows of the accessed rows. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 Block diagram of an exemplary system with a memory provided in an embodiment of the present disclosure;

[0023] Figure 2 Schematic diagram of the row hammer effect provided in an embodiment of the present disclosure;

[0024] Figure 3 Schematic diagram of the composition structure of a memory provided in an embodiment of the present disclosure;

[0025] Figure 4 Schematic diagram of a row hammer refresh circuit provided in an embodiment of the present disclosure;

[0026] Figure 5 Schematic diagram of the corresponding relationship between a hash function and a counter provided in an embodiment of the present disclosure;

[0027] Figure 6 Schematic diagram of the principle of use of a Bloom filter provided in an embodiment of the present disclosure;

[0028] Figure 7 Schematic diagram of the process of a memory performing a row hammer refresh operation provided in an embodiment of the present disclosure;

[0029] Figure 8 Schematic diagram of the operation process of a row hammer refresh circuit provided in an embodiment of the present disclosure;

[0030] Figure 9 Schematic diagram of the implementation process of a control method for a memory provided in an embodiment of the present disclosure.

[0031] In the above figures (which are not necessarily drawn to scale), similar reference numerals may describe similar components in different views. Similar reference numerals with different letter suffixes may represent different examples of similar components. The figures generally illustrate, by way of example and not limitation, the various embodiments discussed herein. Detailed implementation manners

[0032] To make the technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the present disclosure will be further elaborated in detail below in conjunction with the drawings and embodiments. Although the exemplary implementation methods of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the implementation manners set forth herein. On the contrary, these implementation manners are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0033] The present disclosure will be described more specifically by way of example with reference to the accompanying drawings in the following paragraphs. The advantages and features of the present disclosure will become clearer according to the following description and claims. It should be noted that the accompanying drawings are all in very simplified forms and use non-precise scales, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present disclosure.

[0034] In the embodiments of the present disclosure, terms such as "first" and "second" are used to distinguish similar objects and do not necessarily describe a specific order or sequence.

[0035] Figure 1 is a block diagram of an exemplary system with a memory provided by an embodiment of the present disclosure. The system 100 can be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory. As Figure 1 shown, the system 100 may include a host 110 and a memory system 120, and the memory system 120 has one or more memories 130 and a memory controller 140. The host 110 can be a processor of the electronic device (e.g., a central processing unit (CPU)) or a system on a chip (SoC) (e.g., an application processor (AP)). The host 110 can be configured to send data to the memory 130 or receive data from the memory 130.

[0036] In some embodiments, the memory controller 140 is coupled to the memory 130 and the host 110 and is configured to control the memory 130. The memory controller 140 can operate the memory 130 by providing a combination of various control signals CMD and address signals ADDR. For example, the memory controller 140 can control the memory 130 to perform a read operation by a read command RD. The memory controller 140 can control the memory 130 to perform a write operation by a write command WT. The memory controller 140 can also control the memory 130 to perform a refresh operation by a refresh command REF, etc. In some specific embodiments, the memory controller 140 can provide various signals to control the memory to perform access operations (such as writing and reading). For example, an activation command ACT, a read command RD, and a write command WT are used to access the memory 130. The activation command ACT is a row access command. The memory controller 140 simultaneously issues the activation command ACT and a row address signal. The memory 130 synchronously receives the activation command ACT and the row address signal and enables the word line of the memory cell array according to the row address signal.

[0037] In some embodiments, the memory controller 140 may also provide a read command RD to control the memory 130 to perform a read operation, or provide a write command WT to control the memory 130 to perform a write operation. Among them, the column address signal is sent simultaneously with the read command / write command. Exemplarily, the memory 130 may synchronously receive the read command RD and the column address signal, and select the bit lines of the memory cell array according to the column address signal, so as to perform a read operation on the data in the memory cell located at the intersection of the enabled word line and the selected bit line. Exemplarily, the memory 130 may synchronously receive the write command WT and the column address signal, and select the bit lines of the memory cell array according to the column address signal. The memory 130 may receive the data sent from the memory controller 140 during the write operation, and may store the received data in the memory cell located at the intersection of the enabled word line and the selected bit line.

[0038] In some embodiments, the memory controller 140 may provide a refresh command REF to control the memory 130 to perform a refresh operation. Exemplarily, the memory controller 140 provides the refresh command REF to the memory 130 at a fixed period to perform a normal refresh operation. One refresh command REF is only valid for one memory row, and the memory 130 may sequentially perform refresh operations on all memory rows according to the refresh command REF. In some embodiments, when the memory 130 performs a refresh, it does not require external provision of row address information, and the memory can automatically generate row addresses sequentially internally.

[0039] Here, the memory 130 may include all types of memories that perform refresh operations to maintain the data stored in the memory cells. For example, the memory 130 may include a dynamic random access memory DRAM. The memory 130 may include a memory cell array and a peripheral circuit coupled to the memory cell array. The memory cell array may be a DRAM memory cell array. Among them, each DRAM memory cell may include a transistor and a capacitor. The gate of the transistor is connected to the word line, the source is connected to the bit line, and the drain is connected to the capacitor. The memory cell array includes multiple memory rows, and the memory cells of each memory row are coupled to the same word line, and the word line is coupled to the row decoder. The column decoder is respectively coupled to multiple memory columns through multiple bit lines. The peripheral circuit may be coupled to the memory cell array through the word line and the bit line. The peripheral circuit can control the on and off of the transistor by controlling the word line voltage, so as to read the data information stored in the capacitor through the bit line, or write the data information into the capacitor.

[0040] It should be noted that in DRAM, if a certain memory row is repeatedly accessed multiple times during the refresh window, it will cause the charge of the memory cells in the memory row physically adjacent to that memory row to leak, which is the row hammer effect (Rowhammer). Figure 2It is a schematic diagram of the row hammer effect. As Figure 2 shown, the memory row that is repeatedly accessed is called the attacking row. The memory rows physically adjacent to the attacking row are called the victim rows. Due to the repeated access of the attacking row, the victim rows have a charge leakage problem. If the number of accesses to the attacking row reaches a certain amount, the row hammer effect may cause data corruption in the victim rows. It should be noted that referring to Figure 2 , the victim rows can be the two memory rows (such as Row+1 and Row-1) above and below that are physically adjacent to the attacking row (such as the Active Row), or the four memory rows (such as Row+2, Row+1, Row-1, and Row-2) above and below that are physically adjacent to the attacking row. The present disclosure does not make any limitations.

[0041] A relatively effective method to solve the row hammer effect is: perform a row hammer refresh operation, that is, perform a refresh operation on the Target Row Refresh (TRR). Target row refresh means finding the attacking row and refreshing the victim rows adjacent to it. By refreshing the victim rows, the data in the storage units of the victim rows is retained. Therefore, target row refresh can also be understood as victim row refresh. In some specific embodiments, the memory can track the row address signals synchronized with the activation command sent by the memory controller, so as to obtain the number of accesses to each memory row, and then the memory row with the most accesses within a period of time can be determined. This memory row with the most accesses is the attacking row, and the memory can refresh the victim rows of the attacking row, thereby weakening the adverse effects of the row hammer effect.

[0042] The following will combine Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 to describe in detail the execution process of the target row refresh.

[0043] The embodiments of the present disclosure propose a memory, Figure 3 which is a schematic diagram of the composition structure of a memory provided by the embodiments of the present disclosure. Figure 3 shows Figure 1 an example of the memory in Figure 3 . As

[0044] The address buffer 133 may receive address signals ADDR, such as row address signals and column address signals, etc., from the memory controller 140 or the host 110. The address buffer 133 may provide the received column address signal to the column decoder 136, and provide the received row address signal to the row decoder 135 and the row hammer control circuit 134. The address buffer 133 receiving the row address signal is synchronous with the control logic circuit 132 receiving the activation command ACT.

[0045] The control logic circuit 132 may receive various commands CMD from the memory controller 140 or the host 110 and generate various control signals for controlling the operation of the memory 130. Specifically, the command decoder 1321 in the control logic circuit 132 is used to receive various commands CMD and generate various control signals. The control logic circuit 132 may read data from or write data to the memory cell array 131 by using the control signals, or perform other operations. Exemplarily, the control logic circuit 132 may receive the activation command ACT to control the row decoder 135 to activate the memory row indicated by the row address signal. The control logic circuit 132 may receive the refresh command REF to control the row hammer refresh circuit 134 to perform a refresh operation on a certain memory row. Although Figure 3 the control logic circuit 132 and the address buffer 133 in Figure 3 are shown as separate components, the control logic circuit 132 and the address buffer 133 may also be an integrated component. Although

[0046] the activation command ACT and the row address signal are shown as separate signals in

[0047] the row address signal may be considered to be included in the activation command ACT. Similarly, the column address signal may also be considered to be included in the read command RD or the write command WT.

[0048] Here, the row hammer refresh circuit 134 can also monitor the number of times a memory row is accessed and detect the row address of an attacked row that is frequently accessed during the refresh window. Exemplarily, the row hammer refresh circuit 134 is connected to the address buffer 133, for receiving the accessed row address XADD provided by the address buffer 133, counting the number of times each memory row is accessed, determining the memory row with the most access times as the attacked row, and determining the row address to be refreshed of the victim row based on the attacked row. The row hammer refresh circuit 134 can respond to the refresh command REF to perform a refresh operation on the row address to be refreshed, so as to retain the data in the memory cells of the victim row (i.e., the adjacent memory row of the attacked row), thereby weakening the adverse effects caused by the row hammering effect.

[0049] Figure 4 Schematic diagram of a row hammer refresh circuit provided by an embodiment of the present disclosure, as Figure 4 shown, the row hammer refresh circuit 134 includes a sampling circuit 201, a counting circuit 202, a determination circuit 203, a register 204, an address converter 205, a refresh circuit 206, and a control circuit 207. Among them, the sampling circuit 201 samples all the accessed row addresses XADD within a certain time sequence according to the activation command, and sends the address of the currently accessed row obtained by sampling to the counting circuit 202. Among them, the currently accessed row is the memory row accessed in the current access operation. It should be understood that the sampling circuit 201 obtains the address of a currently accessed row each time an access operation is performed within a certain time sequence.

[0050] Refer to Figure 4 , the counting circuit 202 can include multiple counters, and the counting circuit 202 is configured to receive the address of the currently accessed row, map the address of the currently accessed row to at least one counter by using a logic algorithm, and generate a first count value; the first count value is the number of times the currently accessed row is accessed.

[0051] In practical applications, among the addresses of multiple currently accessed rows, different addresses correspond to different logic algorithms, and the same address corresponds to the same logic algorithm. In addition, based on the different logic algorithms, the address of a currently accessed row can be mapped to one counter or multiple counters. Among them, when the address of a currently accessed row is mapped to multiple counters through different logic algorithms, among the multiple values corresponding to the multiple counters, the minimum value is the number of times the currently accessed row is accessed (i.e., the first count value).

[0052] Exemplarily, refer to Figure 4, the counting circuit 202 includes: a Bloom filter; the Bloom filter is configured to: be combined with a plurality of counters, and map the address of the current access row to at least one counter through a hashing algorithm using at least one hash function. Here, each address is mapped to one counter by one hash function (however, there may be duplicate mappings for the counters). In some embodiments, the hashing algorithm may be the CBF (Counting Bloom Filter) algorithm, which is a data structure based on the Bloom filter and can implement the statistics of the occurrence times of data by combining the Bloom filter and counters. The Bloom filter is a probabilistic data structure with high space efficiency and fast query time, used to determine whether an element belongs to a set. It uses a bit array and multiple hash functions. When the bits corresponding to an element after being mapped by the hash functions are all marked as 1, the element may be in the set.

[0053] The Bloom filter is combined with a plurality of counters, so that a counter is saved at each position corresponding to each hash function, used to record the number of times an element appears in the set. When an element needs to be added, the counter at the corresponding position can be incremented by 1; when it is necessary to query whether an element exists, it can be checked whether the count value of the counter at the corresponding position is greater than 0.

[0054] In other words, when the counting circuit receives an address of a current access row, the address can be mapped to the corresponding counter through at least one hash function, and the count value of the counter at the corresponding position is incremented by 1. In this way, all addresses of the current access rows can be counted without the need to store the addresses of the current access rows, thereby saving storage space. In addition, by combining the Bloom filter and counters to count all the accessed storage rows, the addresses of all the accessed rows can be tracked; compared with, for example, the unified multi-faceted attack of TRRespass and the non-uniform multi-faceted attack of Blacksmith, in the embodiments of the present disclosure, after obtaining the address of each access row, the number of times the access row is accessed can be counted, so as to avoid the problem of attack row escape caused by the address of the accessed row not being counted.

[0055] Exemplarily, referring to Figure 4 , the hash function block includes N hash functions, the Bloom filter corresponds to a plurality of counters, the address of each current access row is mapped to N counters through N hash functions, and the count value CountA of the corresponding counter is incremented by 1 on the original value CountB, such as CountA = CountB + 1.

[0056] Referring to Figure 5 、 Figure 6 , Figure 5 is a schematic diagram of the corresponding relationship between a hash function and a counter shown in the embodiments of the present disclosure; Figure 6Schematic diagram of the principle of using a Bloom filter shown in the embodiments of the present disclosure;

[0057] Figure 5 Three hash functions shown in the figure, such as hash function 1, hash function 2, and hash function 3, eight different hash algorithms (such as the first hash algorithm Match[0], the second hash algorithm Match[1], the third hash algorithm Match[2], the fourth hash algorithm Match[3], the fifth hash algorithm Match[4], the sixth hash algorithm Match[5], the seventh hash algorithm Match[6], the eighth hash algorithm Match[7]), and eight counters corresponding one-to-one with the eight hash algorithms, such as counter 0, counter 1, counter 2, counter 3, counter 4, counter 5, counter 6, counter 7. Among them, the address of a current access row can be mapped to three counters by combining three different hash algorithms with three hash functions. Specifically, the address of the current access row is mapped to counter 0 through hash function 1 combined with the first hash algorithm Match[0], mapped to counter 3 through hash function 2 combined with the fourth hash algorithm Match[3], and mapped to counter 6 through hash function 3 combined with the seventh hash algorithm Match[6]. After mapping the address of the current access row to the three counters, the count values of the three counters are each incremented by 1 on the original basis.

[0058] It should be noted that there may be a possibility of duplicate mapping for the count values on each counter. Based on this, when comparing the count values of the three counters (such as counter 0, counter 3, and counter 6), the smallest count value recorded in the three counters is determined as the first count value, that is, the number of accesses to the current access row.

[0059] Exemplarily, referring to Figure 6 , Figure 6 shows a schematic diagram of the addresses of two current access rows being mapped to four counters respectively; among them, the Bloom filter includes four hash functions, namely hash function h i , hash function h j , hash function h k , hash function h r , and seven counters (1, 2, 3, 4, 5, 6, 7). The addresses of the two current access rows are the address x' of the first current access row and the address x i of the second current access row respectively. The address x' of the first current access row is mapped to four counters (2, 5, 6, 7) through four hash functions; specifically, the address x' of the first current access row is mapped to counter 2 through hash function h i , and the count value on counter 2 is "1", and through hash function h jis mapped to counter 5, and the count value on counter 5 is "15", through hash function h k is mapped to counter 6, and the count value on counter 6 is "8", through hash function h r is mapped to counter 7, and the count value on counter 7 is "1". Among the count values of counter 2, counter 5, counter 6, and counter 7, the count values on counter 2 and counter 7 (both are "1") are the access times of the first current access row, that is, the first count value.

[0060] Similarly, the address x of the second current access row i is mapped to three counters (3, 5, 6) through four hash functions; specifically, the address x of the second current access row i through hash function h i is mapped to counter 3, and the count value on counter 3 is "26", through hash function h j is mapped to counter 5, and the count value on counter 5 is "15", through hash function h k is mapped to counter 3, and the count value on counter 3 is "26", through hash function h r is mapped to counter 6, and the count value on counter 6 is "8". Among the three count values corresponding to counter 3, counter 5, and counter 6, the count value on counter 6 ("8") is the access times of the second current access row, that is, the first count value.

[0061] Reference Figure 4 , it is determined that circuit 203 is connected to counting circuit 202, and it is determined that circuit 203 is configured to compare the first count value with the second count value stored in the determining circuit, and determine the attack row address according to the comparison result; the second count value is the access times corresponding to the access row with the most access times recorded by the counting circuit before receiving the address of the current access row.

[0062] Exemplarily, as Figure 4 shown, determining circuit 203 includes a comparator and a latch. Among them, the latch is used to store the access times corresponding to the access row with the most access times recorded by the counting circuit before receiving the address of the current access row, such as the second count value. In some other embodiments, the second count value can also be a preset value set according to the memory performance, which is not limited in the present disclosure.

[0063] The comparator is used to compare the first count value and the second count value. Among them, when the first count value is greater than the second count value, it indicates that the access times of the current access row are greater than the access times corresponding to the access row with the most access times before the current access operation; in other words, the access times of the current access row have reached a certain number. Based on this, the current access row is determined as the attack row. Among them, the attack row address is the address of the current access row.

[0064] When the first count value is less than or equal to the second count value, it indicates that the number of accesses to the currently accessed row is less than or equal to the number of accesses to the row with the most accesses before the current access operation; in other words, the currently accessed row has fewer accesses, and the row hammer effect caused by the access operation on the storage row is smaller. At this time, the subsequent row hammer refresh operation is not performed temporarily.

[0065] As Figure 4 shown, the register 204 is connected to the determination circuit 203, and the register 204 can be used to store the address of the attacked row. It should be noted that the address of the attacked row in the register is updated according to the comparison result of the first count value and the second count value; exemplarily, when the first count value is greater than the second count value, the address of the currently accessed row is stored in the register 204; when the first count value is less than or equal to the second count value, the address stored in the register 204 is not updated.

[0066] Refer to Figure 4 , the address converter 205 is connected to the register 204, and the address converter 205 can be used to determine the victim row address according to the attacked row address; wherein, the victim rows are at least one storage row above and below the attacked row in the physical position; exemplarily, refer to Figure 2 , Figure 4 , the address converter 205 determines the storage rows (such as Row+1 and Row-1) above and below the attacked row (such as Active Row) in the physical position as the victim rows according to the attacked row address, and sends the victim row address to the refresh circuit 206.

[0067] Refer to Figure 4 , the refresh circuit 206 is connected to the address conversion circuit 205, and the refresh circuit 206 is configured to: receive the victim row address and perform a refresh operation on the victim row.

[0068] It should be noted that the refresh operation is performed based on the refresh command REF. Based on this, refer to Figure 4 , the memory further includes a control circuit 207; the control circuit 207 is connected to the refresh circuit 206, and the control circuit 207 is configured to: provide a refresh command, such as a row hammer refresh command RHR; wherein, the refresh circuit 206 performs a refresh operation on the victim row based on the refresh command (such as the row hammer refresh command RHR). Among them, Figure 4 also shows a normal refresh address generator, which is used to provide a normal refresh command to the refresh circuit 206 at a fixed period according to the refresh command REF, which will not be elaborated here.

[0069] In some embodiments, the counting circuit is further configured to clear the first count value after a refresh operation is performed on the victim row. In this way, interference from previous counting information to subsequent counting can be avoided. Additionally, when the first count value is greater than the second count value, the determination circuit is further configured to store the access count of the current access row (i.e., the first count value) in a latch as the second count value stored in the determination circuit during the next access operation. The original second count value stored in the latch can be deleted to avoid interference with subsequent counting information.

[0070] Based on the above row hammer refresh circuit, the following combines Figure 7 and Figure 8 , and details the process of performing the above row hammer refresh operation in the embodiments of the present disclosure; wherein, Figure 7 is a schematic flowchart of a memory performing a row hammer refresh operation shown in the embodiments of the present disclosure; Figure 8 is a schematic flowchart of the operation process of the row hammer refresh circuit shown in the embodiments of the present disclosure.

[0071] Exemplarily, step S701 is executed to start the current access operation. Step S702 is executed to sample the accessed row address XADD based on the activation command of the current access operation and determine that the address of the current access row is obtained through sampling. If it is determined that the address of the current access row is not obtained through sampling, step S706 is executed, that is, the row hammer refresh operation ends. If it is determined that the address of the current access row is obtained through sampling, step S703 is executed.

[0072] In step S703, the address of the current access row is mapped to at least one counter, the count value of the corresponding counter is incremented by 1, and a first count value is generated. It should be understood that when the address of the current access row is mapped to multiple counters through multiple hash functions, the first count value is the smallest count value recorded in the multiple counters.

[0073] Next, step S704 is executed to compare the first count value with the second count value stored in the determination circuit and determine whether the first count value is greater than the second count value. If the first count value is less than or equal to the second count value, step S706 is executed, that is, the row hammer refresh operation ends. If the first count value is greater than the second count value, step S705 is executed.

[0074] In step S705, it is determined that the current access row is an attack row, the address of the current access row is stored in a register, and the access count of the current access row is stored in a latch.

[0075] In step S706, the row hammer refresh operation ends.

[0076] Refer to Figure 8, based on the activation command of the current access operation, the row hammer refresh circuit executes step S801 to start the row hammer refresh operation. Next, step S802 is executed. The counting circuit is used to map the current access address to at least one counter; the determination circuit is used to determine the attacked row according to the count value of the counter; store the attacked row address in the register; the address converter is used to determine the victim row and the victim row address according to the attacked row; the control circuit is used to send the row hammer refresh command to the refresh circuit; the refresh circuit is used to perform the row hammer refresh operation on the victim row. After completing the row hammer refresh operation, step S803 is executed to clear the count value corresponding to the attacked row in the counting circuit; and update the second count value stored in the determination circuit to the first count value. Step S804 is executed, and the row hammer refresh operation ends.

[0077] In the embodiment of the present disclosure, the counting circuit uses a logic algorithm to map the received address of the current access row to at least one counter and generate a first count value. In this way, compared with directly storing the accessed address in the memory, the embodiment of the present disclosure can reduce the storage space occupied by the address of the access row; on the other hand, by mapping the addresses of all accessed rows to obtain counters and generating count values for recording the number of times the accessed rows are accessed, each accessed row can be tracked and monitored, reducing the risk of omission of the addresses of the accessed rows, thereby reducing the row hammering effect on the adjacent rows of the accessed rows.

[0078] Based on the above memory, the embodiment of the present disclosure further provides a memory system, including one or more memories as described in the above embodiments of the present disclosure; and a memory controller coupled to the memory for controlling the memory.

[0079] Based on the above memory, the embodiment of the present disclosure further provides a control method for a memory, refer to Figure 9 , Figure 9 is a schematic flowchart of the implementation process of a control method for a memory provided in the embodiment of the present disclosure; wherein, the memory includes: a counting circuit and a determination circuit; the counting circuit includes a plurality of counters; the control method includes the following steps: Step S901: The counting circuit receives the address of the current access row, uses a logic algorithm to map the address of the current access row to at least one of the counters, and generates a first count value; the first count value is the number of times the current access row is accessed; Step S902: The determination circuit compares the first count value with the second count value stored in the determination circuit, and determines the attacked row address according to the comparison result; the second count value is the number of times the access row with the most access times recorded by the counting circuit before receiving the current access row.

[0080] In some embodiments, the counting circuit includes: a Bloom filter; the mapping of the address of the current access row to at least one of the counters by using a logical algorithm includes: combining the Bloom filter and a plurality of the counters, and mapping the address of the current access row to at least one of the counters by using at least one hash function through a hashing algorithm.

[0081] In some embodiments, when the address of the current access row is mapped to a plurality of the counters by a plurality of the hash functions, the first count value is the count value corresponding to the counter with the smallest numerical value.

[0082] In some embodiments, the memory further includes: a register; the control method further includes: storing the attack row address in the register; wherein, when the first count value is greater than the second count value, the attack row address is the address of the current access row.

[0083] In some embodiments, the memory further includes: an address converter and a refresh circuit; wherein, the control method further includes: the address conversion circuit determines a victim row address according to the attack row address; the victim row is at least one memory row physically located above and below the attack row; and the refresh circuit performs a refresh operation on the victim row.

[0084] In some embodiments, the memory further includes: a control circuit; the control method further includes: the control circuit provides a refresh command; the performing of the refresh operation on the victim row includes: using the refresh circuit and based on the refresh command, performing a refresh operation on the victim row.

[0085] In some embodiments, the control method further includes: after performing the refresh operation on the victim row, clearing the first count value.

[0086] Embodiments of the present disclosure also provide a storage medium, on which executable instructions are stored, and when the executable instructions are executed by a memory controller, the steps of the control method as described in the above embodiments of the present disclosure can be implemented.

[0087] In several embodiments provided by the present disclosure, it should be understood that the disclosed devices and methods can be implemented in a non-target manner. The device embodiments described above are merely illustrative. For example, the division of the units is only a logical function division, and there may be other division methods in actual implementation, such as: a plurality of units or components can be combined, or can be integrated into another system, or some features can be ignored, or not executed. In addition, the couplings between the components shown or discussed are direct couplings.

[0088] The units described above as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed over multiple network units; some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0089] The features disclosed in several method or device embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0090] As mentioned above, the above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present disclosure can easily think of changes or substitutions, which should all be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A memory, characterized in that, comprising: a counting circuit including a plurality of counters and configured to receive an address of a currently accessed row, map the address of the currently accessed row to at least one of the counters by using a logic algorithm, and generate a first count value; the first count value is the number of times the currently accessed row has been accessed; a determining circuit connected to the counting circuit and configured to compare the first count value with a second count value stored in the determining circuit, and determine an attacked row address according to the comparison result; the second count value is the number of times of the most accessed row recorded by the counting circuit before receiving the address of the currently accessed row.

2. The memory according to claim 1, characterized in that, the counting circuit includes: a Bloom filter; the Bloom filter is configured to: be combined with the plurality of counters, and map the address of the currently accessed row to at least one of the counters by using at least one hash function through a hashing algorithm.

3. The memory according to claim 2, characterized in that, when the address of the currently accessed row is mapped to a plurality of the counters by a plurality of the hash functions, the first count value is the smallest count value recorded in the plurality of counters.

4. The memory according to claim 1, characterized in that, the memory further includes: a register connected to the determining circuit and configured to: store the attacked row address; wherein, when the first count value is greater than the second count value, the attacked row address is the address of the currently accessed row.

5. The memory according to claim 4, characterized in that, the memory further includes: an address converter and a refresh circuit; wherein, the address conversion circuit is connected to the register and configured to: determine a victim row address according to the attacked row address; the victim row is at least one storage row physically located above and below the attacked row; the refresh circuit, connected to the address conversion circuit, is configured to: perform a refresh operation on the victim row.

6. The memory according to claim 5, characterized in that, the memory further includes: a control circuit; the control circuit, connected to the refresh circuit, is configured to: provide a refresh command; wherein, the refresh circuit performs a refresh operation on the victim row based on the refresh command.

7. The memory according to claim 6, characterized in that, the counting circuit is further configured to: after performing a refresh operation on the victim row, clear the first count value.

8. A memory system, characterized in that, including one or more memories according to any one of claims 1-7; and a memory controller coupled to the memory for controlling the memory.

9. A control method for a memory, characterized in that, the memory includes: a counting circuit and a determining circuit; wherein, the counting circuit includes a plurality of counters; the control method includes: The counting circuit receives the address of the currently accessed row, maps the address of the currently accessed row to at least one of the counters using a logical algorithm, and generates a first count value; the first count value is the number of times the currently accessed row has been accessed. The determining circuit compares the first count value with a second count value stored in the determining circuit, and determines the attacked row address according to the comparison result; the second count value is the number of times of access corresponding to the row with the most access times recorded by the counting circuit before receiving the currently accessed row.

10. The control method according to claim 9, wherein, the counting circuit includes: a Bloom filter; The mapping of the address of the currently accessed row to at least one of the counters using a logical algorithm includes: Combining the Bloom filter and multiple counters, and mapping the address of the currently accessed row to at least one of the counters through a hashing algorithm using at least one hash function.

11. The control method according to claim 10, wherein, When the address of the currently accessed row is mapped to multiple counters through multiple hash functions, the first count value is the count value corresponding to the counter with the smallest value.

12. The control method according to claim 9, wherein, the memory further includes: a register; the control method further includes: storing the attacked row address in the register; wherein, when the first count value is greater than the second count value, the attacked row address is the address of the currently accessed row.

13. The control method according to claim 12, wherein, the memory further includes: an address converter and a refresh circuit; wherein, the control method further includes: The address conversion circuit determines the victim row address according to the attacked row address; the victim row is at least one memory row physically located above and below the attacked row; and The refresh circuit performs a refresh operation on the victim row.

14. The control method according to claim 13, wherein, the memory further includes: a control circuit; the control method further includes: the control circuit provides a refresh command; The performing a refresh operation on the victim row includes: Using the refresh circuit and based on the refresh command, performing a refresh operation on the victim row.

15. The control method according to claim 14, wherein, the control method further includes: After performing a refresh operation on the victim row, clearing the first count value.

16. A storage medium, wherein, executable instructions are stored on the storage medium, and when the executable instructions are executed by a memory controller, the steps of the control method according to any one of claims 9-15 can be implemented.

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