Shifting register and driving method thereof, gate driving circuit and display device

Abstract

The invention discloses a shift register and a driving method thereof, a gate driving circuit and a display device, which can remove a bootstrap capacitor and help a display panel to have a narrower frame. The shift register comprises an input end and a first output end, the shift register further comprises a reverse control module electrically connected between a first node and a second node, the reverse control module comprises a first sub-input end and a second sub-input end, the first sub-input end is used for accessing a high-potential signal, the second sub-input end is used for accessing a low-potential signal, and the first output end is electrically connected with the first output end. The reverse control module is used for pulling up or pulling down the potential of the second node under the control of the signal of the first node; wherein the reverse control module is directly connected with the control end of the first output module through the second node.

Description

Technical Field

[0001] The present application relates to the field of display technologies, and particularly to a shift register, a driving method thereof, a gate driving circuit, and a display device. Background Art

[0002] In the prior art, for the purpose of achieving low cost and narrow borders, most of them adopt the GOA (Gate driver On Array) technology. The traditional GOA circuit (gate driving circuit) is arranged on both sides of the effective display area and requires a certain width of the black matrix area to block, which results in a certain width of the border of the display panel itself. Considering aspects such as user comfort and operability, ultra-narrow borders or borderless designs are the current trend of consumption and technology. In the prior art, the gate driving circuit includes an output module. The control terminal and the output terminal of the output module are respectively electrically connected to two capacitor electrodes of a bootstrap capacitor. When the output terminal of the output module outputs a scanning signal, the bootstrap capacitor boosts the potential of the control terminal of the output module through the bootstrap effect (capacitor coupling effect) to ensure that the output terminal of the output module stably outputs the scanning signal.

[0003] However, in some products with ultra-high resolutions, such as display panels applied to VR (Virtual Reality) technology, the bootstrap capacitor occupies a large area, which is not conducive to the realization of a narrower border of the display panel. Summary of the Invention

[0004] Embodiments of the present application provide a shift register, a driving method thereof, a gate driving circuit, and a display device, which can improve the problem that the bootstrap capacitor occupies a large area and is not conducive to the realization of a narrower border of the display panel, and is beneficial to the narrow border design of the display panel.

[0005] In a first aspect of the embodiments of the present application, a shift register is provided, including an input terminal and a first output terminal. The shift register further includes:

[0006] An input module, electrically connected to the input terminal and a first node, and the input module is configured to charge the first node under the control of a signal at the input terminal;

[0007] A first output module, electrically connected to the first output terminal and a second node, and the first output module is configured to output a first output signal at the first output terminal under the control of a signal at the second node;

[0008] A first pull-down module, electrically connected to the first output terminal, and the first pull-down module is configured to pull down the potential of the first output terminal under the control of a pull-down control signal;

[0009] A reset module, electrically connected to the first node, for pulling down the potential of the first node under the control of a reset control signal;

[0010] A reverse control module, electrically connected between the first node and the second node, the reverse control module includes a first sub-input terminal and a second sub-input terminal, the first sub-input terminal is used for accessing a signal with a high potential, the second sub-input terminal is used for accessing a signal with a low potential, and the reverse control module is used for pulling up or pulling down the potential of the second node under the control of the signal of the first node;

[0011] Wherein, the reverse control module is directly connected to the control terminal of the first output module through the second node.

[0012] In some embodiments, the first output module includes:

[0013] A first output transistor, and the reverse control module is directly connected to the gate of the first output transistor through the second node.

[0014] In some embodiments, the reverse control module includes:

[0015] A first reverse transistor, which is one of an N-type transistor and a P-type transistor;

[0016] A second reverse transistor, which is the other of an N-type transistor and a P-type transistor;

[0017] Wherein, the gates of the first reverse transistor and the second reverse transistor are both electrically connected to the first node, the second poles of the first reverse transistor and the first poles of the second reverse transistor are both connected to the second node, the first pole of the first reverse transistor accesses a first power supply signal, and the second pole of the second reverse transistor accesses a reset signal.

[0018] In some embodiments, it further includes:

[0019] A second output terminal;

[0020] A second output module, electrically connected to the second output terminal, and the second output module is used for outputting a second output signal at the second output terminal under the control of the potential of the second node;

[0021] Wherein, the reverse control module is directly connected to the control terminal of the second output module through the second node.

[0022] In some embodiments, the second output module includes a second output transistor, and the reset module is directly connected to the gate of the second output transistor through the second node.

[0023] In some embodiments, it further includes:

[0024] A second pull-down module, electrically connected to the second output terminal, and the second pull-down module is configured to pull down the potential of the second output terminal under the control of the pull-down control signal.

[0025] In some embodiments, the first pull-down module includes:

[0026] A first pull-down transistor, with its first pole electrically connected to the first output terminal;

[0027] A second pull-down transistor, with its first pole electrically connected to the second pole of the first pull-down transistor, and the second pole of the second pull-down transistor is connected to the reset signal;

[0028] The gates of the first pull-down transistor and the second pull-down transistor are both connected to the pull-down control signal.

[0029] In some embodiments, the reset module includes:

[0030] A first reset transistor, with its first pole electrically connected to the first node;

[0031] A second reset transistor, with its first pole electrically connected to the second pole of the first reset transistor, and the second pole of the second reset transistor is electrically connected to the reset signal;

[0032] The gates of the first reset transistor and the second reset transistor are both electrically connected to the reset control signal.

[0033] In some embodiments, it further includes:

[0034] A leakage compensation module, whose output terminal is at least electrically connected to the second pole of the first pull-down transistor or the second pole of the first reset transistor, and the leakage compensation module is configured to at least raise the potential of the second pole of the first pull-down transistor or the second pole of the first reset transistor under the control of the compensation control signal.

[0035] In some embodiments, the leakage compensation module includes:

[0036] A leakage compensation transistor, with its gate electrically connected to the compensation control signal, and the first pole of the leakage compensation transistor is connected to the second power supply signal.

[0037] In some embodiments, the control terminal of the leakage compensation module is electrically connected to the first node or the second node, and the potential of the compensation control signal is the potential of the first node or the second node.

[0038] In some embodiments, at least one transistor in the first pull-down module, the reset module, and the reverse control module is a dual-gate transistor.

[0039] In some embodiments, the reset module includes:

[0040] A reset transistor, with a first pole electrically connected to the first node and a second pole of the reset transistor electrically connected to a reset signal;

[0041] Wherein, the reset transistor is a dual-gate transistor and includes a first sub-gate and a second sub-gate;

[0042] The first sub-gate of the reset transistor receives the reset control signal, and the second sub-gate of the reset transistor receives a reset gate signal.

[0043] In some embodiments, the first pull-down module includes:

[0044] A pull-down transistor, with a first pole electrically connected to the first output terminal and a second pole of the pull-down transistor receiving the reset signal;

[0045] Wherein, the pull-down transistor is a dual-gate transistor and both include a first sub-gate and a second sub-gate;

[0046] The first sub-gate of the pull-down transistor is electrically connected to the pull-down control signal, and the second sub-gate of the pull-down transistor receives the reset gate signal.

[0047] In some embodiments, the reverse control module includes:

[0048] A first reverse transistor, which is one of an N-type transistor and a P-type transistor;

[0049] A second reverse transistor, which is the other of an N-type transistor and a P-type transistor;

[0050] Wherein, the first reverse transistor is a dual-gate transistor and includes a first sub-gate and a second sub-gate;

[0051] Wherein, the first sub-gate of the first reverse transistor and the gate of the second reverse transistor are both electrically connected to the first node, the second pole of the first reverse transistor and the first pole of the second reverse transistor are both connected to the second node, the first pole of the first reverse transistor receives a first power signal, and the second pole of the second reverse transistor receives the reset signal; the second sub-gate of the first reverse transistor receives the reset gate signal.

[0052] In some embodiments, the reset gate signal and the reset signal are the same signal.

[0053] In a second aspect of the embodiments of the present application, a gate driving circuit is provided, which includes a plurality of cascaded shift registers described in any one of the above.

[0054] In a third aspect of the embodiments of the present application, a display device is provided, which includes the gate driving circuit described in any one of the above.

[0055] In a fourth aspect of the embodiments of the present application, a method for driving the shift register described in any one of the above is provided, including:

[0056] In the first stage, a first level is input to the input terminal, so that the input module raises the potential of the first node under the action of the first level, and the reverse control module raises the potential of the second node under the action of the high potential of the first node, so that the first output module is turned on, and the first output signal is output at the first output terminal;

[0057] In the second stage, a second level is input to the input terminal, the reset control signal and the pull-down control signal are low-potential signals, the reset module pulls down the potential of the first node under the control of the reset control signal, the reverse control module pulls down the potential of the second node under the action of the low potential of the first node, and the first pull-down module pulls down the potential of the first output terminal under the control of the pull-down control signal.

[0058] In the shift register, its driving method, gate driving circuit, and display device provided by the embodiments of the present application, a reverse control module is provided between the first node and the second node. The reverse control module directly connects the second node to the control end of the first output module. By controlling the second node to be at a high potential or a low potential through the reverse control module, the bootstrap capacitor can be removed, the area occupied by the shift register in the display panel can be reduced, and thus it helps the display panel to have a narrower border. In addition, the reverse control module can prevent the electrical signal of the second node from flowing to the first node, maintain the potential of the second node, and thus maintain the gate voltage of the thin film transistor connected to the second node. Additionally, in the charging stage (the first stage), by controlling the second node to be at a high potential through the reverse control module, the second node can be quickly charged; in the pull-down stage (the second stage), by controlling the second node to be at a low potential through the reverse control module, the potential of the second node can be quickly reduced, improving the opening or closing speed of the first output module (and the second output module), and enhancing the opening and closing performance of the shift register. Description of the Drawings

[0059] Figure 1 It is a first circuit structure block diagram of a shift register provided in the first embodiment of the present application;

[0060] Figure 2Schematic diagram of the flow steps of a driving method for a shift register provided in the first embodiment of the present application;

[0061] Figure 3 The first circuit structure diagram of a shift register provided in the first embodiment of the present application;

[0062] Figure 4 Partial waveform diagram of a shift register provided in the first embodiment of the present application;

[0063] Figure 5 The second circuit structure block diagram of a shift register provided in the first embodiment of the present application;

[0064] Figure 6 The second circuit structure diagram of a shift register provided in the first embodiment of the present application;

[0065] Figure 7 The third circuit structure diagram of a shift register provided in the first embodiment of the present application;

[0066] Figure 8 The first circuit structure diagram of a shift register provided in the second embodiment of the present application;

[0067] Figure 9 The second circuit structure diagram of a shift register provided in the second embodiment of the present application;

[0068] Figure 10 The third circuit structure diagram of a shift register provided in the second embodiment of the present application;

[0069] Figure 11 The first circuit structure diagram of a shift register provided in the third embodiment of the present application;

[0070] Figure 12 The second circuit structure diagram of a shift register provided in the third embodiment of the present application;

[0071] Figure 13 The third circuit structure diagram of a shift register provided in the third embodiment of the present application. Detailed implementation manners

[0072] In order to better understand the technical solutions provided in the embodiments of this specification, the technical solutions in the embodiments of this specification will be described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific features in the embodiments of this specification and the embodiments are detailed descriptions of the technical solutions in the embodiments of this specification, rather than limitations on the technical solutions of this specification. Without conflict, the technical features in the embodiments of this specification and the embodiments can be combined with each other.

[0073] In this text, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprising", "including" or any other variant thereof are intended to cover non-exclusive inclusion, such that a process, method, article or device comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising an..." does not exclude the presence of additional identical elements in the process, method, article or device comprising the element. The term "more than two" includes two or more than two cases.

[0074] The present application provides a shift register, including an input terminal and a first output terminal. The shift register further includes: an input module electrically connected to the input terminal and a first node, the input module being configured to charge the first node under the control of a signal at the input terminal; a first output module electrically connected to the first output terminal and a second node, the first output module being configured to output a first output signal at the first output terminal under the control of a signal at the second node; a first pull-down module electrically connected to the first output terminal, the first pull-down module being configured to pull down the potential of the first output terminal under the control of a pull-down control signal; a reset module electrically connected to the first node, the reset module being configured to pull down the potential of the first node under the control of a reset control signal; a reverse control module electrically connected between the first node and the second node, the reverse control module including a first sub-input terminal and a second sub-input terminal, the first sub-input terminal being configured to receive a high-potential signal, the second sub-input terminal being configured to receive a low-potential signal, the reverse control module being configured to pull up or pull down the potential of the second node under the control of a signal at the first node; wherein the reverse control module is directly connected to the control terminal of the first output module through the second node.

[0075] The present application further provides a gate driving circuit including the foregoing shift register.

[0076] The present application further provides a display device including the foregoing shift register or / and gate driving circuit.

[0077] In the following detailed description, for better explaining the inventive concept of the present application, different embodiments are described, but the descriptions of different embodiments do not serve as a combination limitation of different implementation cases or implementation features in the present application.

[0078] Embodiment 1

[0079] Please refer to Figures 1 to 3 , Figure 1 which is a first circuit structure block diagram of a shift register provided for Embodiment 1 of the present application;Figure 2 Schematic diagram of the flow steps of a driving method for a shift register provided in the first embodiment of the present application; Figure 3 The first circuit structure diagram of a shift register provided in the first embodiment of the present application, Figure 4 Partial waveform schematic diagram of a shift register provided in the first embodiment of the present application.

[0080] As Figure 1 As shown, the present application provides a shift register. The shift register includes an input terminal INPUT and a first output terminal OUT1. The shift register further includes an input module 100, a first output module 200, a first pull-down module 300, a reset module 400, and a reverse control module 500. Among them, the input module 100 is electrically connected to the input terminal INPUT and a first node PU1. The input module 100 is used to charge the first node PU1 under the control of the signal at the input terminal INPUT; the first output module 200 is electrically connected to the first output terminal OUT1 and a second node PU2. The first output module 200 is used to output a first output signal at the first output terminal OUT1 under the control of the signal at the second node PU2; the first pull-down module 300 is electrically connected to the first output terminal OUT1. The first pull-down module 300 is used to pull down the potential of the first output terminal OUT1 under the control of a pull-down control signal RESET1; the reset module 400 is electrically connected to the first node PU1. The reset module 400 is used to pull down the potential of the first node PU1 under the control of a reset control signal RESET2; the reverse control module 500 is electrically connected between the first node PU1 and the second node PU2. The reverse control module 500 includes a first sub-input terminal IN1 and a second sub-input terminal IN2. The first sub-input terminal IN1 is used to access a high-potential signal, and the second sub-input terminal INP2 is used to access a low-potential signal. The reverse control module 500 is used to pull up or pull down the potential of the second node PU2 under the control of the signal at the first node PU1; among them, the reverse control module 500 is directly connected to the control terminal of the first output module 200 through the second node PU2.

[0081] As Figure 2 As shown, a driving method for a shift register provided by the present application includes steps S11 and S12.

[0082] Step S11, in the first stage, input a first level to the input terminal INPUT, so that the input module 100 raises the potential of the first node PU1 under the action of the first level, and the reverse control module 500 raises the potential of the second node PU2 under the action of the high potential of the first node PU1, so that the first output module 200 is turned on, and a first output signal is output at the first output terminal OUT1.

[0083] Specifically, the reverse control module inputs the high-potential signal received at the first sub-input terminal IN1 to the second node PU2 under the control of the signal of the first node PU1, and the first output module 200 outputs a first output signal at the first output terminal OUT1 under the control of the signal of the second node PU2.

[0084] Step S12: In the second stage, a second level is input to the input terminal INPUT, the reset control signal RESET2 and the pull-down control signal RESET1 are low-potential signals, the reset module 400 pulls down the potential of the first node PU1 under the control of the reset control signal, the reverse control module 500 pulls down the potential of the second node PU2 under the effect of the low potential of the first node PU1, and the first pull-down module 300 pulls down the potential of the first output terminal OUT1 under the control of the pull-down control signal RESET1.

[0085] Specifically, the reset module 400 pulls down the potential of the first node PU1, and the reverse control module 500 inputs the low-potential signal received at the second sub-input terminal IN2 to the second node PU2 under the control of the signal of the first node PU1; meanwhile, the first pull-down module 300 pulls down the potential of the first output terminal OUT1 under the control of the pull-down control signal RESET1.

[0086] Specifically, the first output terminal OUT1 can be the output terminal of the current-stage scan signal, and the first output signal can be the current-stage scan signal.

[0087] Specifically, in some examples, the pull-down control signal RESET1 and the reset control signal RESET2 can be the same signal or signals with the same potential. For example, both the pull-down control signal RESET1 and the reset control signal RESET2 are a kind of clock signal, which is not limited herein.

[0088] Specifically, the first level can be a high-potential signal, and the second level can be a low-potential signal.

[0089] In the shift register of the present application, a reverse control module 500 is provided between the first node PU1 and the second node PU2. The reverse control module 500 is directly connected to the control end of the first output module 200 through the second node PU2. By controlling the second node PU2 to be at a high potential or a low potential through the reverse control module 500, the bootstrap capacitor can be removed, the area occupied by the shift register in the display panel can be reduced, and thus it is helpful for the display panel to have a narrower border. In addition, the reverse control module 500 can prevent the electrical signal of the second node PU2 from flowing to the first node PU1, can maintain the potential of the second node PU2, and thus maintains the gate voltage of the thin film transistor electrically connected to the second node PU2. Additionally, in the charging stage (i.e., the above-mentioned first stage), by controlling the second node PU2 to be at a high potential through the reverse control module 500, the second node PU2 can be quickly charged; in the pull-down stage (i.e., the above-mentioned second stage), by controlling the second node PU2 to be at a low potential through the reverse control module 500, the potential of the second node PU2 can be quickly reduced, the opening or closing speed of the first output module 200 can be increased, and the opening and closing performance of the shift register is improved.

[0090] In some embodiments, as Figure 3 shown, the first output module 200 includes a first output transistor M3. The reverse control module 500 is directly connected to the gate of the first output transistor M3 through the second node PU2, thereby achieving the effect of removing the bootstrap capacitor and realizing that the reverse control module 500 is directly connected to the control end of the first output module 200 through the second node PU2.

[0091] In some embodiments, as Figure 3 shown, the reverse control module 500 includes a first reverse transistor M5 and a second reverse transistor M6. The first reverse transistor M5 is one of an N-type transistor and a P-type transistor; the second reverse transistor M6 is the other of an N-type transistor and a P-type transistor; wherein, the gates of the first reverse transistor M5 and the second reverse transistor M6 are both electrically connected to the first node PU1, the second pole of the first reverse transistor M5 and the first pole of the second reverse transistor M6 are both connected to the second node PU2, the first pole of the first reverse transistor M5 is connected to a first power signal, and the second pole of the second reverse transistor M6 is connected to a reset signal VSS.

[0092] It should be noted that the transistor can be a thin film transistor. In the schematic diagram, the upper part is the first pole of the transistor and the lower part is the second pole of the transistor. The first pole of the transistor is one of the source and drain of the transistor, and the second pole of the transistor is the other of the source and drain of the transistor. Moreover, depending on the setting of high and low levels in the specific circuit and the type and characteristics of the transistor, the source and drain of each transistor can be fully interchanged or partially interchanged, which can be easily achieved by those skilled in the art according to the specific application scenario and will not be elaborated here.

[0093] Specifically, the first reverse transistor M5 is an N-type transistor and the second reverse transistor M6 is a P-type transistor, or the first reverse transistor M5 is a P-type transistor and the second reverse transistor M6 is an N-type transistor. The series connection of the first reverse transistor M5 and the second reverse transistor M6 realizes the function of the reverse control module 500. For example, Figure 3 illustrates that when the first reverse transistor M5 is an N-type transistor and the second reverse transistor M6 is a P-type transistor, when the first node PU1 is a high-potential signal, the first reverse transistor M5 is turned on, and the high potential in the first power supply signal VDD1 is input to the second node PU2. When the first node PU1 is a low-potential signal, the second reverse transistor M6 is turned on, and the low potential in the reset signal VSS is input to the second node PU2.

[0094] Specifically, the material of the semiconductor layer of the P-type transistor can be polysilicon, and the material of the semiconductor layer of the N-type transistor can be a metal oxide semiconductor material (IGZO).

[0095] Specifically, the second pole of the first reverse transistor M5 and the first pole of the second reverse transistor M6 are both connected to the second node PU2, that is, the second pole of the first reverse transistor M5 and the first pole of the second reverse transistor M6 are both directly connected to the gate of the first output transistor M3, thereby realizing the removal of the bootstrap capacitor. The reverse control module 500 is directly connected to the control end of the first output module 200 through the second node PU2.

[0096] Specifically, as Figure 3 shown, for example, the input module 100 includes an input transistor M1, the first output module 200 includes a first output transistor M3, the first pull-down module 300 includes a pull-down transistor M4, the reset module 400 includes a reset transistor M2, and the reverse control module 500 includes a first reverse transistor M5 and a second reverse transistor M6. In Figure 3 , the gate of the input transistor M1 is electrically connected to the input control signal ( Figure 3It is exemplified that the input control signal is the reset signal VSS or has the same potential as the reset signal VSS. However, in some examples, the input control signal may be different from the reset signal VSS. The first pole of the input transistor M1 is connected to the signal at the input terminal INPUT (the signal at the input terminal INPUT can be the signal provided by the previous - stage shift register or the stage - transfer signal. For example, the signal at the input terminal INPUT is the signal provided by the second output terminal OUT2 of the previous - stage shift register). The second pole of the input transistor M1 is electrically connected to the first node PU1. The gate of the first output transistor M3 is electrically connected to the second node PU2. The first pole of the first output transistor M3 is connected to the clock signal CLK, and the second pole of the first output transistor M3 is electrically connected to the first output terminal OUT1. The gate of the pull - down transistor M4 is electrically connected to the pull - down control signal RESET1. The first pole of the pull - down transistor M4 is electrically connected to the first output terminal OUT1, and the second pole of the pull - down transistor M4 is electrically connected to the reset signal VSS. The gate of the reset transistor M2 is electrically connected to the reset control signal RESET2. The first pole of the reset transistor M2 is electrically connected to the first node PU1, and the second pole of the reset transistor M2 is electrically connected to the reset signal. The gates of the first inverter transistor M5 and the second inverter transistor M6 are both electrically connected to the first node PU1. The second pole of the first inverter transistor M5 and the first pole of the second inverter transistor M6 are both connected to the second node PU2. The first pole of the first inverter transistor M5 is connected to the first power supply signal VDD1, and the second pole of the second inverter transistor M6 is connected to the reset signal VSS.

[0097] Specifically, Figure 3 it is exemplified that the input transistor M1 and the second inverter transistor M6 are P - type transistors, and the first output transistor M3, the pull - down transistor M4, the first inverter transistor M5, and the reset transistor M2 are N - type transistors.

[0098] Please refer to Figure 4 to illustrate the specific working process of the shift register provided by this application.

[0099] In the first time period t1: The signal at the input terminal INPUT is input to the first node PU1 through the input transistor M1 (at this time, the signal at the input terminal INPUT is at a high potential), making the potential of the first node PU1 at a high potential. The first inverter transistor M5 is turned on, and the high - potential signal of the first power supply signal VDD1 is input to the second node PU2, and the second node PU2 is at a high potential.

[0100] In the second time period t2: The high - potential signal at the second node PU2 controls the first output transistor M3 to turn on, enabling the high - potential signal in the clock signal CLK to be input to the first output terminal OUT1, and the first output terminal OUT1 outputs the first output signal.

[0101] In the third time period t3, the pull-down control signal RESET1 and the reset control signal RESET2 are at high potential; the pull-down control signal RESET1 controls the pull-down transistor M4 to turn on, pulling down the potential of the first output terminal OUT1; the reset control signal RESET2 controls the reset transistor M2 to turn on, pulling down the potential of the first node PU1; at the same time, since the first node PU1 is at a low potential signal at this time, the second reverse transistor M6 turns on, transmitting the reset signal VSS to the second node PU2, and the second node PU2 is also at a low potential.

[0102] In the fourth time period t4, the first output terminal OUT1 of the current-stage shift register stops outputting the scan signal.

[0103] Please refer to Figures 5 to 7 , Figure 5 which is the second circuit structure block diagram of a shift register provided in the first embodiment of the present application; Figure 6 which is the second circuit structure diagram of a shift register provided in the first embodiment of the present application;

[0104] Figure 7 which is the third circuit structure diagram of a shift register provided in the first embodiment of the present application. Figure 6 Compared with Figure 7 the shift register exemplified, the difference is that Figure 6 it is exemplified in Figure 7 that the shift register further includes a second pull-down module 700,

[0105] In some embodiments, as Figure 4 shown, the shift register further includes a second output terminal OUT2 and a second output module 600. The second output module 600 is electrically connected to the second output terminal OUT2, and the second output module 600 is configured to output a second output signal at the second output terminal OUT2 under the control of the potential of the second node PU2; wherein, the reverse control module 500 is directly connected to the control end of the second output module 600 through the second node PU2.

[0106] Specifically, the reverse control module 500 is directly connected to the control end of the second output module 600 through the second node PU2, and at the same time, the bootstrap capacitor between the first node PU1 and the second output terminal OUT2 node is removed, which can further reduce the area occupied by the shift register in the display panel and further reduce the border of the display panel.

[0107] Specifically, the second output terminal OUT2 can be a lower-stage scan signal output terminal or a stage transmission signal output terminal, and the second output signal can be a lower-stage scan signal or a stage transmission signal, which is not limited herein.

[0108] In some embodiments, asFigure 5 As shown, the shift register further includes a second pull-down module 700. The second pull-down module 700 is electrically connected to the second output terminal OUT2, and is configured to pull down the potential of the second output terminal OUT2 under the control of a pull-down control signal RESET1.

[0109] Specifically, Figure 5 In an exemplary shift register in the driving method of the shift register, in the first stage, the second output module 600 outputs a second output signal at the second output terminal OUT2 under the control of the signal at the second node PU2; in the second stage, the second pull-down module 700 pulls down the potential of the second output terminal OUT2 under the control of the pull-down control signal RESET1.

[0110] In some embodiments, as Figure 6 shown, the second output module 600 includes a second output transistor M7. The reset module 400 is directly connected to the gate of the second output transistor M7 through the second node PU2, thereby realizing the removal of the bootstrap capacitor. The reverse control module 500 is directly connected to the control terminal of the second output module 700 through the second node PU2.

[0111] Specifically, as Figure 7 shown, compared with Figure 3 the exemplary shift register, the shift register further includes a second output module 600. The second output module 600 includes a second output transistor M7. The gate of the second output transistor M7 is electrically connected to the second node PU2. The first pole of the second output transistor M7 is connected to the clock signal CLK, and the second pole of the second output transistor M7 is electrically connected to the second output terminal OUT2.

[0112] Specifically, as Figure 6 shown, compared with Figure 7 the exemplary shift register, the shift register further includes a second pull-down module 700. The second pull-down module 700 includes another pull-down transistor M8. The gate of the another pull-down transistor M8 is electrically connected to the pull-down control signal RESET1. The first pole of the another pull-down transistor M8 is electrically connected to the second output terminal OUT2, and the second pole of the another pull-down transistor M8 is electrically connected to the reset signal VSS.

[0113] Embodiment 2

[0114] The shift register of this embodiment is the same as or similar to the shift register in any of the above embodiments, except that the first pull-down module and the leakage compensation module are further introduced. The improved solution in this embodiment can be adopted for any of the shift registers in the above embodiments.

[0115] Please refer to Figures 8 to 10 , Figure 8The first circuit structure diagram of a shift register provided in the second embodiment of the present application; Figure 9 The second circuit structure diagram of a shift register provided in the second embodiment of the present application; Figure 10 The third circuit structure diagram of a shift register provided in the second embodiment of the present application.

[0116] In some embodiments, such as Figure 8 As shown, the first pull-down module 300 includes a first pull-down transistor M4A and a second pull-down transistor M4B. The first pole of the first pull-down transistor M4A is electrically connected to the first output terminal OUT1; the first pole of the second pull-down transistor M4B is electrically connected to the second pole of the first pull-down transistor M4A, and the second pole of the second pull-down transistor M4B is connected to the reset signal VSS; the gates of the first pull-down transistor M4A and the second pull-down transistor M4B are both connected to the pull-down control signal RESET1.

[0117] Specifically, the first pull-down module 300 includes the first pull-down transistor M4A and the second pull-down transistor M4B connected in series, increasing the number of transistors or the total length of the channels between the first output terminal OUT1 and the reset signal VSS. In the first stage, it can better avoid the leakage of the first output terminal OUT1 to the reset signal VSS.

[0118] In some embodiments, such as Figure 9 As shown, the reset module 400 includes a first reset transistor M2A and a second reset transistor M2B. The first pole of the first reset transistor M2A is electrically connected to the first node PU1; the first pole of the second reset transistor M2B is electrically connected to the second pole of the first reset transistor M2A, and the second pole of the second reset transistor M2B is electrically connected to the reset signal VSS; the gates of the first reset transistor M2A and the second reset transistor M2B are both electrically connected to the reset control signal RESET2.

[0119] Specifically, the reset module 400 includes the first reset transistor M2A and the second reset transistor M2B connected in series, increasing the number of transistors or the total length of the channels between the first node PU1 and the reset signal VSS. In the first stage, it can better avoid the leakage of the first node PU1 to the reset signal VSS.

[0120] In some embodiments, such as Figure 8 and Figure 9 As shown, the shift register further includes a leakage compensation module 800. The output terminal of the leakage compensation module 800 is at least electrically connected to the second pole of the first pull-down transistor M4A or the second pole of the first reset transistor M2A. The leakage compensation module 800 is used to at least raise the potential of the second pole of the first pull-down transistor M4A or the second pole of the first reset transistor M2A under the control of the compensation control signal BC.

[0121] Specifically, the output terminal of the leakage compensation module 800 is electrically connected to the second pole of the first pull-down transistor M4A and / or the second pole of the first reset transistor M2A.

[0122] Specifically, in the first stage, the leakage compensation module 800 can further prevent leakage from the first output terminal OUT1 to the reset signal VSS, and / or further prevent leakage of the first node PU1 to the reset signal VSS.

[0123] More specifically, in the first stage, the compensation control signal BC turns on the leakage compensation module 800 (leakage compensation transistor M9), inputs a high-potential signal (second power supply signal VDD2) to the second pole of the first pull-down transistor M4A and / or the second pole of the first reset transistor M2A, reduces the voltage difference between the first pole and the second pole of the first pull-down transistor M4A, and / or reduces the voltage difference between the first pole and the second pole of the first reset transistor M2A, thereby preventing leakage and improving the potential stability of the first output terminal OUT1 and / or the first node PU1.

[0124] In some embodiments, the leakage compensation module 800 includes a leakage compensation transistor M9. The gate of the leakage compensation transistor M9 is electrically connected to the compensation control signal BC, and the first pole of the leakage compensation transistor M9 is connected to the second power supply signal VDD2.

[0125] Specifically, in some examples, the second power supply signal VDD2 and the first power supply signal VDD1 may be the same electrical signal or the same electrical signal.

[0126] In some embodiments, the control terminal of the leakage compensation module 800 is electrically connected to the first node PU1 or the second node PU2, and the potential of the compensation control signal BC is the potential of the first node PU1 or the second node PU2.

[0127] Specifically, the gate of the leakage compensation transistor M9 is electrically connected to the first node PU1 and / or the second node PU2.

[0128] Specifically, in Figure 9 the example, the second pole of the leakage compensation transistor M9 is electrically connected to the second pole of the first reset transistor M2A through a connection terminal PL or a connection electrode.

[0129] Specifically, by electrically connecting the control terminal of the leakage compensation module 800 to the first node PU1 and / or the second node PU2, when the first node PU1 and / or the second node PU2 is at a high potential (i.e., the first stage), the leakage compensation module 800 starts to work synchronously. This can not only prevent leakage and improve the potential stability of the first output terminal OUT1 and / or the first node PU1, but also reduce the number of signal lines in the display panel, which is helpful for the narrow bezel of the display panel.

[0130] Specifically, compared with Figure 8 and Figure 9 the example, Figure 10 the example illustrates that the shift register further includes a second output module 600 and a second pull-down module 700.

[0131] Embodiment 3

[0132] The shift register of this embodiment is the same as or similar to the shift register in any of the above embodiments, except that the first pull-down module 300, and / or the reset module 400, and / or the reverse control module 500 are further introduced. The improvement scheme in this embodiment can be adopted for the shift register in any of the above embodiments.

[0133] Please refer to Figures 11 to 13 , Figure 11 which is the first circuit structure diagram of a shift register provided in Embodiment 3 of the present application; Figure 12 which is the second circuit structure diagram of a shift register provided in Embodiment 3 of the present application; Figure 13 which is the third circuit structure diagram of a shift register provided in Embodiment 3 of the present application.

[0134] In some embodiments, at least one transistor in the first pull-down module 300, the reset module 400, and the reverse control module 500 is a double-gate transistor.

[0135] Specifically, the double-gate transistor includes a first sub-gate and a second sub-gate. The first sub-gate can be one of the top gate and the bottom gate, and the second sub-gate can be the other of the top gate and the bottom gate. The top gate and the bottom gate are disposed on both sides of the semiconductor layer of the double-gate transistor.

[0136] Specifically, at least one of the reset transistor M2, the pull-down transistor M4, and the first reverse transistor M5 is a double-gate transistor, and the double-gate transistors all include a first sub-gate and a second sub-gate.

[0137] In some embodiments, as Figure 11 shown, the reset module 400 includes a reset transistor M2. The first pole of the reset transistor M2 is electrically connected to the first node PU1, and the second pole of the reset transistor M2 is electrically connected to the reset signal VSS; wherein, the reset transistor M2 is a double-gate transistor and includes a first sub-gate and a second sub-gate; the first sub-gate of the reset transistor M2 is connected to the reset control signal RESET2, and the second sub-gate of the reset transistor M2 is connected to the reset gate signal VTC.

[0138] Specifically, the potential of the reset gate signal VTC is less than 0V. The reset transistor M2 is a double-gate transistor. When the Vth (threshold voltage) of the double-gate transistor is greater than 1V, the leakage risk of the reset transistor M2 can be reduced, and the potential stability of the first node PU1 can be maintained.

[0139] In some embodiments, the first pull-down module 300 includes a pull-down transistor M4. The first pole of the pull-down transistor M4 is electrically connected to the first output terminal OUT1, and the second pole of the pull-down transistor M4 accesses the reset signal VSS. Among them, the pull-down transistor M4 is a double-gate transistor and includes a first sub-gate and a second sub-gate. The first sub-gate of the pull-down transistor M4 is electrically connected to the pull-down control signal RESET1, and the second sub-gate of the pull-down transistor M4 accesses the reset gate signal VTC.

[0140] Specifically, the potential of the reset gate signal VTC is less than 0V. The pull-down transistor M4 is a double-gate transistor. When the Vth (threshold voltage) of the double-gate transistor is greater than 1V, the leakage of the pull-down transistor M4 can be reduced, and the potential stability of the first node PU1 can be maintained.

[0141] Specifically, in Figure 12 the example, the second pull-down transistor M8 can also be a double-gate transistor, which can reduce the leakage of the second pull-down transistor M8 and maintain the potential stability of the second node PU2.

[0142] In some embodiments, the reset module 500 includes a first reverse transistor M5 and a second reverse transistor M6. The first reverse transistor M5 is one of an N-type transistor and a P-type transistor; the second reverse transistor M6 is the other of an N-type transistor and a P-type transistor. Among them, the first reverse transistor M5 is a double-gate transistor and includes a first sub-gate and a second sub-gate. Among them, the first sub-gate of the first reverse transistor M5 and the gate of the second reverse transistor M6 are both electrically connected to the first node PU1. The second pole of the first reverse transistor M5 and the first pole of the second reverse transistor M6 are both connected to the second node PU2. The first pole of the first reverse transistor M5 accesses the first power supply signal VDD1, and the second pole of the second reverse transistor M6 accesses the reset signal VSS. The second sub-gate of the first reverse transistor M5 accesses the reset gate signal VTC.

[0143] Specifically, the potential of the reset gate signal VTC is less than 0V. The first reverse transistor M5 is a double-gate transistor. When the Vth (threshold voltage) of the double-gate transistor is greater than 1V, the leakage of the first reverse transistor M5 can be reduced, and the potential stability of the first node PU1 can be maintained.

[0144] In some embodiments, as Figure 13 shown, the reset gate signal VTC and the reset signal VSS are the same signal.

[0145] Specifically, the reset gate signal VTC and the reset signal VSS (when the reset signal VSS is less than 0V) are the same signal or connected, which can simplify the structure of the shift register, reduce the number of traces in the display panel, and is beneficial to narrow bezel design.

[0146] It should be noted that in some embodiments, the first power signal VDD1 and the second power signal VDD can be the same signal or signals with the same potential; in some embodiments, the pull-down control signal RESET1 and the reset control signal RESET2 can be the same signal or signals with the same potential. This not only has the same effects as the above embodiments, but also simplifies the structure of the shift register, reduces the number of traces in the display panel, and is beneficial to narrow bezel design.

[0147] It should be noted that the technical features in the above embodiments / examples can be combined with each other to obtain a new shift register.

[0148] This application also provides a gate driving circuit, which includes a plurality of cascaded shift registers. The shift register is the shift register in any one of the above embodiments or the shift register combined with any two or more technical features in the above embodiments.

[0149] This application also provides a display device, which includes the gate driving circuit in any one of the above. The gate driving circuit includes the shift register in any one of the above or the shift register combined with any two or more technical features in the above embodiments.

[0150] Specifically, the display device can be a smart phone, a laptop computer, a television, a tablet computer or other displays, and the embodiments of this application do not make specific limitations.

[0151] It should be noted that in the above embodiments, the descriptions of the various embodiments have their own focuses. For the parts not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0152] The above embodiments are only used to illustrate the technical solutions of this application, rather than to limit them; although this application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the various embodiments of this application.

[0153] Although the preferred embodiments of this specification have been described, additional changes and modifications can be made by those skilled in the art once they learn of the basic creative concept. Therefore, the appended claims are intended to be interpreted to include the preferred embodiments as well as all changes and modifications that fall within the scope of this specification.

[0154] Obviously, those skilled in the art can make various changes and modifications to this specification without departing from the spirit and scope of this specification. Thus, if these modifications and variations of this specification fall within the scope of the claims of this specification and their equivalent technologies, this specification is also intended to include these modifications and variations.

Claims

1. A shift register, characterized in that, it includes an input terminal and a first output terminal, and the shift register further includes: an input module, electrically connected to the input terminal and a first node, the input module being configured to charge the first node under the control of a signal at the input terminal; a first output module, electrically connected to the first output terminal and a second node, the first output module being configured to output a first output signal at the first output terminal under the control of a signal at the second node; a first pull-down module, electrically connected to the first output terminal, the first pull-down module being configured to pull down the potential of the first output terminal under the control of a pull-down control signal; a reset module, electrically connected to the first node, the reset module being configured to pull down the potential of the first node under the control of a reset control signal; a reverse control module, electrically connected between the first node and the second node, the reverse control module including a first sub-input terminal and a second sub-input terminal, the first sub-input terminal being configured to receive a high-potential signal, the second sub-input terminal being configured to receive a low-potential signal, the reverse control module being configured to pull up or pull down the potential of the second node under the control of a signal at the first node; wherein, the reverse control module is directly connected to the control terminal of the first output module through the second node.

2. The shift register according to claim 1, characterized in that, the first output module includes: a first output transistor, and the reverse control module is directly connected to the gate of the first output transistor through the second node.

3. The shift register according to claim 2, characterized in that, the reverse control module includes: a first reverse transistor, which is one of an N-type transistor and a P-type transistor; a second reverse transistor, which is the other of an N-type transistor and a P-type transistor; wherein, the gates of the first reverse transistor and the second reverse transistor are both electrically connected to the first node, the second pole of the first reverse transistor and the first pole of the second reverse transistor are both connected to the second node, the first pole of the first reverse transistor receives a first power supply signal, and the second pole of the second reverse transistor receives a reset signal.

4. The shift register according to claim 1, characterized in that, it further includes: a second output terminal; a second output module, electrically connected to the second output terminal, the second output module being configured to output a second output signal at the second output terminal under the control of the potential of the second node; wherein, the reverse control module is directly connected to the control terminal of the second output module through the second node.

5. The shift register according to claim 4, characterized in that, the second output module includes a second output transistor, and the reset module is directly connected to the gate of the second output transistor through the second node.

6. The shift register according to claim 4, characterized in that, it further includes: a second pull-down module, electrically connected to the second output terminal, the second pull-down module being configured to pull down the potential of the second output terminal under the control of the pull-down control signal.

7. The shift register according to claim 1, characterized in that, the first pull-down module includes: a first pull-down transistor, with a first pole electrically connected to the first output terminal; a second pull-down transistor, with a first pole electrically connected to a second pole of the first pull-down transistor, and a second pole of the second pull-down transistor accessing a reset signal; the gates of the first pull-down transistor and the second pull-down transistor both access the pull-down control signal.

8. The shift register according to claim 7, characterized in that, the reset module includes: a first reset transistor, with a first pole electrically connected to the first node; a second reset transistor, with a first pole electrically connected to a second pole of the first reset transistor, and a second pole of the second reset transistor electrically connected to the reset signal; the gates of the first reset transistor and the second reset transistor are both electrically connected to the reset control signal.

9. The shift register according to claim 7 or 8, characterized in that, it further includes: a leakage compensation module, with an output terminal at least electrically connected to a second pole of the first pull-down transistor or a second pole of the first reset transistor, and the leakage compensation module is configured to at least raise the potential of the second pole of the first pull-down transistor or the second pole of the first reset transistor under the control of a compensation control signal.

10. The shift register according to claim 9, characterized in that, the leakage compensation module includes: a leakage compensation transistor, with a gate electrically connected to the compensation control signal, and a first pole of the leakage compensation transistor accessing a second power supply signal, the.

11. The shift register according to claim 9, characterized in that, a control terminal of the leakage compensation module is electrically connected to the first node or the second node, and the potential of the compensation control signal is the potential of the first node or the second node.

12. The shift register according to claim 1, characterized in that, at least one transistor in the first pull-down module, the reset module, and the reverse control module is a double-gate transistor.

13. The shift register according to claim 12, characterized in that, the reset module includes: a reset transistor, with a first pole electrically connected to the first node, and a second pole of the reset transistor electrically connected to the reset signal; wherein, the reset transistor is a double-gate transistor and includes a first sub-gate and a second sub-gate; the first sub-gate of the reset transistor accesses the reset control signal, and the second sub-gate of the reset transistor accesses a reset gate signal.

14. The shift register according to claim 12, characterized in that, the first pull-down module includes: a pull-down transistor, with a first pole electrically connected to the first output terminal, and a second pole of the pull-down transistor accessing the reset signal; wherein, the pull-down transistor is a double-gate transistor and both include a first sub-gate and a second sub-gate; the first sub-gate of the pull-down transistor is electrically connected to the pull-down control signal, and the second sub-gate of the pull-down transistor accesses the reset gate signal.

15. The shift register according to claim 12, characterized in that, the reverse control module includes: The first reverse transistor is one of an N-type transistor and a P-type transistor; The second reverse transistor is the other of the N-type transistor and the P-type transistor; Wherein, the first reverse transistor is a double-gate transistor and includes a first sub-gate and a second sub-gate; Wherein, the first sub-gate of the first reverse transistor and the gate of the second reverse transistor are both electrically connected to the first node, the second pole of the first reverse transistor and the first pole of the second reverse transistor are both connected to the second node, the first pole of the first reverse transistor accesses a first power signal, and the second pole of the second reverse transistor accesses a reset signal; the second sub-gate of the first reverse transistor accesses a reset gate signal.

16. The shift register according to any one of claims 12 to 15, characterized in that the reset gate signal and the reset signal are the same signal.

17. A gate driving circuit includes a plurality of cascaded shift registers according to any one of claims 1 to 16.

18. A display device includes the gate driving circuit according to any one of claim 17.

19. A method for driving the shift register according to any one of claims 1 to 16, characterized in that it includes: In a first stage, a first level is input to the input terminal so that the input module raises the potential of the first node under the action of the first level, and the reverse control module raises the potential of the second node under the action of the high potential of the first node, so that the first output module is turned on and the first output signal is output at the first output terminal; In a second stage, a second level is input to the input terminal, the reset control signal and the pull-down control signal are low potential signals, the reset module pulls down the potential of the first node under the control of the reset control signal, the reverse control module pulls down the potential of the second node under the action of the low potential of the first node, and the first pull-down module pulls down the potential of the first output terminal under the control of the pull-down control signal.

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