Receiving circuit and communication equipment

Abstract

The invention discloses a receiving circuit and communication equipment, and belongs to the field of communication. The receiving circuit comprises an analog circuit and a digital circuit; the analog circuit comprises a numerical control delay module; the digital circuit comprises a frequency detection module, a parameter management module and a data receiving module; the frequency detection module is used for detecting the frequency of the target clock signal to obtain a frequency detection result and transmitting the frequency detection result to the parameter management module; the parameter management module is used for obtaining the optimal value of the target receiving parameter based on the frequency detection result, and transmitting the optimal value of the target receiving parameter to the numerical control delay module and the data receiving module; the numerical control delay module is used for calibrating the digital clock signal according to the optimal numerical value of the target receiving parameter to obtain a calibrated digital clock signal; the data receiving module is used for receiving target data according to the optimal numerical value of the target receiving parameter; the target data is obtained by sampling the data from the transmitting end according to the calibrated digital clock signal by the analog circuit.

Description

Technical Field

[0001] This application belongs to the field of communications, and particularly relates to a receiving circuit and a communication device. Background Art

[0002] Currently, in order to ensure that the receiving (RX) end can correctly receive the data sent by the transmitting (TX) end, the RX end needs to know in advance the current rate information of the TX end, so that the receiving rate of the RX end matches the transmitting rate of the TX.

[0003] In related technologies, the RX end first needs to obtain the current rate information of the TX end, and based on the current rate information of the TX end, configure the receiving rate of the RX end, then complete the initialization of the TX end and the RX end, and finally the RX end can normally interact with the TX end for data.

[0004] However, for the MIPI (Mobile Industry Processor Interface) D-PHY (Physical Layer) communication protocol, since there is no regulation on the process of rate negotiation between the TX end and the RX end, the two steps of the RX end obtaining the rate information of the TX and configuring the rate information of the RX end cannot be automatically completed and require manual operation by the user, which affects the communication efficiency. Summary of the Invention

[0005] Embodiments of this application provide a receiving circuit and a communication device, which can solve the problem in related technologies that the communication efficiency is affected by the RX end manually obtaining the rate information of the TX.

[0006] In a first aspect, embodiments of this application provide a receiving circuit, including: an analog circuit and a digital circuit. The analog circuit includes a numerically controlled delay module; the digital circuit includes a frequency detection module, a parameter management module, and a data receiving module connected in sequence; the parameter management module is connected to the numerically controlled delay module, and the numerically controlled delay module is coupled to the data receiving module; The frequency detection module is configured to detect the frequency of a target clock signal to obtain a frequency detection result; and transmit the frequency detection result to the parameter management module; wherein, the target clock signal is obtained based on a differential clock signal from a transmitting end; The parameter management module is configured to obtain an optimal value of a target receiving parameter based on the frequency detection result, and transmit the optimal value of the target receiving parameter to the numerically controlled delay module and the data receiving module; The numerically controlled delay module is configured to calibrate a digital clock signal according to the optimal value of the target receiving parameter to obtain a calibrated digital clock signal; wherein, the digital clock signal is obtained based on a differential clock signal from a transmitting end; The data receiving module is configured to receive target data according to the optimal value of the target receiving parameter; wherein, the target data is obtained by an analog circuit sampling the data from the sending end according to the calibrated digital clock signal.

[0007] In a second aspect, an embodiment of the present application provides a communication device, including the receiving circuit as described in the first aspect.

[0008] In an embodiment of the present application, the receiving circuit includes an analog circuit and a digital circuit. The analog circuit includes a numerically controlled delay module; the digital circuit includes a frequency detection module, a parameter management module, and a data receiving module connected in sequence; the parameter management module is connected to the numerically controlled delay module, and the numerically controlled delay module is coupled to the data receiving module; the frequency detection module is configured to detect the frequency of the target clock signal to obtain a frequency detection result; and transmit the frequency detection result to the parameter management module; wherein, the target clock signal is obtained based on the differential clock signal from the sending end; the parameter management module is configured to obtain the optimal value of the target receiving parameter based on the frequency detection result, and transmit the optimal value of the target receiving parameter to the numerically controlled delay module and the data receiving module; the numerically controlled delay module is configured to calibrate the digital clock signal according to the optimal value of the target receiving parameter to obtain a calibrated digital clock signal; wherein, the digital clock signal is obtained based on the differential clock signal from the sending end; the data receiving module is configured to receive target data according to the optimal value of the target receiving parameter; wherein, the target data is obtained by the analog circuit sampling the data from the sending end according to the calibrated digital clock signal. In this way, compared with the related art where the frequency information of the sending end needs to be manually obtained, in the receiving circuit provided by the embodiment of the present application, the frequency detection result of the sending end is detected by the frequency detection module, and based on the frequency detection result, the optimal value of the target receiving parameter is obtained, so as to enable the numerically controlled delay module to calibrate the digital clock signal according to the optimal value of the target receiving parameter, and then obtain the calibrated digital clock signal, thereby assisting the data receiving module to correctly receive the data from the sending end. Compared with the related art, the step of obtaining the frequency information of the sending end is omitted, and the function of adapting to the current rate of the sending end is realized, improving the communication efficiency. Description of the Drawings

[0009] Figure 1 It is a schematic diagram of the ideal phase of the clock lane and data lane of the receiving end in the related art; Figure 2 It is a schematic diagram of the actual phase of the clock lane and data lane of the receiving end in the related art; Figure 3 It is a schematic flowchart of the communication method between the receiving end and the sending end in the related art; Figure 4 A schematic structural diagram of a receiving circuit provided by an embodiment of the present application; Figure 5 A schematic diagram of the principle of a frequency detection module in the receiving circuit provided by an embodiment of the present application; Figure 6 Another schematic structural diagram of a receiving circuit provided by an embodiment of the present application; Figure 7 A schematic flowchart of a communication method provided by an embodiment of the present application; Figure 8 A schematic diagram of a communication device provided by an embodiment of the present application.

[0010] Explanation of reference numerals: 10 - receiving circuit; 100 - analog circuit; 110 - numerically controlled delay module; 120 - first analog-to-digital converter; 130 - frequency divider; 140 - second analog-to-digital converter; 150 - data sampling module; 160 - serial-to-parallel conversion module; 200 - digital circuit; 210 - frequency detection module; 220 - parameter management module; 230 - data receiving module; 80 - communication device; clock lane - clock channel; data lane - data channel. Detailed implementation manners

[0011] Next, the technical solutions in the embodiments of the present application will be clearly described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art belong to the scope of protection of the present application.

[0012] The terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects, rather than to describe a specific order or sequence. It should be understood that such used data may be interchanged under appropriate circumstances so that the embodiments of the present application can be implemented in an order other than those illustrated or described herein, and the objects distinguished by "first", "second", etc. are generally of the same category, and the number of objects is not limited. For example, the first object may be one or more. In addition, "and / or" in the specification and claims means at least one of the connected objects, and the character " / " generally means an "or" relationship between the associated objects before and after.

[0013] Currently, the MIPI D-PHY protocol supports a very wide range of speeds. For example, the MIPI D-PHY 1.2 protocol stipulates that the speed in the high speed (HS) mode can be any speed within 80 Mbps to 2500 Mbps. The protocol stipulates that part of the timing at the RX (receive) end is related to the speed at the TX (transmit) end. The RX end needs to know the speed at which the TX end sends data before receiving data. On the premise that the speed received by the RX end matches the speed sent by the TX end, the RX end can correctly receive the data sent by the TX end.

[0014] For example, Table 1 below is the receive parameter table for the RX end.

[0015]

[0016] Table 1 Among them, T HS-SETTLE and T HS-SKIP are two receive parameters corresponding to the timing requirements for the RX end in the MIPI D-PHY protocol. T HS-SETTLE refers to the time interval required to discard unstable data when starting to transmit HS data. T HS-SKIP refers to the time interval required to discard unstable data when the HS data transmission ends. Among them, the protocol specifically requires that within the time range of T HS-SETTLE and T HS-SKIP , the RX end needs to ignore the accessed data. If the T HS-SETTLE and T HS-SKIP configured by the RX end do not meet the protocol requirements, the RX end may receive incorrect (data that should have been discarded) data, resulting in the RX end detecting incorrect SoT (Start of Transmission, the starting point of the data packet) and EoT (End of Transmission, the end point of the data packet), thus affecting the correct reception of the entire data packet. As can be seen from Table 1, the RX end configures the optimal values of T HS-SETTLE and T HS-SKIP according to UI (Unit Interval). It should be noted that UI is equal to half of the clock cycle on the clock lane. The specific value of UI is related to the data rate sent by the TX end. The configuration of the receive parameters at the RX end needs to first obtain the rate information of the TX end.

[0017] In summary, in order to ensure that the RX end correctly receives the data packet, it is necessary to first obtain the rate information of the TX end, thereby determining the specific value of UI, and then configuring the optimal values of T HS-SETTLE and T HS-SKIP at the RX end.

[0018] Moreover, the MIPI D-PHY protocol also stipulates that when the rate is higher than 1.5 Gbps, the RX side needs to perform de-skew (compensation for phase deviation) calibration to align the clock signal (clock) of the clock lane to the middle of the data signal (data) of the data lane. For example, Figure 1 is a schematic diagram of the ideal phase of the clock lane and the data lane. As Figure 1 shown, the transition edge of the clock lane is aligned to the center point A of the data lane, which is the ideal sampling point. At this time, the skew (offset) between the clock lane and the data lane does not need to be adjusted, and the RX side can sample the correct data.

[0019] Considering the channel differences between the clock lane and the data lane from D-PHY TX to D-PHY RX, in fact, the transition edge of the clock lane will not perfectly fall on point A, but near point A. Figure 2 is a schematic diagram of the actual phase of the clock lane and the data lane. As Figure 2 shown, the transition edge of the clock lane falls on point D of the data lane. The distance between A and D is the skew (offset) that needs to be calibrated. Considering the worst-case scenario, the transition edge of the clock lane falls on point B / C of the data lane, that is, Figure 2 in which point D coincides with point B / C. At this time, the skew (offset) reaches the maximum, which is UI / 2. Therefore, the maximum skew that the RX needs to calibrate is related to the rate of the TX side.

[0020] Among them, the lower the TX rate, the larger the maximum skew (offset) that the RX needs to calibrate. The larger the skew that the RX calibration needs to cover, the larger the minimum step (unit step) of the calibration, and the greater the calibration error. In order to reduce the calibration error of the RX, the RX side needs to obtain the current rate of the TX side in order to cover the maximum skew at the current rate.

[0021] In summary, during the de-skew calibration process at the RX side, since the maximum skew that the RX side needs to calibrate is related to the rate of the TX side, when used at the D-PHY RX side, in order to ensure that the RX side can complete the de-skew calibration more accurately, the RX side needs to obtain the rate of the TX side in advance during calibration.

[0022] Based on this, as Figure 3 shown, the communication method between the receiving end and the transmitting end in the related art may include: Step 310: The RX end obtains the rate information of the TX end; Step 320: The TX end powers on and initializes; Step 330: The RX end configures the RX end rate based on the rate information of the TX end, and the RX end powers on and initializes; Step 340: The TX end sends data, and the RX end receives data.

[0023] Among them, in the related art, the RX end first needs to obtain the rate of the TX, and configure the receiving rate information of the RX end (such as receiving parameters T HS-SETTLE and T HS-SKIP ) based on the rate information of the TX end, then complete the initialization of the TX end and the RX end, and finally the RX end can normally perform data interaction with the TX end.

[0024] Among them, in the actual application process, a D-PHY RX product will interface with various D-PHY TX products on the market, and the rates of various TX products may also be different. The RX end needs to obtain the rate information of the TX through manual operations by the user. For example, the user queries the user manual of the TX product to obtain the rate information of the TX; the user measures the rate of the TX using an oscilloscope; or the user asks the manufacturer of the TX product to obtain the rate of the TX, and so on.

[0025] Since the MIPI D-PHY protocol does not stipulate the process of rate negotiation between the TX and the RX, the two steps of the RX end obtaining the rate information of the TX in step 310 and configuring the rate information of the RX end in step 330 cannot be automatically completed and require manual operations by the user, and the user needs to have a certain technical foundation, which will cause troubles to some novice users in use.

[0026] In summary, in order to avoid the above problems, the embodiment of the present application can provide a receiving circuit, and the receiving circuit can detect the rate information of the TX end through the clock signal sent by the TX end, so as to implement the adaptive function of the access rate of the RX end.

[0027] Next, in conjunction with the accompanying drawings, the receiving circuit and the communication device provided by the embodiment of the present application will be described in detail through specific embodiments and their application scenarios.

[0028] Figure 4 It is a schematic structural diagram of a receiving circuit provided by an embodiment of the present application.

[0029] As Figure 4As shown in the figure, the receiving circuit 10 provided in the embodiment of the present application may include: an analog circuit 100 and a digital circuit 200. The analog circuit 100 includes a numerically controlled delay module 110; the digital circuit 200 includes a frequency detection module 210, a parameter management module 220, and a data receiving module 230 that are connected in sequence; the parameter management module 220 is connected to the numerically controlled delay module 110, and the numerically controlled delay module 110 is coupled to the data receiving module 230; The frequency detection module 210 is used to detect the frequency of the target clock signal to obtain a frequency detection result; and transmit the frequency detection result to the parameter management module 220; wherein, the target clock signal is obtained based on the differential clock signal from the sending end; The parameter management module 220 is used to obtain the optimal value of the target receiving parameter based on the frequency detection result, and transmit the optimal value of the target receiving parameter to the numerically controlled delay module 110 and the data receiving module 230; The numerically controlled delay module 110 is used to calibrate the digital clock signal according to the optimal value of the target receiving parameter to obtain a calibrated digital clock signal; wherein, the digital clock signal is obtained based on the differential clock signal from the sending end; The data receiving module 230 is used to receive the target data according to the optimal value of the target receiving parameter; wherein, the target data is sampled by the analog circuit 100 from the data from the sending end according to the calibrated digital clock signal.

[0030] In the embodiment of the present application, the frequency detection result can be understood as the detection result of the current rate of the sending end (TX end).

[0031] In the embodiment of the present application, the target receiving parameter is the receiving parameter corresponding to the timing requirement for the RX end in the standard protocol (such as the MIPI D-PHY protocol), and the optimal value of the target receiving parameter can be configured based on the frequency detection result corresponding to the current rate of the sending end.

[0032] In the embodiment of the present application, the data receiving module receives the data from the sending end based on the optimal value of the target receiving parameter to achieve correct reception of the data.

[0033] It should be noted that, compared with the method in the related art that requires manual acquisition of the frequency information of the sending end, in the embodiment of the present application, the frequency detection module detects the frequency detection result of the sending end, and configures the target receiving parameter based on the frequency detection result, so as to enable the numerically controlled delay module to calibrate the digital clock signal according to the optimal value of the target receiving parameter, and then obtain the calibrated digital clock signal, thereby assisting the data receiving module to correctly receive the data from the sending end. Compared with the related art, the step of acquiring the frequency information of the sending end is omitted, the function of adapting to the current rate of the sending end is realized, the communication efficiency is improved, and the user experience can be enhanced.

[0034] According to the receiving circuit provided by the embodiment of the present application, it includes an analog circuit and a digital circuit. The analog circuit includes a numerically controlled delay module; the digital circuit includes a frequency detection module, a parameter management module, and a data receiving module connected in sequence. The frequency detection module is used to detect the frequency of the target clock signal to obtain a frequency detection result, and transmit the frequency detection result to the parameter management module. The parameter management module is connected to the numerically controlled delay module, and the numerically controlled delay module is coupled to the data receiving module. Among them, the target clock signal is obtained based on the differential clock signal from the sending end. The parameter management module is used to obtain the optimal value of the target receiving parameter based on the frequency detection result, and transmit the optimal value of the target receiving parameter to the numerically controlled delay module and the data receiving module. The numerically controlled delay module is used to calibrate the digital clock signal according to the optimal value of the target receiving parameter to obtain a calibrated digital clock signal. Among them, the digital clock signal is obtained based on the differential clock signal from the sending end. The data receiving module is used to receive the target data according to the optimal value of the target receiving parameter. Among them, the target data is sampled by the analog circuit from the data from the sending end according to the calibrated digital clock signal. In this way, compared with the related technology that requires manual acquisition of the frequency information of the sending end, in the receiving circuit provided by the embodiment of the present application, the frequency detection module detects the frequency detection result of the sending end, and based on the frequency detection result, obtains the optimal value of the target receiving parameter, so as to realize that the numerically controlled delay module calibrates the digital clock signal according to the optimal value of the target receiving parameter, and then obtains a calibrated digital clock signal, so as to assist the data receiving module to correctly receive the data from the sending end. Compared with the related technology, the step of obtaining the frequency information of the sending end is omitted, and the function of adapting to the current rate of the sending end is realized, and the communication efficiency is improved.

[0035] In a specific embodiment, in order to accurately detect the current rate of the sending end, in the receiving circuit provided by the embodiment of the present application, the frequency detection module 210 can be used to determine the sampling window by using the internal clock signal, determine the number of cycles of the target clock signal within the sampling window, and calculate the frequency detection result based on the sampling window and the number of cycles.

[0036] For example, the internal implementation principle of the frequency detection module 210 is as Figure 5 shown. The frequency detection module 210 can use an accurate internal clock signal CFG_CLK to count a sampling window T. Determine the number of cycles C of the target clock signal CLK_DDR within the sampling window T, and calculate the frequency detection result based on the sampling window T and the number of cycles C.

[0037] Among them, the formula f CLK_DDR = C / T can be used to obtain the frequency f of the target clock signal CLK_DDR CLK_DDR. On this basis, since the MIPI D-PHY product uses double-edge transmission, the current rate at the TX end is twice the frequency of the target clock signal CLK_DDR. The formula for the TX rate can be f tx = 2f CLK_DDR = 2C / T.

[0038] For example, assume that the sampling window T is 1 ms (the internal clock signal CFG_CLK is 25 MHz, and when the CFG_CLK counts 25,000 cycles, a 1-ms sampling window of 1 ms can be obtained). The number of cycles C of the target clock signal CLK_DDR within the sampling window T is 1,200,000. According to the formula, the frequency f of the target clock signal CLK_DDR can be obtained CLK_DDR = 1,200,000 / 0.001 (s) = 1,200,000,000 Hz = 1.2 GHz. Then, the current rate f at the TX end can be obtained tx = 2f CLK_DDR = 2.4 Gbps.

[0039] In practical applications, the frequency detection module of the receiving circuit is simulated. When T is 1 ms and C is 739,650, the value of f can be obtained according to the formula tx is 1.4793 Gbps. The actual TX rate in the simulation is 1.479 Gbps, which is consistent with the result obtained by the frequency detection module. It can be seen that the detection accuracy of the frequency detection module in the receiving circuit is relatively high.

[0040] In a specific embodiment, the target receiving parameters are used by the data receiving module to correctly receive data, and the optimal value of the target receiving parameters is the best value of the target receiving parameters. To ensure the accuracy of the optimal value of the target receiving parameters, the parameter management module 220 can be used to determine the target unit interval UI based on the frequency detection result; and calculate the target receiving parameters based on the target unit interval UI to obtain the optimal value of the target receiving parameters.

[0041] For example, the target receiving parameters include the first timing parameter T HS-SETTLE and the second timing parameter T HS-SKIP (refer to Table 1 above).

[0042] Among them, the first timing parameter T HS-SETTLE is the time interval required to discard unstable data when starting to transmit HS data. Among them, the second timing parameter T HS-SKIP is the time interval required to discard unstable data when the HS data transmission ends.

[0043] Among them, unstable data refers to data that is not stable, that is, invalid data that needs to be discarded. For example, invalid data that needs to be discarded when starting to transmit HS data, or invalid data that needs to be discarded when the HS data transmission ends.

[0044] Among them, the first timing parameter T HS-SETTLE The optimal value and the second timing parameter T HS-SKIP The optimal value is determined based on the target unit interval UI.

[0045] Among them, HS data is data transmitted in a communication mode where the communication rate is within a specified range. For example, in practical applications, HS data can be data transmitted in the high-speed mode specified by a standard protocol. For example, the MIPI D-PHY1.2 protocol stipulates that the rate of the high-speed (HS) mode can be any rate within 80 Mbps to 2500 Mbps. Correspondingly, HS data is data transmitted in a communication mode where the communication rate is within 80 Mbps to 2500 Mbps.

[0046] Among them, the frequency detection module 210 outputs the detection result (f tx ) to the parameter management module 220, and calculates the size of the target unit interval UI according to the formula UI = 1 / f tx

[0047] For example, assume f tx = 1.4793 Gbps, UI = 1 / (1.4793 Gbps) = 0.676 ns. The minimum value, maximum value, and optimal value of T HS-SETTLE and T HS-SKIP at the current transmission rate can be obtained as shown in Table 2 below:

[0048] Table 2 Among them, the parameter management module 220 can calculate the optimal values of T tx and T HS-SETTLE and T HS-SKIP based on the frequency detection result f output by the frequency detection module 210, and then give the optimal value to the data receiving module 230 to complete the correct reception of the data.

[0049] In this way, the receiving circuit provided by the embodiment of the present application can detect the current rate of the TX end, so that the RX end can work at a rate matching the TX end, realizing the function of automatically adapting to the TX rate.

[0050] In another specific embodiment, in order to access the clock signal from the TX end for frequency detection, as Figure 6As shown in the figure, in the receiving circuit provided by the embodiment of the present application, the analog circuit 100 may further include: a first analog-to-digital converter 120 and a frequency divider 130. Among them, the first analog-to-digital converter 120 is connected to the frequency divider 130, and the frequency divider 130 is connected to the frequency detection module 210.

[0051] In the embodiment of the present application, the first analog-to-digital converter 120 is configured to receive a differential clock signal from the sending end through a first analog front end and convert the differential clock signal into a digital clock signal. In the embodiment of the present application, the frequency divider 130 is configured to perform frequency division processing on the digital clock signal to obtain a target clock signal and transmit the target clock signal to the frequency detection module 210.

[0052] In this way, in the receiving circuit provided by the embodiment of the present application, the first analog-to-digital converter 120 converts the differential clock signal (DP_CK / DN_CK) transmitted from the TX end into a digital clock signal (CLKP / CLKN) through the first analog front end. The frequency divider 130 performs frequency division processing on the digital clock signal (CLKP / CLKN) to obtain a target clock signal CLK_DDR, and then connects the target clock signal CLK_DDR to the frequency detection module 210 for frequency detection to obtain a frequency detection result.

[0053] In addition, the first analog-to-digital converter 120 is further configured to transmit the digital clock signal (CLKP / CLKN) to the numerically controlled delay module 110. In this way, the numerically controlled delay module 110 can calibrate the digital clock signal according to the optimal value of the target reception parameter to obtain a calibrated digital clock signal, and the calibrated digital clock signal can be aligned to the middle of the data signal (to be sampled) to assist in the correct sampling of the data.

[0054] In another specific embodiment, in order to receive data from the TX end, as Figure 6 As shown in the figure, in the receiving circuit 10 provided by the embodiment of the present application, the analog circuit 100 may further include: a second analog-to-digital converter 140 and a data sampling module 150; among them, the second analog-to-digital converter 140 is connected to the data sampling module 150, the numerically controlled delay module 110 is connected to the data sampling module 150, and the data sampling module 150 is coupled to the data receiving module 230.

[0055] In the embodiment of the present application, the second analog-to-digital converter 140 may be configured to convert the differential data signal (DP_DX / DN_DX) transmitted from the TX end into a digital data signal through a second analog front end. In the embodiment of the present application, the data sampling module 150 may be configured to sample the digital data signal output by the second analog-to-digital converter 140.

[0056] Thus, in the receiving circuit provided by the embodiments of the present application, the differential data signal (DP_DX / DN_DX) transmitted from the TX end is converted into a digital data signal by the second analog-to-digital converter 140, and the digital data signal is sampled by the data sampling module 150 to realize data sampling.

[0057] In a specific embodiment, during the process of the data sampling module 150 sampling the digital data signal, in order to correctly receive the data, a numerically controlled delay module can be used for de-skew calibration to calibrate the clock signal (clock) to the middle of the data signal (data). As Figure 6 shown, the receiving circuit provided by the embodiments of the present application further includes: a numerically controlled delay module 110; wherein, the first analog-to-digital converter 120 is connected to the numerically controlled delay module 110, the parameter management module 220 is connected to the numerically controlled delay module 110, and the numerically controlled delay module 110 is connected to the data sampling module 150.

[0058] In the embodiments of the present application, the first analog-to-digital converter 120 is further configured to transmit the digital clock signal (CLKP / CLKN) to the numerically controlled delay module 110; In the embodiments of the present application, the parameter management module 220 is further configured to transmit the optimal value of the configured target receiving parameter to the numerically controlled delay module 110; In the embodiments of the present application, the numerically controlled delay module 110 is configured to calibrate the digital clock signal (CLKP / CLKN) based on the optimal value of the configured target receiving parameter to obtain a calibrated digital clock signal, and transmit the calibrated digital clock signal to the data sampling module 150, so that the data sampling module 150 can correctly sample the digital data signal output by the second analog-to-digital converter 140 based on the calibrated digital clock signal.

[0059] Thus, in the receiving circuit provided by the embodiments of the present application, the numerically controlled delay module 110 calibrates the digital clock signal, so that the data sampling module 150 can realize correct data sampling based on the calibrated digital clock signal.

[0060] In a specific embodiment, in order to output an effective data signal and a working clock signal, as Figure 6 shown, in the receiving circuit 10 provided by the embodiments of the present application, the analog circuit 100 may further include a serial-to-parallel conversion module 160, and the data sampling module 150 is connected to the data receiving module 230 via the serial-to-parallel conversion module 160; the numerically controlled delay module 110 is connected to the serial-to-parallel conversion module 160.

[0061] In the embodiments of the present application, the numerically controlled delay module 110 is further configured to transmit the calibrated digital clock signal to the serial-to-parallel conversion module 160; In the embodiment of the present application, the serial-parallel conversion module 160 is configured to perform serial-parallel conversion processing on the sampled data output by the data sampling module 150 based on the calibrated digital clock signal, to obtain a valid data signal MIPI_DATA[7:0] and a working clock signal MIPI_WORD_CLK, and output them to the data receiving module 230.

[0062] In this way, in the receiving circuit provided by the embodiment of the present application, the serial-parallel conversion module 160 can perform serial-parallel conversion processing on the sampled data output by the data sampling module 150 based on the calibrated digital clock signal, and output a valid data signal MIPI_DATA[7:0] and a working clock signal MIPI_WORD_CLK to the data receiving module 230.

[0063] In practical applications, referring to Figure 6 , the receiving circuit 10 provided by the embodiment of the present application may include an analog circuit 100 part and a digital circuit 200 part; the analog circuit 100 part is further divided into a clock lane and a data lane; wherein the clock lane converts the differential clock signal (DP_CK / DN_CK) transmitted by the TX end into a digital clock signal (CLKP / CLKN), and the digital clock signal (CLKP / CLKN) is used for the numerically controlled delay module 110 in the data lane. The numerically controlled delay module 110 performs de-skew calibration to calibrate the clock signal (clock) to the middle of the data signal (data), so that the data sampling module 150 can sample the correct data, and finally outputs MIPI_DATA[7:0] and MIPI_WORD_CLK to the data receiving module 230 of the digital circuit part through the serial-parallel conversion module 160.

[0064] Among them, for the digital circuit part of the receiving circuit, it mainly includes a frequency detection module 210, a parameter management module 220, and a data receiving module 230. Among them, the parameter management module 220 is responsible for outputting the optimal values of the first timing parameter T HS-SETTLE and the second timing parameter T HS-SKIP corresponding to the current transmission rate to the data receiving module 230 to complete the correct reception of the data.

[0065] Among them, the innovation of the receiving circuit provided by the embodiment of the present application lies in adding a frequency detection module 210 in the digital circuit part, connecting the target clock signal CLK_DDR output by the clock lane to the frequency detection module 210 for frequency detection, obtaining a frequency detection result (f tx ), and the frequency detection result (f tx), which is given to the parameter management module 220. Based on the frequency detection result (f tx ), the parameter management module configures the optimal values of T HS-SETTLE and T HS-SKIP at the current rate, and transmits the optimal values of T HS-SETTLE and T HS-SKIP to the numerical control delay module 110 and the data receiving module 230.

[0066] In this way, the receiving circuit provided by the embodiment of the present application can detect the current rate of the TX end, configure the optimal values of T HS-SETTLE and T HS-SKIP based on the current rate of the TX end, complete the correct reception of the data by the data receiving module 230, so that the RX end can work at a rate matching the TX end, and realize the function of automatically adapting to the TX rate.

[0067] On the other hand, referring to Figure 7 , a communication method provided by the embodiment of the present application may include: Step 710: Power on and initialize the TX end; Step 720: Power on and initialize the RX end; Step 730: The TX end sends data, and the RX end receives data.

[0068] Among them, the RX end includes the receiving circuit provided by the embodiment of the present application, and the RX end can implement all functions of the receiving circuit. To avoid repetition, it will not be elaborated here.

[0069] In this way, compared with the communication process in the related art (such as Figure 3 ), the communication method provided by the embodiment shown in the present application Figure 7 optimizes the communication process shown in Figure 3 , omits the two steps of obtaining the rate of the TX end and configuring the rate of the RX end, enables the RX end to realize the function of adapting to the TX rate, and effectively solves the pain points of users in use.

[0070] Based on the same concept as the above-mentioned receiving circuit embodiment, the embodiment of the present application also provides a communication device.

[0071] As Figure 8 shown, the embodiment of the present application provides a communication device 80, including the receiving circuit 10 of the above embodiment.

[0072] It should be noted that in practical applications, the communication device provided by the embodiment of the present application includes the receiving circuit provided by the above embodiment, and realizes all functions of the receiving circuit. To avoid repetition, it will not be elaborated here.

[0073] It should be noted that in this text, the term "including", "comprising" or any other variant thereof is intended to cover non-exclusive inclusion, such that a process, method, article or device including a series of elements not only includes those elements but also other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the phrase "including a..." does not exclude the presence of additional identical elements in the process, method, article or device including such element. In addition, it should be pointed out that the scope of the methods and devices in the embodiments of the present application is not limited to performing functions in the order shown or discussed, but may also include performing functions in a substantially simultaneous manner or in the reverse order according to the functions involved. For example, the described methods may be performed in an order different from that described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.

[0074] Through the description of the above embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus a necessary general hardware platform. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation. Based on such an understanding, the technical solution of the present application, in essence, or the part that contributes to the prior art can be embodied in the form of a computer software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disc) and includes several instructions for causing a terminal (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods of the various embodiments of the present application.

[0075] The embodiments of the present application have been described above with reference to the accompanying drawings. However, the present application is not limited to the above specific embodiments. The above specific embodiments are merely illustrative and not restrictive. Under the inspiration of the present application, those of ordinary skill in the art can also make many forms without departing from the purpose of the present application and the scope protected by the claims, and all of them fall within the protection scope of the present application.

Claims

1. A receiving circuit, characterized in that: include: An analog circuit (100) and a digital circuit (200), wherein the analog circuit (100) comprises a digitally controlled delay module (110); the digital circuit (200) comprises a frequency detection module (210), a parameter management module (220) and a data receiving module (230) connected in sequence; the parameter management module (220) is connected to the digitally controlled delay module (110), and the digitally controlled delay module (110) is coupled to the data receiving module (230); The frequency detection module (210) is used to detect the frequency of the target clock signal and obtain a frequency detection result; and transmit the frequency detection result to the parameter management module (220); wherein the target clock signal is obtained based on a differential clock signal from a transmitting end; The parameter management module (220) is used to obtain an optimal value of a target reception parameter based on the frequency detection result; and transmit the optimal value of the target reception parameter to the numerical control delay module (110) and the data receiving module (230); The digital control delay module (110) is used to calibrate the digital clock signal according to the optimal value of the target receiving parameter to obtain a calibrated digital clock signal; wherein the digital clock signal is obtained based on a differential clock signal from a transmitting end; The data receiving module (230) is used to receive target data according to the optimal value of the target receiving parameter; wherein the target data is obtained by the analog circuit (100) sampling data from the transmitting end according to the calibrated digital clock signal.

2. The receiving circuit according to claim 1, characterized in that: The frequency detection module (210) is used to determine a sampling window using an internal clock signal, determine the number of cycles of the target clock signal within the sampling window, and calculate the frequency detection result based on the sampling window and the number of cycles.

3. The receiving circuit according to claim 1, characterized in that: The parameter management module (220) is used to determine a target unit interval based on the frequency detection result; and configure a target reception parameter based on the target unit interval to obtain an optimal value of the target reception parameter.

4. The receiving circuit according to claim 3, characterized in that: The target receiving parameter includes a first timing parameter T HS-SETTLE and the second timing parameter T HS-SKIP ; Wherein, the first timing parameter T HS-SETTLE is the time interval required to discard unstable data when starting to transmit HS data. The second timing parameter T HS-SKIP It is a time interval required to discard unstable data at the end of the HS data transmission, wherein the HS data is data transmitted in a communication mode in which the communication rate is within a specified range.

5. The receiving circuit according to any one of claims 1 to 4, characterized in that: The analog circuit (100) comprises a first analog-to-digital converter (120) and a frequency divider (130), wherein the first analog-to-digital converter (120) is connected to the frequency divider (130), and the frequency divider (130) is connected to the frequency detection module (110).

6. The receiving circuit according to claim 5, characterized in that: The first analog-to-digital converter (120) is used to receive a differential clock signal from a transmitting end through a first analog front end, and convert the differential clock signal into a digital clock signal; The frequency divider (130) is used to perform frequency division processing on the digital clock signal to obtain a target clock signal, and transmit the target clock signal to the frequency detection module (210).

7. The receiving circuit according to claim 5, characterized in that: The first analog-to-digital converter (120) is further used to transmit the digital clock signal to the digitally controlled delay module (110).

8. The receiving circuit according to claim 5, characterized in that: The analog circuit (100) further comprises a second analog-to-digital converter (140) and a data sampling module (150); wherein the second analog-to-digital converter (140) is connected to the data sampling module (150), the digital control delay module (110) is connected to the data sampling module (150), and the data sampling module (150) is coupled to the data receiving module (230).

9. The receiving circuit according to claim 8, characterized in that: The analog circuit (100) further comprises a serial-to-parallel conversion module (160), the data sampling module (150) is connected to the data receiving module (230) via the serial-to-parallel conversion module (160); and the digital control delay module (110) is connected to the serial-to-parallel conversion module (160).

10. A communication device, characterized in that: include: A receiving circuit as claimed in any one of claims 1 to 9.

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