Memory manufacturing method, memory, and electronic device

Abstract

The application relates to a memory manufacturing method, a memory and an electronic device. The memory manufacturing method comprises the following steps: providing a substrate, forming a stack structure on the substrate, the stack structure comprising first sub-layers and second sub-layers which are alternately stacked; forming an isolation groove, the isolation groove dividing the stack structure of a memory cell region into strip-shaped structures extending along a first direction; forming a first groove between adjacent first sub-layers along a direction perpendicular to the substrate; forming a first semiconductor channel and a first gate dielectric layer in the first groove, the first semiconductor channel covering a groove wall of the first groove, and the first gate dielectric layer covering the first semiconductor channel; and forming a first word line, the first word line comprising a first horizontal part and a first vertical part, the first horizontal part covering the first gate dielectric layer, the first vertical part being vertically arranged on the substrate, and the first horizontal part and the first vertical part being connected, so that a parasitic device is avoided from being formed by a conductive film layer remaining outside the first groove.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, and in particular to a memory manufacturing method, a memory and an electronic device. BACKGROUND

[0002] With the development of integrated circuit technology, the critical dimension of devices is increasingly reduced, and the types and quantities of devices contained in a single chip are also increased, so that any slight difference in process production can affect the performance of the devices.

[0003] In order to reduce the cost of products as much as possible, people want to make as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet people's current product needs. SUMMARY

[0004] The present application provides a memory manufacturing method, a memory and an electronic device.

[0005] In a first aspect, the present application provides a memory manufacturing method, comprising the following steps:

[0006] A substrate is provided, and a stack structure is formed on the substrate, the stack structure comprising first sub-layers and second sub-layers stacked alternately, and a memory cell region and a bit line region are defined in the stack structure;

[0007] An isolation trench is formed, the isolation trench penetrating through the stack structure in a direction perpendicular to the substrate, the isolation trench extending in a first direction and dividing the stack structure of the memory cell region into at least one strip structure extending in the first direction, the first direction being parallel to the substrate;

[0008] An intermediate region of the strip structure is etched to remove part of the strip structure, and a first trench is formed between adjacent first sub-layers in a direction perpendicular to the substrate;

[0009] A first semiconductor channel and a first gate dielectric layer are formed in the first trench, the first semiconductor channel covering a trench wall of the first trench, and the first gate dielectric layer covering the first semiconductor channel;

[0010] A first word line is formed, the first word line comprising a first horizontal part formed in the first trench and a first vertical part formed in the isolation trench, the first horizontal part covering the first gate dielectric layer, the first vertical part being arranged vertically on the substrate, and the first horizontal part and the first vertical part being connected.

[0011] In one embodiment, forming a first trench between adjacent first sub-layers comprises:

[0012] forming an isolation layer in the isolation groove;

[0013] forming a second groove in the isolation layer, a sidewall of the second groove exposing a part of a surface of the middle region of the strip-shaped structure;

[0014] etching to remove the strip-shaped structure exposed by the second groove, forming the first groove, the first groove and the first sub-layer of the middle region being arranged alternately along a direction perpendicular to the substrate.

[0015] In one embodiment, forming a first semiconductor channel and a first gate dielectric layer in the first groove comprises:

[0016] forming a semiconductor material layer, the semiconductor material layer covering sidewalls of the first groove and sidewalls of the second groove;

[0017] forming a gate dielectric material layer, the gate dielectric material layer covering the semiconductor material layer;

[0018] removing the semiconductor material layer and the gate dielectric material layer in the second groove, the semiconductor material layer in the first groove forming the first semiconductor channel, the gate dielectric material layer in the first groove forming the first gate dielectric layer.

[0019] In one embodiment, forming a first word line comprises:

[0020] forming the first horizontal part in the first groove, the first horizontal part covering the first gate dielectric layer and filling the first groove, a sidewall of the second groove exposing a part of a surface of the first horizontal part;

[0021] forming the first vertical part, the first vertical part contacting the exposed surface of the first horizontal part and filling the second groove.

[0022] In one embodiment, forming the first horizontal part in the first groove comprises:

[0023] after forming the gate dielectric material layer, forming a first gate conductive layer, the first gate conductive layer covering the gate dielectric material layer and filling the first groove and the second groove;

[0024] etching to remove the first gate conductive layer in the second groove, retaining the first gate conductive layer in the first groove, forming the first horizontal part.

[0025] In one embodiment, the manufacturing method comprises:

[0026] The first gate conductive layer, the gate dielectric material layer and the semiconductor material layer in the second trench are etched in sequence to expose the second trench.

[0027] In one of the embodiments, the manufacturing method comprises:

[0028] The isolation layer around the second trench is etched to form a third trench, and the third trench exposes the semiconductor material layer in the second trench.

[0029] The semiconductor material layer, the gate dielectric material layer and the first gate conductive layer in the second trench are etched based on the third trench.

[0030] In one of the embodiments, the first vertical part is formed by:

[0031] A second gate conductive layer is formed, and the second gate conductive layer at least fills the second trench to form the first vertical part.

[0032] In one of the embodiments, the first trench and the bit line region are separated by a preset distance along the first direction.

[0033] In one of the embodiments, the memory cell region and the bit line region are arranged along the first direction in the stack structure defining a selection region, the selection region is arranged at one end of the bit line region along a second direction, and the second direction is parallel to the substrate and intersects the first direction. The manufacturing method further comprises:

[0034] The bit line region is etched to remove part of the stack structure in the bit line region, and a fourth trench is formed between the adjacent first sub-layers in the bit line region along a direction perpendicular to the substrate, and the fourth trench is arranged close to the selection region.

[0035] In one of the embodiments, the manufacturing method further comprises:

[0036] The first semiconductor channel and the first gate dielectric layer are formed in the first trench, and a second semiconductor channel and a second gate dielectric layer are formed in the fourth trench at the same time, the second semiconductor channel covers the slot wall of the fourth trench, and the second gate dielectric layer covers the second semiconductor channel.

[0037] The first word line is formed, and a second word line is formed at the same time, the second word line comprises a second horizontal part formed in the fourth trench and a second vertical part formed in the isolation trench, the second horizontal part covers the second gate dielectric layer and fills the fourth trench, the second vertical part is arranged vertically on the substrate, and the second horizontal part and the second vertical part are connected.

[0038] In one embodiment, the first sub-layer is a silicon oxide layer, and the second sub-layer is a semiconductor doped layer. After forming the isolation trench, the semiconductor doped layer in the bit line region forms a bit line extending in a second direction, which is parallel to the substrate and intersects the first direction.

[0039] In one embodiment, the manufacturing method further comprises:

[0040] etching to remove part of the first sub-layer away from one end of the bit line region, exposing part of the surface of the semiconductor doped layer away from one end of the bit line region;

[0041] forming a dielectric layer covering the exposed surface of the semiconductor doped layer;

[0042] forming an upper electrode covering the dielectric layer.

[0043] In one embodiment, the first sub-layer is a silicon oxide layer, and the second sub-layer is a silicon nitride layer. After forming the isolation trench in the memory cell region, the manufacturing method comprises:

[0044] etching to remove all of the second sub-layer, forming an air layer in the region where the second sub-layer is removed;

[0045] forming a bit line in the air layer in the bit line region, the bit line extending in a second direction, which is parallel to the substrate and intersects the first direction;

[0046] forming a conductor layer filling the region in the air layer that is not filled.

[0047] In one embodiment, the manufacturing method further comprises:

[0048] etching to remove part of the first sub-layer away from one end of the bit line region, exposing part of the surface of the conductor layer away from one end of the bit line region;

[0049] forming a dielectric layer covering the exposed surface of the conductor layer;

[0050] forming an upper electrode covering the dielectric layer.

[0051] In a second aspect, the present application provides a memory, comprising:

[0052] a substrate;

[0053] at least one first word line, the first word line comprising a first vertical portion disposed vertically on the substrate and at least one first horizontal portion arranged in a direction perpendicular to the substrate and connected to the first vertical portion;

[0054] at least one column of memory cells, the column of memory cells comprising at least one memory cell arranged in a direction perpendicular to the substrate;

[0055] the memory cell comprises a cell transistor, the first horizontal portion serving as a gate of the cell transistor, the cell transistor comprising a first gate dielectric layer and a first semiconductor channel disposed in a direction away from the first horizontal portion in sequence, the cell transistor further comprising a first source / drain and a second source / drain disposed on two sides of the first semiconductor channel in a first direction, the first direction being parallel to the substrate.

[0056] In one embodiment, in a plane parallel to the first direction and perpendicular to the substrate, the first semiconductor channel surrounds the first horizontal portion.

[0057] In one embodiment, the first semiconductor channel comprises a connection channel located on one side of the first horizontal portion in a second direction, the second direction being parallel to the substrate and intersecting the first direction.

[0058] In one embodiment, the first semiconductor channel is cup-shaped, and the first semiconductor channel is sleeved on the first horizontal portion.

[0059] In one embodiment, the memory cell further comprises a capacitor, the capacitor being disposed on one side of the cell transistor in the first direction, and the capacitor being connected to the first source / drain of the cell transistor.

[0060] In one embodiment, the capacitor comprises a lower electrode connected to the first source / drain, a dielectric layer disposed between the upper electrode and the lower electrode, and an upper electrode.

[0061] In one embodiment, in a plane parallel to the substrate, the upper electrodes of a plurality of the capacitors are connected to each other to form a closed pattern.

[0062] In one embodiment, the closed pattern has a common upper plate connected to the upper electrodes.

[0063] In one embodiment, the memory further comprises:

[0064] At least one bit line, at least one of the bit lines is arranged in a direction perpendicular to the substrate, the bit line extends in a second direction, the bit line is connected with the second source / drain of the unit transistor arranged in the second direction, and the second direction is parallel to the substrate and intersects the first direction.

[0065] In one of the embodiments, the memory further comprises:

[0066] A second word line, the second word line comprises a second vertical part and at least one second horizontal part, the second vertical part is arranged vertically on the substrate, and at least one of the second horizontal parts is arranged in a direction perpendicular to the substrate and connected with the second vertical part;

[0067] At least one selection transistor, at least one of the selection transistors is arranged in a direction perpendicular to the substrate, the second horizontal part serves as a gate of the selection transistor, the selection transistor comprises a second gate dielectric layer and a second semiconductor channel arranged in a direction away from the second horizontal part in sequence, and the selection transistor further comprises a third source / drain and a fourth source / drain arranged oppositely on both sides of the second semiconductor channel in the second direction; the third source / drain of the selection transistor is connected with the bit line one by one.

[0068] In one of the embodiments, the memory further comprises:

[0069] At least one selection line, at least one of the selection lines is arranged in a direction perpendicular to the substrate, the selection line extends in the first direction, and the selection line is connected with the fourth source / drain of the selection transistor one by one.

[0070] In a third aspect, the present application provides an electronic device, such as the memory of the second aspect.

[0071] The manufacturing method of the memory of the present application, the memory and the electronic device have the following beneficial effects:

[0072] The manufacturing method of the memory of the present application forms a first groove arranged in parallel to the substrate in a strip structure, in the process of manufacturing the first semiconductor channel and the first gate dielectric layer, the film layer for forming the first semiconductor channel and the film layer for forming the first gate dielectric layer cover the exposed surface of the first groove and other structures, the strip structure shields the groove wall of the first groove, the film layer in the first groove is reserved to form the first semiconductor channel and the first gate dielectric layer, and all the film layers outside the first groove are etched and removed, which avoids the existence of residual conductive film layer outside the first groove to form a parasitic device in the memory cell, avoids the influence of the parasitic device on the performance of the memory, can further improve the number of three-dimensional stacks of the memory, and improves the integration density of the memory;

[0073] The memory of the present invention has no conductive film layer left over from the manufacturing process and no parasitic devices, which can improve the response speed of the semiconductor structure, avoid response delay, improve the yield and electrical performance of the semiconductor structure. The first word line includes a first vertical portion and a first horizontal portion. The first horizontal portion serves as the gate of the response transistor and is not limited by the length of the first vertical portion, which can increase the length of the gate of the unit transistor, thereby enhancing the gate control capability of the unit transistor. In addition, the first semiconductor channel at the location of the first horizontal portion can be protected to avoid damage to the first semiconductor channel at the location of the first horizontal portion when removing parasitic channels. Attached Figure Description

[0074] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0075] Figure 1 This is a flowchart illustrating a method for fabricating a memory as provided in some embodiments.

[0076] Figure 2 This is a flowchart illustrating a method for fabricating a memory as provided in some embodiments.

[0077] Figure 3 This is a flowchart illustrating a method for fabricating a memory as provided in some embodiments.

[0078] Figure 4 This is a schematic diagram of a stacked structure formed on a substrate in some embodiments.

[0079] Figure 5 This is a top view of the stacked structure in some embodiments.

[0080] Figure 6 This is a schematic diagram of the structure after the isolation trench is formed in some embodiments.

[0081] Figure 7 This is a top view after the isolation trench has been formed in some embodiments.

[0082] Figure 8 This is a schematic diagram of the structure after the isolation layer is formed in some embodiments.

[0083] Figure 9 This is a schematic diagram of the structure after the first sub-groove is formed in some embodiments.

[0084] Figure 10 This is a top view after the first sub-groove has been formed in some embodiments.

[0085] Figure 11 This is a top view after the first sub-layer of the second region has been removed in some embodiments.

[0086] Figure 12 This is a schematic diagram of the structure of the second region after removing the first sublayer in some embodiments.

[0087] Figure 13 This is a schematic diagram of the structure of the second region after the dielectric layer is formed in some embodiments.

[0088] Figure 14 This is a schematic diagram of the structure of the second region after the upper electrode is formed in some embodiments.

[0089] Figure 15 This is a schematic diagram of the structure of the second region after the common upper electrode is formed in some embodiments.

[0090] Figure 16 This is a schematic diagram of the structure after the second trench is formed in some embodiments.

[0091] Figure 17 In some embodiments, after the second trench is formed along Figure 16 A cross-sectional view of the substrate with the AA line in the middle parallel to it.

[0092] Figure 18 In some embodiments, after the second trench is formed along Figure 16 A cross-sectional view of the BB and CC lines perpendicular to the substrate.

[0093] Figure 19 In some embodiments, after the first trench is formed along... Figure 16 A cross-sectional view of the substrate with the AA line parallel to it.

[0094] Figure 20 In some embodiments, after the first trench is formed along... Figure 16 A cross-sectional view of the BB and CC lines perpendicular to the substrate.

[0095] Figure 21 In some embodiments, after forming the semiconductor material layer along... Figure 16 A cross-sectional view of the BB and CC lines perpendicular to the substrate.

[0096] Figure 22 In some embodiments, after the gate dielectric material layer is formed, along Figure 16 A cross-sectional view of the BB and CC lines perpendicular to the substrate.

[0097] Figure 23 In some embodiments, after the first gate conductive layer is formed along... Figure 16Cross-sectional view along line B-B and C-C of FIG. 1 1.

[0098] Figure 24 Cross-sectional view along line B-B and C-C of FIG. 1 1 after removing the first gate conductive layer in the second trench and the fifth trench for some embodiments. Figure 16 Cross-sectional view along line B-B and C-C of FIG. 1 1.

[0099] Figure 25 Cross-sectional view along line B-B and C-C of FIG. 1 1 after removing the gate dielectric layer in the second trench and the fifth trench for some embodiments. Figure 16 Cross-sectional view along line B-B and C-C of FIG. 1 1.

[0100] Figure 26 Cross-sectional view along line B-B and C-C of FIG. 1 1 after forming the first horizontal portion and the second horizontal portion for some embodiments. Figure 16 Cross-sectional view along line B-B and C-C of FIG. 1 1.

[0101] Figure 27 Cross-sectional view along line B-B and C-C of FIG. 1 1 after forming the second gate conductive layer for some embodiments. Figure 16 Cross-sectional view along line B-B and C-C of FIG. 1 1.

[0102] Figure 28 Cross-sectional view along line B-B and C-C of FIG. 1 1 after forming the first word line and the second word line for some embodiments. Figure 16 Cross-sectional view along line B-B and C-C of FIG. 1 1.

[0103] Figure 29 Cross-sectional view along line A-A of FIG. 1 1 after forming the third trench and the sixth trench for some embodiments. Figure 16 Cross-sectional view along line A-A of FIG. 1 1.

[0104] Figure 30 Cross-sectional view along line B-B and C-C of FIG. 1 1 after forming the third trench and the sixth trench for some embodiments. Figure 16 Cross-sectional view along line B-B and C-C of FIG. 1 1.

[0105] Figure 31 Cross-sectional view along line A-A of FIG. 1 1 after forming the first horizontal portion and the second horizontal portion for some embodiments. Figure 16 Cross-sectional view along line A-A of FIG. 1 1.

[0106] Figure 32 Cross-sectional view along line B-B and C-C of FIG. 1 1 after forming the first horizontal portion and the second horizontal portion for some embodiments. Figure 16 Cross-sectional view along line B-B and C-C of FIG. 1 1.

[0107] Figure 33 Cross-sectional view along line A-A of FIG. 1 1 after forming the first word line and the second word line for some embodiments. Figure 16 Cross-sectional view along line A-A of FIG. 1 1.

[0108] Figure 34 FIG. 2 is a cross-sectional view along line B-B in FIG. 1 taken perpendicular to the substrate after forming the first and second word lines in some embodiments. Figure 16 FIG. 3 is a cross-sectional view along line C-C in FIG. 1 taken perpendicular to the substrate after forming the first and second word lines in some embodiments.

[0109] Figure 35 FIG. 4 is a structural diagram of forming a stack structure on the substrate in some embodiments.

[0110] Figure 36 FIG. 5 is a structural diagram after forming the isolation trench in some embodiments.

[0111] Figure 37 FIG. 6 is a structural diagram after forming the first isolation layer in some embodiments.

[0112] Figure 38 FIG. 7 is a top view after forming the first isolation layer in some embodiments.

[0113] Figure 39 FIG. 8 is a structural diagram after forming the second sub-trench in some embodiments.

[0114] Figure 40 FIG. 9 is a top view after forming the second sub-trench in some embodiments.

[0115] Figure 41 FIG. 10 is a cross-sectional view along line D-D in FIG. 9 taken perpendicular to the substrate after forming the second sub-trench in some embodiments. Figure 40

[0116] FIG. 11 is a cross-sectional view along line D-D in FIG. 9 taken perpendicular to the substrate after forming the air layer in some embodiments. Figure 42 Figure 40 FIG. 12 is a cross-sectional view along line D-D in FIG. 9 taken perpendicular to the substrate after forming the conductor layer in some embodiments.

[0117] Figure 43 Figure 40 FIG. 13 is a cross-sectional view along line D-D in FIG. 9 taken perpendicular to the substrate after forming the second isolation layer in some embodiments.

[0118] Figure 44 FIG. 14 is a structural diagram after forming the first sub-trench in some embodiments.

[0119] Figure 45 FIG. 15 is a cross-sectional view along line E-E in FIG. 14 taken parallel to the substrate after forming the first sub-trench in some embodiments. Figure 44

[0120] FIG. 16 is a structural diagram after removing the first sub-layer of the second region in some embodiments. Figure 46

[0121] FIG. 17 is a structural diagram of a perspective view of the second region after forming the capacitor in some embodiments. Figure 47

[0122] FIG. 18 is a structural diagram of a perspective view of the second region after forming the capacitor in some embodiments.​​ Figure 48 Structure diagram of a perspective view of a second region after forming a common upper plate for some embodiments.

[0123] Figure 49 Structure diagram of a perspective view of a second region after forming a second trench and a fifth trench for some embodiments. Figure 44 Cross-sectional view along line E-E parallel to the substrate for some embodiments.

[0124] Figure 50 Structure diagram of a perspective view of a second region after forming a first trench and a fourth trench for some embodiments. Figure 44 Cross-sectional view along line E-E parallel to the substrate for some embodiments.

[0125] Figure 51 Structure diagram of a perspective view of a second region after forming a first horizontal portion and a second horizontal portion for some embodiments. Figure 44 Cross-sectional view along line E-E parallel to the substrate for some embodiments.

[0126] Figure 52 Structure diagram of a perspective view of a memory provided for some embodiments.

[0127] Figure 53 Cross-sectional view along line F-F parallel to the substrate for some embodiments. Figure 52

[0128] Cross-sectional view along line G-G, H-H perpendicular to the substrate for some embodiments. Figure 54 Figure 52 Cross-sectional view along line I-I perpendicular to the substrate for some embodiments.

[0129] Figure 55 Figure 52 Cross-sectional view along line J-J perpendicular to the substrate for some embodiments.

[0130] Figure 56 Cross-sectional view along line I-I perpendicular to the substrate for some embodiments. Figure 52

[0131] Cross-sectional view along line J-J perpendicular to the substrate for some embodiments. Figure 57 Figure 52 Cross-sectional view along line I-I perpendicular to the substrate for some embodiments.

[0132] Figure 58 Figure 52 Cross-sectional view along line J-J perpendicular to the substrate for some embodiments.

[0133] BRIEF DESCRIPTION OF DRAWINGS

[0134] ​​​​100, substrate; 130, isolation trench; 131, first sub-trench; 132, second sub-trench; 200, stack structure; 210, first sub-layer; 220, second sub-layer; 220a, semiconductor doped layer; 230, isolation layer; 231, first isolation layer; 232, second isolation layer; 240, air layer; 250, conductor layer; 300, bar structure; 410, semiconductor material layer; 420, gate dielectric material layer; 430, first gate conductive layer; 440, second gate conductive layer; 121, first trench; 221, second trench; 321, third trench; 421, fourth trench; 521, fifth trench; 621, sixth trench; 161, first semiconductor channel; 1611, connecting channel; 171, first gate dielectric layer; 261, second semiconductor channel; 271, second gate dielectric layer; 181, first source / drain; 182, second source / drain; 281, third source / drain; 282, fourth source / drain; 600, capacitor; 610, dielectric layer; 620, upper electrode; 630, lower electrode; 640, common upper plate;

[0135] BL, bit line; WL1, first word line; WL2, second word line; HS1, first horizontal section; VP1, first vertical section; HS2, second horizontal section; VP2, second vertical section; SUC, storage unit column; SU, storage unit; MCT, cell transistor; G1, gate of cell transistor; ST, select transistor; G2, gate of select transistor; SL, select line;

[0136] Z1, storage unit area; Z2, bit line area; Z3, select area; A1, first area; A2, second area; A11, intermediate area;

[0137] D1, first direction; D2, second direction; D3, third direction. DETAILED DESCRIPTION

[0138] For the purposes of this application, the application will now be described in more detail with reference to the enclosed drawings. In the drawings, preferred embodiments of the application are shown. The application may, however, be carried out in many different ways, and the application should not be construed to be limited to the embodiments described herein below. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the application to those skilled in the art.

[0139] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description herein is for describing particular embodiments only and is not intended to be limiting of the application.

[0140] It will be understood that when an element or layer is referred to as being "on" or "connected to" another element or layer, it can be directly on or connected to the other element or layer or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element or layer, there are no intervening elements or layers present. It will also be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section; for example, a first doped type could be termed a second doped type; and similarly, a second doped type could be termed a first doped type; a first doped type and a second doped type being different doped types, e.g., a first doped type can be P-type and a second doped type can be N-type, or a first doped type can be N-type and a second doped type can be P-type.

[0141] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and / or operation in addition to the orientations depicted in the figures. For example, if a device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can also be oriented in the other direction (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0142] The singular forms "a", "an", and "the" include plural referents unless the context clearly dictates otherwise. It will be further understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. Also, as used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0143] Embodiments of the application are described herein with reference to the drawings, which show exemplary embodiments of the application (and intermediate structures) in cross-sectional view as idealized representations. Variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments of the application should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and / or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Similarly, a buried region formed by implantation can result in some implantation in a region between the buried region and the surface through which the implant was performed. Thus, the regions illustrated in the figures are schematic only and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the application.

[0144] A method for fabricating a memory is provided in an exemplary embodiment of the present disclosure, as shown in Figure 1 Figure 1 A flow chart of a method for fabricating a memory is shown, according to an exemplary embodiment of the present disclosure. The embodiment is not limited to a semiconductor structure, and will be described below with a memory as a Dynamic Random Access Memory (DRAM) as an example, but the embodiment is not limited thereto. The memory in the embodiment can also be other types of memories, such as a Static Random-Access Memory (SRAM), a flash EPROM, a Ferroelectric Random Access Memory (FRAM), a Magnetic Random-Access Memory (MRAM).

[0145] As shown in Figure 1 A method for fabricating a memory is provided in some embodiments of the present disclosure, including the following steps:

[0146] Step S110: providing a substrate, forming a stack structure on the substrate, the stack structure including first sub-layers and second sub-layers alternately spaced, defining a memory cell region and a bit line region in the stack structure.

[0147] Step S120: forming an isolation trench, the isolation trench penetrating the stack structure in a direction perpendicular to the substrate, the isolation trench extending in a first direction, dividing the stack structure of the memory cell region into at least one strip structure extending in the first direction, the first direction being parallel to the substrate.

[0148] Step S130: etching a middle region of the strip structure, removing part of the strip structure, forming a first trench between adjacent first sub-layers in a direction perpendicular to the substrate.​

[0149] Step S140: forming a first semiconductor channel and a first gate dielectric layer in the first trench, the first semiconductor channel covering the sidewall of the first trench, and the first gate dielectric layer covering the first semiconductor channel.

[0150] Step S150: forming a first word line, the first word line including a first horizontal part formed in the first trench and a first vertical part formed in the isolation trench, the first horizontal part covering the first gate dielectric layer, and the first vertical part being vertically arranged on the substrate, and the first horizontal part and the first vertical part being connected.

[0151] In step S110, referring to Figure 4 or referring to Figure 35 , the substrate 100 can be a semiconductor substrate, and the material of the semiconductor substrate can include silicon (Si), silicon germanium (SiGe), silicon germanium carbon (SiGeC), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), indium phosphide (InP), or other III / V semiconductor material or II / VI semiconductor material. Alternatively, for example, the semiconductor substrate can be a layered substrate including, for example, Si / SiGe, Si / SiC, silicon-on-insulator (SOI), or silicon germanium-on-insulator. The substrate 100 can be a single-layer structure or a multi-layer structure.

[0152] Referring to Figure 4 or referring to Figure 35 , the stack structure 200 includes first sub-layers 210 and second sub-layers 220 alternately stacked in a direction (third direction D3) perpendicular to the top surface of the substrate 100. In some embodiments, referring to Figure 4 , the first sub-layers 210 are silicon oxide layers, and the second sub-layers 220 are semiconductor doped layers (which can be, for example, polysilicon layers). In other embodiments, referring to Figure 35 , the first sub-layers 210 are silicon oxide layers, and the second sub-layers 220 are silicon nitride layers.

[0153] In this embodiment, the top layer and the bottom layer of the stack structure 200 are both first sub-layers 210, and the second sub-layers 220 are arranged at positions for subsequent formation of memory cells SU.

[0154] Referring to Figure 5 , based on the stack structure 200, a memory cell region Z1 and a bit line region Z2 are divided, the memory cell region Z1 is used to form memory cells SU in an array above the substrate 100, and the bit line region Z2 is used to form a bit line BL, the memory cell region Z1 and the bit line region Z2 are arranged along a first direction D1, and referring to Figure 5 , along the first direction D1, an independent memory cell region Z1 can be defined on each side of the bit line region Z2.

[0155] In step S120, referring to Figure 5 , Figure 6 , Figure 7 or referring to Figure 36 , a mask layer (not shown in the figure) is formed on the top surface of the stack structure 200, the mask layer is patterned to expose part of the top surface of the stack structure 200 in the memory cell region Z1, the stack structure 200 exposed by the patterned mask layer is etched to form isolation trenches 130, the isolation trenches 130 expose part of the top surface of the substrate 100, and the isolation trenches 130 divide the stack structure 200 in the memory cell region Z1 into a plurality of strip structures 300, the strip structures 300 extend along the first direction D1, and the plurality of strip structures 300 are arranged along the second direction D2, i.e., the strip structures 300 and the strip structures 300 are arranged alternately along the second direction D2.

[0156] In step S130, referring to Figure 17 , Figure 19 , Figure 20 or Figure 50 , the middle region A11 of the strip structure 300 can be etched based on the isolation trench 130 (refer to Figure 6 or Figure 36 ), and the first trenches 121 are formed in the middle region A11 of the strip structure 300, the first trenches 121 are arranged along the third direction D3, the first trenches 121 are parallel to the substrate 100, and the strip structure 300 around the first trenches 121 shields the first trenches 121. After the first trenches 121 are formed, the middle region A11 of the strip structure 300, the first sub-layer 210 (refer to Figure 20 ) and the first trenches 121 are arranged alternately along the third direction D3.

[0157] In some embodiments, along the first direction D1, the first trenches 121 and the bit line region Z2 are spaced apart by a predetermined distance, so as to avoid the distance between the subsequently formed first word line and the bit line region Z2 being too close, which affects the electrical isolation effect between devices in the memory.

[0158] In step S140, referring to Figures 20-26 , or referring to Figures 29-32 , or referring to Figure 51 , the first semiconductor channel 161 and the first gate dielectric layer 171 are formed in the first trenches 121 (refer to Figure 19 or Figure 50 ), and a suitable deposition process can be used to sequentially deposit a semiconductor material layer 410 and a gate dielectric material layer 420, the semiconductor material layer 410 and the gate dielectric material layer 420 are laminated to cover the slot wall of the first trench 121 and the exposed surface of the stack structure 200 of the strip structure 300, the isolation trench 130 and the bit line region Z2.

[0159] Then, the semiconductor material layer 410 and the gate dielectric material layer 420 are etched using an etching process, and the strip structure 300 is aligned with the first trench 121 (see reference). Figure 19 or Figure 50 The trench walls form a shield, and the semiconductor material layer 410 and the gate dielectric material layer 420 in the first trench 121 are etched and retained, forming a first semiconductor channel 161 and a first gate dielectric layer 171 in the first trench 121. The semiconductor material layer 410 and the gate dielectric material layer 420 covering the trench walls of the first trench 121 and the exposed surfaces of the strip structure 300, the isolation trench 130 and the stacked structure 200 of the bit line region Z2 are all etched and removed, thereby ensuring that there are no residual semiconductor material layers 410 and gate dielectric material layers 420 in the areas outside the first trench 121.

[0160] In step S150, refer to Figure 27 , Figure 28 , Figure 33 , Figure 34 , Figure 52 , Figure 53 The first horizontal portion HS1 and the first vertical portion VP1 of the first word line WL1 can be formed in different processes. For example, the first horizontal portion HS1 can be formed in the same process step as the first semiconductor channel 161 and the first gate dielectric layer 171, and then the first vertical portion VP1 is formed in the isolation trench 130; or, in some embodiments, the first horizontal portion HS1 and the first vertical portion VP1 of the first word line WL1 can be formed in the same process step.

[0161] The disclosed memory fabrication method involves forming a first trench parallel to the substrate in a strip structure. During the fabrication of the first semiconductor channel and the first gate dielectric layer, the film layer forming the first semiconductor channel and the film layer forming the first gate dielectric layer cover the exposed surfaces of the first trench and other structures. The strip structure is used to shield the trench walls of the first trench, retaining the film layer in the first trench to form the first semiconductor channel and the first gate dielectric layer. All film layers outside the first trench are etched away to prevent residual conductive film layers outside the first trench from forming parasitic devices in the memory cells. This avoids parasitic devices affecting the performance of the memory and can further increase the number of layers in the three-dimensional stacking of the memory, thereby improving the integration density of the memory.

[0162] In some embodiments: step S130 forms a first trench between adjacent first sublayers, including the following steps:

[0163] Step S131: Form an isolation layer in the isolation trench.

[0164] Step S132: A second trench is formed in the isolation layer, and one sidewall of the second trench exposes part of the surface of the middle region of the strip structure.

[0165] Step S133: etching to remove the strip structure exposed by the second trench, forming the first trench, the first trench and the first sub-layer in the middle region being arranged alternately along the direction perpendicular to the substrate.

[0166] In step S131, referring to Figure 9 Any suitable deposition process can be used to form the isolation layer 230, which fills the isolation trench 130, and the material of the isolation layer 230 can include at least one of silicon oxide, silicon nitride, or silicon oxynitride. It can be understood that the isolation layer 230 can be formed by one-time deposition or by multiple-time deposition.

[0167] In step S132, referring to Figure 17 or referring to Figure 49 The portion of the isolation layer 230 close to the strip structure 300 is etched to form the second trench 221, which exposes part of the surface of the middle region A11 of the strip structure 300.

[0168] In step S133, referring to Figure 19 or referring to Figure 50 The strip structure 300 is etched based on the second trench 221 to remove part of the structure in the middle region A11, and the first trench 121 is formed in the middle region A11 along the third direction D3, and the first trench 121 and the first sub-layer 210 are arranged alternately along the third direction D3. In some embodiments, a wet etching process can be used to form the first trench 121, and an etching liquid is injected into the second trench 221 to remove part of the structure in the middle region A11 by etching, wherein the etching liquid can etch and remove the second sub-layer 220 or other film layers formed at the original position of the second sub-layer 220.

[0169] The manufacturing method of the memory of the present disclosure forms a second trench close to the strip structure in the isolation layer, and then forms a first trench by etching the strip structure based on the sidewall of the second trench, which reduces the process of etching the stack structure to form a hole or trench that penetrates through the stack structure, reduces the process difficulty, not only improves the process efficiency and reduces the process cost, but also improves the yield of the product.

[0170] In some embodiments, step S140: forming a first semiconductor channel and a first gate dielectric layer in the first trench, includes the following steps:

[0171] Step S141: forming a semiconductor material layer, which covers the sidewall of the first trench and the sidewall of the second trench.

[0172] Step S142: forming a gate dielectric material layer, which covers the semiconductor material layer.

[0173] Step S143: removing the semiconductor material layer and the gate dielectric material layer in the second trench, the semiconductor material layer in the first trench forms a first semiconductor channel, and the gate dielectric material layer in the first trench forms a first gate dielectric layer.

[0174] In step S141, referring to Figure 20 、 Figure 21 , an atomic layer deposition (ALD) process can be used to deposit the semiconductor material layer 410, which covers the sidewalls of the first trench 121 and the second trench 221 and the top surface of the stack structure 200.

[0175] The semiconductor material layer 410 can be monocrystalline silicon or polycrystalline silicon, or an oxide semiconductor layer, and the material of the oxide semiconductor layer 410 can include indium gallium zinc oxide. For example, the material of the oxide semiconductor layer 410 can include at least one of the following materials: zinc tin oxide (ZTO), indium zinc oxide (IZO), indium tin oxide (ITO), tungsten-doped indium oxide (IWO), zinc oxide (ZnOx), indium oxide (InOx, In2O3), tin oxide (SnO2), titanium oxide (TiOx), indium zinc tin oxide (InSnOx), zinc oxynitride (ZnxOyNz), magnesium zinc oxide (MgxZnyOz), indium zinc oxide (InxZnyOz), indium gallium zinc oxide (InxGayZnzOa), zirconium indium zinc oxide (ZrxInyZnzOa), hafnium indium zinc oxide (HfxInyZnzOa), tin indium zinc oxide (SnxInyZnzOa), aluminum tin indium zinc oxide (AlxSnyInzZnaOd), silicon indium zinc oxide (SixInyZnzOa), zinc tin oxide (ZnxSnyOz), aluminum zinc tin oxide (AlxZnySnzOa), gallium zinc tin oxide (GaxZnySnzOa), zirconium zinc tin oxide (ZrxZnySnzOa), indium gallium silicon oxide (InGaSiO).

[0176] In step S142, referring to Figure 22As shown, the gate dielectric material layer 420 can be deposited by an atomic layer deposition process, and the gate dielectric material layer 420 covers the semiconductor material layer 410. The material of the gate dielectric material layer can include at least one of aluminum oxide (Al2O3), hafnium oxide (HfO2), hafnium oxynitride (HfON), zirconium oxide (ZrO2), tantalum oxide (Ta2O5), titanium oxide (TiO2), strontium titanium oxide (SrTiO3), hafnium silicate (HfSiO), zirconium silicate (ZrSiO), strontium silicate (SrSiO); or alternatively, the material of the gate dielectric material layer can include at least one of hafnium silicate oxynitride (HfSiON), zirconium silicate oxynitride (ZrSiON), strontium silicate oxynitride (SrSiON).

[0177] In step S143, referring to Figure 24 、 Figure 25 、 Figure 26 , the gate dielectric material layer 420 and the semiconductor material layer 410 in the second trench 221 can be removed in sequence from the center of the second trench 221 to the direction of the trench wall; referring to Figure 29 , as shown, a third trench 321 can be formed at the outer periphery of the second trench 221 to expose the semiconductor material layer 410 in the second trench 221, and the semiconductor material layer 410 and the gate dielectric material layer 420 in the second trench 221 can be removed in sequence from the trench wall to the center of the second trench 221.

[0178] In some embodiments, step S150 of forming the first word line includes the following steps:

[0179] Step S151: forming a first horizontal part in the first trench, the first horizontal part covering the first gate dielectric layer and filling the first trench, and a side wall of the second trench exposing part of the surface of the first horizontal part.

[0180] Step S152: forming a first vertical part, the first vertical part contacting the exposed surface of the first horizontal part and filling the second trench.

[0181] In step S151 of forming the first horizontal part in the first trench, the following steps are included:

[0182] Step S1511: forming a first gate conductive layer, the first gate conductive layer covering the gate dielectric material layer and filling the first trench and the second trench.

[0183] This step is performed after step S142 of forming the gate dielectric material layer 420. Referring to Figure 23As shown, the first gate conductive layer 430 can be deposited by any one of a chemical vapor deposition (CVD) process, an atomic layer deposition process, or a sputtering process, and fills the second trench 221 and the region of the first trench 121 that is not filled.

[0184] Step S1512: etching to remove the first gate conductive layer in the second trench, and retaining the first gate conductive layer in the first trench, to form a first horizontal portion.

[0185] This step can be performed before step S143, or after step S143.

[0186] In some examples, referring to Figures 24-26 As shown, the first gate conductive layer 430, the gate dielectric material layer 420, and the semiconductor material layer 410 in the second trench 221 can be sequentially etched to expose the second trench 221.

[0187] In some examples, referring to Figure 29 As shown, a portion of the isolation layer 230 around the second trench 221 is etched to form a third trench 321, and the third trench 321 exposes the semiconductor material layer 410 in the second trench 221; then, the semiconductor material layer 410, the gate dielectric material layer 420, and the first gate conductive layer 430 in the second trench 221 are etched based on the third trench 321.

[0188] In step S152, a first vertical portion VP1 is formed, including forming a second gate conductive layer 440, and the second gate conductive layer 440 at least fills the second trench 221, to form the first vertical portion VP1.

[0189] In some examples, referring to Figure 23 , Figure 27 As shown, the material of the first gate conductive layer 430 and the material of the second gate conductive layer 440 can be selected from at least one of titanium or a titanium compound, tantalum or a tantalum compound, tungsten or a tungsten compound, copper or a copper compound, and the material of the first gate conductive layer 430 and the material of the second gate conductive layer 440 can be the same or different.

[0190] In some embodiments, referring to Figure 4 As shown, in step S120, a selection region Z3 is defined in the stack structure 200 while the memory cell region Z1 and the bit line region Z2 are defined, the memory cell region Z1 and the bit line region Z2 are arranged along a first direction D1, and the selection region Z3 is at one end of the bit line region Z2 along a second direction D2, and the second direction D2 is parallel to the substrate 100 and intersects the first direction D1.

[0191] The manufacturing method of the memory of some embodiments further includes the following steps:

[0192] As shown in Figure 18 , Figure 50 , Figure 4 , the bit line region Z2 is etched to remove part of the stack structure 200 of the bit line region Z2 to form a fourth trench 421 between the adjacent first sub-layers 210 in the bit line region Z2 in a direction perpendicular to the substrate 100, and the fourth trench 421 is arranged close to the selection region Z3. The above step can be performed simultaneously with step S130. First, the part of the isolation layer 230 close to the selection region Z3 is etched to form a fifth trench 521, and the fifth trench 521 exposes part of the stack structure 200 of the bit line region Z2. Based on the fifth trench 521, the stack structure 200 of the bit line region Z2 is etched to form the fourth trench 421 in the bit line region Z2.

[0193] As shown in Figure 31 , Figure 51 , the first semiconductor channel 161 and the first gate dielectric layer 171 are formed in the first trench 121 at the same time, and the second semiconductor channel 261 and the second gate dielectric layer 271 are formed in the fourth trench 421, the second semiconductor channel 261 covers the trench wall of the fourth trench 421, and the second gate dielectric layer 271 covers the second semiconductor channel 261.

[0194] As shown in Figure 33 , Figure 52 , Figure 53 , the second word line WL2 is formed at the same time as the first word line WL1, the second word line WL2 includes a second horizontal part HS2 formed in the fourth trench 421 and a second vertical part VP2 formed in the isolation trench 130, the second horizontal part HS2 covers the second gate dielectric layer 271 and fills the fourth trench 421, the second vertical part VP2 is arranged vertically on the substrate 100, and the second horizontal part HS2 and the second vertical part VP2 are connected.

[0195] Some embodiments of the present disclosure provide a manufacturing method of a memory, as shown in Figure 2 , Figure 2 , Figures 4-34 is a flow chart of a manufacturing method of a memory according to some embodiments of the present disclosure, Figures 4-34 , Figures 52-56 The manufacturing method of the memory will be introduced below in combination with Figure 2 As shown in

[0196] Step S210: providing a substrate, forming a stack structure on the substrate, the stack structure comprising first sub-layers and second sub-layers alternately stacked, defining a memory cell region, a bit line region and a select region in the stack structure, the memory cell region and the bit line region arranged along a first direction, the select region arranged along a second direction at one end of the bit line region.

[0197] Referring to Figure 4 The substrate 100 in the present embodiment is the same as the substrate 100 in step S110, and will not be described again here.

[0198] Referring to Figure 4 , Figure 5 As shown in FIG. 2, the stack structure 200 comprises first sub-layers 210 and second sub-layers 220 alternately stacked along a third direction D3, the first sub-layers 210 are silicon oxide layers, and the second sub-layers 220 are semiconductor doped layers, the semiconductor doped layers are conductive doped polysilicon layers, and the semiconductor doped layers can have a P-type conductive type or an N-type conductive type. The top layer and the bottom layer of the stack structure 200 are both the first sub-layers 210.

[0199] The stack structure 200 can be formed on the substrate 100 by using the following embodiments:

[0200] Referring to Figure 4 , Figure 5 As shown in FIG. 2, the stack structure 200 can be formed by alternately depositing the silicon oxide layers and the semiconductor doped layers by using any one of a chemical vapor deposition process, an atomic layer deposition process or a sputtering deposition process, and repeating the cycle for several times. The silicon oxide layers and the semiconductor doped layers of the stack structure 200 can be alternately stacked for 2-1024 layers or more. For example, the silicon oxide layers and the semiconductor doped layers can be alternately stacked for 48 layers, 64 layers, 128 layers, 256 layers or 512 layers, etc.

[0201] Referring to Figure 5 , the stack structure 200 is laid out according to the structure of the memory to be formed, and the memory cell region Z1, the bit line region Z2 and the select region Z3 are defined in the stack structure 200. In some embodiments, one memory cell region Z1 is defined on each side of the bit line region Z2 along the first direction D1, and the select region Z3 is defined at one end of the bit line region Z2 along the second direction D2. The first direction D1 is parallel to the substrate 100, and the second direction D2 is parallel to the substrate 100 and intersects the first direction D1.

[0202] Step S220: forming an isolation trench, the isolation trench penetrating the stack structure in a direction perpendicular to the substrate, the isolation trench extending along the first direction and dividing the stack structure of the memory cell region into at least one strip structure extending along the first direction, the semiconductor doped layer of the bit line region forming a bit line extending along the second direction, and the semiconductor doped layer of the select region forming a select line extending along the first direction.

[0203] As Figure 6 73 Figure 7 74 Figure 4 75 Figure 5 76A first mask layer (not shown in the figure) is formed on the top surface of the stack structure 200, the first mask layer exposes part of the top surface of the stack structure 200 in the memory cell region Z1 and part of the top surface of the stack structure 200 in the selection region Z3, and the stack structure 200 exposed by the mask layer is etched to form an isolation trench 130, the isolation trench 130 divides the stack structure 200 in the memory cell region Z1 into strip structures 300 extending along the first direction D1 and arranged along the second direction D2, at the same time, the second sub-layer 220 (hereinafter referred to as the semiconductor doped layer) reserved in the bit line region Z2 is directly formed into a bit line BL (see Figure 33 77) extending along the second direction D2 and arranged along the third direction D3, the semiconductor doped layer reserved is directly formed into a selection line SL (see Figure 33 78) extending along the first direction D1 and arranged along the third direction D3, and the selection line SL in the selection region Z3 and the strip structure 300 in the memory cell region Z1 are arranged along the second direction D2. 79

[0204] 80Step S230: forming an isolation layer in the isolation trench. 81

[0205] 82As shown in Figure 8 83, referring to Figure 6 84, Figure 7 85, any one of the chemical vapor deposition process or the atomic layer deposition process can be selected to deposit the isolation layer 230, and the isolation layer 230 fills the isolation trench 130. The material of the isolation layer 230 can include at least one of silicon oxide, silicon nitride or silicon oxynitride. 86

[0206] 87Step S240: forming a capacitor at one end of the memory cell region away from the bit line region. 88

[0207] 89Forming a capacitor at one end of the memory cell region away from the bit line region includes the following steps: 90

[0208] 91Step S241: etching to remove part of the first sub-layer at one end away from the bit line region, exposing part of the surface of the semiconductor doped layer at one end away from the bit line region. 92

[0209] 93Etching to remove part of the first sub-layer 210 at one end away from the bit line region Z2 can adopt the following steps: 94

[0210] 95Along the first direction D1, the strip structure 300 in the memory cell region Z1 defines a first region A1 and a second region A2 arranged in sequence away from the bit line region Z2 (see Figure 11 96), the first region A1 is close to the bit line region Z2, and the second region A2 is away from the bit line region Z2. 97

[0211] 98As​​​ Figure 9 , Figure 10 As shown, a second mask layer (not shown) is formed on the top surface of the structure. The second mask layer exposes the top surface of the isolation layer 230 connected to the second region A2. Based on the second mask layer, the isolation layer 230 is etched to remove the isolation layer 230 connected to the second region A2, exposing a portion of the isolation trench 130 away from the bit line region Z2. The isolation trench 130 exposed in this step is defined as the first sub-trench 131. The first sub-trench 131 exposes the surface of the strip structure 300 of the second region A2.

[0212] Then, refer to Figure 11 , Figure 12 As shown, based on the first sub-trench 131, the strip structure 300 is etched to remove the first sub-layer 210 (hereinafter collectively referred to as the silicon oxide layer) of the second region A2, exposing the surface of the semiconductor doped layer of the second region A2. Exemplarily, a dry process or a wet process can be used to etch and remove the silicon oxide layer of the second region A2.

[0213] Step S242: Form a dielectric layer that covers the exposed surface of the semiconductor doped layer.

[0214] like Figure 13 As shown, refer to Figure 12 A dielectric layer 610 is deposited using an atomic layer deposition process, and the dielectric layer 610 uniformly covers the exposed surface of the semiconductor doped layer in the second region A2. The material of the dielectric layer 610 may include at least one of strontium titanate (SrTiO3), aluminum oxide (Al2O3), zirconium oxide (ZrO), or hafnium oxide (HfO2).

[0215] Step S243: Form the upper electrode, which is covered by a dielectric layer.

[0216] like Figure 14 As shown, refer to Figure 13 The upper electrode 620 can be deposited using an atomic layer deposition process. The upper electrode 620 covers the surface of the dielectric layer 610. The material of the upper electrode 620 may include at least one of high melting point metals, such as cobalt (Co), titanium (Ti), nickel (Ni), tungsten (W), and / or molybdenum (Mo); or the material of the upper electrode 620 may also include metal nitrides, such as titanium nitride, titanium silicon nitride, titanium aluminum nitride, tantalum nitride, tantalum silicon nitride, tantalum aluminum nitride, and / or tungsten nitride.

[0217] The semiconductor doped layer covered by dielectric layer 610 (i.e., the semiconductor doped layer of the second region A2), dielectric layer 610 and upper electrode 620 form a capacitor 600 at one end of memory cell region Z1 away from bit line region Z2 (i.e., the second region A2), and the semiconductor doped layer covered by dielectric layer 610 (i.e., the semiconductor doped layer of the second region A2) serves as the lower electrode 630 of capacitor 600.

[0218] In some embodiments, the following steps are performed after step S243:

[0219] Step S244: Form a common upper electrode plate, which covers the upper electrode and fills the unfilled areas between the semiconductor doped layers and the unfilled areas in the first sub-trench.

[0220] like Figure 15 As shown, refer to Figure 14 The common upper electrode 640 can be formed using any one of the following deposition processes: chemical vapor deposition, physical vapor deposition, atomic layer deposition, or sputtering. The common upper electrode 640 covers the surface of the upper electrode 620 of each capacitor 600 and fills the unfilled areas between the semiconductor doped layers of the second region A2 and the unfilled areas in the first sub-trench 131. The material of the common upper electrode 640 can include a semiconductor material doped with conductive ions or a conductive metal. For example, the material of the common upper electrode 640 can include monocrystalline silicon or polycrystalline silicon, and the material of the common upper electrode 640 can also include at least one of tungsten, cobalt, titanium, and / or nickel. In this way, the area of ​​the memory can be fully utilized, increasing the memory's storage capacity.

[0221] Step S250: A second trench is formed in the isolation layer, and one sidewall of the second trench exposes a portion of the surface of the middle region of the strip structure. At the same time, a fifth trench is formed in the isolation layer, and one sidewall of the fifth trench exposes a portion of the surface of the stacked structure of the bit line region.

[0222] like Figure 16 , Figure 17 , Figure 18 As shown, a third mask layer (not shown) is formed on the top surface of the structure. The third mask layer defines the patterns of the second trench 221 and the fifth trench 521. The third mask layer is etched away to expose the isolation layer 230, forming the second trench 221 and the fifth trench 521 respectively. The second trench 221 is located in the memory cell area Z1 (see reference). Figure 5 The second trench 221 exposes a portion of the surface of the middle region A11 of the strip structure 300. In this embodiment, the middle region A11 of the strip structure 300 refers to the first region A1 (refer to...). Figure 11 The middle area A11. The fifth groove 521 is close to the selection area Z3 (refer to...). Figure 5The fifth groove 521 exposes part of the surface of the stack structure 200 in the bit line region Z2.

[0223] Step S260: etching the middle region of the strip-shaped structure to remove part of the strip-shaped structure, forming a first groove between the adjacent first sub-layers in a direction perpendicular to the substrate, and etching the bit line region to remove part of the stack structure in the bit line region, forming a fourth groove between the adjacent first sub-layers in the bit line region in a direction perpendicular to the substrate, the fourth groove being arranged close to the selection region.

[0224] As shown in Figure 19 , Figure 20 , Figure 17 , Figure 18 , the stack structure 200 can be etched by a wet process, the semiconductor doped layer exposed by the second groove 221 is etched and removed, a first groove 121 is formed in the middle region Al 1 of the first region Al (see Figure 11 ), the first groove 121 and the second groove 221 are connected, and the first groove 121 divides the semiconductor doped layer of the memory cell region Z1 into two segments arranged independently on both sides of the first groove 121 in the first direction D1. Figure 52 , Figure 55 , Figure 56 As shown in ,

[0225] , in the first region Al, the semiconductor doped layer on the left side of the first groove 121 serves as a first source / drain electrode 181 of a cell transistor MCT of a subsequent formed memory cell SU, and the semiconductor doped layer on the right side of the first groove 121 serves as a second source / drain electrode 182 of the cell transistor MCT of the subsequent formed memory cell SU. It can be seen that the first source / drain electrode 181 is connected to the capacitor 600, and the second source / drain electrode 182 is connected to the bit line BL. Figure 19 , Figure 20 , Figure 17 , Figure 18 , the semiconductor doped layer exposed by the fifth groove 521 is etched and removed, a fourth groove 421 is formed in the middle region Al 1 of the bit line region Z2, the fourth groove 421 and the fifth groove 521 are connected, and the fourth groove 421 divides the semiconductor doped layer of the bit line region Z2 into two segments arranged independently on both sides of the fourth groove 421 in the second direction D2. Figure 52 , Figure 55 , Figure 56 As shown in ,

[0226] Step S270: A first semiconductor channel and a first gate dielectric layer are formed in a first trench, the first semiconductor channel covering the trench wall of the first trench and the first gate dielectric layer covering the first semiconductor channel. At the same time, a second semiconductor channel and a second gate dielectric layer are formed in a fourth trench, the second semiconductor channel covering the trench wall of the fourth trench and the second gate dielectric layer covering the second semiconductor channel.

[0227] The following implementation methods can be adopted, such as Figure 21 , Figure 22 , Figure 23 As shown, a semiconductor material layer 410, a gate dielectric material layer 420, and a first gate conductive layer 430 are formed sequentially. The semiconductor material layer 410 covers the trench walls of the first trench 121, the second trench 221, the fourth trench 421, and the fifth trench 521. The gate dielectric material layer 420 covers the semiconductor material layer 410. The first gate conductive layer 430 covers the gate dielectric material layer 420 and fills the unfilled areas of the first trench 121, the second trench 221, the fourth trench 421, and the fifth trench 521.

[0228] like Figure 26 Or such as Figure 32 As shown, the semiconductor material layer 410, gate dielectric material layer 420, and first gate conductive layer 430 in the second trench 221 and the semiconductor material layer 410, gate dielectric material layer 420, and first gate conductive layer 430 in the fifth trench 521 are etched away. The semiconductor material layer 410, gate dielectric material layer 420, and first gate conductive layer 430 in the first trench 121 are retained, and the first semiconductor channel 161, the first gate dielectric layer 171, and the first horizontal portion HS1 of the first word line WL1 are formed respectively. The semiconductor material layer 410, gate dielectric material layer 420, and first gate conductive layer 430 in the fourth trench 421 are retained, and the second semiconductor channel 261, the second gate dielectric layer 271, and the second horizontal portion HS2 of the second word line WL2 are formed respectively.

[0229] In some embodiments, the semiconductor material layer 410, the gate dielectric material layer 420, and the first gate conductive layer 430 are removed from the second trench 221 and the fifth trench 521, using the following implementation:

[0230] like Figure 24 As shown, refer to Figure 23 The first gate conductive layer 430 in the second trench 221 is removed by wet etching, and the first gate conductive layer 430 in the fifth trench 521 is also removed, exposing the gate dielectric material layer 420 in the second trench 221 and the fifth trench 521. Then, as... Figure 25 As shown, refer to Figure 24, a wet etching process is used to remove the gate dielectric material layer 420 in the second trench 221, and simultaneously remove the gate dielectric material layer 420 in the fifth trench 521, to expose the semiconductor material layer 410 in the second trench 221 and the fifth trench 521. Then, as shown in Figure 26 , referring to Figure 25 , a wet etching process is used to remove the semiconductor material layer 410 in the second trench 221, and simultaneously remove the semiconductor material layer 410 in the fifth trench 521, to expose the second trench 221 and the fifth trench 521.

[0231] The first gate conductive layer 430, the gate dielectric material layer 420 and the semiconductor material layer 410 are removed layer by layer from the center of the trench to the wall of the trench, which is simple in process, reduces the process steps, saves the process time and reduces the process cost.

[0232] In some embodiments, the semiconductor material layer 410, the gate dielectric material layer 420 and the first gate conductive layer 430 in the second trench 221 and the fifth trench 521 are removed by the following implementation:

[0233] First, as shown in Figure 29 , Figure 30 , the partial isolation layer 230 around the second trench 221 is etched and removed to form a third trench 321, which exposes the semiconductor material layer 410 in the second trench 221, and simultaneously, the partial isolation layer 230 around the fifth trench 521 is etched and removed to form a sixth trench 621, which exposes the semiconductor material layer 410 in the sixth trench 621.

[0234] A fourth mask layer can be formed on the top surface of the structure, which exposes the top surface of the partial isolation layer 230 around the second trench 221 and the top surface of the partial isolation layer 230 around the fifth trench 521, the isolation layer 230 exposed by the fourth trench 421 is etched and removed, and the third trench 321 is formed around the second trench 221, and the sixth trench 621 is formed around the fifth trench 521.

[0235] Then, as shown in Figure 31 , referring to Figure 30 , the semiconductor material layer 410, the gate dielectric material layer 420 and the first gate conductive layer 430 in the second trench 221 are etched and removed layer by layer based on the third trench 321, and simultaneously, the semiconductor material layer 410, the gate dielectric material layer 420 and the first gate conductive layer 430 in the fifth trench 521 are etched and removed layer by layer based on the sixth trench 621.

[0236] The semiconductor material layer 410, the gate dielectric material layer 420 and the first gate conductive layer 430 in the second trench 221 and the fifth trench 521 can be removed by layer-by-layer etching using a wet process. Etching the film layers in the second trench 221 and the fifth trench 521 from the sidewall of the trench to the center can ensure that the semiconductor material layer 410 in the second trench 221 and the fifth trench 521 is completely removed, avoid the existence of residual semiconductor material layer 410 in the second trench 221 or the fifth trench 521 to form a parasitic device in the memory, further improve the performance and quality of the memory. In addition, in the embodiment, the third trench 321 is formed outside the second trench 221, which can increase the size of the first vertical part VP1 formed subsequently, and reduce the resistance of the first word line WL1. Similarly, the embodiment can also reduce the resistance of the second word line WL2.

[0237] Step S280: forming the first word line while forming the second word line.

[0238] As shown in Figure 33 , Figure 34 , the first word line WL1 includes the first horizontal part HS1 formed in the first trench 121 and the first vertical part VP1 formed in the isolation trench 130, the first horizontal part HS1 covers the first gate dielectric layer 171, and the first vertical part VP1 is vertically arranged on the substrate 100 and fills the second trench 221, and the first horizontal part HS1 and the first vertical part VP1 are connected.

[0239] As shown in Figure 33 , Figure 34 , the second word line WL2 includes the second horizontal part HS2 formed in the fourth trench 421 and the second vertical part VP2 formed in the isolation trench 130, the second horizontal part HS2 covers the second gate dielectric layer 271, and the second vertical part VP2 is vertically arranged on the substrate 100 and fills the fifth trench 521, and the second horizontal part HS2 and the second vertical part VP2 are connected.

[0240] Referring to Figure 26 , Figure 31 , Figure 32 , the first horizontal part HS1 of the first word line WL1 and the first horizontal part HS1 of the second word line WL2 have been formed in step S270, and only the first vertical part VP1 of the first word line WL1 and the second vertical part VP2 of the second word line WL2 need to be formed.

[0241] As shown in Figure 27 , the first word line WL1 includes the first horizontal part HS1 formed in the first trench 121 and the first vertical part VP1 formed in the isolation trench 130, the first horizontal part HS1 covers the first gate dielectric layer 171, and the first vertical part VP1 is vertically arranged on the substrate 100 and fills the second trench 221, and the first horizontal part HS1 and the first vertical part VP1 are connected.As shown, the second gate conductive layer 440 can be formed by any of the following deposition processes: chemical vapor deposition, atomic layer deposition, physical vapor deposition, or sputtering. The second gate conductive layer 440 fills the second trench 221 and the fifth trench 521 respectively. It is understood that in the embodiment where the third trench 321 and the sixth trench 621 are formed, the second gate conductive layer 440 also fills the third trench 321 and the sixth trench 621.

[0242] like Figure 28 As shown, etching removes the second gate conductive layer 440 covering the top surface of the structure. The second gate conductive layer 440 in the second trench 221 forms a first vertical portion VP1. The first vertical portion VP1 covers the first horizontal portion HS1, and the first horizontal portion HS1 together forms a first word line WL1. In some embodiments, the second gate conductive layer 440 in the second trench 221 and the third trench 321 together form the first vertical portion VP1.

[0243] The second gate conductive layer 440 in the fifth trench 521 forms a second vertical portion VP2, which covers the second horizontal portion HS2 and together forms a second word line WL2. In some embodiments, the second gate conductive layers 440 in the fifth trench 521 and the sixth trench 621 together form the second vertical portion VP2.

[0244] The memory fabrication method of this embodiment forms a three-dimensional architecture based on a stacked structure of silicon oxide and semiconductor doped layers. When forming the semiconductor doped layer, the conductive ions in the semiconductor doped layer are activated by in-situ doping to make the semiconductor doped layer conductive. In this way, after forming the isolation trench, the semiconductor doped layer in the bit line region directly forms the bit line, and the semiconductor doped layer in the select region forms the select line. There is no need to perform the step of replacing the conductive material, which improves the process efficiency.

[0245] The memory fabrication method of this embodiment forms a second trench and a fifth trench in the isolation layer, reducing the steps of etching the stacked structure. At the same time, the stacked structure is used to protect the first trench and the fourth trench. The semiconductor material layer, the gate dielectric material layer and the first gate conductive layer in the second trench and the fifth trench are removed in an inside-out or outside-in manner to avoid the formation of parasitic devices by residual conductive materials. This avoids the parasitic devices affecting the performance of the memory and can further increase the number of layers in the three-dimensional stack of the memory, thereby improving the integration density of the memory.

[0246] The memory fabrication method of this embodiment uses channel-all-around (CAA) transistors formed in the memory. CAA transistors have lower off-state current, which can reduce memory leakage current, thereby reducing memory power consumption, reducing the size of devices in the memory, and increasing the array density of devices in the memory.

[0247] This disclosure provides a method for manufacturing a memory through several embodiments, such as... Figure 3 As shown, Figure 3 A flowchart illustrating a method for manufacturing a memory according to some embodiments of the present disclosure is shown. Figures 35-53 This is a schematic diagram illustrating the various stages of memory fabrication. The following section combines... Figures 35-53 And refer to Figure 52 , Figure 57 , Figure 58 The methods for manufacturing memory are introduced. For example... Figure 3 As shown, the method for manufacturing the memory includes the following steps:

[0248] Step S310: Provide a substrate and form a stacked structure on the substrate. The stacked structure includes alternating first and second sublayers. Define a memory cell region, a bit line region, and a select region in the stacked structure. The memory cell region and the bit line region are arranged along a first direction, and the select region is located at one end of the bit line region along a second direction.

[0249] Reference Figure 35 As shown, the stacked structure 200 includes a first sublayer 210 and a second sublayer 220 alternately stacked along the third direction D3. The first sublayer 210 is a silicon oxide layer, and the second sublayer 220 is a silicon nitride layer. The top and bottom layers of the stacked structure 200 are both the first sublayer 210 (i.e., silicon oxide layers).

[0250] In some embodiments, the stacked structure 200 is formed on the substrate 100, which can be implemented in the following ways:

[0251] Reference Figure 35 As shown, silicon oxide and silicon nitride layers can be deposited alternately using any of the following deposition processes: chemical vapor deposition, atomic layer deposition, or sputtering, and this process can be repeated several times to form the stacked structure 200. The silicon oxide and silicon nitride layers of the stacked structure 200 can be stacked alternately in 2 to 1024 or more layers. For example, silicon oxide and silicon nitride layers can be stacked alternately in 48, 64, 128, 256, or 512 layers, etc.

[0252] Reference Figure 5 The stacked structure 200 is laid out according to the structure of the memory to be formed. A memory cell region Z1, a bit line region Z2, and a select region Z3 are defined on the stacked structure 200. In this embodiment, a memory cell region Z1 is defined on each side of the bit line region Z2 along the first direction D1, and a select region Z3 is defined at one end of the bit line region Z2 along the second direction D2. The first direction D1 is parallel to the substrate 100, and the second direction D2 is parallel to the substrate 100 and intersects the first direction D1.

[0253] Step S320: forming an isolation trench, the isolation trench vertically penetrating the stack structure, the isolation trench extending along the first direction and dividing the stack structure of the memory cell region into at least one strip structure extending along the first direction.

[0254] The embodiments of forming the isolation trench are the same as those in step S220 of the above embodiment, and are not described herein again.

[0255] Some embodiments and the above embodiment are different in that, as shown in Figure 36 , referring to Figure 36 , the stack structure 200 includes silicon oxide layers and silicon nitride layers arranged alternately, thus, after the isolation trench 130 is formed, the stack structure 200 reserved in the bit line region Z2 extends along the second direction D2, and the stack structure 200 reserved in the selection region Z3 extends along the first direction D1.

[0256] Step S330: etching to remove all the second sub-layers, and forming an air layer in the region where the second sub-layers are removed.

[0257] In this embodiment, etching to remove all the second sub-layers includes the following steps:

[0258] Step S331: forming a first isolation layer, the first isolation layer filling part of the isolation trench.

[0259] As shown in Figure 37 , a chemical vapor deposition process or a physical vapor deposition process can be selected to deposit the first isolation layer 231, and the material of the first isolation layer 231 can include at least one of silicon oxide, silicon nitride or silicon oxynitride.

[0260] Step S332: etching to remove part of the first isolation layer, forming a second sub-trench in the isolation trench, and exposing part of the sidewall of the stack structure.

[0261] As shown in Figure 38 , along the first direction D1, the strip structure 300 in the memory cell region Z1 defines a first region A1 and a second region A2 arranged in sequence away from the bit line region Z2, the first region A1 is close to the bit line region Z2, and the second region A2 is away from the bit line region Z2.

[0262] In this embodiment, as shown in Figure 39 , Figure 40 , Figure 41As shown, a fifth mask layer (not shown) is formed on the top surface of the structure. The fifth mask layer exposes part of the top surface of the first isolation layer 231. The first isolation layer 231 exposed by the fifth mask layer is etched away, exposing part of the isolation trench 130. In some embodiments, the isolation trench 130 exposed in this step is defined as the second sub-trench 132. The second sub-trench 132 exposes part of the sidewall of the stacked structure 200 of the first region A1. The retained first isolation layer 231 is used to support the architecture of the stacked structure 200.

[0263] Step S333: Remove all of the second sub-layer by etching the second sub-trench.

[0264] like Figure 42 As shown, refer to 39. Figure 40 , Figure 41 Etching solution is injected into the second sub-trench 132. The etching solution can be a phosphoric acid solution. The etching solution dissolves and removes all of the second sub-layer 220 (i.e., silicon nitride layer, hereinafter referred to as silicon nitride layer). After removing all of the silicon nitride layer, an air layer 240 is formed in the original position of the silicon nitride layer. Along the third direction D3, the silicon oxide layer and the air layer 240 are alternately arranged.

[0265] Step S340: A bit line is formed in the air layer of the bit line region. The bit line extends along a second direction, which is parallel to the substrate and intersects with the first direction.

[0266] Bit line BL is formed in the air layer 240 of bit line region Z2, using the following implementation method:

[0267] Reference Figure 42 , Figure 53 A conductive metal material layer can be deposited using atomic layer deposition (ALD) or chemical vapor deposition (CVD). The conductive metal material layer fills the air layer and part of the second sub-trench 132. Then, the conductive metal material layer outside the bit line region Z2 is etched away. The conductive metal material layer in the air layer 240 of the bit line region Z2 is retained to form the bit line BL. The bit line BL extends along the second direction D2 and is spaced apart along the third direction D3.

[0268] The material of bit line BL may include at least one of titanium or titanium compounds, tantalum or tantalum compounds, tungsten or tungsten compounds, copper or copper compounds. In some embodiments, the material of bit line BL includes metallic tungsten. Bit line BL has lower resistance and better conductivity.

[0269] Step S350: Form a conductor layer, which fills the area of ​​the air layer that was not filled.

[0270] like Figure 43 As shown, refer to Figure 42The conductor layer 250 can be deposited using atomic layer deposition (ALD) or chemical vapor deposition (CVD) processes to fill the unfilled areas of the air layer and the second sub-trench 132. Then, the conductor layer material in the second sub-trench 132 is etched away, forming the conductor layer 250 in the unfilled areas of the air layer 240. (Refer to...) Figure 53 The conductor layer 250 of the selection region Z3 forms a selection line SL, which extends along the first direction D1 and is spaced apart along the third direction D3.

[0271] The material of conductor layer 250 may include titanium or titanium compounds, tantalum or tantalum compounds, and in some embodiments, the material of conductor layer 250 includes titanium nitride.

[0272] like Figure 44 As shown, refer to Figure 43 Then, the second isolation layer 232 is filled into the second sub-groove 132.

[0273] Step S360: A capacitor is formed at the end of the memory cell region away from the bit line region.

[0274] In some embodiments, a capacitor is formed at the end of the memory cell region away from the bit line region, including the following steps:

[0275] Step S361: Etch away a portion of the first sublayer at the end away from the bit line region, exposing a portion of the surface of the conductor layer at the end away from the bit line region.

[0276] like Figure 45 As shown, refer to Figure 44 A second mask layer (not shown in the figure) is formed on the top surface of the structure. The second mask layer exposes the top surface of the first isolation layer 231 connected to the second region A2. Based on the second mask layer, the first isolation layer 231 connected to the second region A2 is etched away to form a first sub-trench 131 connected to the second region A2. The sidewalls of the first sub-trench 131 expose part of the surface of the silicon oxide layer and the conductor layer 250 of the second region A2.

[0277] Then, as Figure 46 As shown, refer to Figure 45 The silicon oxide layer of the second region A2 is removed by etching based on the first sub-trench 131, exposing the surface of the conductor layer 250 of the second region A2.

[0278] Step S362: Form a dielectric layer that covers the surface exposed by the conductor layer.

[0279] Reference Figure 47As shown, the dielectric layer 610 is formed by an atomic layer deposition process, and uniformly covers the exposed surface of the semiconductor doped layer in the second region A2. The material of the dielectric layer 610 is the same as that of the dielectric layer 610 formed in step S242 in the above embodiment, and is not repeated here.

[0280] Step S363: Forming an upper electrode, the upper electrode covering the dielectric layer.

[0281] Referring to Figure 47 As shown, the upper electrode 620 is formed by an atomic layer deposition process, and covers the surface of the dielectric layer 610. The material of the upper electrode 620 is the same as that of the upper electrode 620 formed in step S243 in the above embodiment, and is not repeated here.

[0282] The conductor layer 250 covered by the dielectric layer 610 (i.e. the conductor layer 250 in the second region A2), the dielectric layer 610, and the upper electrode 620 form a capacitor 600 at one end of the memory cell region Z1 away from the bit line region Z2 (i.e. the second region A2), and the conductor layer 250 covered by the dielectric layer 610 (i.e. the conductor layer 250 in the second region A2) serves as a lower electrode 630 of the capacitor 600.

[0283] In some embodiments, the following steps are further performed after step S363:

[0284] Step S364: Forming a common upper plate, the common upper plate covering the upper electrode and filling the unfilled regions between the conductor layers 250 and the unfilled regions in the first sub-trenches.

[0285] Referring to Figure 48 As shown, in some embodiments, the process of forming the common upper plate 640, the material of the common upper plate 640, and the selection are the same as those in step S244 in the above embodiment, and are not repeated here.

[0286] Step S370: Forming a second trench, the second trench exposing part of the sidewall of the first region, and simultaneously forming a fifth trench, one sidewall of the fifth trench exposing part of the sidewall of the bit line region.

[0287] As Figure 49 As shown, a third mask layer (not shown in the figure) is formed on the top surface of the structure, the third mask layer defining the pattern of the second trench 221 and the fifth trench 521. The third mask layer is etched to expose the first isolation layer 231 and the second isolation layer 232, respectively forming the second trench 221 and the fifth trench 521.

[0288] In the first direction D1, the second trench 221 and the bit line region Z2 are spaced apart by a predetermined distance, and the second trench 221 is arranged close to the bar-shaped structure 300 and exposes part of the sidewall of the bar-shaped structure 300.

[0289] Along the second direction D2, the fifth trench 521 and the selection area Z3 are spaced apart by a preset distance. The fifth trench 521 is close to the stacked arrangement of the bit line area Z2 and exposes part of the sidewall of the stacked bit line area Z2.

[0290] Step S380: Etch the middle region of the strip structure to remove part of the strip structure, and form a first trench between adjacent first sublayers along the direction perpendicular to the substrate. At the same time, etch the bit line region to remove part of the stacked structure in the bit line region, and form a fourth trench between adjacent first sublayers in the bit line region along the direction perpendicular to the substrate. The fourth trench is located close to the selection region.

[0291] like Figure 50 As shown, based on the second trench 221, the strip structure 300 is etched to remove the conductor layer 250 exposed by the second trench 221, forming the first trench 121. (Refer to...) Figure 52 , Figure 57 , Figure 58 The first trench 121 divides the conductor layer 250 of the storage cell area Z1 into two segments independently disposed on both sides of the first trench 121 along the first direction D1, as shown in the figure. Figure 55 As shown, in the first region A1, the conductor layer 250 located to the left of the first trench 121 serves as the first source / drain 181 of the cell transistor MCT in the subsequently formed memory cell SU, and the conductor layer 250 located to the right of the first trench 121 serves as the second source / drain 182 of the cell transistor MCT in the subsequently formed memory cell SU. It can be seen that the first source / drain 181 is connected to the capacitor 600, and the second source / drain 182 is connected to the bit line.

[0292] like Figure 50 As shown, based on the etching of bit line region Z2 in the fifth trench 521, the conductive metal material layer exposed by the fifth trench 521 is removed to form the fourth trench 421. (Refer to...) Figure 52 , Figure 57 , Figure 58 The fourth trench 421 divides the conductive metal material layer of the bit line region Z2 into two segments independently disposed on both sides of the fourth trench 421 along the second direction D2. The part far away from the selection line SL serves as the third source / drain 281 of the subsequently formed selection transistor ST, and the part close to the selection region Z3 serves as the fourth source / drain 282 of the subsequently formed selection transistor ST. It can be seen that the third source / drain 281 is connected to the bit line BL, and the fourth source / drain 282 is connected to the selection line SL.

[0293] Step S390: A first semiconductor channel and a first gate dielectric layer are formed in a first trench, the first semiconductor channel covering the trench wall of the first trench and the first gate dielectric layer covering the first semiconductor channel. At the same time, a second semiconductor channel and a second gate dielectric layer are formed in a fourth trench, the second semiconductor channel covering the trench wall of the fourth trench and the second gate dielectric layer covering the second semiconductor channel.

[0294] Step S400: Form the first character line and simultaneously form the second character line.

[0295] Reference Figure 51 , Figure 52 , Figure 53 As shown, the implementation methods of steps S390 and S400 in some embodiments are the same as those of steps S270 and S280 in the above embodiments, and will not be repeated here.

[0296] The memory fabrication method of this embodiment can form a three-dimensional memory architecture based on a stacked structure formed by silicon oxide and silicon nitride layers, or it can form a three-dimensional memory architecture based on a stacked structure formed by silicon oxide and semiconductor doped layers. The memory fabrication method has a wide range of applications.

[0297] Some embodiments provide a memory, see reference Figure 52 , Figure 55 , Figure 56 , Figure 57 , Figure 58 and refer to Figure 33 , Figure 53 The memory includes a substrate 100, at least one first word line WL1, and at least one column of memory cells SUC. The first word line WL1 includes a first vertical portion VP1 and at least one first horizontal portion HS1. The first vertical portion VP1 is vertically disposed on the substrate 100, and the at least one first horizontal portion HS1 is spaced apart along a direction perpendicular to the substrate 100 and connected to the first vertical portion VP1. The at least one column of memory cells SUC includes at least one memory cell SU spaced apart along a direction perpendicular to the substrate 100. The memory cell SU includes a unit transistor MCT. The first horizontal portion HS1 serves as the gate G1 of the unit transistor MCT. The unit transistor MCT includes a first gate dielectric layer 171 and a first semiconductor channel 161 sequentially disposed along a direction away from the first horizontal portion HS1. The unit transistor MCT also includes a first source / drain 181 and a second source / drain 182 disposed opposite to each other on both sides of the first semiconductor channel 161 along a first direction D1. The first direction D1 is parallel to the substrate 100. The memory has no conductive film layer left over from the manufacturing process and no parasitic devices, which can improve the response speed of the semiconductor structure, avoid response delay, and improve the yield and electrical performance of the semiconductor structure.

[0298] The first word line WL1 includes a first vertical part VP1 and at least one first horizontal part HS1, the first horizontal part HS1 serving as a gate G1 of the unit transistor MCT, the first horizontal part HS not being limited in length by the first vertical part VP1 of the first word line WL1, and the first horizontal part HS being capable of increasing the length of the gate G1 of the unit transistor MCT, thereby enhancing the control capability of the gate G1 of the unit transistor MCT; in addition, the first semiconductor channel 161 at the position of the first horizontal part HS1 can be protected from damage to the first semiconductor channel 161 at the position of the first horizontal part HS1 when removing the parasitic channel.

[0299] In some embodiments, referring to Figure 52 、 Figure 53 , the first semiconductor channel 161 surrounds the first horizontal part HS1 in a plane parallel to the first direction D1 and perpendicular to the substrate 100, and such an arrangement can enhance the control capability of the gate G1 of the unit transistor MCT.

[0300] In some embodiments, referring to Figure 52 、 Figure 53 , the first semiconductor channel 161 includes a connecting channel 1611 located at one side of the first horizontal part HS1 in a second direction D2 parallel to the substrate 100 and intersecting the first direction D1, and such an arrangement enables the first semiconductor channel 161 to further cover the first horizontal part HS1, thereby further enhancing the control capability of the gate G1 of the unit transistor MCT.

[0301] In some embodiments, referring to Figure 52 、 Figure 53 , and referring to Figure 33 、 Figure 53 , the first semiconductor channel 161 is cup-shaped and is sleeved on the first horizontal part HS1.

[0302] One side of the first horizontal part HS1 is connected to the first vertical part VP1, and the entire outer periphery of the first horizontal part HS1, except for the region connected to the first vertical part VP1, is covered by the first semiconductor channel 161, such as shown in Figure 52 、 Figure 53 In some embodiments, the first horizontal part HS1 is square or rectangular in a cross-sectional view parallel to the substrate 100, one side of the first horizontal part HS1 is connected to the first vertical part VP1, and the remaining five sides of the first horizontal part HS1 are covered by the first semiconductor channel 161, the first semiconductor channel 161 covering a larger area of the first horizontal part HS1, and the control capability of the gate G1 of the unit transistor MCT is greater.

[0303] In some embodiments, as Figure 55 , Figure 56 As shown, the memory cell SU also includes a semiconductor doped layer 220a. The semiconductor doped layer 220a includes two segments disposed opposite each other on both sides of the first semiconductor channel 161 along the first direction D1. The first source / drain 181 and the second source / drain 182 are respectively disposed in the semiconductor doped layer 220a on both sides of the first semiconductor channel 161.

[0304] In some embodiments, such as Figure 57 , Figure 58 As shown, the memory cell SU also includes a conductor layer 250, which includes two sections disposed opposite each other on both sides of the first semiconductor channel 161 along the first direction D1. The first source / drain 181 and the second source / drain 182 are respectively disposed in the conductor layer 250 on both sides of the first semiconductor channel 161.

[0305] In some embodiments, the storage unit SU further includes a memory device for storing data, which may be a capacitor 600, a magnetic tunnel junction, or a phase change component.

[0306] In some embodiments, refer to Figure 52 , Figure 55 , Figure 56 , Figure 57 , Figure 58 The storage cell SU also includes a capacitor 600. Along the first direction D1, the capacitor 600 is disposed on one side of the cell transistor MCT, and the capacitor 600 is connected to the first source / drain 181 of the cell transistor MCT.

[0307] In some embodiments, refer to Figure 52 , Figure 55 , Figure 56 , Figure 57 , Figure 58 The capacitor 600 includes a lower electrode 630, a dielectric layer 610, and an upper electrode 620. The lower electrode 630 is connected to the first source / drain 181, and the dielectric layer 610 is disposed between the upper electrode 620 and the lower electrode 630. The dielectric layer 610 covers the lower electrode 630, and the upper electrode 620 covers the dielectric layer 610.

[0308] In some embodiments, refer to Figure 52 , Figure 55 , Figure 56 , Figure 57 , Figure 58 The lower electrode 630 of the capacitor 600 is disposed in the semiconductor doped layer 220a. The lower electrode 630 of the capacitor 600 is disposed on the same side as the first source / drain 181. The first source / drain 181 is disposed close to the first semiconductor channel 161, and the lower electrode 630 of the capacitor 600 is disposed away from the first semiconductor channel 161.

[0309] In some embodiments, referring to Figure 52 , Figure 55 , Figure 56 , Figure 57 , Figure 58 , the lower electrode 630 of the capacitor 600 is disposed in the conductor layer 250, and the lower electrode 630 of the capacitor 600 is disposed on the same side as the first source / drain 181, the first source / drain 181 is disposed close to the first semiconductor channel 161, and the lower electrode 630 of the capacitor 600 is disposed away from the first semiconductor channel 161.

[0310] In some embodiments, referring to Figure 52 , Figure 55 , Figure 56 , Figure 57 , Figure 58 , the upper electrodes 620 of the plurality of capacitors 600 are connected to each other to form a closed pattern in a plane parallel to the substrate 100, and such a configuration can increase the relative area of the upper electrode 620 and the lower electrode 630, and increase the capacitance.

[0311] In some embodiments, referring to Figure 52 , Figure 55 , Figure 56 , Figure 57 , Figure 58 , the closed pattern has a common upper plate 640 connected to the upper electrodes 620, and such a configuration can increase the volume ratio of the capacitors 600 in the memory, and increase the storage capacitance of the memory.

[0312] In some embodiments, referring to Figure 52 , Figure 55 , Figure 56 , Figure 57 , Figure 58 , the memory further comprises at least one bit line BL, the bit line BL is arranged in a direction perpendicular to the substrate 100, the bit line BL extends along the second direction D2, the bit line BL is connected to the second source / drain of the plurality of unit transistors MCT arranged along the second direction D2, the second direction D2 is parallel to the substrate 100 and intersects the first direction D1, and the bit line BL is used to perform read or write operations on the storage unit SU where the unit transistor MCT is located when the unit transistor MCT is turned on.

[0313] In some embodiments, referring to Figure 52 , Figure 55 , Figure 56 , Figure 57 , Figure 58 ​The memory further comprises a second word line WL2, the second word line WL2 comprising a second vertical part VP2 and at least one second horizontal part HS2, the second vertical part VP2 being vertically arranged on the substrate 100, and the at least one second horizontal part HS2 being spaced apart along a direction perpendicular to the substrate 100 and connected with the second vertical part VP2.

[0314] Referring to Figure 52 , Figure 55 , Figure 56 , Figure 57 , Figure 58 The memory further comprises at least one selection transistor ST, the at least one selection transistor ST being spaced apart along a direction perpendicular to the substrate 100, the second horizontal part HS2 serving as a gate G2 of the selection transistor ST, the selection transistor ST comprising a second gate dielectric layer 271 and a second semiconductor channel 261 arranged in sequence along a direction away from the second horizontal part HS2, and the selection transistor ST further comprising a third source / drain electrode 281 and a fourth source / drain electrode 282 oppositely arranged on two sides of the second semiconductor channel 261 along the second direction D2; the third source / drain electrode 281 of the selection transistor ST and the bit line BL are connected one by one.

[0315] Referring to Figure 52 , Figure 55 , Figure 56 , Figure 57 , Figure 58 The memory further comprises at least one selection line SL, the at least one selection line SL being spaced apart along a direction perpendicular to the substrate 100, the selection line SL extending along the first direction D1, and the selection line SL and the fourth source / drain electrode 282 of the selection transistor ST being connected one by one. The selection line SL is used to provide a voltage to the selection transistor ST, and the voltage is used to control the conduction or cutoff of the selection transistor ST, so as to control the storage unit SU connected with the bit line BL through the bit line BL.

[0316] Some embodiments provide an electronic device, the electronic device comprising the memory in the above embodiments.

[0317] The electronic device can be a mobile phone, a computer, a tablet computer, a television, an artificial intelligence device, etc.

[0318] The technical features of the above embodiments can be combined in any manner. To make the description concise, not all possible combinations of the technical features of the above embodiments are described, but it should be considered that any combination of the technical features is within the scope of the present disclosure as long as the combination does not exist contradictions.

[0319] The above embodiments only express several implementation ways of the present application, and the description is relatively specific and detailed, but it should not be understood as a limitation to the patent scope of the application. It should be pointed out that for ordinary skilled persons in the art, several modifications and improvements can be made without departing from the concept of the present application, which all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.

Claims

1. A method of fabricating a memory, comprising: The method comprises the following steps: providing a substrate, forming a stack structure on the substrate, the stack structure comprising first sub-layers and second sub-layers stacked alternately, defining a memory cell region and a bit line region in the stack structure; forming an isolation trench, the isolation trench penetrating the stack structure in a direction perpendicular to the substrate, the isolation trench extending in a first direction, dividing the stack structure of the memory cell region into at least one strip structure extending in the first direction, the first direction being parallel to the substrate; etching a middle region of the strip structure, removing part of the strip structure, forming a first trench between adjacent first sub-layers in a direction perpendicular to the substrate; forming a first semiconductor channel and a first gate dielectric layer in the first trench, the first semiconductor channel covering a trench wall of the first trench, the first gate dielectric layer covering the first semiconductor channel; forming a first word line, the first word line comprising a first horizontal part formed in the first trench and a first vertical part formed in the isolation trench, the first horizontal part covering the first gate dielectric layer, the first vertical part being arranged vertically on the substrate, the first horizontal part and the first vertical part being connected.

2. The method of claim 1, wherein forming a first trench between adjacent first sub-layers comprises: forming an isolation layer in the isolation trench; forming a second trench in the isolation layer, one sidewall of the second trench exposing part of a surface of the middle region of the strip structure; etching and removing the strip structure exposed by the second trench, forming the first trench, the first trench of the middle region and the first sub-layers being arranged alternately in a direction perpendicular to the substrate.

3. The method of claim 2, wherein forming a first semiconductor channel and a first gate dielectric layer in the first trench comprises: forming a semiconductor material layer, the semiconductor material layer covering a trench wall of the first trench and a trench wall of the second trench; forming a gate dielectric material layer, the gate dielectric material layer covering the semiconductor material layer; removing the semiconductor material layer and the gate dielectric material layer in the second trench, the semiconductor material layer in the first trench forming the first semiconductor channel, and the gate dielectric material layer in the first trench forming the first gate dielectric layer.

4. The method of claim 3, wherein forming a first word line comprises: forming the first horizontal part in the first trench, the first horizontal part covering the first gate dielectric layer and filling the first trench, one sidewall of the second trench exposing part of a surface of the first horizontal part; forming the first vertical part, the first vertical part contacting the exposed surface of the first horizontal part and filling the second trench.

5. The method of claim 4, wherein forming the first horizontal part in the first trench comprises: after forming the gate dielectric material layer, forming a first gate conductive layer, the first gate conductive layer covering the gate dielectric material layer and filling the first trench and the second trench; etching and removing the first gate conductive layer in the second trench, retaining the first gate conductive layer in the first trench, forming the first horizontal part.

6. The method of fabricating memory according to claim 5, wherein, the manufacturing method comprises: The first gate conductive layer, the gate dielectric material layer, and the semiconductor material layer in the second trench are sequentially etched away to expose the second trench.

7. The method of claim 5, wherein The manufacturing method includes: Etching removes a portion of the isolation layer surrounding the second trench to form a third trench, the third trench exposing the semiconductor material layer located in the second trench; The semiconductor material layer, the gate dielectric material layer, and the first gate conductive layer in the second trench are removed by etching in the third trench.

8. The method of fabricating memory of claim 4, wherein, The formation of the first vertical portion includes: A second gate conductive layer is formed, which at least fills the second trench to form the first vertical portion.

9. The method of fabricating memory according to any one of claims 1-8, wherein, Along the first direction, the first groove and the bit line area are spaced by a preset distance.

10. The method of fabricating memory according to any one of claims 1-8, wherein, In the stacked structure, a selection area is defined, the memory cell area and the bit line area are arranged along the first direction, the selection area is along a second direction at one end of the bit line area, and the second direction is parallel to the substrate and intersects the first direction; The manufacturing method further includes: The bit line region is etched to remove a portion of the stacked structure in the bit line region. A fourth trench is formed between adjacent first sublayers in the bit line region along a direction perpendicular to the substrate. The fourth trench is located near the selection region.

11. The method of fabricating memory of claim 10, wherein, The manufacturing method further includes: While forming the first semiconductor channel and the first gate dielectric layer in the first trench, a second semiconductor channel and a second gate dielectric layer are formed in the fourth trench, the second semiconductor channel covering the trench wall of the fourth trench, and the second gate dielectric layer covering the second semiconductor channel; While forming the first word line, a second word line is formed. The second word line includes a second horizontal portion formed in the fourth trench and a second vertical portion formed in the isolation trench. The second horizontal portion covers the second gate dielectric layer and fills the fourth trench. The second vertical portion is vertically disposed on the substrate. The second horizontal portion and the second vertical portion are connected.

12. The method of claim 1, wherein The first sub-layer is a silicon oxide layer, and the second sub-layer is a semiconductor doped layer. After the isolation trench is formed, the semiconductor doped layer in the bit line region forms a bit line extending along a second direction, which is parallel to the substrate and intersects with the first direction.

13. The method of claim 12, wherein The manufacturing method further includes: Etching removes a portion of the first sublayer away from the bit line region, exposing a portion of the surface of the semiconductor doped layer away from the bit line region; A dielectric layer is formed, which covers the exposed surface of the semiconductor doped layer; An upper electrode is formed, which covers the dielectric layer.

14. The method of fabricating memory of claim 1, wherein, The first sublayer is a silicon oxide layer, and the second sublayer is a silicon nitride layer; After forming isolation trenches in the storage cell area, the manufacturing method includes: The entire second sublayer is etched away, and an air layer is formed in the area where the second sublayer has been removed; A bit line is formed in the air layer of the bit line region, the bit line extending along a second direction, the second direction being parallel to the substrate and intersecting the first direction; A conductor layer is formed to fill the region not filled by the air layer.

15. The method of claim 14, wherein The manufacturing method further includes: A first sub-layer is etched to remove a portion of the first sub-layer away from one end of the bit line region, exposing a portion of a surface of the conductor layer away from the one end of the bit line region; A dielectric layer is formed to cover the exposed surface of the conductor layer; An upper electrode is formed to cover the dielectric layer.

16. A memory, comprising: The memory includes: a substrate; at least one first word line, the first word line including a first vertical portion and at least one first horizontal portion, the first vertical portion being vertically arranged on the substrate, and the at least one first horizontal portion being spaced apart along a direction perpendicular to the substrate and connected to the first vertical portion; at least one column of memory cells, the column of memory cells including at least one memory cell spaced apart along the direction perpendicular to the substrate; the memory cell including a cell transistor, the first horizontal portion serving as a gate of the cell transistor, the cell transistor including a first gate dielectric layer and a first semiconductor channel arranged in sequence away from the first horizontal portion, and the cell transistor further including a first source / drain and a second source / drain oppositely arranged on two sides of the first semiconductor channel along a first direction, the first direction being parallel to the substrate; in a plane parallel to the first direction and perpendicular to the substrate, the first semiconductor channel surrounds the first horizontal portion.

17. The memory of claim 16, wherein, the first semiconductor channel includes a connection channel located on one side of the first horizontal portion in a second direction, the second direction being parallel to the substrate and intersecting the first direction.

18. The memory of claim 16, wherein, the first semiconductor channel is cup-shaped, and the first semiconductor channel is sleeved on the first horizontal portion.

19. The memory of claim 16, wherein, the memory cell further includes a capacitor, the capacitor being arranged on one side of the cell transistor along the first direction, and the capacitor being connected to the first source / drain of the cell transistor.

20. The memory of claim 19, wherein, the capacitor includes a lower electrode connected to the first source / drain, a dielectric layer, and an upper electrode, the dielectric layer being arranged between the upper electrode and the lower electrode.

21. The memory of claim 20, wherein, in a plane parallel to the substrate, the upper electrodes of a plurality of the capacitors are connected to each other to form a closed pattern.

22. The memory of claim 21, wherein, the closed pattern has a common upper plate connected to the upper electrodes.

23. The memory of claim 16, wherein, The memory further includes: at least one bit line, the at least one bit line being spaced apart along a direction perpendicular to the substrate, the bit line extending along a second direction, and the bit line being connected to the second source / drain of a plurality of the cell transistors arranged along the second direction, the second direction being parallel to the substrate and intersecting the first direction.

24. The memory of claim 23, wherein, The memory further includes: a second word line, the second word line including a second vertical portion and at least one second horizontal portion, the second vertical portion being vertically arranged on the substrate, and the at least one second horizontal portion being spaced apart along a direction perpendicular to the substrate and connected to the second vertical portion; At least one selection transistor, at least one of the selection transistor is arranged along a direction perpendicular to the substrate, the second horizontal part as the gate of the selection transistor, the selection transistor comprises a second gate dielectric layer and a second semiconductor channel arranged in sequence along a direction away from the second horizontal part, the selection transistor further comprises a third source / drain and a fourth source / drain oppositely arranged on both sides of the second semiconductor channel along the second direction; the third source / drain of the selection transistor and the bit line are connected one by one.

25. The memory of claim 24, wherein, The memory further comprises: At least one selection line, at least one of the selection line is arranged along a direction perpendicular to the substrate, the selection line extends along the first direction, and the selection line and the fourth source / drain of the selection transistor are connected one by one.

26. An electronic device, comprising: The memory comprises any one of claims 16 to 25.

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