Semiconductor device and manufacturing method thereof

Abstract

A semiconductor device including a highly integrated memory cell and a method of manufacturing the semiconductor device are provided. The semiconductor device may include a horizontally arranged switching element including a nanosheet and a horizontal wire surrounding the nanosheet; a pyramid-shaped first contact node formed on a first edge of the horizontally arranged nanosheets; vertical wires including a pyramid portion surrounding the first contact node, each vertical wire coupled to a different one of the horizontally arranged nanosheets; data storage elements, each data storage element coupled to a different one of the second edges of the horizontally arranged nanosheets; and a support.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10 - 2023 - 0172410, filed on December 1, 2023, and Korean Patent Application No. 10 - 2024 - 0174313, filed on November 29, 2024, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical field

[0003] Embodiments of the present disclosure relate to semiconductor devices, and more particularly, to semiconductor devices including three - dimensional (3D) memory cells and methods of manufacturing such semiconductor devices. Background art

[0004] Recently, in order to cope with the trend of large capacity and miniaturization of storage devices, a three - dimensional (3D) storage device has been proposed, in which multiple memory cells are stacked. Summary of the invention

[0005] Embodiments of the present disclosure relate to a semiconductor device including highly integrated memory cells and a method of manufacturing such semiconductor device.

[0006] According to an embodiment of the present disclosure, a semiconductor device may include: a switch element disposed horizontally, the switch element including a nanosheet and a horizontal wire surrounding the nanosheet; a pyramidal first contact node formed on a first edge of the horizontally disposed nanosheet; a vertical wire including a pyramidal portion surrounding the first contact node, each vertical wire being coupled to a different one of the horizontally disposed nanosheets; a data storage element, each data storage element being coupled to a different one of second edges of the horizontally disposed nanosheet; and a support.

[0007] According to an embodiment of the present invention, a method of manufacturing a semiconductor device may include: forming a barrier layer on a substrate; forming narrow sheets disposed horizontally and vertically on the barrier layer; forming a support including support recesses that simultaneously expose edges of the vertically disposed narrow sheets and expose edges of the horizontally disposed narrow sheets; forming first contact nodes disposed horizontally and vertically, each first contact node being coupled to a different one of the edges of the horizontally and vertically disposed narrow sheets; and forming vertical wires commonly coupled to the vertically disposed first contact nodes, each vertical wire being coupled to a different one of the horizontally disposed first contact nodes and disposed in the support recesses.

[0008] According to one embodiment of the present disclosure, a semiconductor device may include: a substrate; a memory cell array including horizontally and vertically arranged nanosheet transistors and vertical wires, each vertical wire being coupled to a different one of the horizontally arranged nanosheet transistors and commonly coupled to the vertically arranged nanosheet transistors; a barrier layer formed between the memory cell array and the substrate; and a support for supporting the vertical wires. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1A is a schematic perspective view showing a memory cell according to an embodiment of the present disclosure.

[0010] Figure 1B is along Figure 1A a schematic cross-sectional view of the memory cell taken along the line X1-X1' shown.

[0011] Figure 2A is a schematic perspective view showing a semiconductor device according to an embodiment of the present disclosure.

[0012] Figure 2B is showing Figure 2A a partial perspective view of the second layer shown in

[0013] Figure 2C is showing Figure 2B a partial perspective view of the second wire shown in

[0014] Figure 2D is showing Figure 2B a partial perspective view of the first spacer shown in

[0015] Figure 2E is showing Figure 2B a partial perspective view of the second spacer and the etch stop spacer shown in

[0016] Figure 3A is a schematic perspective view showing a semiconductor device according to an embodiment of the present disclosure.

[0017] Figure 3B is a schematic plan view showing a semiconductor device according to an embodiment of the present disclosure.

[0018] Figure 4A is along Figure 3B a schematic cross-sectional view of the semiconductor device taken along the line A-A' shown.

[0019] Figure 4B is along Figure 3B a schematic cross-sectional view of the semiconductor device taken along the line B-B' shown.

[0020] Figure 4C is along Figure 3BSchematic cross-sectional view of a semiconductor device taken along the line A1 - A1'.

[0021] Figures 5A to 34B Views showing a semiconductor device formed by a method of manufacturing a semiconductor device according to an embodiment of the present disclosure are presented.

[0022] Figure 35A and 35B are schematic cross-sectional views of a semiconductor device according to an embodiment of the present disclosure.

[0023] Figure 36A and 36B Views showing a stacked component according to an embodiment of the present disclosure are presented. Detailed Description

[0024] Embodiments of the present disclosure may be described herein with reference to cross-sectional views, plan views, and block diagrams, which are ideal schematic diagrams of semiconductor devices. It should be noted that the structure of the drawings may be modified by manufacturing techniques and / or tolerances. Embodiments of the present disclosure are not limited to the specific structures described in the embodiments and shown in the drawings, but may include other embodiments, or modifications of the described embodiments, including any variations in the structures that may result from the requirements of the manufacturing process. Therefore, the regions shown in the drawings have schematic properties, and the shapes of the regions shown in the drawings are intended to illustrate the specific structures of the respective elements, rather than to limit the scope of the embodiments of the present disclosure.

[0025] The following embodiments relate to three-dimensional (3D) memory cells having vertically stacked memory cells for increasing memory cell density and reducing parasitic capacitance.

[0026] Figure 1A is a schematic perspective view showing a memory cell MC according to an embodiment of the present disclosure. Figure 1B is along Figure 1A Schematic cross-sectional view of the memory cell MC taken along the line X1 - X1'.

[0027] Referring to Figure 1A and 1B , the memory cell MC may include a first wire BL, a switching element TR, and a data storage element CAP.

[0028] The first conductor BL can be vertically oriented along the first direction D1. The first conductor BL can include a bit line. The first conductor BL can be referred to as a "vertical conductor", "vertically oriented bit line", "vertically extending bit line", or "cylindrical bit line". The first conductor BL can include a conductive material. The first conductor BL can include a silicon-based material, a metal-based material, or a combination thereof. The first conductor BL can include polysilicon, metal, metal nitride, metal silicide, or a combination thereof. The first conductor BL can include polysilicon, titanium nitride, tungsten, or a combination thereof. For example, the first conductor BL can include a titanium nitride / tungsten (TiN / W) stack, where titanium nitride and tungsten are stacked in sequence.

[0029] The switching element TR has the function of controlling the supply of voltage or current to the data storage element CAP during data writing and data reading operations on the data storage element CAP. The switching element TR can include a nanosheet HL, a nanosheet dielectric layer GD, and a second conductor WL. The second conductor WL can include a horizontal conductor or a horizontal word line, and the nanosheet HL can include an active layer. The switching element TR can include a transistor, in which case the second conductor WL can be used as a gate electrode. The switching element TR can also be referred to as a "nanosheet transistor", "access element", or "selection element". The second conductor WL can be referred to as a "horizontal gate electrode" or "horizontal word line".

[0030] The nanosheet HL can extend in a second direction D2 that intersects the first direction D1. The second conductor WL can extend in a third direction D3 that intersects the first direction D1 and the second direction D2. The first direction D1 can be a vertical direction, the second direction D2 can be a first horizontal direction, and the third direction D3 can be a second horizontal direction. The nanosheet HL can extend in the first horizontal direction, i.e., the second direction D2, and the second conductor WL can extend in the second horizontal direction, i.e., the third direction D3. The nanosheet HL can be referred to as a "horizontal layer".

[0031] The nanosheet HL can include a channel CH, a first doped region SR between the channel CH and the first conductor BL, and a second doped region DR between the channel CH and the data storage element CAP. The first doped region SR can be electrically coupled to the first conductor BL, and the second doped region DR can be electrically coupled to the data storage element CAP. The height of the second doped region DR in the first direction D1 can be greater than the height of the channel CH in the first direction D1. The length of the second doped region DR in the second direction D2 can be less than the length of the channel CH in the second direction D2. The lengths of the first doped region SR, the channel CH, and the second doped region DR in the third direction D3 can be equal to each other.

[0032] The nanosheet HL may include a first region NS and a second region WS that are horizontally disposed along a second direction D2. The second region WS may extend from the first region NS. The second region WS may have a thickness that gradually increases from the first region NS toward the data storage element CAP along the second direction D2 between the first region NS and the data storage element CAP. The average vertical height or thickness of the second region WS in a first direction D1 may be greater than the average vertical height or thickness of the first region NS. Hereinafter, the first region NS is referred to as the "narrow sheet", and the second region WS is referred to as the "wide sheet".

[0033] The narrow sheet NS may have a flat plate shape. The wide sheet WS may have a fan shape. The wide sheet WS may have a thickness that gradually increases in the second direction D2. The narrow sheet NS may be referred to as a "flat plate-like sheet", and the wide sheet WS may be referred to as a "fan-shaped sheet". The boundary portion between the narrow sheet NS and the wide sheet WS may have a curvature.

[0034] A first doped region SR and a channel CH may be disposed in the narrow sheet NS, and a second doped region DR may be disposed in the wide sheet WS. The channel CH formed in the narrow sheet NS may be referred to as a "narrow channel" or a "flat channel". A part of the second doped region DR may extend to be disposed in the narrow sheet NS. The second doped region DR may include a thick portion disposed in the wide sheet WS and a thin portion disposed in the narrow sheet NS. The sides of the wide sheet WS and the second doped region DR that are in contact with the data storage element CAP may each have a flat side shape.

[0035] The horizontal length of the wide sheet WS in the second direction D2 may be less than the horizontal length of the narrow sheet NS. The narrow sheet NS may be referred to as the "long sheet", and the wide sheet WS may be referred to as the "short sheet".

[0036] The nanosheet HL may include a semiconductor material. For example, the nanosheet HL may include polysilicon, single-crystalline silicon, germanium, or silicon germanium. In some embodiments, the nanosheet HL may include an oxide semiconductor material. For example, the oxide semiconductor material may include indium gallium zinc oxide (IGZO), InSnZnO, ZnSnO, or a combination thereof. In some embodiments, the nanosheet HL may include a conductive metal oxide. In some embodiments, the nanosheet HL may include a two-dimensional material, such as MoS 2 、WS 2 or MoSe 2 。

[0037] When the nanosheet HL is formed of an oxide semiconductor material, the channel CH may also be formed of an oxide semiconductor material, and the first doped region SR and the second doped region DR may be omitted. The nanosheet HL may also be referred to as an "active layer" or a "thin body".

[0038] The first doped region SR and the second doped region DR may be doped with impurities of the same conductivity type. The first doped region SR and the second doped region DR may each be doped with N-type conductive impurities or P-type conductive impurities. The first doped region SR and the second doped region DR may include at least one impurity selected from arsenic (As), phosphorus (P), boron (B), indium (In), and combinations thereof. The first doped region SR may be coupled to the first wire BL, and the second doped region DR may be coupled to the data storage element CAP. The first doped region SR and the second doped region DR may be referred to as "the first source / drain region and the second source / drain region".

[0039] The nanosheet HL may be horizontally oriented from the first wire BL along the second direction D2.

[0040] The second wire WL may have a gate-all-around (GAA) structure. For example, the second wire WL may surround the nanosheet HL and extend in the third direction D3. The nanosheet dielectric layer GD may be formed between the nanosheet HL and the second wire WL. The nanosheet dielectric layer GD may surround the nanosheet HL. The second wire WL may surround the nanosheet HL on the nanosheet dielectric layer GD.

[0041] The second wire WL may include a metal-based material, a semiconductor material, or a combination thereof. The second wire WL may include molybdenum, molybdenum nitride, ruthenium, titanium nitride, tungsten, polysilicon, or a combination thereof. For example, the second wire WL may include a TiN / W stack, in which titanium nitride and tungsten are stacked in sequence. The second wire WL may include an N-type work function material or a P-type work function material. The N-type work function material may have a low work function of about 4.5 eV or less, and the P-type work function material may have a high work function of about 4.5 eV or more. The second wire WL may include a stack of a low work function material and a high work function material.

[0042] The nanosheet dielectric layer GD may be disposed between the nanosheet HL and the second wire WL. The nanosheet dielectric layer GD may be referred to as a "gate dielectric layer" or a "channel side dielectric layer". The nanosheet dielectric layer GD may include silicon oxide, silicon nitride, metal oxide, metal oxide nitride, metal silicate, high-k material, ferroelectric material, antiferroelectric material, or a combination thereof. The nanosheet dielectric layer GD may include SiO 2 、Si 3 N 4 、HfO 2 、Al 2 O 3 、ZrO 2 、AlON, HfON, HfSiO, HfSiNO, HfZrO, or a combination thereof. The nanosheet dielectric layer GD may be formed by thermal oxidation of a semiconductor material.

[0043] The data storage element CAP may include a storage element such as a capacitor. The data storage element CAP may be horizontally disposed from the switching element TR in the second direction D2. The data storage element CAP may include a first electrode SN, a second electrode PN on the first electrode SN, and a dielectric layer DE between the first electrode SN and the second electrode PN. The first electrode SN may horizontally extend from the nanosheet HL in the second direction D2. The first electrode SN, the dielectric layer DE, and the second electrode PN may be horizontally disposed in the second direction D2. The first electrode SN may include an internal space and a plurality of outer surfaces, and the internal space of the first electrode SN may include a plurality of inner surfaces. The outer surface of the first electrode SN may include a vertical outer surface and a plurality of horizontal outer surfaces. The vertical outer surface of the first electrode SN may vertically extend in the first direction D1, and the horizontal outer surface of the first electrode SN may horizontally extend in the second direction D2 or the third direction D3. The internal space of the first electrode SN may be a three-dimensional space. The dielectric layer DE may conformally cover the inner surface of the first electrode SN. The second electrode PN may be disposed in the internal space of the first electrode SN on the dielectric layer DE. Some outer surfaces of the first electrode SN may be electrically coupled to the second doped region DR of the nanosheet HL. The second electrode PN of the data storage element CAP may be coupled to the common plate PL.

[0044] The data storage element CAP may have a three-dimensional structure. The first electrode SN may have a three-dimensional structure, which may have a three-dimensional structure horizontally oriented in the second direction D2. In an example of the three-dimensional structure, the first electrode SN may have a cylindrical shape. The cylindrical shape of the first electrode SN may include a cylindrical inner surface and a cylindrical outer surface. Some cylindrical outer surfaces of the first electrode SN may be electrically coupled to the second doped region DR of the nanosheet HL. The dielectric layer DE and the second electrode PN may be disposed on the cylindrical inner surface of the first electrode SN.

[0045] In some embodiments, the first electrode SN may be columnar or tubular. Tubular may refer to a structure in which a columnar and a cylindrical shape are combined.

[0046] The first electrode SN and the second electrode PN may include a metal, a noble metal, a metal nitride, a conductive metal oxide, a conductive noble metal oxide, a metal carbide, a metal silicide, or a combination thereof. For example, the first electrode SN and the second electrode PN may include titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO2), iridium (Ir), iridium oxide (IrO2), platinum (Pt), molybdenum (Mo), molybdenum nitride (MoN), molybdenum oxide (MoO), titanium nitride / tungsten (TiN / W) stack, tungsten nitride / tungsten (WN / W) stack, titanium silicon nitride / titanium nitride stack (TiSiN / TiN), titanium nitride / titanium silicon nitride (TiN / TiSiN) stack, or a combination thereof. The second electrode PN may also include a combination of a metal-based material and a silicon-based material. For example, the second electrode PN may be a titanium nitride / silicon germanium / tungsten nitride (TiN / SiGe / WN) stack. In the titanium nitride / silicon germanium / tungsten nitride (TiN / SiGe / WN) stack, silicon germanium may be a gap-filling material filling the interior of the first electrode SN, titanium nitride (TiN) may be used as the second electrode PN of the data storage element CAP, and tungsten nitride may be a low-resistance material.

[0047] The dielectric layer DE may be referred to as a "capacitor dielectric layer" or a "storage layer". The dielectric layer DE may include silicon oxide, silicon nitride, a high-k material, a perovskite material, or a combination thereof. The high-k material may include hafnium oxide (HfO 2 ), zirconium oxide (ZrO 2 ), aluminum oxide (Al 2 O 3 ), lanthanum oxide (La 2 O 3 ), titanium oxide (TiO 2 ), tantalum oxide (Ta 2 O 5 ), niobium oxide (Nb 2 O 5 ), or strontium titanate (SrTiO 3 ). In some embodiments, the dielectric layer DE may be formed of a composite layer including two or more layers of the above high-k materials.

[0048] The dielectric layer DE may be formed of a zirconium (Zr)-based oxide. The dielectric layer DE may have a stacked structure including zirconium oxide (ZrO 2 ). The dielectric layer DE may include a ZA (ZrO 2 / Al 2 O 3 ) stack or a ZAZ (ZrO 2 / Al 2 O 3 / ZrO2 ) Stack. The ZA stack may have alumina (Al 2 O 3 ) stacked on zirconia (ZrO 2 ). The ZAZ stack may have a structure in which zirconia (ZrO 2 ) and alumina (Al 2 O 3 ) and zirconia (ZrO 2 ) are stacked in sequence. Each of the ZA stack and the ZAZ stack may be referred to as a "zirconia (ZrO 2 ) base layer". In some embodiments, the dielectric layer DE may be formed of a hafnium (Hf)-based oxide. The dielectric layer DE may have a stacked structure including hafnium oxide (HfO 2 ). The dielectric layer DE may include an HA (HfO 2 / Al 2 O 3 ) stack or an HAH (HfO 2 / Al 2 O 3 / HfO 2 ) stack. The HA stack may have a structure in which alumina (Al 2 O 3 ) is stacked on hafnium oxide (HfO 2 ). The HAH stack may have a structure in which hafnium oxide (HfO 2 ), alumina (Al 2 O 3 ) and hafnium oxide (HfO2) are stacked in sequence. Each of the HA stack and the HAH stack may be referred to as a "hafnium oxide (HfO 2 ) base layer". In the ZA stack, the ZAZ stack, the HA stack, and the HAH stack, alumina (Al 2 O 3 ) may have a larger bandgap energy than zirconia (ZrO 2 ) and hafnium oxide (HfO 2 ). Alumina (Al 2 O 3 ) may have a lower dielectric constant than zirconia (ZrO 2 ) and hafnium oxide (HfO 2 ). Thus, the dielectric layer DE may include a stack of a high-k material and a high-bandgap material, and the high-bandgap material has a larger bandgap energy than the high-k material. The dielectric layer DE may include silicon oxide (SiO 2 ) as an addition to alumina (Al 2 O 3High-bandgap materials other than 2 / Al 2 O 3 / ZrO 2 / Al 2 O 3 ) stack, ZAZAZ (ZrO 2 / Al 2 O 3 / ZrO 2 / Al 2 O 3 / ZrO 2 ) stack, HAHA (HfO 2 / Al 2 O 3 / HfO 2 / Al 2 O 3 ) stack, HAHAH (HfO 2 / Al 2 O 3 / HfO 2 / Al 2 O 3 / HfO 2 ) stack, HZAZH (HfO 2 / ZrO 2 / Al 2 O 3 / ZrO 2 / HfO 2 ) stack, ZHZAZHZ (ZrO 2 / HfO 2 / ZrO 2 / Al 2 O 3 / ZrO 2 / HfO 2 / ZrO 2 ) stack, HZHZ (HfO 2 / ZrO 2 / HfO 2 / ZrO 2 ) stack or AHZAZHA (Al 2 O 3 / HfO 2 / ZrO 2 / Al 2 O 3 / ZrO 2 / HfO2 / Al 2 O 3 ) stack. In the above stack structure, aluminum oxide (Al 2 O 3 ) can be thinner than zirconia (ZrO 2 ) and hafnium oxide (HfO 2 ).

[0049] In some embodiments, the dielectric layer DE may include a high-k material and a high bandgap material. Specifically, the dielectric layer DE may have a laminated structure or a hybrid structure. According to the laminated structure, multiple layers of high-k materials and multiple layers of high bandgap materials are stacked. According to the hybrid structure, the high-k material and the high bandgap material are mixed.

[0050] In some embodiments, the dielectric layer DE may include a ferroelectric material, an antiferroelectric material, or a combination thereof. For example, the dielectric layer DE may include HfZrO.

[0051] In some embodiments, the dielectric layer DE may include a combination of a high-k material and a ferroelectric material, a combination of a high-k material and an antiferroelectric material, or a combination of a high-k material or a ferroelectric material and an antiferroelectric material.

[0052] In some embodiments, an interface control layer may be further formed between the first electrode SN and the dielectric layer DE to reduce leakage current. The interface control layer may include titanium oxide (TiO 2 ), tantalum oxide (Ta 2 O 5 ), niobium oxide (Nb 2 O 5 ), niobium nitride (NbN), or a combination thereof. The interface control layer may also be formed between the second electrode PN and the dielectric layer DE.

[0053] The data storage element CAP may include a three-dimensional capacitor. The data storage element CAP may include a metal-insulator-metal (MIM) capacitor. The data storage element CAP may be replaced with another data storage material. For example, the data storage material may be a thyristor, a phase change material, a magnetic tunnel junction (MTJ), or a variable resistance material.

[0054] The memory cell MC may further include a first contact node BLC and a second contact node SNC. The first contact node BLC may be disposed between the first wire BL and the nanosheet HL. The first contact node BLC may include a metal-based material or a semiconductor material. For example, the first contact node BLC may include titanium, titanium nitride, tungsten, or a combination thereof. In addition, the first contact node BLC may include doped polysilicon, and the first doped region SR may include impurities diffused from the first contact node BLC. The second contact node SNC may be disposed between the nanosheet HL and the first electrode SN. The second contact node SNC may include a metal-based material or a semiconductor material. For example, the second contact node SNC may include titanium, titanium nitride, tungsten, or a combination thereof. In addition, the second contact node SNC may include doped silicon, and the second doped region DR may include impurities diffused from the second contact node SNC. The height of the first contact node BLC in the first direction D1 may be less than the height of the second contact node SNC in the first direction D1. The height of the first contact node BLC in the first direction D1 may be greater than the height of the channel CH in the first direction D1. The first contact node BLC and the second contact node SNC may each include phosphorus-doped polysilicon or arsenic-doped polysilicon.

[0055] The first contact node BLC may be selectively grown from the narrow sheet NS of the nanosheet HL. The first contact node BLC may be formed by selective epitaxial growth (SEG). For example, the first contact node BLC may be a silicon epitaxial layer formed by selective epitaxial growth (SEG). The first contact node BLC may be a doped silicon epitaxial layer. The second contact node SNC may be selectively grown from the wide sheet WS of the nanosheet HL. The second contact node SNC may be formed by selective epitaxial growth (SEG). For example, the second contact node SNC may be a silicon epitaxial layer formed by selective epitaxial growth (SEG). The second contact node SNC may be a doped silicon epitaxial layer. The first contact node BLC may be a phosphorus-doped silicon epitaxial layer.

[0056] The first contact node BLC may be a narrow-sheet side contact node, and the second contact node SNC may be a wide-sheet side contact node.

[0057] The nanosheet HL may include a first edge and a second edge. The first edge may refer to a part of the first doped region SR electrically coupled to the first wire BL, and the second edge may be a part of the second doped region DR electrically coupled to the first electrode SN of the data storage element CAP.

[0058] The memory cell MC may further include an ohmic contact layer BLO located between the first contact node BLC and the first wire BL. The ohmic contact layer BLO may include a metal silicide, such as titanium silicide or molybdenum silicide.

[0059] The memory cell MC may further include a first spacer SP1, a second spacer SP2, and an etch stop spacer SP3. The first spacer SP1 may be disposed between the second wire WL and the second doped region DR. The second spacer SP2 may be disposed between the first wire BL and the second wire WL. The etch stop spacer SP3 may be disposed between the first wire BL and the second spacer SP2. The first spacer SP1 and the second spacer SP2 may each include a dielectric material. The first spacer SP1 and the second spacer SP2 may each include silicon oxide, silicon nitride, or a combination thereof. The first spacer SP1 and the second spacer SP2 may each include silicon nitride. The etch stop spacer SP3 may include a material different from the first spacer SP1 and the second spacer SP2. The etch stop spacer SP3 may have an etch selectivity with respect to the first spacer SP1 and the second spacer SP2. The etch stop spacer SP3 may be a material selectively grown from the second spacer SP2. The etch stop spacer SP3 may include silicon oxycarbide (SiOC). The silicon oxycarbide may be selectively grown from the surface of the silicon nitride.

[0060] The first spacer SP1 may surround a first portion of the nanosheet HL, the second wire WL may surround a second portion of the nanosheet HL, and the second spacer SP2 may surround a third portion of the nanosheet HL. The first portion, the second portion, and the third portion of the nanosheet HL may be defined in the narrow sheet NS.

[0061] The first contact node BLC may have a pyramid shape, and the ohmic contact layer BLO and the first wire BL may each have a pyramid shape covering the first contact node BLC. For example, the first contact node BLC, the ohmic contact layer BLO, and the first wire BL may each be a quadrangular pyramid shape. The first contact node BLC may be a phosphorus-doped silicon epitaxial layer, and the phosphorus-doped silicon epitaxial layer may be grown to have a pyramid shape. The contact resistance may be improved by controlling the size of the first contact node BLC.

[0062] Figure 2A is a schematic perspective view showing a semiconductor device 100V according to an embodiment of the present disclosure. Figure 2B is a showing Figure 2A a partial perspective view of the second layer L2 shown in Figure 2C is a showing Figure 2B a partial perspective view of the second wire WL shown in Figure 2D is a showing Figure 2B a partial perspective view of the first spacer SP1 shown in Figure 2E is a showing Figure 2B a partial perspective view of the second spacer SP2 and the etch stop spacer SP3 shown in

[0063] Reference Figures 2A to 2E, the semiconductor device 100V may include a three-dimensional array of memory cells MC. The detailed description of the memory cell MC is provided above with reference to Figure 1A and Figure 1B A detailed description of the memory cell MC is provided.

[0064] The semiconductor device 100V may include memory cells MC arranged horizontally as HA and vertically as VA. The memory cells MC in each horizontal arrangement HA may be horizontally spaced apart in the third direction D3. The memory cells MC in each vertical arrangement VA may be vertically stacked in the first direction D1. The memory cells MC in the horizontal arrangement HA may be vertically stacked in the first direction D1. The stacking of the horizontal arrangement HA may include the stacking of the vertical arrangement VA. The memory cells MC in each horizontal arrangement HA may be coupled to different first wires BL and share a second wire WL. The memory cells MC in each vertical arrangement VA may share different second wires WL and be coupled to one first wire BL. The first wire BL may include a body portion MBL and a plurality of pyramid portions PBL. The body portion MBL may refer to the portion where the pyramid portions PBL are interconnected.

[0065] Each vertical arrangement VA may be composed of a plurality of layers L1, L2, and L3. For example, the vertical arrangement VA of the semiconductor device 100V may have a first layer L1, a second layer L2, and a third layer L3 stacked vertically in sequence.

[0066] Each memory cell MC may include a first wire BL having a pyramid shape, a nanosheet HL, and a data storage element CAP. The nanosheet HL may include a first doped region SR, a channel CH, and a second doped region DR. A first contact node BLC and an ohmic contact layer BLO may be formed between the first doped region SR of the nanosheet HL and the first wire BL. A second contact node SNC may be formed between the second doped region DR of the nanosheet HL and the data storage element CAP. The nanosheet HL may be surrounded by a nanosheet dielectric layer GD. The second wire WL may extend in the third direction D3 while surrounding the channel CH of the nanosheet HL on the nanosheet dielectric layer GD. The memory cell MC may further include a first spacer SP1, a second spacer SP2, and an etch stop spacer SP3.

[0067] The first spacer SP1 may surround a first portion of the nanosheet HL in the horizontal arrangement HA, the second wire WL may surround a second portion of the nanosheet HL in the horizontal arrangement HA, the second spacer SP2 may surround a third portion of the nanosheet HL in the horizontal arrangement HA. The etch stop spacer SP3 may surround a fourth portion of the nanosheet HL in the horizontal arrangement HA.

[0068] More specifically, the first spacer SP1, the second spacer SP2, and the etch stop spacer SP3 may extend in the third direction D3 while surrounding the nanosheet HL in the horizontal arrangement HA. Specifically, the first spacer SP1 may extend in the third direction D3 while surrounding the second doped region DR in the horizontal arrangement HA. The second spacer SP2 and the etch stop spacer SP3 may extend in the third direction D3 while surrounding the first doped region SR in the horizontal arrangement HA. The second wire WL may extend in the third direction D3 while surrounding the channel CH of the nanosheet HL in the horizontal arrangement HA. In this way, the second wire WL, the first spacer SP1, the second spacer SP2, and the etch stop spacer SP3 may surround the nanosheet HL disposed on the same horizontal plane.

[0069] The semiconductor device 100V may further include a support BLS, and the support BLS may include a support recess for the first wire BL arranged horizontally. The first wire BL may be disposed in the support recess. The support BLS may contact the etch stop spacer SP3. The first wire BL may be supported by the support BLS. The support BLS may extend vertically in the first direction D1. The support BLS may include a dielectric material. The first wire BL may be formed to be self-aligned with the support recess of the support BLS. The support BLS may include a low-k material, silicon carbon oxide, silicon nitride, air gap, or a combination thereof.

[0070] Figure 3A is a schematic perspective view showing a semiconductor device 100 according to an embodiment of the present disclosure. Figure 3B is a schematic plan view showing a semiconductor device 100 according to an embodiment of the present disclosure. Figure 4A is along Figure 3B a schematic cross-sectional view of the semiconductor device 100 taken along the line A-A' shown. Figure 4B is along Figure 3B a schematic cross-sectional view of the semiconductor device 100 taken along the line B-B' shown. Figure 4C is along Figure 3B a schematic cross-sectional view of the semiconductor device 100 taken along the line A1-A1' shown. The above is with reference to Figures 1A to 2E provides a detailed description of the following overlapping components.

[0071] With reference to Figures 3A to 4C , the semiconductor device 100 may include a memory cell array MCA. The memory cell array MCA may include a three-dimensional array of memory cells MC. Each memory cell MC may include a first wire BL, a switching element TR, and a data storage element CAP, and the switching element TR may include a second wire WL, a nanosheet dielectric layer GD, and a nanosheet HL.

[0072] The memory cell array MCA may include a first sub - cell array MCA1 and a second sub - cell array MCA2. The first sub - cell array MCA1 and the second sub - cell array MCA2 may each include a three - dimensional array of memory cells MC. The memory cells MC in the first sub - cell array MCA1 may share a first vertical wire BLA, and the memory cells MC in the second sub - cell array MCA2 may share a second vertical wire BLB. The first vertical wire BLA and the second vertical wire BLB may each have a pyramid shape. The bottom of the first vertical wire BLA and the bottom of the second vertical wire BLB may be electrically isolated from each other.

[0073] The first sub - cell array MCA1 may include memory cells MC arranged horizontally and vertically. Each memory cell MC of the first sub - cell array MCA1 may include a first vertical wire BLA, a switching element TR, and a data storage element CAP. The switching element TR may include a second wire WL and a nanosheet HL. The switching element TR of the memory cell MC may be a nanosheet transistor. The first sub - cell array MCA1 may include nanosheet transistors arranged horizontally and vertically. The first sub - cell array MCA1 may include a horizontally arranged first vertical wire BLA. The first sub - cell array MCA1 may include second wires WL arranged horizontally and vertically. The first sub - cell array MCA1 may include data storage elements CAP arranged horizontally and vertically.

[0074] The second sub - cell array MCA2 may include memory cells MC arranged horizontally and vertically. Each memory cell MC of the second sub - cell array MCA2 may include a second vertical wire BLB, a switching element TR, and a data storage element CAP. The switching element TR may include a second wire WL and a nanosheet HL. The switching element TR of the memory cell MC may be a nanosheet transistor. The second sub - cell array MCA2 may include nanosheet transistors arranged horizontally and vertically. The second sub - cell array MCA2 may include a horizontally arranged second vertical wire BLB. The second sub - cell array MCA2 may include second wires WL arranged horizontally and vertically. The second sub - cell array MCA2 may include data storage elements CAP arranged horizontally and vertically.

[0075] The first wire BL may extend vertically in a first direction D1, the nanosheet HL may extend in a second direction D2, and the second wire WL may extend horizontally in a third direction D3.

[0076] The first inter-cell dielectric layer IL1 may be disposed between data storage elements CAP that are adjacent to each other in a third direction D3. The second inter-cell dielectric layer IL2 may be disposed between second wires WL that are vertically stacked in a first direction D1. The third inter-cell dielectric layer IL3 may be disposed between first electrodes SN of data storage elements CAP that are vertically stacked in a first direction D1. The first to third inter-cell dielectric layers IL1, IL2, and IL3 may each include silicon oxide, silicon carbon oxide (SiCO), silicon nitride, or a combination thereof. The first inter-cell dielectric layer IL1 may be referred to as a "device isolation layer".

[0077] Each memory cell MC may further include a first contact node BLC and a second contact node SNC. The first contact node BLC may be disposed between a first vertical wire (BLA) and a nanosheet HL and between a second vertical wire (BLB) and the nanosheet HL. The first contact node BLC may include a metal-based material or a semiconductor material. For example, the first contact node BLC may include titanium, titanium nitride, tungsten, or a combination thereof. In addition, the first contact node BLC may include doped polysilicon, and a first doped region SR may include impurities diffused from the first contact node BLC. The second contact node SNC may be disposed between the nanosheet HL and the first electrode SN. The second contact node SNC may include a metal-based material or a semiconductor material. For example, the second contact node SNC may include titanium, titanium nitride, tungsten, or a combination thereof. In addition, the second contact node SNC may include doped polysilicon, and a second doped region DR may include impurities diffused from the second contact node SNC. The height of the first contact node BLC in the first direction D1 may be less than the height of the second contact node SNC in the first direction D1. The height of the first contact node BLC in the first direction D1 may be greater than the height of the channel CH in the first direction D1. The first contact node BLC and the second contact node SNC may each include phosphorus-doped polysilicon or arsenic-doped polysilicon.

[0078] Each memory cell MC may further include an ohmic contact layer BLO located between the first contact node BLC and the first wire BL. The ohmic contact layer BLO may include a metal silicide, such as titanium silicide or molybdenum silicide.

[0079] The first contact node BLC can be selectively grown from the nanosheet HL. The first contact node BLC can be formed by selective epitaxial growth (SEG). For example, the first contact node BLC can be a silicon epitaxial layer formed by selective epitaxial growth (SEG). The first contact node BLC can be a doped silicon epitaxial layer. The second contact node SNC can be selectively grown from the nanosheet HL. The second contact node SNC can be formed by selective epitaxial growth (SEG). For example, the second contact node SNC can be a silicon epitaxial layer formed by selective epitaxial growth (SEG). The second contact node SNC can be a doped silicon epitaxial layer. The first contact node BLC can be a phosphorus-doped silicon epitaxial layer.

[0080] Each memory cell MC can further include a first spacer SP1, a second spacer SP2, and an etch stop spacer SP3. The first spacer SP1 can be disposed between the second wire WL and the second doped region DR. The second spacer SP2 can be disposed between the first wire BL and the second wire WL. The etch stop spacer SP3 can be disposed between the first wire BL and the second spacer SP2. The first spacer SP1 and the second spacer SP2 can each include a dielectric material. The first spacer SP1 and the second spacer SP2 can each include silicon oxide, silicon nitride, or a combination thereof. The first spacer SP1 and the second spacer SP2 can each include silicon nitride. The etch stop spacer SP3 can include a material different from the first spacer SP1 and the second spacer SP2. The etch stop spacer SP3 can have an etch selectivity with respect to the first spacer SP1 and the second spacer SP2. The etch stop spacer SP3 can be a material selectively grown from the second spacer SP2. The etch stop spacer SP3 can include silicon oxycarbide (SiOC). The silicon oxycarbide can be selectively grown from the surface of the silicon nitride.

[0081] The first spacer SP1 can surround a first portion of the nanosheet HL, the second wire WL can surround a second portion of the nanosheet HL, and the second spacer SP2 can surround a third portion of the nanosheet HL. The first portion, the second portion, and the third portion of the nanosheet HL can be defined in the narrow sheet NS.

[0082] The first contact node BLC can have a pyramid shape, and the ohmic contact layer BLO and the first wire BL can each have a pyramid shape covering the first contact node BLC. The first contact node BLC can be a phosphorus-doped silicon epitaxial layer, and the phosphorus-doped silicon epitaxial layer can be grown to have a pyramid shape. The contact resistance can be improved by controlling the size of the first contact node BLC.

[0083] The memory cell array MCA may include a plurality of second wires WL vertically stacked along a first direction D1. The memory cell array MCA may include a plurality of nanosheets HL vertically stacked along the first direction D1. The memory cell array MCA may include a plurality of data storage elements CAP vertically stacked along the first direction D1. The memory cell array MCA may include a plurality of first wires BLA and BLB spaced apart in a third direction D3. The memory cell array MCA may include dummy second wires WLU disposed at a level higher than the uppermost second wire WL and a dummy second wire WLL disposed at a level lower than the lowermost second wire WL. The dummy second wires WLU and WLL may each have a linear shape extending horizontally.

[0084] The memory cell array MCA may include a stack of a plurality of hard mask layers HM1 and HM2 disposed at a level higher than the uppermost second wire WL.

[0085] The lower structure LS and the barrier layer LSL may be disposed below the memory cell array MCA. The barrier layer LSL may prevent electrical contact between the first vertical wire BLA and the second vertical wire BLB and the lower structure LS. The barrier layer LSL may prevent electrical contact between the data storage element CAP and the lower structure LS. The barrier layer LSL may include a dielectric material. The lower structure LS may be a material suitable for semiconductor processing. The lower structure LS may include one or more of a conductive material, a dielectric material, and a semiconductor material. The lower structure LS may include silicon, single-crystalline silicon, polycrystalline silicon, amorphous silicon, silicon germanium, single-crystalline silicon germanium, polycrystalline silicon germanium, carbon-doped silicon, a combination thereof, or multiple layers thereof. The lower structure LS may further include another semiconductor material such as germanium. The lower structure LS may further include a III-V semiconductor substrate, such as a compound semiconductor substrate such as GaAs.

[0086] The inter-array dielectric layer BLF may be disposed between the first vertical wire BLA and the second vertical wire BLB. The inter-array dielectric layer BLF may include a dielectric material. For example, the inter-array dielectric layer BLF may include silicon oxide in which air gaps are embedded.

[0087] The first vertical wire BLA and the second vertical wire BLB may be formed to be self-aligned with the support BLS. The first vertical wires BLA disposed adjacent to each other in the third direction D3 may be isolated from each other by the support BLS. The second vertical wires BLB disposed adjacent to each other in the third direction D3 may be isolated from each other by the support BLS. The first vertical wire BLA and the second vertical wire BLB disposed adjacent to each other in the second direction D2 may be isolated from each other by the inter-array dielectric layer BLF.

[0088] The nanosheets HL of the switching element TR horizontally arranged along the third direction D3 may share a second wire WL. The nanosheets HL of the switching element TR horizontally arranged in the third direction D3 may be coupled to different first wires BL. The switching elements SR stacked in the first direction D1 may share a first wire BL, and the switching elements TR horizontally arranged in the third direction D3 may share a second wire WL.

[0089] The second electrode PN of the data storage element CAP may be coupled to the common plate PL.

[0090] Return reference Figure 4B , the memory cell array MCA may include a second wire WL arranged vertically and a second inter-cell dielectric layer IL2 arranged vertically. Each second inter-cell dielectric layer IL2 may be disposed between the second wires WL. The memory cell array MCA may include dummy second wires WLU at a level higher than the uppermost second wire WL and dummy second wires WLL at a level lower than the lowermost second wire WL, respectively. The dummy second wires WLU and WLL may each have a linear shape extending horizontally.

[0091] The nanosheet dielectric layer GD may surround the nanosheet HL, and the second wire WL may surround the nanosheet HL on the nanosheet dielectric layer GD.

[0092] The semiconductor device 100 may further include a support BLS, and the support BLS may include support recesses for a first vertical wire BLA and a second vertical wire BLB arranged horizontally. The first vertical wire BLA and the second vertical wire BLB may be disposed in the support recesses. The support BLS may contact the etch stop spacer SP3. The first vertical wire BLA and the second vertical wire BLB may be supported by the support BLS. The support BLS may extend vertically in the first direction D1. The support BLS may include a dielectric material. The first vertical wire BLA and the second vertical wire BLB may be formed to be self-aligned with the support recesses of the support BLS. The support BLS may include a low-k material, silicon carbon oxide, silicon nitride, an air gap, or a combination thereof.

[0093] According to Figures 1A to 4C, the semiconductor device 100 may include horizontally arranged switching elements TR, each switching element TR including a nanosheet HL and a second wire WL surrounding the nanosheet HL. Each first vertical wire BLA has a pyramid shape and is coupled to a first edge of the horizontally arranged nanosheet HL. A data storage element CAP is coupled to a second edge of the horizontally arranged nanosheet HL. The support BLS includes a support recess filled with the first vertical wire BLA. A first spacer SP1 is disposed between the data storage element CAP and the second wire WL and surrounds the nanosheet HL. A second spacer SP2 is disposed between the first vertical wire BLA and the second wire WL and surrounds the nanosheet HL. An etch stop spacer SP3 is disposed between the second spacer SP2 and the first vertical wire BLA. The first vertical wire BLA may be formed to be self-aligned in the support recess of the support BLS, and the etch stop spacer SP3 may have an etch selectivity with respect to the first spacer SP1 and the second spacer SP2.

[0094] According to Figures 1A to 4C , the semiconductor device 100 may include horizontally arranged switching elements TR, each switching element TR including a nanosheet HL and a second wire WL surrounding the nanosheet HL. Each second vertical wire BLB has a pyramid shape and is coupled to a first edge of the horizontally arranged nanosheet HL. A data storage element CAP is coupled to a second edge of the horizontally arranged nanosheet HL. The support BLS includes a support recess filled with the second vertical wire BLB. A first spacer SP1 is disposed between the data storage element CAP and the second wire WL and surrounds the nanosheet HL. A second spacer SP2 is disposed between the second vertical wire BLB and the second wire WL and surrounds the nanosheet HL. An etch stop spacer SP3 is disposed between the second spacer SP2 and the second vertical wire BLB. The second vertical wire BLB may be formed to be self-aligned in the support recess of the support BLS, and the etch stop spacer SP3 may have an etch selectivity with respect to the first spacer SP1 and the second spacer SP2.

[0095] According to Figures 1A to 4C, the semiconductor device 100 may include a first sub-unit array MCA1, a second sub-unit array MCA2, an inter-array dielectric layer BLF, and a support. The first sub-unit array MCA1 includes a first vertical wire BLA arranged horizontally, the second sub-unit array MCA2 includes a second vertical wire BLB arranged horizontally, the inter-array dielectric layer BLF is between the first sub-unit array MCA1 and the second sub-unit array MCA2, and the support BLS includes a support recess filled with the first vertical wire BLA arranged horizontally and the second vertical wire BLB arranged horizontally, wherein each first vertical wire BLA has a pyramid shape and each second vertical wire BLB has a pyramid shape. The first sub-unit array MCA1 and the second sub-unit array MCA2 may each include a three-dimensional array of memory cells MC, and each memory cell MC may include a switching element TR arranged horizontally, and each switching element TR includes a nanosheet HL and a second wire WL surrounding the nanosheet HL. The nanosheet HL may include a narrow sheet NS and a wide sheet WS. Each memory cell MC may further include a first contact node BLC, an ohmic contact layer BLO, a second contact node SNC, and a data storage element CAP.

[0096] Figures 5A to 34B Views of a semiconductor device formed by a method of manufacturing a semiconductor device according to an embodiment of the present disclosure are shown.

[0097] Figure 5A It is a plan view showing the structure of a horizontal plane of a second mold layer to describe a method of forming a mold stack SB. Figure 5B is along Figure 5A a cross-sectional view of the structure taken along line A-A' shown in Figure 5C is along Figure 5A a cross-sectional view of the structure taken along line A1-A1' shown in

[0098] Referring to Figures 5A to 5C , a barrier layer 11A may be formed on the substrate 11, and a mold stack SB may be formed on the barrier layer 11A.

[0099] The substrate 11 may be a material suitable for semiconductor processing. The substrate 11 may include one or more of a conductive material, a dielectric material, and a semiconductor material. The substrate 11 may include silicon, single-crystalline silicon, polycrystalline silicon, amorphous silicon, silicon germanium, single-crystalline silicon germanium, polycrystalline silicon germanium, carbon-doped silicon, a combination thereof, or a multi-layer thereof. The substrate 11 may further include another semiconductor material such as germanium. The substrate 11 may further include a III-V group semiconductor substrate, for example, a compound semiconductor substrate such as GaAs.

[0100] The barrier layer 11A may include a dielectric material. The barrier layer 11A may include silicon oxide, silicon carbon oxide, or a combination thereof. The mold stack SB may include an alternating stack of a first mold layer 12 and a second mold layer 13.

[0101] The first mold layer 12 can be alternately stacked with the second mold layer 13. The first mold layer 12 and the second mold layer 13 can be epitaxially grown multiple times to form a mold stack SB. The first mold layer 12 can be disposed on top of the mold stack SB.

[0102] The first mold layer 12 and the second mold layer 13 can be different semiconductor materials. The first mold layer 12 can include silicon germanium or single-crystalline silicon germanium. The second mold layer 13 can include single-crystalline silicon. The first mold layer 12 and the second mold layer 13 can be formed by an epitaxial growth process. During the epitaxial growth process, the lowermost first mold layer 12 can be used as a seed layer. Each first mold layer 12 can be thinner than each second mold layer 13. The first mold layer 12 can include a first epitaxial growth layer, and the second mold layer 13 can include a second epitaxial growth layer.

[0103] In one embodiment, multiple single-crystalline silicon germanium layers can be alternately stacked with multiple single-crystalline silicon layers in the mold stack SB. For example, the first mold layer 12 can be a single-crystalline silicon germanium layer, and the second mold layer 13 can be a single-crystalline silicon layer. The stacking of the single-crystalline silicon germanium layer and the single-crystalline silicon layer (SiGe / Si stack) can be stacked multiple times. The first mold layer 12 can be referred to as a "sacrificial layer", and the second mold layer 13 can be referred to as a "nanosheet target layer" or a "recess target layer".

[0104] The mold stack SB can be referred to as a "vertical stack". The mold stack SB can be formed by alternately stacking multiple sacrificial layers and multiple nanosheet target layers. The sacrificial layer can be a single-crystalline silicon germanium layer, and the nanosheet target layer can be a single-crystalline silicon layer.

[0105] The thickness ratio of the first mold layer 12 and the second mold layer 13 in the mold stack SB can be variously modified. For example, the thickness of each first mold layer 12 can be about 5 to 20 nm, and the thickness of each second mold layer 13 can be about 50 to 80 nm. The number of the first mold layer 12 and the number of the second mold layer 13 in the mold stack SB can be variously modified. In some embodiments, a triple stack including the first mold layer 12, the second mold layer 13, and the first mold layer 12 can be defined at the lowermost and uppermost portions of the mold stack SB. The thickness of the second mold layer 13 in the triple stack can be less than the thickness of the second mold layer 13 in the mold stack SB.

[0106] The first hard mask layer 14 can be formed on the mold stack SB. The first hard mask layer 14 can include a dielectric material such as an oxide-based material, a nitride-based material, a carbon-based material, or a combination thereof. For example, the first hard mask layer 14 can include SiO 2 , Si 3 N 4 , amorphous carbon, or a combination thereof.

[0107] Subsequently, the first hard mask layer 14 can be used as a stopper to etch some parts of the mold stack SB, and a plurality of sacrificial isolation openings 15 can be formed. The sacrificial isolation openings 15 can be initial openings for cell isolation. From a top view perspective, the cross-sections of the sacrificial isolation openings 15 can each have a rectangular shape. In some embodiments, the cross-sections of the sacrificial isolation openings 15 can each have a circular or elliptical shape. In some embodiments, the sacrificial isolation openings 15 can be referred to as "sacrificial isolation trenches". The sacrificial isolation openings 15 can extend perpendicularly along a first direction D1 and longitudinally along a second direction D2. The sacrificial isolation openings 15 can be arranged at a predetermined interval along a third direction D3. The etching process for forming the sacrificial isolation openings 15 can stop at the barrier layer 11A.

[0108] Figure 6A is a plan view showing the structure of the horizontal plane of the second mold layer to describe a method for forming the sacrificial linear openings 18 and 19. Figure 6B is along Figure 6A a cross-sectional view of the structure taken along the line A-A' shown. Figure 6C is along Figure 6A a cross-sectional view of the structure taken along the line A1-A1' shown.

[0109] Referring to Figures 6A to 6C , a sacrificial isolation layer 16 can be formed to fill the sacrificial isolation openings 15. The sacrificial isolation layer 16 can include the same material. The sacrificial isolation layer 16 can be formed of a dielectric material. The sacrificial isolation layer 16 can have an etching selectivity with respect to the mold stack SB. For example, each sacrificial isolation layer 16 can include silicon oxide, silicon nitride, silicon carbon oxide, silicon carbonitride, or a combination thereof. Forming the sacrificial isolation layer 16 can include forming a sacrificial isolation material on the mold stack SB to fill the sacrificial isolation openings 15 and planarizing the sacrificial isolation material, thereby exposing the surface of the first hard mask layer 14.

[0110] The sacrificial isolation layer 16 can extend perpendicularly along the first direction D1 and longitudinally along the second direction D2. The sacrificial isolation layer 16 can be arranged at a predetermined interval along the third direction D3. Each sacrificial isolation layer 16 can include a stack of a first sacrificial sub-spacer layer and a first sacrificial gap filling layer. The first sacrificial sub-spacer layer can be silicon nitride, and the first sacrificial gap filling layer can be silicon oxide. The sacrificial isolation layer 16 can penetrate the mold stack SB along the first direction D1.

[0111] Subsequently, a second hard mask layer 17 can be formed on the mold stack SB and the sacrificial isolation layer 16. The second hard mask layer 17 can include silicon nitride. The second hard mask layer 17 can be formed by etching a second hard mask material using a mask layer such as photoresist. The second hard mask layer 17 can have a plurality of linear openings defined therein.

[0112] The second hard mask layer 17 can be used as an etch stopper to etch some portions of the mold stack SB. Accordingly, a plurality of sacrificial linear openings 18 and 19 can be formed between the sacrificial isolation layers 16. The sacrificial linear openings can include a first sacrificial linear opening 18 and a second sacrificial linear opening 19. From a top view perspective, the first sacrificial linear opening 18 and the second sacrificial linear opening 19 can be linear openings extending along a third direction D3. The first sacrificial linear opening 18 and the second sacrificial linear opening 19 can extend vertically in a first direction D1. The sacrificial isolation layers 16 can be disposed between the first sacrificial linear opening 18 and the second sacrificial linear opening 19 along a second direction D2. From a top view perspective, the cross-sections of the first sacrificial linear opening 18 and the second sacrificial linear opening 19 can each have a rectangular shape. In some embodiments, the cross-sections of the first sacrificial linear opening 18 and the second sacrificial linear opening 19 can each have a circular shape or an oval shape. The widths of the first sacrificial linear opening 18 and the second sacrificial linear opening 19 in the second direction D2 can be less than the widths in the third direction D3. The first sacrificial linear opening 18 and the second sacrificial linear opening 19 can be referred to as "sacrificial linear trenches". The sacrificial isolation layers 16 can not contact the first sacrificial linear opening 18 and the second sacrificial linear opening 19.

[0113] Figure 7A is a plan view showing the structure of a horizontal plane of a second mold layer to describe a method of forming linear sacrificial layers 18L and 19L, Figure 7B is along Figure 7A the cross-sectional view of the structure taken along the line A-A' shown in

[0114] Referring to Figure 7A and Figure 7B, linear sacrificial layers 18L and 19L can be formed to fill the first linear sacrificial opening 18 and the second linear sacrificial opening 19. The linear sacrificial layers can include a first linear sacrificial layer 18L and a second linear sacrificial layer 19L. From a top view perspective, the first linear sacrificial layer 18L and the second linear sacrificial layer 19L can have a linear shape extending along the third direction D3. The first linear sacrificial layer 18L and the second linear sacrificial layer 19L can extend vertically in the first direction D1. The sacrificial isolation layer 16 can be disposed between the first linear sacrificial layer 18L and the second linear sacrificial layer 19L along the second direction D2. From a top view perspective, the cross-sections of the first linear sacrificial layer 18L and the second linear sacrificial layer 19L can each have a rectangular shape. In some embodiments, the cross-sections of the first linear sacrificial layer 18L and the second linear sacrificial layer 19L can each have a circular shape or an oval shape. The first linear sacrificial layer 18L and the second linear sacrificial layer 19L can include the same material. The first linear sacrificial layer 18L and the second linear sacrificial layer 19L can be formed of a dielectric material. For example, the first linear sacrificial layer 18L and the second linear sacrificial layer 19L can each include silicon oxide, silicon nitride, silicon carbon oxide, silicon carbon nitride, or a combination thereof. The sacrificial isolation layer 16 can be not in contact with the first linear sacrificial layer 18L and the second linear sacrificial layer 19L.

[0115] Figure 8A is a plan view showing the structure of the horizontal plane of the second mold layer to describe the depression of the second mold layer 12. Figure 8B is along Figure 8A the cross-sectional view of the structure taken along the line A-A' shown. Figure 8C is along Figure 8A the cross-sectional view of the structure taken along the line A1-A1' shown.

[0116] Referring to Figures 8A to 8C , in the first linear sacrificial layer 18L and the second linear sacrificial layer 19L, the first linear sacrificial layer 18L can be selectively removed. The second hard mask layer 17 can be used as an etch stopper to remove the first linear sacrificial layer 18L. Thus, the first linear opening 20 can be formed. From a top view perspective, the first linear opening 20 can be horizontally spaced apart from the second linear sacrificial layer 19L in the second direction D2.

[0117] The etching process for forming the first linear opening 20 can stop at the barrier layer 11A.

[0118] Subsequently, the first mold layer 12 and the second mold layer 13 can be selectively depressed through the first linear opening 20.

[0119] The difference in etching selectivity between the first mold layer 12 and the second mold layer 13 can be used to selectively recess the first mold layer 12. The first mold layer 12 can be removed using a wet etching process or a dry etching process. For example, when the first mold layer 12 includes a silicon germanium layer and the second mold layer 13 includes a single crystal silicon layer, an etchant or etching gas selective to the single crystal silicon layer can be used to etch the silicon germanium layer. The first mold layer having its original thickness can be retained, as shown by the reference numeral "12A".

[0120] Subsequently, a part (first part) of each second mold layer 13 can be recessed to form a narrow sheet 13N. A wet etching process or a dry etching process can be used to recess the second mold layer 13. The original main body part 13A and the narrow sheet 13N can be formed by the partial recessing of each second mold layer 13. The original main body part 13A can maintain its original thickness T1, and the narrow sheet 13N can have a thickness T2 less than the original thickness T1. The horizontal length of the original main body part 13A in the second direction D2 can be equal to or different from the horizontal length of the narrow sheet 13N in the second direction D2. The combination of the original main body part 13A and the narrow sheet 13N can be referred to as a "preliminary active layer". The narrow sheet 13N can be referred to as a "flat sheet" or a "projecting narrow sheet".

[0121] The recessing process for forming the narrow sheet 13N can be referred to as a "thinning process" or a "trimming process" of the second mold layer 13. To form the narrow sheet 13N, the upper surface, lower surface, and side surfaces of the second mold layer 13 can be recessed. The narrow sheet 13N can be referred to as a "thin body active layer". The narrow sheet 13N can include a single crystal silicon layer. The recessing process for forming the narrow sheet 13N can use, for example, hot SC-1 (HSC1). HSC1 can include ammonium hydroxide (NH 4 OH), hydrogen peroxide (H 2 O 2 ) and water (H 2 O) mixed in a ratio of 1:4:20. Using HSC1, the second mold layer 13 can be selectively etched.

[0122] The narrow sheet 13N can be formed by the partial recessing process of the second mold layer 13 as described above. The inter-nanosheet recess 21 can be formed between the vertically arranged narrow sheets 13N. The upper surface and the lower surface of the narrow sheet 13N can each include a flat surface. The boundary part between the original main body part 13A and the narrow sheet 13N can be vertical or have a curvature. Each first mold layer 12A can be disposed between the vertically stacked original main body parts 13A. Horizontally arranged and vertically arranged narrow sheets 13N can be formed above the barrier layer 11A.

[0123] Figure 9A is a plan view showing the structure of the narrow sheet horizontal plane to describe a method of forming the opening 22 of the sacrificial isolation layer horizontal plane. Figure 9Bis a cross-sectional view of the structure taken along Figure 9A the line A-A' shown in

[0124] Referring to Figure 9A and 9B , the sacrificial isolation layer 16 can be selectively peeled off through the recesses 21 between the nanosheets. Accordingly, each sacrificial isolation layer horizontal plane opening 22 can be formed between the original body portions 13A in the third direction D3.

[0125] The side surface of the first mold layer 12A, the side surface of the original body portion 13A, and the side surface of the narrow sheet 13N can be exposed in the third direction D3 through the sacrificial isolation layer horizontal plane opening 22.

[0126] Figure 10A is a plan view showing the structure of the narrow sheet horizontal plane to describe a method of forming the first inter-unit dielectric layer 23, the first spacer layer 26A, and the second inter-unit dielectric layer 27. Figure 10B is a cross-sectional view of the structure taken along Figure 10A the line A-A' shown in Figure 10C is a cross-sectional view of the structure taken along Figure 10A the line A1-A1' shown in Figure 10D is a cross-sectional view of the structure taken along Figure 10A the line B-B' shown in

[0127] Referring to Figures 10A to 10D , the first inter-unit dielectric layer 23 can be formed in the sacrificial isolation layer horizontal plane opening 22. Each first inter-unit dielectric layer 23 can include a dielectric material. Each first inter-unit dielectric layer 23 can include silicon oxide, silicon nitride, silicon carbon oxide, or a combination thereof. Forming the first inter-unit dielectric layer 23 can include forming a dielectric material that fills the sacrificial isolation layer horizontal plane opening 22 and performing an etch-back process on the dielectric material.

[0128] The first inter-unit dielectric layer 23 can fill a part of the sacrificial isolation layer horizontal plane opening 22. The side surface of the first mold layer 12A and the side surface of the original body portion 13A can be covered by the first inter-unit dielectric layer 23 in the third direction D3. The first inter-unit dielectric layer 23 can expose the side surface of the narrow sheet 13N. The other parts of the sacrificial isolation layer horizontal plane opening 22, i.e., the non-gap filling parts, can expose the side surface of the narrow sheet 13N.

[0129] Subsequently, a nanosheet dielectric layer 25 can be formed on the exposed portion of the narrow sheet 13N. The nanosheet dielectric layer 25 can be referred to as a "gate dielectric layer".

[0130] The nanosheet dielectric layer 25 can be formed by oxidizing the surface of the narrow sheet 13N. In some embodiments, the nanosheet dielectric layer 25 can be formed by a deposition process and an oxidation process of silicon oxide. The nanosheet dielectric layer 25 can include silicon oxide, silicon nitride, metal oxide, metal oxide nitride, metal silicate, high-k material, ferroelectric material, antiferroelectric material, or a combination thereof. The nanosheet dielectric layer 25 can include SiO 2 、Si 3 N 4 、HfO 2 、Al 2 O 3 、ZrO 2 、AlON, HfON, HfSiO, HfSiON, or a combination thereof. The nanosheet dielectric layer 25 can be formed on all surfaces of the narrow sheet 13N.

[0131] The first spacer layer 26A can be formed on the nanosheet dielectric layer 25. The first spacer layer 26A can include silicon nitride. The first spacer layer 26A can surround and cover the narrow sheet 13N on the nanosheet dielectric layer 25. The first spacer layer 26A can be thicker than the nanosheet dielectric layer 25.

[0132] The second inter-unit dielectric layer 27 can be formed on the first spacer layer 26A. The second inter-unit dielectric layer 27 can include silicon oxide. A deposition and etch-back process of silicon oxide can be performed to form the second inter-unit dielectric layer 27. The second inter-unit dielectric layer 27 can be disposed in the nanosheet recess 21 on the first spacer layer 26A. The second inter-unit dielectric layer 27 can not be disposed in the first linear opening 20. A non-gap-fill space 27R can be defined on the side surface of the second inter-unit dielectric layer 27.

[0133] The nanosheet dielectric layer 25 and the first spacer layer 26A can also be formed on the surface of the barrier layer 11A.

[0134] As described above, the first spacer layer 26A can be disposed between the narrow sheets 13N along the third direction D3.

[0135] Figure 11A is a plan view showing the structure of the narrow sheet horizontal plane to describe the method of forming the first spacer 26. Figure 11B is along Figure 11A The cross-sectional view of the structure taken along the line A-A' shown. Figure 11C is along Figure 11A The cross-sectional view of the structure taken along the line A1-A1' shown. Figure 11D is along Figure 11A The cross-sectional view of the structure taken along the line B-B' shown.

[0136] Refer to Figures 11A to 11D, the first spacer layer 26A can be selectively recessed through the first linear opening 20. The remaining first spacer layer can become the first spacer 26.

[0137] When forming the first spacer 26, a first linear surrounding recess 28 surrounding the narrow fin 13N can be formed on the nanosheet dielectric layer 25. Each second inter-unit dielectric layer 27 can be disposed between the vertically disposed first linear surrounding recesses 28. An upper dummy horizontal recess 28U can be formed above the uppermost second inter-unit dielectric layer 27, and a lower dummy horizontal recess 28L can be formed below the lowermost second inter-unit dielectric layer 27L. The upper dummy horizontal recess 28U and the lower dummy horizontal recess 28L can each have a non-surrounding shape, i.e., a flat shape.

[0138] The first spacer 26 can surround a first portion of the narrow fin 13N on the nanosheet dielectric layer 25 on the same horizontal plane.

[0139] Figure 12A is a plan view showing the structure of the narrow fin horizontal plane to describe a method of forming the horizontal wire layer 29A. Figure 12B is along Figure 12A a cross-sectional view of the structure taken along the line A-A' shown. Figure 12C is along Figure 12A a cross-sectional view of the structure taken along the line A1-A1' shown. Figure 12D is along Figure 12A a cross-sectional view of the structure taken along the line B-B' shown.

[0140] Referring to Figures 12A to 12D , a horizontal wire layer 29A filling the linear surrounding recess 28 can be formed.

[0141] Figure 13A is a plan view showing the structure of the narrow fin horizontal plane to describe a method of forming the horizontal wire 29. Figure 13B is along Figure 17A a cross-sectional view of the structure taken along the line A-A' shown. Figure 13C is along Figure 13A a cross-sectional view of the structure taken along the line A1-A1' shown. Figure 13D is along Figure 13A a cross-sectional view of the structure taken along the line B-B' shown.

[0142] Referring to Figures 13A to 13D , a horizontal wire 29 filling the first linear surrounding recess 28 can be formed. The horizontal wire 29 can extend horizontally in the third direction D3.

[0143] Forming the horizontal wire 29 may include performing a horizontal etch-back process on the horizontal wire layer 29A. Each horizontal wire 29 may simultaneously surround the narrow fin 13N in the same horizontal plane. Each horizontal wire 29 may include a metal-based material, a semiconductor material, or a combination thereof. Each horizontal wire 29 may include molybdenum, molybdenum nitride, ruthenium, titanium nitride, tungsten, polysilicon, or a combination thereof. For example, each horizontal wire 29 may include a titanium nitride and tungsten (TiN / W) stack, where the titanium nitride and W are stacked in sequence. Each horizontal wire 29 may include an N-type work function material or a P-type work function material. The N-type work function material may have a low work function of about 4.5 eV or less, and the P-type work function material may have a high work function of about 4.5 eV or greater. Each second inter-unit dielectric layer 27 may be disposed between the plurality of horizontal wires 29 along the first direction D1. The horizontal wire 29 surrounding the narrow fin 13N may be referred to as a "gate-all-around (GAA) electrode". The narrow fin 13N may be referred to as a "nanosheet channel", "nanowire", or "nanowire channel".

[0144] The lower dummy horizontal electrode 29L may be formed on the barrier layer 11A. The upper dummy horizontal electrode 29U may be formed above the topmost horizontal wire 29. The dummy horizontal electrodes 29L and 29U may each have a non-surrounding shape.

[0145] The horizontal wire 29 may surround a second portion of the narrow fin 13N on the nanosheet dielectric layer 25 in the same horizontal plane.

[0146] After forming the horizontal wire 29, a second linear surrounding recess 29V may be defined to open a third portion of the narrow fin 13N. The second linear surrounding recess 29V may be a space for forming the second spacer and the etch stop spacer.

[0147] The second linear surrounding recess 29V may surround a third portion of the narrow fin 13N on the nanosheet dielectric layer 25 in the same horizontal plane.

[0148] Figure 14A is a plan view showing the structure of the narrow fin horizontal plane to describe a method of forming the second spacer 30 and the etch stop spacer 31. Figure 14B is along Figure 14A a cross-sectional view of the structure taken along the line A-A' shown. Figure 14C is along Figure 14A a cross-sectional view of the structure taken along the line B1-B1' shown.

[0149] Referring to Figures 14A to 14C , a plurality of spacer materials may be formed in the second linear surrounding recess 29V.

[0150] A second spacer 30 may be formed on one side of each horizontal wire 29. The second spacer 30 may include silicon oxide, silicon nitride, silicon carbon oxide, an embedded air gap, or a combination thereof. The second spacer 30 may contact one side of each horizontal wire 29 and cover an edge portion of the second inter-unit dielectric layer 27. The second spacer 30 may surround all surfaces of the narrow fin 13N on the nanosheet dielectric layer 25.

[0151] Subsequently, an etch stop spacer 31 may be formed on the second spacer 30. The etch stop spacer 31 may be selectively grown from the surface of the second spacer 30.

[0152] The etch stop spacer 31 may include a material different from that of the first spacer 26 and the second spacer 30. The etch stop spacer 31 may have an etch selectivity with respect to the first spacer 26 and the second spacer 30. The etch stop spacer 31 may be a material selectively grown from the second spacer 30. The etch stop spacer 31 may include silicon carbon oxide (SiOC). The silicon carbon oxide may be selectively grown from the surface of silicon nitride.

[0153] Figure 15A is a plan view showing the structure of the horizontal plane of the narrow fin to describe a method of forming the first sacrificial spacer layer 32A. Figure 15B is along Figure 15A a cross-sectional view of the structure taken along the line A-A' shown. Figure 15C is along Figure 15A a cross-sectional view of the structure taken along the line B-B' shown. Figure 15D is along Figure 15A a cross-sectional view of the structure taken along the line B1-B1' shown.

[0154] Referring to Figures 15A to 15D , the first sacrificial spacer layer 32A may be formed on the etch stop spacer layer 31. The first sacrificial spacer layer 32A may include polysilicon. The first sacrificial spacer layer 32A may surround the narrow fin 13N on the nanosheet dielectric layer 25 at the same horizontal plane.

[0155] Figure 16A is a plan view showing the structure of the horizontal plane of the narrow fin to describe a method of forming the first sacrificial spacer 32. Figure 16B is along Figure 16A a cross-sectional view of the structure taken along the line A-A' shown. Figure 16C is along Figure 16A a cross-sectional view of the structure taken along the line B-B' shown. Figure 16D is along Figure 16A a cross-sectional view of the structure taken along the line B1-B1' shown.

[0156] Referring to Figures 16A to 16D, the first sacrificial spacer layer 32A can be cut, and the first sacrificial spacer 32 can be formed on the same horizontal plane between the narrow fins 13N. The first sacrificial spacer 32 can be used to fix the bridging edges when forming subsequent sacrificial growth layers.

[0157] Figure 17A is a plan view showing the structure of the horizontal plane of the narrow fins to describe a method of forming the second sacrificial spacer 33. Figure 17B is along Figure 17A the cross-sectional view of the structure taken along the line A-A' shown. Figure 17C is along Figure 17A the cross-sectional view of the structure taken along the line B-B' shown. Figure 17D is along Figure 17A the cross-sectional view of the structure taken along the line B1-B1' shown.

[0158] Referring to Figures 17A to 17D , the second sacrificial spacer 33 can be formed on the first sacrificial spacer 32. The second sacrificial spacer 33 can expose a part of the first sacrificial spacer 32. The second sacrificial spacer 33 can contact the etch stop spacer 31.

[0159] Subsequently, the second sacrificial spacer 33 can be used as a barrier to remove the first sacrificial spacer 32. Thus, the inter-fin gap 32G can be formed on the same horizontal plane between the narrow fins 13N.

[0160] Figure 18A is a plan view showing the structure of the horizontal plane of the narrow fins to describe a method of exposing the edges of the narrow fins 13N. Figure 18B is along Figure 18A the cross-sectional view of the structure taken along the line A-A' shown. Figure 18C is along Figure 18A the cross-sectional view of the structure taken along the line B-B' shown.

[0161] Referring to Figures 18A to 18C , the second sacrificial spacer 33 can be used as a barrier to recess the nanosheet dielectric layer 25. Thus, the edges of the narrow fins 13N can be exposed, as shown by the reference numeral "34".

[0162] Figure 19A is a plan view showing the structure of the horizontal plane of the narrow fins to describe a method of exposing the edges of the narrow fins 13N. Figure 19B is along Figure 19A the cross-sectional view of the structure taken along the line A-A' shown. Figure 19C is along Figure 19A the cross-sectional view of the structure taken along the line B-B' shown. Figure 19D is along Figure 19A the cross-sectional view of the structure taken along the line B1-B1' shown.

[0163] Reference Figures 19A to 19D ,the second sacrificial spacer 33 can be selectively removed. Accordingly, the etch stop spacer 31 can be exposed, as indicated by reference numeral "35", and the edge of the narrow fin 13N and a portion of the nanosheet dielectric layer 25 can be exposed. The etch stop spacer 31 can be used as an etch stopper when removing the second sacrificial spacer 33.

[0164] Figure 20A is a plan view showing the structure of the narrow fin horizontal plane to describe a method of cutting the narrow fin 13N. Figure 20B is along Figure 20A a cross-sectional view of the structure taken along the line A-A' shown. Figure 20C is along Figure 20A a cross-sectional view of the structure taken along the line B-B' shown.

[0165] Reference Figures 20A to 20C ,the edge of the narrow fin 13N can be cut (see reference numeral "36"). The horizontal length of the narrow fin 13N in the third direction D3 can be reduced.

[0166] Figure 21A is a plan view showing the structure of the narrow fin horizontal plane to describe a method of partially recessing the nanosheet dielectric layer 25. Figure 21B is along Figure 20A a cross-sectional view of the structure taken along the line A-A' shown. Figure 21C is along Figure 21A a cross-sectional view of the structure taken along the line B-B' shown.

[0167] Reference Figures 21A to 21C ,a portion of the nanosheet dielectric layer 25 can be horizontally recessed. Accordingly, an edge portion of the narrow fin 13N, such as the protruding edge 13E of the narrow fin 13N (see reference numeral "37"), can be exposed. The narrow fins 13N can be vertically spaced apart from each other by a gap G.

[0168] Figure 22A is a plan view showing the structure of the narrow fin horizontal plane to describe a method of forming the sacrificial growth layer 38. Figure 22B is along Figure 22A a cross-sectional view of the structure taken along the line A-A' shown. Figure 22C is along Figure 22A a cross-sectional view of the structure taken along the line B-B' shown.

[0169] Reference Figures 22A to 22C, a sacrificial growth layer 38 can be formed on the protruding edge 13E of the narrow strip 13N. The sacrificial growth layer 38 can be formed by selective epitaxial growth (SEG). The sacrificial growth layer 38 can cover all surfaces of the protruding edge 13E of the narrow strip 13N. Each sacrificial growth layer 38 can have a pyramid shape. Each sacrificial growth layer 38 can include a silicon-germanium epitaxial layer. The sacrificial growth layer 38 can include a convex profile 38A, and a gap 38B can be formed between the vertically arranged sacrificial growth layers 38.

[0170] Figure 23A is a plan view showing the structure of the horizontal plane of the narrow strip to describe a method of forming the support 39. Figure 23B is along Figure 23A a cross-sectional view of the structure taken along the line A-A' shown. Figure 23C is along Figure 23A a cross-sectional view of the structure taken along the line B-B' shown.

[0171] Referring to Figures 23A to 23C , a deposition and etching process of a support material can be performed on the sacrificial growth layer 38. Thus, the support 39 for supporting the sacrificial growth layer 38 can be formed. The supports 39 arranged adjacent to each other can be spaced apart from each other in the second direction D2. Each support 39 can include a dielectric material. Each support 39 can include silicon nitride. The support 39 can have an overall structure for supporting the sacrificial growth layer 38. The support 39 can include a void filler 39A filled in the gap 38B formed between the sacrificial growth layers 38. The support 39 can expose the convex profile 38A of the sacrificial growth layer 38.

[0172] Figure 24A is a plan view showing the structure of the horizontal plane of the narrow strip to describe a method of forming the initial support recess 39R. Figure 24B is along Figure 24A a cross-sectional view of the structure taken along the line A-A' shown. Figure 24C is along Figure 24A a cross-sectional view of the structure taken along the line B-B' shown.

[0173] Referring to Figures 24A to 24C , the sacrificial growth layer 38 can be removed to form the initial support recess 39R. The initial support recess 39R can extend vertically in the first direction D1 and be spaced apart from each other in the second direction D2. The initial support recess 39R can expose the protruding edges 13E of the vertically arranged narrow strips 13N. The void filler 39A can be exposed through the initial support recess 39R.

[0174] Figure 25A is a plan view showing the structure of the horizontal plane of the narrow strip to describe a method of removing the void filler 39A. Figure 25B is along Figure 25ACross-sectional view of the structure taken along the line A-A' shown. Figure 25C is taken along Figure 25A Cross-sectional view of the structure taken along the line B-B' shown.

[0175] Referring to Figures 25A to 25C , the void filler 39A can be removed through the initial support recess 39R. The volume of the initial support recess 39R can expand while removing the void filler 39A. The expanded initial support recess can become the support recess 40.

[0176] The support recesses 40 can extend vertically in the first direction D1 and be spaced apart from each other in the second direction D2. The support recesses 40 can expose the protruding edges 13E of the vertically arranged narrow pieces 13N.

[0177] Figure 26A Is a plan view of the structure showing the horizontal plane of the narrow piece to describe a method for cutting the edge of the narrow piece 13N. Figure 26B is taken along Figure 26A Cross-sectional view of the structure taken along the line A-A' shown. Figure 26C is taken along Figure 26A Cross-sectional view of the structure taken along the line B-B' shown.

[0178] Referring to Figures 26A to 26C , the protruding edge 13E of the narrow piece 13N can be cut through the support recess 40. Therefore, the protruding edge 13E of the narrow piece 13N can be not arranged in the support recess 40.

[0179] The support recess 40 can have a structure in which pyramidal recesses are combined.

[0180] Figure 27A Is a plan view of the structure showing the horizontal plane of the narrow piece to describe a method for forming the first contact node 41. Figure 27B is a view showing along Figure 27A Cross-sectional view of the structure taken along the line A-A' shown in Figure 27C is taken along Figure 27A Cross-sectional view of the structure taken along the line B-B' shown.

[0181] Referring to Figures 27A to 27C, the first contact node 41 can be formed on one side surface of the narrow fin 13N. Forming the first contact node 41 can include selective epitaxial growth (SEG). For example, a semiconductor material can grow from the narrow fin 13N by selective epitaxial growth (SEG). Each first contact node 41 can include SEG Si. Since each narrow fin 13N includes single-crystalline silicon, a silicon layer can grow epitaxially along the crystal surface of the side surface of the narrow fin 13N. The first contact node 41 can be formed on the narrow fin 13N in the support recess 40. Each first contact node 41 can have a pyramid shape. The first contact nodes 41 can be spaced apart from each other.

[0182] Each first contact node 41 can include a dopant. When growing the silicon layer using selective epitaxial growth (SEG), the dopant can be doped in-situ. Therefore, each first contact node 41 can be a doped epitaxial layer. Each first contact node 41 can include an N-type dopant as the dopant. The N-type dopant can include phosphorus, arsenic, antimony, or a combination thereof. The first contact node 41 can include a phosphorus-doped silicon epitaxial layer formed by selective epitaxial growth (SEG), i.e., doped SEG-SiP.

[0183] Each first doping region 42 can be formed on one side of each narrow fin 13N. A heat treatment process can be performed to form the first doping region 42, so that the dopant can diffuse from the first contact node 41.

[0184] Figure 28A is a plan view showing the structure of the narrow fin horizontal plane to describe the method of forming the vertical wires 44A and 44B. Figure 28B is shown along Figure 28A the cross-sectional view of the structure taken along the line A-A' shown in Figure 28C is along Figure 28A the cross-sectional view of the structure taken along the line B-B' shown in

[0185] Referring to Figures 28A to 28C , an ohmic contact layer 43 can be formed on the first contact node 41. Each ohmic contact layer 43 can include a metal silicide. Forming the ohmic contact layer 43 can include depositing a metal base layer on the first contact node 41 and performing a heat treatment process on the silicidation reaction of the metal base layer and the first contact node 41. The ohmic contact layer 43 can have a pyramid shape surrounding the first contact node 41.

[0186] Subsequently, vertical wires 44A and 44B can be formed on the ohmic contact layer 43. The vertical wires can include a first vertical wire 44A and a second vertical wire 44B that are horizontally spaced apart from each other. The first vertical wire 44A and the second vertical wire 44B can be commonly coupled to the first contact node 41 through the ohmic contact layer 43. The first vertical wire 44A and the second vertical wire 44B can be commonly coupled to the narrow fin 13N disposed along the first direction D1. The first vertical wire 44A and the second vertical wire 44B can vertically extend in the first direction D1. The first vertical wire 44A and the second vertical wire 44B can each include a metal-based material. The first vertical wire 44A and the second vertical wire 44B can each include titanium nitride, tungsten, or a combination thereof.

[0187] A deposition and blanket etch process can be performed on the vertical wire material to form the first vertical wire 44A and the second vertical wire 44B.

[0188] The bottoms of the first vertical wire 44A and the second vertical wire 44B can contact the barrier layer 11A. The barrier layer 11A can prevent bridging between the substrate 11 and the first vertical wire 44A and the second vertical wire 44B. The bottoms of the first vertical wire 44A and the second vertical wire 44B can be discontinuous from each other. The first vertical wire 44A and the second vertical wire 44B can fill the support recess 40 while covering the ohmic contact layer 43.

[0189] The support 39 can surround the first vertical wire 44A and the second vertical wire 44B.

[0190] As described above, the support 39 can include the support recess 40. The first contact node 41, the ohmic contact layer 43, and the first vertical wire 44A and the second vertical wire 44B can fill the support recess 40. The pyramid-shaped first contact node 41 can be electrically coupled to the narrow fin 13N, and the ohmic contact layer 43 can surround the first contact node 41. The first vertical wire 44A and the second vertical wire 44B can include a combination of pyramid-shaped raised portions. The pyramid-shaped raised portions of the first vertical wire 44A and the second vertical wire 44B can surround the first contact node 41. The ohmic contact layer 43 can be disposed between the pyramid-shaped raised portions of the first vertical wire 44A and the second vertical wire 44B and the first contact node 41. The first vertical wire 44A disposed adjacent to each other in the third direction D3 can be spaced apart from each other by the support 39. The second vertical wire 44B disposed adjacent to each other in the third direction D3 can be spaced apart from each other by the support 39.

[0191] Figure 29A is a plan view showing the structure of the narrow fin horizontal plane to describe a method of forming the second linear opening 46. Figure 29B is along Figure 29ACross-sectional view of the structure taken along the line A-A' shown.

[0192] Referring to Figure 29A and Figure 29B , an inter-array dielectric layer 45 can be formed to fill the first linear opening 20 in the first vertical wire 44A and the second vertical wire 44B. The inter-array dielectric layer 45 can extend vertically in the first direction D1 and horizontally in the third direction D3. The first vertical wire 44A and the second vertical wire 44B disposed adjacent to each other in the second direction D2 can be isolated by the inter-array dielectric layer 45. The inter-array dielectric layer 45 can include a dielectric material. The inter-array dielectric layer 45 can include silicon oxide, silicon nitride, air gap, or a combination thereof.

[0193] Subsequently, the second linear sacrificial layer 19L can be removed. Thus, a second linear opening 46 can be formed.

[0194] After forming the second linear opening 46, the first mold layer 12A can be selectively recessed through the second linear opening 46. The difference in etching selectivity between the first mold layer 12A and the original body portion 13A can be used to selectively recess the first mold layer 12A. A wet etching process or a dry etching process can be used to remove the first mold layer 12A. For example, when the first mold layer 12A includes a silicon germanium layer and the original body portion 13A includes a single crystal silicon layer, an etchant or etching gas selective with respect to the single crystal silicon layer can be used to etch the silicon germanium layer.

[0195] Subsequently, the original body portion 13A can be recessed. A wet etching process or a dry etching process can be used to recess the original body portion 13A. The vertical thickness of the original body portion 13A can be reduced, as shown by the reference numeral "13S". Hereinafter, the original body portion with the reduced vertical thickness is referred to as the "recessed body portion 13S".

[0196] Each inter-body recess 47 can be formed between the vertically disposed recessed body portions 13S.

[0197] Figure 30A is a plan view showing the structure of the narrow sheet horizontal plane to describe the method of forming the nanosheet HL. Figure 30B is along Figure 30A Cross-sectional view of the structure taken along the line A-A' shown.

[0198] Referring to Figure 30A and 30B , a third inter-unit dielectric layer 48 can be formed to fill the inter-body recess 47. Each third inter-unit dielectric layer 48 can include silicon oxide.

[0199] After forming the third inter-unit dielectric layer 48, a storage opening 49 may be formed through a horizontal recess of the recessed body portion 13S. The storage opening 49 may be referred to as a "capacitor opening". The nano-sheet HL may be formed through the horizontal recess of the recessed body portion 13S. Each nano-sheet HL may include a narrow sheet 13N and a wide sheet 13W. The wide sheet 13W of the nano-sheet HL may refer to the remaining recessed body portion 13S after recessing. The average vertical height of the wide sheet 13W of the nano-sheet HL in the first direction D1 may be greater than the average vertical height of the narrow sheet 13N. The thickness of the wide sheet 13W of the nano-sheet HL may gradually increase in the second direction D2. The horizontal length of the wide sheet 13W in the second direction D2 may be less than the horizontal length of the narrow sheet 13N. The wide sheet 13W of the nano-sheet HL may have a fan shape. The wide sheet 13W may be referred to as a "fan-shaped sheet", and the narrow sheet 13N may be referred to as a "flat plate-shaped sheet".

[0200] To form the nano-sheets HL each including the wide sheet 13W, the recessed body portion 13S may be etched isotropically or anisotropically. One side of the wide sheet 13W, i.e., the side exposed by each storage opening 49, may have a flat shape. One side of the wide sheet 13W may have various shapes.

[0201] Each nano-sheet HL may include a first edge and a second edge. The first edge may refer to the portion electrically coupled to the first vertical wire 44A, the second vertical wire 44B, the first contact node 41, and the ohmic contact layer 43, and the second edge may refer to the portion exposed by each storage opening 49.

[0202] Each storage opening 49 may be disposed between the third inter-unit dielectric layers 48.

[0203] In some embodiments, the horizontal recess of the recessed body portion 13S for forming the wide sheet 13W may stop at the boundary region between the narrow sheet 13N and the wide sheet 13W.

[0204] Referring to Figures 5A to 30B , the narrow sheet 13N may be formed by recessing a first portion of the second mold layer 13, and the wide sheet 13W may be formed by recessing a second portion of the second mold layer 13. The wide sheet 13W may be horizontally continuous from the narrow sheet 13N.

[0205] Figure 31A is a plan view showing the structure of the nano-sheet horizontal plane to describe a method of forming the second contact node 50. Figure 31B is along Figure 31A The cross-sectional view of the structure taken along the line A-A' shown.

[0206] Referring to Figure 31A and Figure 31B , a pre-cleaning process may be performed on one side of each nano-sheet HL, i.e., on the surface of each wide sheet 13W.

[0207] Subsequently, the second contact node 50 can be formed on one side of the nanosheet HL, i.e., on the wide sheet 13W. Forming the second contact node 50 can include selective epitaxial growth (SEG). For example, semiconductor material can be grown from the side surface of the wide sheet 13W by selective epitaxial growth (SEG). Each second contact node 50 can include SEG Si. Since each wide sheet 13W includes single-crystalline silicon, the silicon layer can be epitaxially grown along the crystal surface of the side surface of the wide sheet 13W.

[0208] Each second contact node 50 can include a dopant. When the silicon layer is grown using selective epitaxial growth (SEG), the dopant can be doped in-situ. Therefore, each second contact node 50 can be a doped epitaxial layer. Each second contact node 50 can include an N-type dopant as the dopant. The N-type dopant can include phosphorus, arsenic, antimony, or a combination thereof. The second contact node 50 can include a phosphorus-doped silicon epitaxial layer formed by selective epitaxial growth (SEG), i.e., doped SEG SiP.

[0209] Since the second contact node 50 is formed using selective epitaxial growth (SEG), a void-free or seam-free second contact node 50 can be formed. Since the second contact node 50 is formed using selective epitaxial growth (SEG), the process of forming the second contact node 50 can be simplified.

[0210] Each second contact node 50 can be disposed between vertically stacked third inter-dielectric layers 48.

[0211] The second doped region 51 can be formed in the wide sheet 13W of the nanosheet HL. A heat treatment process can be performed to form the second doped region 51, so that the dopant can diffuse from the second contact node 50.

[0212] Each nanosheet HL can include a first doped region 42, a second doped region 51, and a channel 52. The channel 52 can be defined between the first doped region 42 and the second doped region 51. The first doped region 42 and the channel 52 can be formed in each narrow sheet 13N, and the second doped region 51 can be formed in each wide sheet 13W. A part of each second doped region 51 can extend into the narrow sheet 13N. One side of each second doped region 51 of the nanosheet HL can be coupled to the channel 52, and the other side of each second doped region 51 of the nanosheet HL can be coupled to the second contact node 50.

[0213] In some embodiments, an ohmic contact layer including metal silicide can be further formed after forming the second contact node 50.

[0214] Figure 32A is a plan view showing the structure of the nanosheet horizontal plane to describe a method of forming the first electrode 53.Figure 32B is a cross-sectional view of a structure taken along Figure 32A the line A-A’ shown.

[0215] Referring to Figure 32A and Figure 32B , the first electrode 53 of the data storage element can be formed on the second contact node 50. Each first electrode 53 can have a horizontally oriented cylindrical shape. Each first electrode 53 can be disposed in a different one of the storage openings 49. The first electrodes 53 disposed adjacent to each other in the second direction D2 can be spaced apart from each other by the second linear opening 46. The first electrodes 53 disposed adjacent to each other in the third direction D3 can be spaced apart from each other by the first inter-unit dielectric layer 23. The first electrodes 53 disposed adjacent to each other in the first direction D1 can be spaced apart from each other by the third inter-unit dielectric layer 48. Forming the first electrode 53 can include depositing a metal material, gap-filling a sacrificial material, and isolating the metal material in the vertical / horizontal directions. The sacrificial material can include an oxide or polysilicon.

[0216] Each first electrode 53 can include an internal space and a plurality of outer surfaces, and the internal space of the first electrode 53 can include a plurality of inner surfaces. The outer surface of the first electrode 53 can include vertical outer surfaces and a plurality of horizontal outer surfaces. The vertical outer surface of the first electrode 53 can extend vertically in the first direction D1, and the horizontal outer surface of the first electrode 53 can extend horizontally in the second direction D2 or the third direction D3. The internal space of the first electrode 53 can be a three-dimensional space. The first electrode 53 can have a cylindrical shape.

[0217] Among the outer surfaces of the first electrode 53, the vertical outer surface can be electrically coupled to the nanosheet HL and the second contact node 50.

[0218] The first electrode 53 can include a metal, a noble metal, a metal nitride, a conductive metal oxide, a conductive noble metal oxide, a metal carbide, a metal silicide, or a combination thereof. For example, the first electrode 53 can include titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO 2 ), iridium (Ir), iridium oxide (IrO 2 ), platinum (Pt), molybdenum (Mo), molybdenum oxide (MoO), a titanium nitride / tungsten (TiN / W) stack, a tungsten nitride / tungsten (WN / W) stack, a titanium silicon nitride / titanium nitride (TiSiN / TiN) stack, or a combination thereof.

[0219] Figure 33A is a plan view of a structure showing a narrow sheet horizontal plane to describe a method of partially recessing the third inter-unit dielectric layer 48. Figure 33B is alongFigure 33A Cross-sectional view of the structure taken along line A-A' shown

[0220] Referring to Figure 33A and Figure 33B , a part of the dielectric layer 48 between the third units can be horizontally recessed (see reference numeral "54"). Accordingly, the outer wall of the first electrode 53 can be partially exposed. Each first electrode 53 can have a semi-cylindrical shape. The horizontal recess depth of the dielectric layer 48 between the third units can be a depth that does not expose the second contact node 50. The semi-cylindrical shape of each first electrode 53 can include a cylindrical inner surface and a semi-cylindrical outer surface.

[0221] Figure 34A is a plan view of the structure showing the horizontal plane of the narrow sheet to describe a method of forming the second electrode 56. Figure 34B is along Figure 34A Cross-sectional view of the structure taken along line A-A' shown

[0222] Referring to Figure 34A and Figure 34B , the dielectric layer 55 and the second electrode 56 can be sequentially formed on each first electrode 53. The first electrode 53, the dielectric layer 55, and the second electrode 56 can be data storage elements CAP. The second electrodes 56 of the data storage elements CAP can be merged with each other to form a common plate PL.

[0223] The dielectric layer 55 and the second electrode 56 can be disposed on the cylindrical inner surface of the first electrode 53. A part of the dielectric layer 55 and a part of the second electrode 56 can extend to be disposed on the semi-cylindrical outer surface of the first electrode 53. The second electrode 56 can vertically extend in the first direction D1.

[0224] The dielectric layer 55 can be referred to as a "capacitor dielectric layer" or a "storage layer". The dielectric layer 55 can include silicon oxide, silicon nitride, a high-k material, a ferroelectric material, an antiferroelectric material, a perovskite material, or a combination thereof. The dielectric layer 55 can include hafnium oxide (HfO 2 ), zirconium oxide (ZrO 2 ), aluminum oxide (Al 2 O 3 ), lanthanum oxide (La 2 O 3 ), titanium oxide (TiO 2 ), tantalum oxide (Ta 2 O 5 ), niobium oxide (Nb 2 O 5 ), or strontium titanate (SrTiO 3 ). The dielectric layer 55 can include ZA (ZrO 2 / Al 2 O3 ) Stack, ZAZ (ZrO 2 / Al 2 O 3 / ZrO 2 ) Stack, ZAZA (ZrO 2 / Al 2 O 3 / ZrO 2 / Al 2 O 3 ) Stack, ZAZAZ (ZrO 2 / Al 2 O 3 / ZrO 2 / Al 2 O 3 / ZrO 2 ) Stack, HA (HfO 2 / Al 2 O 3 ) Stack, HAH (HfO 2 / Al 2 O 3 / HfO 2 ) Stack, HAHA (HfO 2 / Al 2 O 3 / HfO 2 / Al 2 O 3 ) Stack, HAHAH (HfO 2 / Al 2 O 3 / HfO 2 / Al 2 O 3 / HfO 2 ) Stack, HZAZH (HfO 2 / ZrO 2 / Al 2 O 3 / ZrO 2 / HfO 2 ) Stack, ZHZAZHZ (ZrO 2 / HfO 2 / ZrO 2 / Al 2 O 3 / ZrO 2 / HfO 2 / ZrO 2 ) Stack, HZHZ (HfO 2 / ZrO 2 / HfO 2 / ZrO 2 ) Stack, or AHZAHZA (Al2 O 3 / HfO 2 / ZrO 2 / Al 2 O 3 / HfO 2 / ZrO 2 / Al 2 O 3 ) stack.

[0225] The second electrode 56 may include a metal, a noble metal, a metal nitride, a conductive metal oxide, a conductive noble metal oxide, a metal carbide, a metal silicide, or a combination thereof. For example, the second electrode 56 may include titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO 2 ), iridium (Ir), iridium oxide (IrO 2 ), platinum (Pt), molybdenum (Mo), molybdenum oxide (MoO), titanium nitride / tungsten (TiN / W) stack, tungsten nitride / tungsten (WN / W) stack, titanium silicon nitride / titanium nitride (TiSiN / TiN) stack, or a combination thereof. The second electrode 56 may also include a combination of a metal-based material and a silicon-based material. For example, the second electrode 56 may have a structure in which titanium nitride, tungsten, and polysilicon are sequentially stacked.

[0226] In some embodiments, a lower interface control layer may be further formed between the first electrode 53 and the dielectric layer 55 to reduce leakage current. An upper interface control layer may be formed between the second electrode 56 and the dielectric layer 55. The lower interface control layer and the upper interface control layer may each include titanium oxide (TiO 2 ), tantalum oxide (Ta 2 O 5 ), niobium (Nb), niobium oxide (Nb 2 O 5 ), niobium nitride (NbN), niobium oxynitride (NbON), or a combination thereof. The lower interface control layer and the upper interface control layer may each include a single-layer structure or a double-layer structure. For example, the upper interface control layer may include a stack of titanium oxide (TiO 2 ) and niobium oxide (Nb 2 O 5 ).

[0227] In some embodiments, the recesses of the first inter-cell dielectric layer 23 and the third inter-cell dielectric layer 48 may be omitted Figure 33B . Subsequently, referring to Figure 34B , the dielectric layer 55 and the second electrode 56 may be formed. Thus, a data storage element CAP having a concave shape may be formed.

[0228] According to the above embodiments, the first vertical wire 44A and the second vertical wire 44B can be formed by self-aligning with the support 36 without high aspect ratio etching. Thus, a memory cell array including memory cells of the same size can be formed.

[0229] In addition, according to the above embodiments, since high aspect ratio etching is not performed to form the first vertical wire 44A and the second vertical wire 44B, the cost can be reduced.

[0230] Figure 35A and Figure 35B is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present disclosure.

[0231] Referring to Figure 35A , the semiconductor device 201 may include a memory cell array MCA, a peripheral circuit portion PERI, and a bonding interface BS. The bonding interface BS may be provided between the memory cell array MCA and the peripheral circuit portion PERI. In the semiconductor device 201, the memory cell array MCA may be provided at a level higher than that of the peripheral circuit portion PERI. The semiconductor device 201 may be referred to as a "cell array on PERI (COP) structure" or a "PERI under cell array (PUC) structure". The memory cell array MCA may include a substrate on which back grinding is performed and a memory cell array. For example, as referred to Figure 34A and Figure 34B described, after forming the data storage element CAP, the substrate 11 may be flipped by wafer flipping, and then partial back grinding may be performed on the substrate 11.

[0232] Referring to Figure 35B , the semiconductor device 202 may include a memory cell array MCA, a peripheral circuit portion PERI, and a bonding interface BS. The bonding interface BS may be provided between the memory cell array MCA and the peripheral circuit portion PERI. In the semiconductor device 202, the memory cell array MCA may be provided at a level lower than that of the peripheral circuit portion PERI. The semiconductor device 202 may be referred to as a "cell array over PERI (POC) structure" or a "PERI under cell array (CUP) structure". Forming the peripheral circuit portion PERI may include forming a plurality of control circuits on a peripheral circuit substrate and forming multi-level interconnections on the control circuits.

[0233] In Figure 35A and Figure 35BAmong them, the bonding interface BS may include pad bonding, hybrid bonding, oxide-oxide bonding, metal-metal bonding, or a combination thereof. Hybrid bonding may refer to a combination of pad bonding and oxide-oxide bonding. Pad bonding may include forming unit bonding pads for a memory cell array, forming peripheral circuit bonding pads for a peripheral circuit portion, performing wafer flipping so that the unit bonding pads and the peripheral circuit bonding pads face each other, and performing wafer bonding.

[0234] After forming the unit bonding pads and the peripheral circuit bonding pads, Figure 35A The semiconductor device 201 shown may perform wafer flipping on the substrate on which the memory cell array is formed, such that the unit bonding pads and the peripheral circuit pads face each other. After forming the unit pads and the peripheral circuit pads, Figure 35B The semiconductor device 202 shown in may perform wafer flipping on the substrate on which the peripheral circuit portion is formed, such that the unit pads and the peripheral circuit pads face each other.

[0235] Figure 36A and Figure 36B show various views of a stacked component according to an embodiment of the present disclosure.

[0236] Referring to Figure 36A , the stacked component 300 may include components of semiconductor wafers. For example, the stacked component 300 may include a first semiconductor wafer BSD and a plurality of second semiconductor wafers 301. The first semiconductor wafer BSD may include logic circuits. Each second semiconductor wafer 301 may include a memory cell array according to the above embodiment. Each second semiconductor wafer 301 may include a structure in which a memory cell array and a peripheral circuit portion are stacked, such as Figure 35A the semiconductor device 201 shown or Figure 35B the conductor device 202 shown. The logic circuits of the first semiconductor wafer BSD may be different from the peripheral circuit portions of the second semiconductor wafers 301. The second semiconductor wafers 301 may be electrically coupled to each other through through-silicon vias TSVs and a chip-level bonding interface CBS. The first semiconductor wafer BSD and the lowermost second semiconductor wafer 301 may be electrically coupled to each other through the chip-level bonding interface CBS. The second semiconductor wafers 301 may be referred to as "core wafers", "semiconductor chips", or "memory chips".

[0237] The chip-level bonding interface CBS may include microbumps, pad bonding, hybrid bonding, oxide-oxide bonding, metal-metal bonding, or a combination thereof.

[0238] In some embodiments, the second semiconductor wafers 301 may be wafer-flipped and back-grinded to form the chip-level bonding interface CBS.

[0239] Referring toFigure 36B The stacked component 400 may include components of semiconductor wafers. For example, the stacked component 400 may include a first semiconductor wafer BSD, a plurality of second semiconductor wafers 401, and a plurality of third semiconductor wafers 402. The first semiconductor wafer BSD may include logic circuits. Each second semiconductor wafer 401 and each third semiconductor wafer 402 may include a memory cell array according to the above embodiments. The second semiconductor wafers 401 and the third semiconductor wafers 402 may have different structures.

[0240] Each second semiconductor wafer 401 may include a structure in which a memory cell array and a peripheral circuit portion are stacked, such as Figure 35A the semiconductor device 201 shown. Each third semiconductor wafer 402 may include a structure in which a memory cell array and a peripheral circuit portion are stacked, such as Figure 35B the semiconductor device 202 shown in.

[0241] In some embodiments, each second semiconductor wafer 401 may include Figure 35B the semiconductor device 202 shown, and each third semiconductor wafer 402 may include Figure 35A the conductor device 201 shown.

[0242] The logic circuits of the first semiconductor wafer BSD may be different from the peripheral circuit portions of the second semiconductor wafers 401 and the third semiconductor wafers 402. The second semiconductor wafers 401 and the third semiconductor wafers 402 may be electrically coupled to each other through through-silicon vias TSVs and a chip-level bonding interface CBS. The first semiconductor wafer BSD and the lowermost second semiconductor wafer 401 may be electrically coupled to each other through the chip-level bonding interface CBS. The second semiconductor wafers 401 and the third semiconductor wafers 402 may be referred to as "core wafers", "semiconductor chips", or "memory chips".

[0243] The chip-level bonding interface CBS may include micro-bumps, pad bonding, hybrid bonding, oxide-oxide bonding, metal-metal bonding, or a combination thereof.

[0244] In some embodiments, a wafer flip and back grinding process may be performed to form the chip-level bonding interface CBS. For example, the wafer flip and back grinding may be performed on the second semiconductor wafers 401 and / or the third semiconductor wafers 402.

[0245] Figure 36A and Figure 36B the stacked components 300 and 400 shown in may be high bandwidth memories.

[0246] According to the embodiments of the present disclosure, vertical wires may be formed by self-aligning with a support without high aspect ratio etching.

[0247] According to various embodiments of the present disclosure, a memory cell array including memory cells having the same size may be formed.

[0248] According to various embodiments of the present disclosure, since high aspect ratio etching is not performed to form vertical wires, the cost may be reduced.

[0249] Although the embodiments of the present disclosure have been described and illustrated with reference to specific embodiments and the accompanying drawings, the disclosed embodiments are not limiting. In addition, it should be noted that, without departing from the spirit and / or scope of the present disclosure and the appended claims, those skilled in the art will recognize, based on the present disclosure, that the embodiments may be implemented in various ways by substitution, change, and modification. In addition, these embodiments may be combined to form additional embodiments.

Claims

1. A semiconductor device, comprising: A horizontally arranged switch element, the switch element comprising a nanosheet and a horizontal wire surrounding the nanosheet; a pyramid-shaped first contact node formed on a first edge of the horizontally arranged nanosheet; a vertical conductive line including a pyramid portion surrounding the first contact node, each of the vertical conductive lines being coupled to a different one of the horizontally arranged nanosheets; data storage elements, each of the data storage elements coupled to a different one of the second edges of the horizontally arranged nanosheets; and A support member surrounds the vertical wire. 2 . The semiconductor device according to claim 1 , wherein the support member includes a plurality of support recesses, and the pyramid portion of the vertical conductive line has a structure filling the support recesses. 3 . The semiconductor device of claim 1 , wherein the support comprises a low-k material, silicon oxycarbide, silicon nitride, an air gap, or a combination thereof.

4. The semiconductor device according to claim 1, further comprising: a first spacer disposed between the data storage element and the horizontal conductive line and surrounding the nanosheet; a second spacer disposed between the vertical conductive line and the horizontal conductive line and surrounding the nanosheet; and An etch stop spacer is disposed between the vertical conductive line and the horizontal conductive line and surrounds the nanosheet. 5 . The semiconductor device of claim 4 , wherein the etch stop spacer comprises a different material from the first spacer and the second spacer. 6 . The semiconductor device according to claim 1 , wherein each of the first contact nodes comprises a selective epitaxial growth layer. 7 . The semiconductor device of claim 1 , wherein each of the first contact nodes comprises a doped silicon epitaxial layer. 8 . The semiconductor device according to claim 1 , further comprising an ohmic contact layer disposed between the vertical conductive line and the first contact node and having a pyramid shape covering the first contact node. 9 . The semiconductor device of claim 1 , wherein each of the nanosheets comprises a first doping region and a second doping region horizontally spaced apart from each other and a channel formed between the first doping region and the second doping region. 10 . The semiconductor device according to claim 1 , wherein each of the nanosheets comprises single crystalline silicon, an oxide semiconductor material, a two-dimensional material, or a combination thereof. 11 . The semiconductor device of claim 1 , further comprising a second contact node formed between the second edge of the nanosheet and the data storage element. 12 . The semiconductor device according to claim 11 , wherein each of the second contact nodes comprises a selective epitaxial growth layer.

13. The semiconductor device according to claim 1, wherein each of the nanosheets comprises: a narrow strip coupled to each of the vertical conductors; and A wide sheet is coupled to each of the data storage elements and has a thickness gradually increasing from the narrow sheet toward the data storage elements.

14. A method for manufacturing a semiconductor device, the method comprising: forming a barrier layer on a substrate; forming horizontally arranged and vertically arranged narrow flakes on the barrier layer; forming a support member including a support recess, the support recess simultaneously exposing the edge of the vertically arranged narrow piece and the edge of the horizontally arranged narrow piece respectively; forming horizontally arranged and vertically arranged first contact nodes, each of the first contact nodes being coupled to a different one of the edges of the horizontally arranged and vertically arranged narrow slices; and Vertical conductive lines commonly coupled to the vertically arranged first contact nodes are formed, each of the vertical conductive lines being coupled to a different one of the horizontally arranged first contact nodes and disposed in the supporting recess.

15. The method according to claim 14, wherein: Forming the support member including the support recess comprises: forming the protruding edges of the narrow pieces arranged horizontally and vertically; forming a sacrificial growth layer covering the protruding edges of the horizontally and vertically arranged narrow slices; forming a support member partially covering the sacrificial growth layer and exposing a portion of the sacrificial growth layer; forming the supporting recess by removing the sacrificial growth layer; and The protruding edges of the horizontally and vertically arranged narrow pieces are cut. 16 . The method of claim 15 , wherein forming the sacrificial growth layer comprises selectively epitaxially growing a silicon germanium layer.

17. The method according to claim 15, wherein: The protruding edges forming the narrow pieces arranged horizontally and vertically include: forming etch stop spacers covering upper and lower surfaces of the horizontally and vertically arranged narrow slices; forming a first sacrificial spacer disposed between the horizontally arranged narrow slices; forming a second sacrificial spacer covering upper and lower surfaces of the edges of the horizontally and vertically arranged narrow slices on the etch stop spacer and the first sacrificial spacer; removing the first sacrificial spacer using the second sacrificial spacer as a stopper; The second sacrificial spacers are removed to form the protruding edges of the horizontally and vertically arranged narrow slices. 18 . The method of claim 17 , wherein each of the first sacrificial spacers comprises polysilicon and each of the second sacrificial spacers comprises silicon nitride.

19. The method of claim 14, wherein the support comprises a low-k material, silicon oxycarbide, silicon nitride, an air gap, or a combination thereof.

20. The method of claim 14, further comprising forming an ohmic contact layer on the first contact node before forming the vertical conductive line.

21. The method of claim 14, further comprising: forming a first spacer around a first portion of the horizontally and vertically arranged narrow slices; forming a horizontal conductive line on the first spacer to surround a second portion of the horizontally arranged narrow slice; and A second spacer is formed on the horizontal conductive line surrounding a third portion of the horizontally arranged narrow piece.

22. The method of claim 21, wherein the horizontal conductive line comprises a gate wrap structure surrounding the horizontally arranged narrow slices.

23. The method according to claim 14, wherein the step of forming the horizontally arranged and vertically arranged narrow flakes on the barrier layer comprises: forming a horizontally arranged and vertically arranged nanosheet target layer on the barrier layer; and A first portion of the nanosheet target layer is selectively recessed to form the horizontally and vertically arranged narrow flakes.

24. The method according to claim 23, further comprising: After forming the vertical conductive line, selectively recessing a second portion of the nanosheet target layer to form horizontally and vertically arranged wide sheets; selectively forming a second contact node from a side surface of the wide sheet; and Data storage elements are formed, each of the data storage elements being coupled to a different one of the second contact nodes.

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