Three-dimensional memory and preparation method thereof, memory system and electronic equipment
By achieving three-dimensional integration in the NOR Flash memory, by alternately forming a stacked first dielectric layer and conductive layer, and embedding multiple gate structures and channel structures, the density and capacity of the NOR Flash memory is solved, and a higher storage density and capacity is achieved.
Patent Information
- Application Number
- CN202510074987.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-17
- Publication Date
- 2025-06-03
AI Technical Summary
NOR Flash memory cannot compete with 3D NAND and DRAM in smaller sizes and higher density due to its planar structure, resulting in unavailability in high-performance computer and server scenarios.
Three-dimensional integration of the memory cells is achieved by alternately forming a stacked first dielectric layer and a conductive layer on the substrate, and embedding a plurality of gate structures and channel structures therein. This design significantly improves storage density so that more data can be stored in the same physical space.
A significant improvement in storage density is achieved, so that more data can be stored in the same physical space, overcoming the bottlenecks of planar structure memory in size reduction and density improvement.
Smart Images
Figure CN120091567A_ABST
Abstract
Description
Technical Field
[0001] This application belongs to the field of semiconductor technology, and particularly relates to a three-dimensional memory, a manufacturing method thereof, a storage system, and an electronic device. Background Art
[0002] Flash memory circuits are mainly divided into two types: NOR Flash arrays and NAND Flash arrays. Whether it is NOR Flash or NAND Flash, voltage is applied to the word line (WL), bit line (BL), and source line (SL) to select a specific Flash device in the Flash array for read and write operations. Compared with NAND Flash, NOR Flash has a faster read and write speed, but a lower storage density.
[0003] Through three-dimensional integration technology, Flash devices are vertically stacked to achieve higher storage density and larger storage capacity. For NAND Flash, 3D NAND memories based on three-dimensional integration are already very mature. Compared with NAND Flash, there has been no progress in the three-dimensional integration of NOR Flash. With the advancement of semiconductor manufacturing processes, the sizes of MOS and DRAM memories have been continuously reduced, and their densities have been continuously increased. 3D NAND overcomes the bottleneck of the size reduction of planar Flash devices through three-dimensional integration. However, NOR Flash memories are stuck at the 28nm process node due to their planar structure, lagging behind the most advanced DRAM in terms of read and write speed and storage density. This makes NOR Flash unable to be applied in scenarios for high-performance computers and servers. Summary of the Invention
[0004] Embodiments of this application provide a three-dimensional memory, a manufacturing method thereof, a storage system, and an electronic device, which achieve three-dimensional integration of storage units, significantly improve storage density, and enable more data to be stored in the same physical space.
[0005] On the one hand, embodiments of this application provide a three-dimensional memory. The three-dimensional memory can be a NOR Flash memory. The three-dimensional memory includes a substrate, a plurality of first dielectric layers and a plurality of conductive layers, which are stacked on the substrate. The first dielectric layers and the conductive layers are alternately arranged. The conductive layers include a source line and a bit line. The three-dimensional memory further includes a plurality of gate structures and a plurality of channel structures. Along the direction perpendicular to the substrate, the plurality of gate structures penetrate through the plurality of first dielectric layers and the plurality of conductive layers, and the gate structures are located between the source line and the bit line. A channel structure surrounds the outside of one gate structure, and the side surface of the channel structure is connected to the source line and the bit line.
[0006] In some embodiments, the above-mentioned source line includes a first bus bar and a plurality of first fingers connected to the first bus bar, and the first fingers extend along a first direction parallel to the substrate;
[0007] The above-mentioned bit line includes a second bus bar and a plurality of second fingers connected to the second bus bar, and the second fingers extend along the first direction;
[0008] Along a second direction parallel to the substrate, the first fingers and the second fingers are alternately arranged, and the second direction intersects the first direction.
[0009] In some embodiments, a plurality of the above-mentioned gate structures are located between the first fingers and the second fingers;
[0010] The side surface of the above-mentioned channel structure is connected to the first fingers and the second fingers.
[0011] In some embodiments, the above-mentioned three-dimensional memory further includes a second dielectric layer;
[0012] Along a direction perpendicular to the substrate, the second dielectric layer penetrates through the plurality of first dielectric layers and the plurality of conductive layers, and the second dielectric layer is located between the source line and the bit line;
[0013] Along a direction perpendicular to the substrate, the above-mentioned gate structure also penetrates through the second dielectric layer.
[0014] The three-dimensional memory provided by the embodiments of the present application includes a substrate, a plurality of first dielectric layers and a plurality of conductive layers stacked on the substrate, and the first dielectric layers and the conductive layers are alternately arranged. The first dielectric layers are used for electrically isolating adjacent conductive layers. These layers are alternately stacked on the substrate to form a multi-layer structure, and this design helps to increase the density and integration degree of memory cells. Each conductive layer includes a source line and a bit line, which are used for transmitting current in the three-dimensional memory. The specific configuration of the source line and the bit line determines the data read / write path.
[0015] The three-dimensional memory further includes a plurality of gate structures and a plurality of channel structures. The plurality of gate structures penetrate through the plurality of first dielectric layers and the plurality of conductive layers along a direction perpendicular to the substrate, and the gate structures are located between the source line and the bit line. Each channel structure surrounds the outside of a gate structure, and the side surface of the channel structure is connected to the source line and the bit line to form a complete current loop. The gate structure serves as the control electrode of the transistor, and controls the current flow in the channel by changing the gate voltage. When the gate voltage is high enough, the carriers (electrons or holes) in the channel are attracted to form a conductive channel, allowing current to pass through.
[0016] The three-dimensional integration of the memory cell is achieved by stacking multiple first dielectric layers and conductive layers and embedding a gate structure and a channel structure therein, significantly improving the storage density and enabling more data to be stored in the same physical space.
[0017] On the other hand, an embodiment of the present application also provides a method for manufacturing a three-dimensional memory, including:
[0018] Alternately form stacked first dielectric layers and conductive layers on a substrate;
[0019] Form trenches that penetrate the first dielectric layer and the conductive layer in a direction perpendicular to the substrate, and the trenches separate the conductive layer to form source lines and bit lines;
[0020] Form a plurality of gate structures and a plurality of channel structures. In a direction perpendicular to the substrate, the plurality of gate structures penetrate the first dielectric layer and the conductive layer, and the gate structures are located between the source lines and the bit lines; a channel structure surrounds the outside of a gate structure, and the side surface of the channel structure is connected to the source lines and the bit lines.
[0021] In some embodiments, the shape of the positive projection of the trenches on the substrate is a bow shape to separate the conductive layer to form interdigitated source lines and bit lines.
[0022] In some embodiments, after forming the trenches, the manufacturing method further includes:
[0023] Form a second dielectric layer that is located in the trenches;
[0024] Form a plurality of vias that penetrate the second dielectric layer in a direction perpendicular to the substrate, and the side walls of the plurality of vias expose the source lines and the bit lines;
[0025] Form the channel structures and the gate structures on the side walls of the plurality of vias in sequence.
[0026] In some embodiments, the plurality of vias also penetrate the first dielectric layer and the conductive layer.
[0027] On the other hand, an embodiment of the present application also provides a storage system, including the above three-dimensional memory; a controller electrically connected to the three-dimensional memory.
[0028] On the other hand, an embodiment of the present application also provides an electronic device, including the above storage system.
[0029] The preparation method provided by the embodiments of the present application forms stacked first dielectric layers and conductive layers alternately on a substrate, where the first dielectric layers are used to isolate the conductive layers; trenches are formed in a direction perpendicular to the substrate, the trenches penetrate through the first dielectric layers and the conductive layers, and the conductive layers are separated by the trenches to form source lines and bit lines; in a direction perpendicular to the substrate, a plurality of gate structures and a plurality of channel structures are formed, the plurality of gate structures penetrate through the first dielectric layers and the conductive layers, and the gate structures are located between the source lines and the bit lines; a channel structure surrounds the outside of a gate structure, and the side surface of the channel structure is electrically connected to the source lines and the bit lines to ensure that charges can be effectively transmitted and stored in the memory. By alternately stacking the first dielectric layers and the conductive layers and forming trenches, gate structures and channel structures therein, a three-dimensional memory structure is formed. This three-dimensional structure can significantly improve the storage capacity and integration degree of the memory. Description of the Drawings
[0030] The above and / or additional aspects and advantages of the present application will become apparent and be readily understood from the following description of the embodiments in conjunction with the accompanying drawings, where:
[0031] Figure 1 It is a front view of a three-dimensional memory structure provided by an embodiment of the present application;
[0032] Figure 2 It is a top view of a three-dimensional memory structure provided by an embodiment of the present application;
[0033] Figure 3 It is a top view of a cylindrical Flash device structure provided by an embodiment of the present application;
[0034] Figure 4 It is a flowchart of a method for preparing a three-dimensional memory provided by an embodiment of the present application;
[0035] Figures 5 to 9 It is a view of each step of a method for preparing a three-dimensional memory provided by an embodiment of the present application;
[0036] Figure 10 It is a schematic structural diagram of a storage system provided by an embodiment of the present application; Detailed Embodiments
[0037] Next, the technical solutions in some embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments provided by the present application, all other embodiments obtained by those of ordinary skill in the art belong to the scope of protection of the present application.
[0038] Unless otherwise required by the context, throughout the specification and claims, the term "comprising" is interpreted in an open, inclusive sense, that is, "including, but not limited to".
[0039] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the embodiments of the present application, unless otherwise specified, the meaning of "a plurality" is two or more.
[0040] When describing some embodiments, the expression "connected" and its derivatives may be used. The term "connected" should be understood in a broad sense. For example, "connected" may be a fixed connection, a detachable connection, or an integral body; it may be directly connected or indirectly connected through an intermediate medium. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components have direct physical contact or electrical contact with each other.
[0041] In addition, the use of "based on" implies openness and inclusiveness because a process, step, calculation, or other action "based on" one or more of the stated conditions or values may, in practice, be based on additional conditions or values beyond those stated.
[0042] It should be understood that when a layer or element is referred to as being on another layer or substrate, it may be that the layer or element is directly on the other layer or substrate, or there may be an intermediate layer between the layer or element and the other layer or substrate.
[0043] Exemplary embodiments are described herein with reference to cross-sectional views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of regions are exaggerated for clarity. Thus, variations in the shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances can be envisioned. Therefore, the exemplary embodiments should not be construed as being limited to the shapes of the regions shown herein, but rather include shape deviations caused, for example, by manufacturing. Thus, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shape of the regions of the device and are not intended to limit the scope of the exemplary embodiments.
[0044] Examples of the embodiments are shown in the drawings, where like or similar reference numerals designate like or similar elements or elements having like or similar functions throughout. The embodiments described below with reference to the drawings are exemplary only for explaining the present application and should not be construed as limiting the present application.
[0045] Existing NOR Flash devices all have a planar structure and face a bottleneck in further reducing the device size at the 28 nm process node because the process of planar structure Flash devices is difficult to be compatible with the FinFET transistor process of more advanced process nodes. This bottleneck limits the further improvement of the NOR Flash storage density and capacity.
[0046] In view of the above problems, an embodiment of the present application provides a three-dimensional memory, as Figure 1 shown, Figure 1 which is a schematic structural diagram of a three-dimensional memory provided by an embodiment of the present application.
[0047] As Figure 1 shown, the three-dimensional memory 10 includes a substrate 101, a plurality of first dielectric layers 102 and a plurality of conductive layers 103, which are stacked on the substrate 101, and the first dielectric layers 102 and the conductive layers 103 are alternately arranged; the conductive layer 103 includes a source line 1031 and a bit line 1032; wherein the source line 1031 is generally used to provide current or voltage to the memory cell, and the bit line 1032 is used to read or write data in the memory cell. A plurality of gate structures 104 penetrate through the plurality of first dielectric layers 102 and the plurality of conductive layers 103 in a direction perpendicular to the substrate 101, and the gate structure 104 is located between the source line 1031 and the bit line 1032, and functions to control the current passing through the channel structure 105. A plurality of channel structures 105, one channel structure 105 surrounds the outside of one gate structure 104, and the side surface of the channel structure 105 is connected to the source line 1031 and the bit line 1032.
[0048] The three-dimensional memory 10 provided by the embodiment of the present application includes a substrate 101, a plurality of first dielectric layers 102 and a plurality of conductive layers 103 stacked on the substrate 101, and the first dielectric layers 102 and the conductive layers 103 are alternately arranged. The first dielectric layer 102 is used for electrically isolating adjacent conductive layers 103. These layers are alternately stacked on the substrate 101 to form a multi-layer structure, and this design helps to increase the density and integration degree of the memory cells. Each conductive layer 103 includes a source line 1031 and a bit line 1032, which are used for transmitting current in the three-dimensional memory. The specific configuration of the source line 1031 and the bit line 1032 determines the data read / write path.
[0049] The three-dimensional memory 10 further includes a plurality of gate structures 104 and a plurality of channel structures 105. The plurality of gate structures 104 penetrate through the plurality of first dielectric layers 102 and the plurality of conductive layers 103 in a direction perpendicular to the substrate 101, and the gate structure 104 is located between the source line 1031 and the bit line 1032. Each channel structure 105 surrounds the outside of one gate structure 104, and the side surface of the channel structure 105 is connected to the source line 1031 and the bit line 1032 to form a complete current loop. The gate structure 104 serves as the control electrode of the transistor, and controls the current flow in the channel by changing the gate voltage. When the gate voltage is high enough, the carriers (electrons or holes) in the channel are attracted to form a conductive channel, allowing current to pass through.
[0050] The three-dimensional integration of the memory cell is achieved by stacking multiple first dielectric layers 102 and conductive layers 103 and embedding a gate structure 104 and a channel structure 105 therein, significantly improving the storage density and enabling more data to be stored within the same physical space.
[0051] In some embodiments, as Figure 2 shown, the source line 1031 includes a first bus bar 106 and a plurality of first fingers 107 connected to the first bus bar 106. The first fingers 107 extend in a first direction parallel to the substrate 101, such as Figure 2 the X direction shown; the bit line 1032 includes a second bus bar 108 and a plurality of second fingers 109 connected to the second bus bar 108. The second fingers 109 extend in the first direction; along a second direction parallel to the substrate 101, the first fingers 107 and the second fingers 109 are alternately arranged. The second direction intersects the first direction, i.e., the Y direction, and usually forms a right angle or other specific angles. By alternately arranging the first fingers 107 and the second fingers 109, the space on the substrate can be utilized to the maximum extent. This layout enables more memory cells to be accommodated within a limited area, thereby increasing the density and capacity of the memory.
[0052] In some embodiments, as Figure 2 , Figure 3 shown, a plurality of gate structures 104 are located between the first fingers 107 and the second fingers 109; the side surfaces of the channel structure 105 are connected to the first fingers 107 and the second fingers 109. The channel structure 105 is located below the gate structure 104 and is controlled by a gate voltage. When the gate voltage reaches a certain threshold, a conductive channel is formed in the channel structure 105, allowing current to flow from the source line 1031 to the bit line 1032.
[0053] In some embodiments, the three-dimensional memory 10 further includes a second dielectric layer 110; along a direction perpendicular to the substrate 101, the second dielectric layer 110 penetrates through the plurality of first dielectric layers 102 and the plurality of conductive layers 103, and the second dielectric layer 110 is located between the source line 1031 and the bit line 1032; along a direction perpendicular to the substrate 101, the gate structure 104 also penetrates through the second dielectric layer 110. In the vertical direction, the second dielectric layer 110 serves to isolate the source line 1031 and the bit line 1032, preventing electrical connection between the source line 1031 and the bit line 1032, thereby ensuring the normal operation of the memory cell and maintaining the overall stability of the stacked structure.
[0054] On the other hand, an embodiment of the present application also provides a method for manufacturing a three-dimensional memory, as Figure 4 shown, Figure 4 is a flowchart of a method for manufacturing a three-dimensional memory provided by an embodiment of the present application, Figures 5 to 9These are the step diagrams for fabricating a 3D memory provided by embodiments of the present application.
[0055] As Figure 4 shown, the fabrication method includes the following steps S10 to S50:
[0056] Step S10: As Figure 5 shown, a stacked first dielectric layer 102 and a conductive layer 103 are alternately formed on a substrate 101;
[0057] Exemplarily, the first dielectric layer 102 is deposited and formed on the substrate 101 by chemical vapor deposition (CVD) or physical vapor deposition (PVD). The conductive layer 103 is deposited on the first dielectric layer 102. The material of the conductive layer 103 is usually a metal such as copper, aluminum, etc. or an alloy, and a doped semiconductor material may also be used. The above deposition steps are repeated multiple times to alternately form multiple first dielectric layers 102 and conductive layers 103 on the substrate 101. This alternating stacked structure provides a basis for subsequent circuit patterning.
[0058] Step S20: A trench 116 is formed. Along a direction perpendicular to the substrate 101, the trench 116 penetrates through the first dielectric layer 102 and the conductive layer 103, and the trench 116 separates the conductive layer 103 to form a source line 1031 and a bit line 1032;
[0059] Exemplarily, a photoresist is applied on the conductive layer 103, and a desired pattern is formed by dry etching or wet etching to remove a part of the conductive layer 103 and the underlying first dielectric layer 102 to form the trench 116, as Figure 6 shown. The shape of the positive projection of the trench 116 on the substrate 101 is bow-shaped to separate the conductive layer 103 to form finger-shaped source line 1031 and bit line 1032.
[0060] Step S30: An insulating dielectric is filled in the trench 116 to form a second dielectric layer 110;
[0061] As Figure 7 shown, an insulating material such as silicon dioxide or other low dielectric constant materials is filled in the trench 116 by chemical vapor deposition (CVD) to form the second dielectric layer 110 to isolate the source line 1031 and the bit line 1032 and prevent short circuits between them. The excess insulating dielectric on the upper surface is removed by chemical mechanical polishing (CMP) to form a structure as Figure 10 shown.
[0062] Step S40: A plurality of vias 111 are formed. Along a direction perpendicular to the substrate 101, the plurality of vias 111 penetrate through the second dielectric layer 110, and the sidewalls of the plurality of vias 111 expose the source line 1031 and the bit line 1032;
[0063] Exemplarily, asFigure 8 As shown, using photolithography technology, the required via pattern is transferred to the photoresist through a mask. Using dry etching such as reactive ion etching or wet etching technology, a part of the second dielectric layer 110 is removed along the pattern defined by the photoresist to form a via 111. And along the direction perpendicular to the substrate 101, the via 111 completely penetrates the second dielectric layer 110, and the side walls of the via 111 expose the source line 1031 and the bit line 1032. At the same time, multiple vias also penetrate the first dielectric layer 102 and the conductive layer 103.
[0064] Step S50: Form a plurality of gate structures 104 and a plurality of channel structures 105. Along the direction perpendicular to the substrate 101, the plurality of gate structures 104 penetrate the first dielectric layer 102 and the conductive layer 103, and the gate structures 104 are located between the source line 1031 and the bit line 1032; a channel structure 105 surrounds the outside of a gate structure 104, and the side surface of the channel structure 105 is connected to the source line 1031 and the bit line 1032.
[0065] Exemplarily, as Figure 9 shown, a layer of semiconductor material, such as polysilicon, single crystal silicon, etc., is first deposited on the inner wall of the via 111 by chemical vapor deposition (CVD) as the potential material for the channel structure 105. Then a layer of insulating material, such as silicon dioxide (SiO2) or silicon nitride (Si3N4), is deposited as the gate oxide layer 112 for isolating the channel material and the subsequent charge trap material. Then a layer of charge trap material, such as silicon nitride or high-k dielectric material, is deposited as the charge trap layer 113 for capturing charges and storing information. This layer of material plays a key role in the storage device. Then another layer of insulating material is deposited as the isolation layer 114 between the charge trap material and the word line material. Finally, a layer of conductive material, such as polysilicon, metal or metal alloy, is deposited as the word line material, i.e., the gate layer 115. This layer of material will be used to apply a control voltage on the gate structure 104 to regulate the current in the channel. By chemical mechanical polishing (CMP), the excess material on the upper surface is removed, and finally the structure as Figure 9 shown is formed. In this structure, the gate structure 104 is composed of the gate oxide layer 112, the charge trap layer 113, the isolation layer 114 and the gate layer 115, and they are tightly filled in the via. The plurality of gate structures 104 penetrate the first dielectric layer 102 and the conductive layer 103, and the gate structures 104 are located between the source line 1031 and the bit line 1032. A channel structure 105 surrounds the outside of the gate structure 104, and its side surface forms an electrical connection with the source line 1031 and the bit line 1032.
[0066] On the other hand, the embodiments of the present application also provide a storage system, Figure 10 which is a schematic structural diagram of the storage system provided by the embodiments of the present application.
[0067] As shown Figure 10 in FIG. 1, the storage system 200 includes a controller 201 and the 3D memory 10 in any of the above embodiments. The controller 201 is electrically connected to the 3D memory 10.
[0068] Exemplarily, the controller 201 receives instructions from external devices such as computers, smartphones, etc., parses these instructions, and accordingly sends read / write requests to the 3D memory 10, and the 3D memory 10 is responsible for storing a large amount of data.
[0069] On the other hand, an embodiment of the present application further provides an electronic device, and the electronic device includes the storage system in the above embodiment.
[0070] Exemplarily, when the electronic device needs to store or read data, corresponding instructions can be sent to the controller 201. The controller 201 parses these instructions, and according to the storage location and type of the data, sends read / write requests to the 3D memory 10. After receiving the requests, the 3D memory 10 performs corresponding read / write operations through its internal storage units and circuits, and returns the results to the controller 201. The controller 201 then transmits the results to the electronic device to complete the entire data storage or read process.
[0071] The present invention proposes a brand-new 3D NOR Flash array, which greatly improves the storage density and storage capacity of NOR Flash through a 3D integration method, and can be embedded into the memory hierarchy as a new type of Storage-Class Memory (SCM) with a read / write speed faster than 3D NAND and a storage density and capacity greater than DRAM, greatly improving the performance of high-performance computing systems.
[0072] The above is only the specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art can think of changes or substitutions within the technical scope disclosed by the present application, and all of them should be covered by the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.
Claims
1. A three-dimensional memory, characterized in that: include: substrate; A plurality of first dielectric layers and a plurality of conductive layers are stacked on the substrate, wherein the first dielectric layers and the conductive layers are alternately arranged; the conductive layers include source lines and bit lines; Multiple gate structures; Along a direction perpendicular to the substrate, the plurality of gate structures penetrate the plurality of first dielectric layers and the plurality of conductive layers, and the gate structures are located between the source lines and the bit lines; A plurality of channel structures are provided, wherein a channel structure surrounds an outer side of a gate structure, and a side surface of the channel structure is connected to the source line and the bit line.
2. The three-dimensional memory according to claim 1, characterized in that: The source line includes a first bus bar and a plurality of first interdigital fingers connected to the first bus bar, wherein the first interdigital fingers extend along a first direction parallel to the substrate; The bit line includes a second bus bar and a plurality of second interdigital fingers connected to the second bus bar, wherein the second interdigital fingers extend along the first direction; The first interdigitating fingers and the second interdigitating fingers are arranged alternately along a second direction parallel to the substrate, and the second direction intersects the first direction.
3. The three-dimensional memory according to claim 2, characterized in that: A plurality of the gate structures are located between the first interdigital fingers and the second interdigital fingers; The side surface of the channel structure is connected to the first inserting finger and the second inserting finger.
4. The three-dimensional memory according to claim 1, characterized in that: The three-dimensional memory further includes a second dielectric layer; The second dielectric layer penetrates the plurality of first dielectric layers and the plurality of conductive layers along a direction perpendicular to the substrate, and the second dielectric layer is located between the source line and the bit line; The gate structure also penetrates the second dielectric layer along a direction perpendicular to the substrate.
5. A method for preparing a three-dimensional memory, characterized in that: include: Alternatingly forming stacked first dielectric layers and conductive layers on a substrate; forming a groove, wherein the groove penetrates the first dielectric layer and the conductive layer in a direction perpendicular to the substrate, and the groove separates the conductive layer to form a source line and a bit line; A plurality of gate structures and a plurality of channel structures are formed, wherein the plurality of gate structures penetrate the first dielectric layer and the conductive layer along a direction perpendicular to the substrate, and the gate structures are located between the source lines and the bit lines; a channel structure surrounds the outside of a gate structure, and the side surfaces of the channel structure are connected to the source lines and the bit lines.
6. The preparation method according to claim 5, characterized in that: The orthographic projection of the trench on the substrate is in an arc shape, so as to separate the conductive layer to form a source line and a bit line in a finger-like shape.
7. The preparation method according to claim 5, characterized in that: After forming the groove, the preparation method further comprises: forming a second dielectric layer, wherein the second dielectric layer is located in the trench; forming a plurality of via holes, wherein the plurality of via holes penetrate the second dielectric layer in a direction perpendicular to the substrate, and the side walls of the plurality of via holes expose the source line and the bit line; The channel structure and the gate structure are sequentially formed on the side walls of the plurality of via holes.
8. The preparation method according to claim 7, characterized in that: The plurality of vias also penetrate the first dielectric layer and the conductive layer.
9. A storage system, characterized in that: include: The three-dimensional memory as claimed in any one of claims 1 to 4; A controller is electrically connected to the three-dimensional memory.
10. An electronic device, characterized in that: Comprising the storage system as claimed in claim 9.