A MOSFET device with electric field and carrier modulation

Abstract

The application relates to a MOSFET device with electric field and carrier modulation, and belongs to the technical field of semiconductor devices. The device is provided with a P-pillar region between a polysilicon doped region of a gate and an N+ region of a drain to form a super-junction extended gate. By introducing the super-junction extended gate, in the case of forward conduction, a positive voltage is added to the gate and extended to the entire P-pillar, an electron accumulation region is formed in the drift region close to the oxide layer region, thereby reducing the specific on-resistance of the device and improving the transconductance. In the case of blocking voltage, a high voltage is added to the drain of the device, and a mutual depletion effect is generated between the P-pillar region and the drift region, which jointly modulates and optimizes the electric field distribution of the drift region of the MOSFET device, so that the device has a higher breakdown voltage BV, thereby obtaining a higher device merit value, and finally improving the static performance of the device.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device technology and relates to a MOSFET device with electric field and carrier modulation. Background Technology

[0002] Power semiconductor devices are among the fundamental components of electronic products and core components of modern electronic power systems, serving as switches, drivers, and rectifiers. Among them, the most typical MOS-gated high-voltage power device used in low-to-medium power applications is the power MOSFET. MOSFET (Metal Oxide Semiconductor Field-Effect Transistor) is a power semiconductor device widely used in various electronic products and systems. Due to its advantages such as simple drive circuitry, fast switching speed, negative temperature coefficient of conduction current, low manufacturing cost, and mature technology, MOSFET has become the dominant device in the 10–900V rated voltage range. Data processing, consumer electronics, industrial electronics, and wireless communication all have huge market demand for MOSFETs. Due to this large market demand, China's MOSFET industry has developed rapidly in recent years. Based on the different directions of internal current flow, power MOSFETs can be divided into lateral power MOSFETs and vertical power MOSFETs. Among them, the vertical power MOSFET was proposed by H.W. Collins et al. in 1979. It adopts a self-aligned double diffusion process, forming a conductive channel through the lateral diffusion difference of the two diffusions, which greatly improves the voltage withstand level and reliability of the device. The vertical power MOSFET combines the advantages of bipolar transistors and ordinary MOS devices. Compared with bipolar transistors, it has higher input impedance, lower drive power, and better frequency characteristics.

[0003] The key to high-voltage power MOSFET design is achieving both low specific on-resistance (Ron,sp) and high off-state breakdown voltage (BV). However, existing high-voltage power MOSFETs generally employ a "unipolar conduction + neutral region drift" current transport mode, where current is transported by carriers ionized from impurities in the neutral drift region. Therefore, Ron,sp is inversely proportional to the doping concentration (Nd) in the drift region. However, to improve the breakdown voltage of power MOSFETs, it is necessary to reduce the doping concentration in the drift region and increase the drift region length (Ld). This results in a "silicon limit" relationship between the breakdown voltage and specific on-resistance of power MOSFETs: Ron,sp ∝ BV².5. This leads to a sharp increase in power dissipation as the breakdown voltage rises, thus reducing the efficiency of the power system. Effectively mitigating the "silicon limit" contradiction between the breakdown voltage and specific on-resistance of power MOSFETs has become a research hotspot and a critical issue in the industry.

[0004] Therefore, a new device structure needs to be designed to improve the key indicators of MOSFET static performance, such as lower on-resistance, higher breakdown voltage, and better figure of merit than traditional devices. Summary of the Invention

[0005] In view of this, the purpose of the present invention is to provide a MOSFET device with electric field and carrier modulation. By introducing a superjunction extended gate, a positive voltage is applied to the gate of the device under forward conduction, and the voltage is extended to the entire P-pillar. This causes an electron accumulation region to form in the N-type drift region near the silicon dioxide layer, thereby significantly reducing the specific on-resistance and increasing the transconductance. Under blocking voltage, a high voltage is applied to the drain of the device, and a mutual depletion effect occurs between the P-pillar and the N-type drift region. This effect jointly modulates and optimizes the electric field distribution in the N-type drift region of the MOSFET device, resulting in a higher breakdown voltage BV and thus a higher figure of merit, ultimately improving the static performance of the device.

[0006] To achieve the above objectives, the present invention provides the following technical solution:

[0007] A MOSFET device with electric field and carrier modulation includes: a source P+ region, a source N+ region, a P-well region, a drift region, a first drain N+ region, a polysilicon doped region, a P-pillar region, an oxide layer, a second drain N+ region, a drain P+ region, and metal electrodes for the source, drain, and gate.

[0008] The drift region is located on the surface of the first drain N+ region, the P-well region is located on the surface of the drift region, and the source P+ region and source N+ region are located on the surface of the P-well region.

[0009] In this device, the source P+ region, source N+ region, P-well region, drift region, and first drain N+ region are all located on one side of the oxide layer.

[0010] The second drain N+ region is located on the surface of the drain P+ region, the P-pillar region is located on the surface of the second drain N+ region, and the polysilicon doped region is located on the surface of the P-pillar region.

[0011] In this device, the polysilicon doped region, the P-pillar region, the second drain N+ region, and the drain P+ region are all located on the other side of the oxide layer.

[0012] Furthermore, the source metal electrode is located on the surface of the source P+ region and the source N+ region; the drain metal electrode is located at the bottom of the device and is in contact with the first drain N+ region, the oxide layer and the drain P+ region respectively; the gate metal electrode is located on the surface of the polysilicon doped region.

[0013] Furthermore, the oxide layer is made of silicon dioxide, and its thickness is preferably 0.05 μm.

[0014] Furthermore, the polycrystalline silicon doped region is P-type doped, and the preferred doping concentration is 1×10⁻⁶. 19 cm -3 .

[0015] Furthermore, the drift region is doped with N-type doping, and the preferred doping concentration is 1.3 × 10⁻⁶. 15 cm -3 .

[0016] The beneficial effects of this invention are as follows: Based on traditional MOSFET devices, this invention modifies the gate structure to propose a novel MOSFET device with electric field and carrier modulation. The proposed device adds a P-pillar region to the gate region, forming a superjunction extended gate. By introducing the superjunction extended gate, under forward conduction, a positive voltage is applied to the gate and extended to the entire P-pillar region, causing an electron accumulation region to form near the silicon dioxide oxide layer in the N-type drift region. This significantly reduces the specific on-resistance and increases the transconductance. Furthermore, under blocking voltage, a high voltage is applied to the drain, resulting in mutual depletion between the P-pillar region and the N-type drift region. This mutual modulation optimizes the electric field distribution in the N-type drift region, leading to a higher breakdown voltage (BV) and thus a higher figure of merit, ultimately improving the device's static performance. Therefore, the MOSFET device with electric field and carrier modulation proposed in this invention improves the static performance of traditional MOSFET devices.

[0017] Other advantages, objectives, and features of the invention will be set forth in part in the description which follows, and in part will be apparent to those skilled in the art from the following examination, or may be learned from practice of the invention. The objectives and other advantages of the invention can be realized and obtained through the following description. Attached Figure Description

[0018] To make the objectives, technical solutions, and advantages of the present invention clearer, the preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings, wherein:

[0019] Figure 1 This is a schematic diagram of the overall structure of a MOSFET device with electric field and carrier modulation proposed in an embodiment of the present invention;

[0020] Figure 2 This is a schematic diagram illustrating the working mechanism of a MOSFET device with electric field and carrier modulation proposed in an embodiment of the present invention. Figure 2 (a) is a mechanism diagram of the device under forward conduction. Figure 2 (b) is a mechanism diagram under the device's blocking withstand voltage condition;

[0021] Figure 3 The concentration in the drift region of the superjunction extended gate MOSFET, conventional trench gate MOSFET, superjunction trench gate MOSFET, and auxiliary gate MOSFET is 1.3 × 10⁻⁶. 15 cm -3 A comparison of breakdown voltages under different conditions;

[0022] Figure 4The electric field distribution in the drift region of a superjunction extended gate MOSFET, conventional trench gate MOSFET, superjunction trench gate MOSFET, and auxiliary gate MOSFET during avalanche breakdown is shown.

[0023] Figure 5 This study compares superjunction extended-gate MOSFETs, conventional trench-gate MOSFETs, superjunction trench-gate MOSFETs, and auxiliary-gate MOSFETs under conditions of 15V gate voltage, 25V drain voltage, and a doping concentration of 1.3×10⁻⁶. 15 cm -3 A comparison of the output characteristic curves of the four devices when forward conduction is shown in the following figure;

[0024] Figure 6 For superjunction extended gate MOSFETs and conventional trench gate MOSFETs, superjunction trench gate MOSFETs, and auxiliary gate MOSFETs, at a gate voltage of 15V and a doping concentration of 1.3 × 10⁻⁶, 15 cm -3 A comparison of the transfer characteristic curves of the four devices during forward conduction;

[0025] Figure 7 This is a graph showing the trends of breakdown voltage and specific on-resistance of four types of devices: superjunction extended gate MOSFET, conventional trench gate MOSFET, superjunction trench gate MOSFET, and auxiliary gate MOSFET, as a function of drift region concentration or charge compensation. Figure 7 (a) is a comparison graph showing the changes in breakdown voltage and specific on-resistance between a traditional trench gate MOSFET and an auxiliary gate MOSFET. Figure 7 (b) is a comparison graph of the breakdown voltage and specific on-resistance of the superjunction trench gate MOSFET and the superjunction extended gate MOSFET in this case.

[0026] Figure 8 A comparison of the silicon-limited relationships between superjunction extended gate MOSFETs and conventional trench gate MOSFETs, superjunction trench gate MOSFETs, and auxiliary gate MOSFETs;

[0027] Figure 9 A comparison chart showing the changes in feedback capacitance between superjunction extended gate MOSFETs and conventional trench gate MOSFETs, superjunction trench gate MOSFETs, and auxiliary gate MOSFETs;

[0028] Figure 10 A comparison chart of the reverse recovery performance of superjunction extended gate MOSFETs, conventional trench gate MOSFETs, superjunction trench gate MOSFETs, and auxiliary gate MOSFETs;

[0029] Figure 11 This is a schematic diagram of the fabrication process for the superjunction extended gate MOSFET device implemented in this case.

[0030] Reference numerals: 1-Source metal electrode; 2-Source P+ region; 3-Source N+ region; 4-P-well region; 5-Drift region; 6-First drain N+ region; 7-Drain metal electrode; 8-Gate metal electrode; 9-Polysilicon doped region; 10-P-pillar region; 11-Oxide layer; 12-Second drain N+ region; 13-Drain P+ region. Detailed Implementation

[0031] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0032] The accompanying drawings are for illustrative purposes only and are schematic diagrams, not actual pictures. They should not be construed as limiting the invention. To better illustrate the embodiments of the invention, some parts in the drawings may be omitted, enlarged, or reduced, and do not represent the actual product dimensions. It is understandable to those skilled in the art that some well-known structures and their descriptions may be omitted in the drawings.

[0033] In the accompanying drawings of the embodiments of the present invention, the same or similar reference numerals correspond to the same or similar components. In the description of the present invention, it should be understood that if terms such as "upper," "lower," "left," "right," "front," and "rear" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, they are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, the terms used to describe positional relationships in the drawings are only for illustrative purposes and should not be construed as limiting the present invention. For those skilled in the art, the specific meaning of the above terms can be understood according to the specific circumstances.

[0034] like Figure 1 As shown, a superjunction extended gate MOSFET device with electric field and carrier modulation proposed in an embodiment of the present invention is shown. The device includes: a source metal electrode 1, a source P+ region 2, a source N+ region 3, a P-well region 4, a drift region 5, a first drain N+ region 6, a drain metal electrode 7, a gate metal electrode 8, a polysilicon doped region 9, a P-pillar region 10, an oxide layer 11, a second drain N+ region 12, and a drain P+ region 13.

[0035] The right side of source P+ region 2 is adjacent to the left side of source N+ region 3, and its lower part is in contact with the upper part of P-well region 4. Source P+ region 2 has a length of 1.0 μm along the x-axis, 1.0 μm along the y-axis, and 1.0 μm along the z-axis, with a P-type impurity concentration of 1.0 × 10⁻⁶. 19 cm -3 .

[0036] The right side of the source N+ region 3 is adjacent to the left side of the oxide layer 11, the left side is adjacent to the source P+ region 2, and the lower part is in contact with the upper part of the P-well region 4. The source N+ region 3 has a length of 1.0 μm along the x-axis, 1.0 μm along the y-axis, and 1.0 μm along the z-axis, with an N-type impurity concentration of 1.0 × 10⁻⁶. 19 cm -3 .

[0037] The right side of P-well region 4 is adjacent to the left side of oxide layer 11. Above it, it contacts the lower part of source P+ region 2 and source N+ region 3, and below it, it contacts drift region 5. P-well region 4 has a length of 2.0 μm along the x-axis, 1.0 μm along the y-axis, and 0.6 μm along the z-axis. The concentration of P-type impurities is 2.0 × 10⁻⁶. 17 cm -3 .

[0038] The drift region 5 is in contact with the first drain N+ region 6 below, the P-well region 4 above, and the left side of the oxide layer 11 on its right. The drift region 5 has a length of 2.0 μm along the x-axis, 1.0 μm along the y-axis, and 13.4 μm along the z-axis, with an N-type impurity concentration of 1.3 × 10⁻⁶. 15 cm -3 .

[0039] The first drain N+ region 6 is in contact with the drift region 5 above, and its right side is in contact with the left side of the oxide layer 11. The first drain N+ region 6 has a length of 2.0 μm along the x-axis, a length of 1.0 μm along the y-axis, and a length of 1.0 μm along the z-axis, with an N-type impurity concentration of 1.0 × 10⁻⁶. 19 cm -3 .

[0040] The polysilicon doped region 9 is in contact with the P-pillar region 10 below and adjacent to the oxide layer 11 on the left. The polysilicon doped region 9 has a length of 2.0 μm along the x-axis, 1.0 μm along the y-axis, and 1.6 μm along the z-axis, with a P-type impurity concentration of 1.0 × 10⁻⁶. 19 cm -3 .

[0041] The P-pillar region 10 is in contact with the polysilicon doped region 9 above, the second drain N+ region 12 below, and adjacent to the oxide layer 11 on the left. The P-pillar region 10 has a length of 2.0 μm along the x-axis, 1.0 μm along the y-axis, and 13.4 μm along the z-axis, with a P-type impurity concentration of 1.3 × 10⁻⁶. 15 cm -3 .

[0042] The left side of oxide layer 11 is adjacent to source N+ region 3, P-well region 4, drift region 5, and first drain N+ region 6, while the right side is adjacent to polysilicon doped region 9, P-pillar region 10, second drain N+ region 12, and drain P+ region 13. The length of oxide layer 11 along the x-axis is 0.05 μm, along the y-axis is 1.0 μm, and along the z-axis is 16 μm.

[0043] The second drain N+ region 12 is in contact with the P-pillar region 10 above and the drain P+ region 13 below, and is in contact with the oxide layer 11 to its left. The second drain N+ region 12 has a length of 2.0 μm along the x-axis, 1.0 μm along the y-axis, and 0.5 μm along the z-axis, and the N-type impurity concentration is 1.0 × 10⁻⁶. 19 cm -3 .

[0044] The upper part of the drain P+ region 13 is in contact with the upper part of the second drain N+ region 12, and its left side is in contact with the oxide layer 11. The drain P+ region 13 has a length of 2.0 μm along the x-axis, a length of 1.0 μm along the y-axis, and a length of 0.5 μm along the z-axis, with a P-type impurity concentration of 1.0 × 10⁻⁶. 19 cm -3 .

[0045] The source metal electrode 1 is in contact with the source P+ region 2 and the source N+ region 3 below.

[0046] The drain metal electrode 7 is in contact with the first drain N+ region 6 and the drain P+ region 13.

[0047] The gate metal electrode 8 is in contact with the polysilicon doped region 9 below.

[0048] Figure 2 The diagram shown illustrates the working mechanism of a MOSFET device (superjunction extended gate MOSFET) with electric field and carrier modulation proposed in an embodiment of the present invention. Figure 2(a) is a mechanism diagram of the device under forward conduction. It can be seen that under forward conduction, when a positive voltage is applied to the gate and drain, the P-pillar region 10 below the P-type impurity-doped polysilicon region (polysilicon doped region 9) extends the positive voltage to the second drain N+ region 12 and cuts it off. Figure 2 (b) is a mechanism diagram under the blocking withstand voltage condition of the device. It can be seen that under the blocking withstand voltage condition, a high voltage is applied to the drain. The device is withstand voltage by the P-well region 4 / drift region 5 and the second drain N+ region 12 / P-pillar region 10. At the same time, the drift region 5 and the P-pillar region 10 will deplete each other.

[0049] Figure 3 The concentration in the drift region of the superjunction extended gate MOSFET, conventional trench gate MOSFET, superjunction trench gate MOSFET, and auxiliary gate MOSFET is 1.3 × 10⁻⁶. 15 cm -3 A comparison chart of breakdown voltages under different conditions. From Figure 3 It can be seen that, under the same conditions, traditional trench-gate MOSFETs and auxiliary-gate MOSFETs will break down earlier, and the breakdown voltage of the superjunction trench-gate MOSFET is slightly higher than that of the superjunction extended-gate MOSFET of this invention. This is because the silicon dioxide layer thickness in the superjunction extended-gate MOSFET is set very thin, only 0.05μm. Therefore, under the blocking voltage, the N-type doped drift region 5 in the device will mutually deplete with the P-pillar region 10, jointly modulating and optimizing the electric field distribution in the drift region of the device, thus the device can obtain a higher breakdown voltage. This breakdown voltage mechanism is the same as that of the superjunction trench-gate MOSFET, so the breakdown voltages of the two devices are roughly the same. However, since there is no silicon dioxide isolation layer between the N-pillar and P-pillar in the superjunction trench-gate MOSFET, they will mutually deplete more completely, resulting in a higher breakdown voltage. The traditional trench-gate MOSFET and auxiliary-gate MOSFET devices that break down earlier are due to the lack of an optimized structure for electric field modulation in the drift region, hence their breakdown voltage is lower than that of the superjunction extended-gate MOSFET. Figure 3 The simulation results show that the breakdown voltages BV of the superjunction extended gate MOSFET, the conventional trench gate MOSFET, the superjunction trench gate MOSFET, and the auxiliary gate are 325.0V, 224.0V, 325.9V, and 242.3V, respectively.

[0050] Figure 4 This diagram illustrates the longitudinal electric field distribution in the drift region of a superjunction extended-gate MOSFET, a conventional trench-gate MOSFET, a superjunction trench-gate MOSFET, and an auxiliary-gate MOSFET under avalanche breakdown conditions. Figure 4It can be seen that the electric field distribution in the drift region of the superjunction extended gate MOSFET and the superjunction trench gate MOSFET is very uniform compared to the other two comparative devices. This is because both structures employ a superjunction structure, where the P-type pillars and N-type pillars mutually deplete each other, further modulating and optimizing the electric field distribution in the drift region. Furthermore, from... Figure 4 As can be seen, traditional trench gate MOSFETs and auxiliary gate MOSFETs have a peak electric field of about 14μm in the Z direction. This is because the breakdown voltage of these two devices is the breakdown voltage of the N-type drift region / P-well region, so breakdown occurs here.

[0051] Figure 5 This study compares superjunction extended-gate MOSFETs, conventional trench-gate MOSFETs, superjunction trench-gate MOSFETs, and auxiliary-gate MOSFETs under conditions of 15V gate voltage, 25V drain voltage, and a doping concentration of 1.3×10⁻⁶. 15 cm -3 Under these conditions, the output characteristic curves of the four devices during forward conduction are shown. From... Figure 5 As can be seen, under the same conditions, the superjunction extended gate MOSFET and the auxiliary gate MOSFET of the comparison device have the best and roughly the same conduction performance, while the conventional trench gate MOSFET and the superjunction trench gate MOSFET have poor forward conduction performance. This is because the introduction of the superjunction extended gate in the superjunction extended gate MOSFET extends the positive gate potential to the entire P-pillar region. The P-pillar, silicon dioxide isolation layer, and N-type pillar are similar to the MIS structure. When a positive voltage is applied to the gate, a large number of electrons accumulate on the right side of the N-drift region, resulting in a bulk electron accumulation effect. Therefore, a high-concentration electron accumulation layer is generated in its drift region, further increasing the electron concentration in the drift region, greatly reducing the specific on-resistance of the device, and improving the output characteristics. After calculation, the specific on-resistance R of the superjunction extended gate MOSFET, conventional trench gate MOSFET, superjunction trench gate MOSFET, and auxiliary gate MOSFET are... on,sp They are respectively: 3.17mΩ·cm 2 24.5mΩ·cm 2 10.6mΩ·cm 2 3.41mΩ·cm 2 .

[0052] Figure 6 For superjunction extended gate MOSFETs and conventional trench gate MOSFETs, superjunction trench gate MOSFETs, and auxiliary gate MOSFETs, at a gate voltage of 15V and a doping concentration of 1.3 × 10⁻⁶, 15 cm -3 Under the condition of forward conduction, the transfer characteristic curves of the four devices are shown. The drain-source voltage V of the devices is set. DS The gate-source voltage is 1V. GSThe scan starts at 0V and stops at 15V. Figure 6 As can be seen, the current control capability of the superjunction extended gate MOSFET device and the comparative auxiliary gate MOSFET device are similar, and the superjunction extended gate MOSFET device is significantly better than the other two comparative devices. The superjunction extended gate MOSFET generates an electron accumulation effect by extending the P-pillar of the gate voltage, resulting in a high-concentration electron channel on the right side of the drift region. This further enhances the conductivity of the device and strengthens the gate's control over current I. DS The control capability significantly improves the transconductance of the device. m This further improves the transfer characteristics of the devices. By differentiating the transfer characteristic curves of the four devices, the peak transconductance g of the superjunction extended gate MOSFET, conventional trench gate MOSFET, superjunction trench gate MOSFET, and auxiliary gate MOSFET are obtained. m The values ​​are 14.3 mS / mm, 9.1 mS / mm, 10.0 mS / mm and 13.9 mS / mm, respectively.

[0053] Figure 7 The breakdown voltage and specific on-resistance of four types of devices—superjunction extended gate MOSFET, conventional trench gate MOSFET, superjunction trench gate MOSFET, and auxiliary gate MOSFET—are shown to change with drift region concentration or charge compensation. Figure 7 (a) Comparison of the breakdown voltage and specific on-resistance of traditional trench gate MOSFET and auxiliary gate MOSFET; Figure 7 (b) is a comparison graph showing the changes in breakdown voltage and specific on-resistance between the superjunction trench gate MOSFET and the superjunction extended gate MOSFET of this invention. From Figure 7 As shown in (a), the doping concentration in the drift region is 7 × 10⁻⁶. 14 cm -3 Up to 1.5×10 15 cm -3 Within this range, as the doping concentration of the N-type drift region increases, the breakdown voltage and specific on-resistance of both traditional trench-gate MOSFETs and auxiliary-gate MOSFETs gradually decrease. From Figure 7 As shown in (b), since both superjunction extended gate MOSFETs and superjunction trench gate MOSFETs contain superjunction structures, the doping concentration ratio (Q) of their P-pillars and N-pillars is... N / Q P This affects the withstand voltage BV and the specific on-resistance R. on,spFor superjunction extended gate MOSFETs, when QN / QP < 1.0, the breakdown voltage BV increases with the ratio, because when the N-pillar concentration is too low, the N-pillars will deplete prematurely, leading to breakdown. When QN / QP > 1.0, BV decreases with the ratio, because when the N-pillar concentration is too high, the depletion region width narrows, and the maximum electric field strength increases, leading to breakdown. Furthermore, due to the high concentration of electrons accumulated in the device under forward conduction conditions, the specific on-resistance R... on,sp It decreases slightly as the ratio increases. At this point, the breakdown voltage BV of the superjunction extended gate MOSFET is 325V, which is higher than the on-resistance R. on,sp It is 3.17 mΩ·cm 2 .

[0054] Figure 8 This chart compares the silicon limit relationship between the superjunction extended gate MOSFET and conventional trench gate MOSFETs, superjunction trench gate MOSFETs, and auxiliary gate MOSFETs. As can be seen from the chart, the superjunction extended gate MOSFET device implemented in this case breaks the contradictory "silicon limit" relationship of MOSFET devices using Single Resulf, Double Resulf, and Triple Resulf technologies, and its figure of merit is higher than the other three comparative devices. The figure of merit for the superjunction extended gate MOSFET, conventional trench gate MOSFET, superjunction trench gate MOSFET, and auxiliary gate MOSFET is 31.8 MW / cm². 2 2.87MW / cm 2 9.72MW / cm 2 26.38MW / cm 2 By adding a superjunction extended gate, the superjunction extended gate MOSFET achieves a higher breakdown voltage, but at the same time, due to the electron accumulation effect, its specific on-resistance is also reduced, which better solves the "silicon limit" relationship of traditional devices and greatly improves the static performance of the device.

[0055] Figure 9 This section compares the changes in feedback capacitance between a superjunction extended-gate MOSFET and a conventional trench-gate MOSFET, a superjunction trench-gate MOSFET, and an auxiliary-gate MOSFET. Because the gate of the superjunction extended-gate MOSFET is connected to the drain via a P-pillar, its gate-drain distance is shortened, so initially C... RSS Maximum. As voltage increases, the superjunction extended gate MOSFET exhibits a C value similar to the other comparative devices. RSS This is because the P-pillar accelerates the depletion of the N-type drift region, leading to C RSS Decrease. From Figure 9As can be seen, the feedback capacitance curve of the superjunction extended gate MOSFET is slightly lower than that of the other three structures. The feedback capacitance C of the superjunction extended gate MOSFET, conventional trench gate MOSFET, superjunction trench gate MOSFET, and auxiliary gate MOSFET are shown in the figure. RSS They are: 92.8 pF / cm 2 156.2 pF / cm 2 110.9 pF / cm 2 129pF / cm 2 .

[0056] Figure 10 This section compares the reverse recovery performance of superjunction extended-gate MOSFETs with that of conventional trench-gate MOSFETs, superjunction trench-gate MOSFETs, and auxiliary-gate MOSFETs. Figure 10 It can be seen that the reverse recovery time of the superjunction extended gate MOSFET is relatively short. This is because the presence of the P-pillar modulates the electric field in the drift region, resulting in a uniform electric field distribution, which allows charges to move rapidly within the electric field. The reverse recovery times of the conventional trench gate MOSFET, the superjunction trench gate MOSFET, and the auxiliary gate MOSFET are respectively t RR The reverse recovery times were 30.61 ns, 19.49 ns, and 20.03 ns, respectively, while the proposed superjunction extended gate MOSFET device has a shorter reverse recovery time of 16.29 ns. The peak reverse recovery current If of the superjunction extended gate MOSFET, conventional trench gate MOSFET, superjunction trench gate MOSFET, and auxiliary gate MOSFET are compared. RRM They are: 184.55 A / cm 2 161.29A / cm 2 241.25A / cm 2 115.11A / cm 2 Through the analysis of Figure 9 Integrating the curve yields the reverse recovery charge Q of the device. RR The reverse recovery charge Q of the superjunction extended gate MOSFET and the comparative device RR They are: 2.07 μC / cm 2 3.53μC / cm 2 2.79μC / cm 2 1.78μC / cm 2 .

[0057] Table 1 Comparison of various relevant parameters of different devices

[0058]

[0059]

[0060] Another embodiment of the present invention proposes a fabrication process for MOSFET devices with electric field and carrier modulation, such as... Figure 11 As shown. The main processes include: First, etching and oxidizing the substrate to etch out the positions of the P-pillar and polysilicon doped regions; second, epitaxy and ion implantation to form the source P+ and N+ regions, as well as the P-well, drain P+, and drain N+ regions; third, substrate thinning, ion implantation, and etching again; fourth, polysilicon doping; and finally, deposition of metal electrodes to form the source, gate, and drain metals.

[0061] In summary, this invention provides a MOSFET device with electric field and carrier modulation. A superjunction extended gate is formed by introducing a P-type doped P-pillar portion beneath the polysilicon-doped gate portion of the MOSFET device. A silicon dioxide layer is introduced in the middle of the MOSFET device, dividing the entire device into a control region and a conduction region. The introduction of the superjunction extended gate allows a positive voltage to be applied to the gate during forward conduction, extending the voltage and creating an electron accumulation region near the silicon dioxide layer in the N-type drift region. This modulates the transport range and concentration of carriers, significantly reducing the specific on-resistance and increasing the transconductance. During blocking, a high voltage is applied to the drain, causing mutual depletion between the P-pillar and the N-type drift region. This mutually modulates and optimizes the electric field distribution in the N-type drift region of the MOSFET device, resulting in a higher breakdown voltage (BV) and thus a higher figure of merit. Therefore, this invention proposes a MOSFET device with electric field and carrier modulation that improves the static performance of traditional MOSFET devices without compromising dynamic performance.

[0062] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A MOSFET device with electric field and carrier modulation, characterized in that, The device includes a source P+ region (2), a source N+ region (3), a P-well region (4), a drift region (5), a first drain N+ region (6), a polysilicon doped region (9), a P-pillar region (10), an oxide layer (11), a second drain N+ region (12), and a drain P+ region (13). The drift region (5) is located on the surface of the first drain N+ region (6), the P-well region (4) is located on the surface of the drift region (5), and the source P+ region (2) and the source N+ region (3) are located on the surface of the P-well region (4); the source P+ region (2), the source N+ region (3), the P-well region (4), the drift region (5) and the first drain N+ region (6) are all located on one side of the oxide layer (11); The second drain N+ region (12) is located on the surface of the drain P+ region (13), the P-pillar region (10) is located on the surface of the second drain N+ region (12), and the polysilicon doped region (9) is located on the surface of the P-pillar region (10); the polysilicon doped region (9), the P-pillar region (10), the second drain N+ region (12), and the drain P+ region (13) are all located on the other side of the oxide layer (11).

2. The MOSFET device according to claim 1, characterized in that, The device also includes a source metal electrode (1), a drain metal electrode (7), and a gate metal electrode (8); wherein the source metal electrode (1) is located on the surface of the source P+ region (2) and the source N+ region (3); the drain metal electrode (7) is located at the bottom of the device and is in contact with the first drain N+ region (6), the oxide layer (11), and the drain P+ region (13), respectively; the gate metal electrode (8) is located on the surface of the polysilicon doped region (9).

3. The MOSFET device according to claim 1 or 2, characterized in that, The thickness of the oxide layer (11) is 0.05 μm.

4. The MOSFET device according to claim 1 or 2, characterized in that, The oxide layer (11) is made of silicon dioxide.

5. The MOSFET device according to claim 1 or 2, characterized in that, The doping type of the polycrystalline silicon doped region (9) is P-type doping.

6. The MOSFET device according to claim 1 or 2, characterized in that, The doping concentration of the polycrystalline silicon doped region (9) is 1×10⁻⁶. 19 cm -3 .

7. The MOSFET device according to claim 1, characterized in that, The drift region (5) is N-type doped.

8. The MOSFET device according to claim 1, characterized in that, The doping concentration of the drift region (5) is 1.3 × 10⁻⁶. 15 cm -3 .

Images