Back-contact battery with a specific antireflection layer structure, its manufacturing method, and photovoltaic module

Abstract

The present invention belongs to the technical field of back contact batteries, and particularly relates to a back contact battery with a specific anti-reflection layer structure, a manufacturing method thereof, and a photovoltaic module, including an oxide layer provided on the light-receiving surface of a silicon wafer, and further including a first hydrogenated silicon nitride layer, a second hydrogenated silicon nitride layer, and a third hydrogenated silicon nitride layer sequentially provided on the outer surface of the oxide layer to form an anti-reflection layer; wherein, the effective hydrogen doping concentration of the first hydrogenated silicon nitride layer, the second hydrogenated silicon nitride layer, and the third hydrogenated silicon nitride layer gradually increases, and the thickness gradually increases; and the corrosion rate and corrosion resistance time of the first hydrogenated silicon nitride layer, the second hydrogenated silicon nitride layer, and the third hydrogenated silicon nitride layer are within a suitable range. The back contact battery of the present invention can maximize the protection of the oxide layer while injecting more hydrogen, effectively passivate defects and impurities, achieve the optimal optical effect and passivation level, improve the conversion efficiency and stability of the battery; and at the same time improve the density.

Description

Technical Field

[0001] The present invention belongs to the technical field of back contact batteries, and particularly relates to a back contact battery with a specific antireflection layer structure, a manufacturing method thereof, and a photovoltaic module. Background Art

[0002] In existing back contact batteries, the light-receiving surface is usually passivated by an intrinsic amorphous silicon layer + an N-type amorphous silicon layer, or by a tunneling oxide layer + an N-type polysilicon layer or an N-type oxygen-doped amorphous layer, and then an antireflection layer is stacked.

[0003] Hydrogen passivation has long been proven to be able to effectively passivate defects and impurities and improve the electrical properties of silicon materials. However, if hydrogen passivation is directly carried out on the surface of silicon oxide, the silicon oxide passivation layer will be severely damaged. And if hydrogen passivation is carried out after the antireflection layer, due to the too thick film layer of the silicon nitride antireflection layer, the effect of hydrogen passivation will be greatly reduced.

[0004] It should be noted that this part of the content of the present invention only provides background technology related to the present invention, and does not necessarily constitute prior art or well-known technology. Summary of the Invention

[0005] The purpose of the present invention is to overcome the defect of poor hydrogen passivation effect of back contact batteries existing in the prior art, and provide a back contact battery with a specific antireflection layer structure, a manufacturing method thereof, and a photovoltaic module. This back contact battery can maximize the protection of the oxide layer while injecting more hydrogen, effectively passivate defects and impurities, achieve the optimal optical effect and passivation level, improve the conversion efficiency and stability of the battery; and improve the compactness at the same time.

[0006] To achieve the above purpose, in the first aspect, the present invention provides a back contact battery with a specific antireflection layer structure, including a silicon wafer, a first semiconductor layer and a second semiconductor layer alternately arranged on the back surface of the silicon wafer, an oxide layer arranged on the light-receiving surface of the silicon wafer, and further including a first hydrogenated silicon nitride layer, a second hydrogenated silicon nitride layer, and a third hydrogenated silicon nitride layer sequentially arranged on the outer surface of the oxide layer to form an antireflection layer; wherein, the effective hydrogen doping concentration of the first hydrogenated silicon nitride layer, the second hydrogenated silicon nitride layer, and the third hydrogenated silicon nitride layer gradually increases, and the thickness gradually increases; and the etching rates of the first hydrogenated silicon nitride layer, the second hydrogenated silicon nitride layer, and the third hydrogenated silicon nitride layer are 0.20 nm / s - 0.23 nm / s, 0.16 nm / s - 0.20 nm / s, and 0.10 nm / s - 0.16 nm / s respectively, and the corrosion resistance time ratios of the first hydrogenated silicon nitride layer, the second hydrogenated silicon nitride layer, and the third hydrogenated silicon nitride layer are 1:(2 - 4.5):(5 - 13.5), wherein, the etching rate is obtained by etching the corresponding hydrogenated silicon nitride layer with a 5% hydrofluoric acid solution by mass concentration, and the corrosion resistance time is the time required to completely remove the corresponding hydrogenated silicon nitride layer with a 5% hydrofluoric acid solution by mass concentration.

[0007] In some preferred embodiments of the present invention, the ratio of the effective hydrogen doping concentrations of the first hydrogen-doped silicon nitride layer, the second hydrogen-doped silicon nitride layer, and the third hydrogen-doped silicon nitride layer is 1:(1.5 - 4):(2.5 - 6), and / or the effective hydrogen doping concentrations of the first hydrogen-doped silicon nitride layer, the second hydrogen-doped silicon nitride layer, and the third hydrogen-doped silicon nitride layer are 1.5×10 19 cm -3 -4×10 19 cm -3 、4×10 19 cm -3 -6×10 19 cm -3 、7×10 19 cm -3 -9×10 19 cm -3 respectively.

[0008] In some preferred embodiments of the present invention, the ratio of the thicknesses of the first hydrogen-doped silicon nitride layer, the second hydrogen-doped silicon nitride layer, and the third hydrogen-doped silicon nitride layer is 1:(2 - 3):(4 - 6).

[0009] In some preferred embodiments of the present invention, the thickness of the first hydrogen-doped silicon nitride layer is 15 - 25 nm, the thickness of the second hydrogen-doped silicon nitride layer is 35 - 45 nm, and the thickness of the third hydrogen-doped silicon nitride layer is 60 - 90 nm.

[0010] In some preferred embodiments of the present invention, the ratio of the sum of the thicknesses of the first hydrogen-doped silicon nitride layer, the second hydrogen-doped silicon nitride layer, and the third hydrogen-doped silicon nitride layer to the thickness of the oxide layer is (19 - 35):1, and / or the thickness of the oxide layer is 3 - 5 nm.

[0011] Preferably, the corrosion resistance time of the first hydrogen-doped silicon nitride layer is 65 - 125 s.

[0012] In some preferred embodiments of the present invention, the first semiconductor layer includes a first passivation layer and a first doped silicon layer, the second semiconductor layer includes a second passivation layer and a second doped silicon layer, and the first passivation layer and the second passivation layer are each independently a tunneling oxide layer or an intrinsic silicon layer.

[0013] In some preferred embodiments of the present invention, the first semiconductor layer includes a tunneling oxide layer and a first doped polysilicon layer, the second semiconductor layer includes an intrinsic silicon layer and a second doped silicon layer; the ratio of the sum of the thicknesses of the first hydrogen-doped silicon nitride layer, the second hydrogen-doped silicon nitride layer, and the third hydrogen-doped silicon nitride layer to the thicknesses of the intrinsic silicon layer and the tunneling oxide layer is (50 - 160):(3 - 15):1.

[0014] Preferably, the oxide layer is formed by an oxidation annealing process of the first semiconductor layer.

[0015] In some preferred embodiments of the present invention, both ends of the second semiconductor layer extend outwardly to cover a part of the back surface of the adjacent first semiconductor layer, and a first semiconductor opening region that does not cover the second semiconductor layer is formed on the back surface of the first semiconductor layer. A second semiconductor opening region is formed between adjacent first semiconductor layers. The second semiconductor opening region and the first semiconductor opening region are arranged at intervals, and the region between them is an interval region; in the interval region, a mask layer is provided or not provided between the first semiconductor layer and the second semiconductor layer.

[0016] In some preferred embodiments of the present invention, the back contact battery further includes a metal electrode and a conductive film layer disposed on the outer surfaces of the first semiconductor layer and the second semiconductor layer. An isolation groove is formed on a part of the conductive film layer located in the interval region; the metal electrode is disposed on the outer surfaces of the respective conductive film layers corresponding to the second semiconductor opening region and the first semiconductor opening region.

[0017] Second, the present invention provides a manufacturing method of a back contact battery, including the following steps:

[0018] S1. Provide a double-sided polished silicon wafer;

[0019] S2. Sequentially form a first semiconductor layer corresponding film layer and a mask layer on the back surface of the silicon wafer; annealing is not performed during the process of forming the first semiconductor layer corresponding film layer;

[0020] S3. Perform etching and opening on the back surface obtained in S2 to form a second semiconductor opening region;

[0021] S4. Through texturing and cleaning, then select whether to perform the step of removing the mask layer outside the second semiconductor opening region on the back surface of the silicon wafer according to needs;

[0022] S5. Perform oxidation annealing on the first semiconductor layer corresponding film layer obtained in S4 to form a first semiconductor layer, and simultaneously form an oxide layer on the light-receiving surface of the silicon wafer during the oxidation annealing process;

[0023] S6. Sequentially deposit a first hydrogenated silicon nitride layer, a second hydrogenated silicon nitride layer, and a third hydrogenated silicon nitride layer on the outer surface of the oxide layer on the light-receiving surface of the silicon wafer to form an antireflection layer;

[0024] During the control of deposition, the hydrogen flow rates incorporated into the first hydrogenated silicon nitride layer, the second hydrogenated silicon nitride layer, and the third hydrogenated silicon nitride layer gradually increase, and the deposition times gradually increase. Also, control the corrosion rates of the obtained first hydrogenated silicon nitride layer, second hydrogenated silicon nitride layer, and third hydrogenated silicon nitride layer to be 0.20 nm / s - 0.23 nm / s, 0.16 nm / s - 0.20 nm / s, and 0.10 nm / s - 0.16 nm / s respectively. The corrosion resistance times of the first hydrogenated silicon nitride layer, second hydrogenated silicon nitride layer, and third hydrogenated silicon nitride layer are in the ratio of 1:(2 - 4.5):(5 - 13.5). Herein, the corrosion rate is obtained by subjecting the corresponding hydrogenated silicon nitride layer to corrosion testing with a 5% hydrofluoric acid solution, and the corrosion resistance time is the time required for the complete removal of the corresponding hydrogenated silicon nitride layer by a 5% hydrofluoric acid solution;

[0025] S7. Then perform backwashing. The backwashing solution includes an alkaline solution and an acid solution containing hydrofluoric acid. During this period, control the ratio of the corrosion resistance time of the third hydrogenated silicon nitride layer to the treatment time of the acid solution to be (6 - 12):1;

[0026] S8. Deposit a second semiconductor layer on the back surface obtained in S7.

[0027] In some preferred embodiments of the present invention, the hydrogen flow rate incorporated into the first hydrogenated silicon nitride layer during deposition is 1000 - 2000 sccm, the hydrogen flow rate incorporated into the second hydrogenated silicon nitride layer during deposition is 3000 - 4000 sccm, and the hydrogen flow rate incorporated into the third hydrogenated silicon nitride layer during deposition is 5000 - 6000 sccm.

[0028] In some preferred embodiments of the present invention, the conditions for depositing the first hydrogenated silicon nitride layer include: introducing silane, ammonia, and hydrogen, with a reaction temperature of 400 - 450 °C, a power of 6000 - 7000 W, and a reaction time of 150 - 300 s; the conditions for depositing the second hydrogenated silicon nitride layer include: introducing silane, ammonia, and hydrogen, with a reaction temperature of 400 - 500 °C, a power of 5000 - 6000 W, and a reaction time of 300 - 500 s; the conditions for depositing the third hydrogenated silicon nitride layer include: introducing silane, ammonia, and hydrogen, with a reaction temperature of 400 - 500 °C, a power of 4000 - 5000 W, and a reaction time of 500 - 800 s.

[0029] In some preferred embodiments of the present invention, in S6, the conditions for depositing the first hydrogenated silicon nitride layer, the second hydrogenated silicon nitride layer, and the third hydrogenated silicon nitride layer each independently further include: a silane flow rate of 1200 - 1800 sccm, an ammonia flow rate of 5000 - 10000 sccm, and a reaction pressure of 1500 - 3000 mtorr.

[0030] In some preferred embodiments of the present invention, the conditions for the oxidation annealing in S5 include: the annealing temperature is 850 - 950 °C, the annealing pressure is 100 mbar - 500 mbar, oxygen and nitrogen are introduced, the oxygen flow rate is 1000 - 3000 sccm, the nitrogen flow rate is 3000 - 10000 sccm, and the annealing time is 10 - 60 min.

[0031] In some preferred embodiments of the present invention, in S7, the alkaline solution is a weak alkaline solution, and the backwashing is carried out in the way of first cleaning with the weak alkaline solution, then cleaning with water, and finally cleaning with the acidic solution.

[0032] Further preferably, the weak alkaline solution is a mixed aqueous solution containing ammonia water and hydrogen peroxide. The mass concentration of ammonia water in the weak alkaline solution is 2% - 5%, and the mass concentration of hydrogen peroxide is 3% - 5%.

[0033] Preferably, the mass concentration of hydrofluoric acid in the acidic solution is 1% - 10%.

[0034] In some preferred embodiments of the present invention, the conditions for the backwashing include: the treatment temperature is 20 °C - 40 °C, the treatment time of the acidic solution is 0.5 - 2 min, and the treatment time of the weak alkaline solution is 0.1 - 2 min.

[0035] In some preferred embodiments of the present invention, the manufacturing method of the back contact battery further includes:

[0036] S9. Etch openings on a part of the second semiconductor layer on the back of the silicon wafer to form a first semiconductor opening area arranged at intervals with the second semiconductor opening area, and then clean;

[0037] S10. Deposit a conductive film layer on the back obtained in S9;

[0038] S11. Etch openings on a part of the conductive film layer located between the first semiconductor opening area and the second semiconductor opening area to form isolation grooves;

[0039] S12. Form metal electrodes on the outer surfaces of the corresponding conductive film layers in the areas where the first semiconductor opening area and the second semiconductor opening area are located respectively.

[0040] In a third aspect, the present invention provides a back contact battery, which is obtained by the manufacturing method of the back contact battery described in the second aspect.

[0041] In a fourth aspect, the present invention provides a photovoltaic module, which includes the back contact battery having a specific antireflection layer structure described in the first aspect, or includes the back contact battery described in the third aspect.

[0042] Beneficial effects:

[0043] Through the above technical solutions, the present invention deposits a first hydrogenated silicon nitride layer, a second hydrogenated silicon nitride layer, and a third hydrogenated silicon nitride layer on the outer surface of the light-receiving surface oxide layer, and the effective hydrogen doping concentrations of the three gradually increase and the thicknesses gradually increase. As a hydrogenated anti-reflection layer for staged hydrogen doping, it can protect the oxide layer to the greatest extent while injecting more hydrogen, effectively passivate defects and impurities, achieve the optimal optical effect and passivation level, and improve the conversion efficiency of the battery; at the same time, gradient hydrogen doping can slow down the silicon nitride deposition rate, improve the density, and make the corrosion rates of the hydrogenated silicon nitride layers within a suitable low range. The lower the corrosion rate, the better its density, further improving the battery conversion efficiency.

[0044] Among them, the present invention also controls the ratio of the corrosion resistance time of each hydrogenated silicon nitride layer to be appropriate, which is beneficial for each hydrogenated silicon nitride layer to take into account passivation while being able to resist the corrosion of subsequent chemical solutions during preparation, reduce the impact on passivation, and is conducive to improving the conversion efficiency and stability of the battery, preparing for mass production.

[0045] In the preferred embodiment of the present invention, the oxide layer is formed through the oxidation annealing process of the first semiconductor layer. Although the conventional N-type polycrystalline layer on the front surface passivation is not provided, it will reduce the field passivation, but the oxide layer formed by oxidation annealing is thicker, more dense, and the anti-reflection layer used is a specific hydrogenated silicon nitride, which makes up for the field passivation, can increase the hydrogen injection amount while protecting the oxide layer, and makes the hydrogen passivation effect reach the best, thus being more conducive to improving the overall passivation level and further improving the battery conversion efficiency.

[0046] In the manufacturing method of the present invention, the corrosion rates and the ratio of the corrosion resistance time of the deposited first hydrogenated silicon nitride layer, second hydrogenated silicon nitride layer, and third hydrogenated silicon nitride layer are controlled within their respective appropriate ranges, and in cooperation with subsequent backwashing using a backwashing solution including an acid solution, the acid solution in the backwashing will corrode part of the silicon nitride to achieve the effect of cleaning the surface and making the texture surface more rounded, and at the same time can ensure that after subsequent backwashing, the anti-reflection layer still has sufficient thickness, thereby being conducive to ensuring the anti-reflection effect of the front anti-reflection layer and protecting the passivation effect of the front film layer, and further ensuring the short-circuit current of the battery and improving the passivation level of the battery. The present invention also cooperates with the formation of an oxide layer on the light-receiving surface of the silicon wafer during the oxidation annealing process, greatly saving equipment costs.

[0047] In the manufacturing method of the present invention, the ratio of the corrosion resistance time of the third hydrogenated silicon nitride layer to the treatment time of the acid solution is also controlled within an appropriate range, which can ensure that the formed hydrogenated silicon nitride anti-reflection layer is not corroded by the solution during the acid solution treatment process, ensure the anti-reflection effect of the light-receiving surface, and facilitate further improving the battery conversion efficiency and the stability of the battery. Description of the Drawings

[0048] To more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the attached drawings required for the embodiments. It should be understood that the following attached drawings only show some embodiments of the present invention, and thus should not be regarded as limiting the scope. For those of ordinary skill in the art, without creative efforts, other relevant attached drawings can also be obtained based on these attached drawings.

[0049] Figure 1 Structural schematic diagram of the silicon wafer after polishing and cleaning in the embodiment of the present invention;

[0050] Figure 2 Structural schematic diagram of forming a first semiconductor layer and a mask layer on the back surface of the silicon wafer in the embodiment of the present invention;

[0051] Figure 3 Structural schematic diagram of the silicon wafer after oxidation annealing in the embodiment of the present invention;

[0052] Figure 4 Structural schematic diagram of forming an antireflection layer on the light-receiving surface of the silicon wafer in the embodiment of the present invention;

[0053] Figure 5 Structural schematic diagram of forming a second semiconductor layer and a first semiconductor opening region on the back surface of the silicon wafer in the embodiment of the present invention;

[0054] Figure 6 Structural schematic diagram of depositing a transparent conductive film layer on the back surface of the silicon wafer in the embodiment of the present invention;

[0055] Figure 7 Structural schematic diagram of forming a metal electrode on the back surface of the silicon wafer in the embodiment of the present invention.

[0056] Explanation of reference numerals

[0057] Silicon wafer 1, tunneling oxide layer 2, N-type doped amorphous silicon layer 3, mask layer 4, oxide layer 5, first hydrogenated silicon nitride layer 6-1, second hydrogenated silicon nitride layer 6-2, third hydrogenated silicon nitride layer 6-3, intrinsic amorphous silicon layer 7, P-type doped amorphous silicon layer 8, transparent conductive film layer 9. Detailed implementation manners

[0058] In the present invention, unless otherwise stated, orientation terms such as "upper, lower, left, right" generally refer to the orientation understood in combination with the attached drawings and actual applications.

[0059] In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present invention, "a plurality" means two or more, unless otherwise specifically defined.

[0060] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being "above", "above" or "above" a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being "below", "below" or "below" a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0061] The endpoints and any values of the ranges disclosed herein are not limited to the precise ranges or values, and these ranges or values should be understood to include values close to these ranges or values. For numerical ranges, the endpoint values of each range, the endpoint values of each range and the individual point values, and the individual point values can be combined with each other to obtain one or more new numerical ranges, which should be considered as specifically disclosed in this article. Among them, the terms "optional" and "optional" all mean that they may be included or not included (or may be present or not).

[0062] In the present invention, the area close to the silicon wafer is referred to as the inside, and the area far from the silicon wafer is referred to as the outside.

[0063] In a first aspect, the present invention provides a back-contact cell with a specific anti-reflection layer structure, comprising a silicon wafer, a first semiconductor layer and a second semiconductor layer alternately arranged on the back of the silicon wafer, an oxide layer arranged on the light-receiving surface of the silicon wafer, and also comprising a first hydrogen-doped silicon nitride layer, a second hydrogen-doped silicon nitride layer, and a third hydrogen-doped silicon nitride layer sequentially arranged on the outer surface of the oxide layer to form an anti-reflection layer; wherein the effective hydrogen doping concentration of the first hydrogen-doped silicon nitride layer, the second hydrogen-doped silicon nitride layer, and the third hydrogen-doped silicon nitride layer gradually increases, and the thickness gradually increases; and the first hydrogen-doped silicon nitride layer, the second hydrogen-doped silicon nitride layer, and the third hydrogen-doped silicon nitride layer The corrosion rates are 0.20nm / s-0.23nm / s, 0.16nm / s-0.20nm / s, and 0.10nm / s-0.16nm / s, respectively. The ratio of the corrosion resistance time of the first hydrogen-doped silicon nitride layer, the second hydrogen-doped silicon nitride layer, and the third hydrogen-doped silicon nitride layer is 1:(2-4.5):(5-13.5), wherein the corrosion rate is obtained by subjecting the corresponding hydrogen-doped silicon nitride layer to a corrosion test using a hydrofluoric acid solution with a mass concentration of 5%, and the corrosion resistance time is the time required for the corresponding hydrogen-doped silicon nitride layer to be completely removed by a hydrofluoric acid solution with a mass concentration of 5%.

[0064] Preferably, in the present invention, the corrosion resistance time of the first hydrogen-doped silicon nitride layer is 65-125s.

[0065] In some preferred embodiments of the present invention, the ratio of the effective hydrogen doping concentrations of the first hydrogen-doped silicon nitride layer, the second hydrogen-doped silicon nitride layer, and the third hydrogen-doped silicon nitride layer is 1:(1.5 - 4):(2.5 - 6), and more preferably 1:(1.5 - 2.9):(3.0 - 6.0). Using the appropriate ratio of the effective hydrogen doping concentrations of the first hydrogen-doped silicon nitride layer, the second hydrogen-doped silicon nitride layer, and the third hydrogen-doped silicon nitride layer is more conducive to improving the passivation level and achieving a better passivation effect.

[0066] In some preferred embodiments of the present invention, the effective hydrogen doping concentrations of the first hydrogen-doped silicon nitride layer, the second hydrogen-doped silicon nitride layer, and the third hydrogen-doped silicon nitride layer are 1.5×10 19 cm -3 -4×10 19 cm -3 、4×10 19 cm -3 -6×10 19 cm -3 、7×10 19 cm -3 -9×10 19 cm -3 . Using the appropriate range of the effective hydrogen doping concentrations of the first hydrogen-doped silicon nitride layer, the second hydrogen-doped silicon nitride layer, and the third hydrogen-doped silicon nitride layer is more conducive to improving the denseness of the film layer and enhancing the anti-corrosion ability of the film layer.

[0067] In some preferred embodiments of the present invention, the ratio of the thicknesses of the first hydrogen-doped silicon nitride layer, the second hydrogen-doped silicon nitride layer, and the third hydrogen-doped silicon nitride layer is 1:(2 - 3):(4 - 6), and more preferably 1:(2.0 - 3.0):(4.0 - 5.0). Using the appropriate ratio of the thicknesses of the first hydrogen-doped silicon nitride layer, the second hydrogen-doped silicon nitride layer, and the third hydrogen-doped silicon nitride layer is more conducive to improving the passivation level while taking into account the optical effect.

[0068] In some preferred embodiments of the present invention, the thickness of the first hydrogen-doped silicon nitride layer is 15 - 25 nm, the thickness of the second hydrogen-doped silicon nitride layer is 35 - 45 nm, and the thickness of the third hydrogen-doped silicon nitride layer is 60 - 90 nm. Using the appropriate thicknesses of the first hydrogen-doped silicon nitride layer, the second hydrogen-doped silicon nitride layer, and the third hydrogen-doped silicon nitride layer is more conducive to minimizing the optical loss to the greatest extent.

[0069] In some preferred embodiments of the present invention, the ratio of the sum of the thicknesses of the first hydrogen-doped silicon nitride layer, the second hydrogen-doped silicon nitride layer, and the third hydrogen-doped silicon nitride layer to the thickness of the oxide layer is (19 - 35):1, more preferably (27 - 35):1, and further preferably (27 - 33):1, which is more conducive to protecting the oxide layer to the greatest extent while injecting the most hydrogen.

[0070] In some preferred embodiments of the present invention, the thickness of the oxide layer is 3 - 5 nm.

[0071] The oxide layer of the present invention is preferably silicon oxide.

[0072] Preferably, the oxide layer is formed by an oxidation annealing process of the first semiconductor layer.

[0073] In some preferred embodiments of the present invention, the first semiconductor layer includes a first passivation layer and a first doped silicon layer, the second semiconductor layer includes a second passivation layer and a second doped silicon layer, and the first passivation layer and the second passivation layer are each independently a tunneling oxide layer or an intrinsic silicon layer. The first doped silicon layer and the second doped silicon layer are each independently polysilicon, amorphous silicon, or microcrystalline silicon. The present invention is applicable to heterojunction passivation and combined passivation structures, etc.

[0074] In some preferred embodiments of the present invention, the first semiconductor layer includes a tunneling oxide layer and a first doped polysilicon layer, and the second semiconductor layer includes an intrinsic silicon layer and a second doped silicon layer. The second doped silicon layer can be doped amorphous silicon or microcrystalline silicon. The intrinsic silicon layer is preferably an intrinsic amorphous silicon layer. Adopting a combined passivation structure and cooperating with a specific antireflection layer structure is more conducive to improving the open - circuit voltage and short - circuit current of the battery.

[0075] Preferably, the ratio of the sum of the thicknesses of the first hydrogenated silicon nitride layer, the second hydrogenated silicon nitride layer, and the third hydrogenated silicon nitride layer to the thicknesses of the intrinsic silicon layer and the tunneling oxide layer is (50 - 160):(3 - 15):1, which is more conducive to ensuring high - level passivation on the front side while minimizing optical losses to the greatest extent, and is more conducive to improving the open - circuit voltage and short - circuit current of the battery.

[0076] The thicknesses and corresponding doping concentrations of the tunneling oxide layer and the first doped polysilicon layer, the intrinsic silicon layer and the second doped silicon layer can refer to the prior art. Exemplarily, the thickness of the tunneling oxide layer is 1 - 2 nm, the thickness of the first doped polysilicon layer is 150 - 300 nm, and the effective doping concentration is 1e19 cm -3 -5e20cm -3 , the thickness of the intrinsic silicon layer is 5 - 15 nm, the thickness of the second doped silicon layer is 10 - 35 nm, and the effective doping concentration is 1e18cm -3 -9e19cm -3 .

[0077] One of the first doped polysilicon layer and the second doped silicon layer is N - type, and the other is P - type.

[0078] In some preferred embodiments of the present invention, both ends of the second semiconductor layer extend outwardly to cover a part of the back surface of the adjacent first semiconductor layer, and a first semiconductor opening region that does not cover the second semiconductor layer is formed on the back surface of the first semiconductor layer. A second semiconductor opening region is formed between adjacent first semiconductor layers. The second semiconductor opening region and the first semiconductor opening region are arranged at intervals, and the region between them is the spacer region.

[0079] Further preferably, in the spacer region, a mask layer is provided or not provided between the first semiconductor layer and the second semiconductor layer.

[0080] The widths of the second semiconductor opening region and the first semiconductor opening region can be selected within the scope of the prior art according to actual needs. Exemplarily, the width W2 of the second semiconductor opening region is 0.3 - 0.6 mm, and the width W1 of the first semiconductor opening region is 0.1 - 0.3 mm.

[0081] In some preferred embodiments of the present invention, the back-contact battery further includes a metal electrode and a conductive film layer disposed on the outer surfaces of the first semiconductor layer and the second semiconductor layer. An isolation groove is formed on the part of the conductive film layer located in the spacer region; the metal electrode is disposed on the outer surfaces of the conductive film layers corresponding to the second semiconductor opening region and the first semiconductor opening region respectively.

[0082] In a second aspect, the present invention provides a method for manufacturing a back-contact battery, including the following steps:

[0083] S1. Provide a double-sided polished silicon wafer;

[0084] S2. Sequentially form a first semiconductor layer corresponding film layer and a mask layer on the back surface of the silicon wafer; annealing is not performed during the formation of the first semiconductor layer corresponding film layer in this step.

[0085] S3. Perform etching and opening on the back surface obtained in S2 to form a second semiconductor opening region;

[0086] S4. Through texturing and cleaning, then select whether to perform the step of removing the mask layer outside the second semiconductor opening region on the back surface of the silicon wafer according to needs;

[0087] S5. Perform oxidation annealing on the first semiconductor layer corresponding film layer obtained in S4 to form a first semiconductor layer, and an oxide layer is formed on the light-receiving surface of the silicon wafer simultaneously during the oxidation annealing process;

[0088] S6. Sequentially deposit a first hydrogenated silicon nitride layer, a second hydrogenated silicon nitride layer, and a third hydrogenated silicon nitride layer on the outer surface of the oxide layer on the light-receiving surface of the silicon wafer to form an antireflection layer.

[0089] During the control of the deposition of the first hydrogenated silicon nitride layer, the second hydrogenated silicon nitride layer, and the third hydrogenated silicon nitride layer, the gradually increasing hydrogen gas flow rate and deposition time are correspondingly incorporated, and the corrosion rates of the obtained first hydrogenated silicon nitride layer, second hydrogenated silicon nitride layer, and third hydrogenated silicon nitride layer are controlled to be 0.20 nm / s - 0.23 nm / s, 0.16 nm / s - 0.20 nm / s, and 0.10 nm / s - 0.16 nm / s, respectively. The corrosion resistance time ratios of the first hydrogenated silicon nitride layer, second hydrogenated silicon nitride layer, and third hydrogenated silicon nitride layer are 1:(2 - 4.5):(5 - 13.5). Among them, the corrosion rate is obtained by corrosion testing of the corresponding hydrogenated silicon nitride layer with a hydrofluoric acid solution with a mass concentration of 5%, and the corrosion resistance time is the time required for the complete removal of the corresponding hydrogenated silicon nitride layer with a hydrofluoric acid solution with a mass concentration of 5%.

[0090] S7. Then, backwashing is performed. The backwashing solution includes an alkaline solution and an acid solution containing hydrofluoric acid. During this period, the ratio of the corrosion resistance time of the third hydrogenated silicon nitride layer to the treatment time of the acid solution is controlled to be (6 - 12):1;

[0091] S8. Deposit a second semiconductor layer on the back surface obtained in S7.

[0092] In step S7 of the present invention, controlling the ratio of the corrosion resistance time of the third hydrogenated silicon nitride layer to the treatment time of the acid solution within an appropriate range is beneficial to making the thicknesses of the remaining hydrogenated silicon nitrides the same, ensuring that their refractive indices remain unchanged, and ultimately improving the conversion efficiency of the finished battery.

[0093] In S2, the type and thickness of the mask layer can refer to the prior art. Exemplarily, the mask layer can be at least one of silicon nitride, silicon oxynitride, and silicon oxide, and the mask layer thickness is 50 - 200 nm.

[0094] The corresponding film layer of the first semiconductor layer in S2 refers to the corresponding film layer contained in the first semiconductor layer, and these corresponding film layers are formed by steps other than annealing. Some of the corresponding film layers form the final film layer after annealing; that is, annealing is not performed only in the conventional formation steps. The first semiconductor layer in S2 can be formed by in-situ doping deposition using tube PECVD, LPCVD or PVD and then oxidized and annealed in S5. Preferably, tube PECVD in-situ doping is used. Exemplarily, the deposition process of the first semiconductor layer includes: in the first stage, nitrous oxide is introduced, the flow rate of nitrous oxide is 8000 - 12000 sccm, glow discharge is turned on, and a tunneling oxide layer is formed through chemical reaction. The reaction temperature in the first stage is 400 - 450 °C, the reaction pressure is 100 - 2000 mtorr, and the time is 10 - 60 s; then it enters the second stage. In the second stage, silane, phosphine, and hydrogen are introduced. The flow rate of silane is 1000 - 3000 sccm, the flow rate of the mixed gas of hydrogen carrying phosphine is 2000 - 4000 sccm, the flow rate of hydrogen introduced alone is 7000 - 9000 sccm, glow discharge is turned on, and an N-type amorphous silicon layer is formed through chemical reaction. The reaction temperature in the second stage is 400 - 450 °C, the reaction time is 500 - 1500 s, and the reaction pressure is 100 - 2000 mtorr. The N-type amorphous silicon layer is the corresponding film layer of the N-type polysilicon layer in the first semiconductor layer, and the N-type amorphous silicon layer forms the N-type polysilicon layer after being oxidized and annealed in S5.

[0095] Preferably in the present invention, the conditions for oxidation annealing in S5 include: the annealing pressure is 100 mbar - 500 mbar, oxygen and nitrogen are introduced, the oxygen flow rate is 1000 - 3000 sccm, the nitrogen flow rate is 3000 - 10000 sccm, and the annealing time is 10 - 60 min.

[0096] Preferably in the present invention, the annealing temperature for oxidation annealing in S5 is 850 - 950 °C. In the present invention, different annealing temperatures can be selected according to the target film layer to be formed. For example, when a polysilicon layer needs to be formed, the annealing temperature is selected to be 900 - 950 °C, and when an amorphous silicon layer needs to be formed, the annealing temperature is selected to be 850 - 899 °C.

[0097] In some preferred embodiments of the present invention, the hydrogen flow rate incorporated during the deposition of the first hydrogenated silicon nitride layer is 1000 - 2000 sccm, the hydrogen flow rate incorporated during the deposition of the second hydrogenated silicon nitride layer is 3000 - 4000 sccm, and the hydrogen flow rate incorporated during the deposition of the third hydrogenated silicon nitride layer is 5000 - 6000 sccm. By adopting an appropriate range of hydrogen flow rates incorporated, first hydrogenated silicon nitride layer, second hydrogenated silicon nitride layer, and third hydrogenated silicon nitride layer with appropriate hydrogen doping concentrations can be obtained, which is more conducive to improving the film layer density and the anti-corrosion ability of the film layer.

[0098] In some preferred embodiments of the present invention, the conditions for depositing the first hydrogenated silicon nitride layer include: introducing silane, ammonia, and hydrogen, with a reaction temperature of 400 - 450 °C, a power of 6000 - 7000 W, and a reaction time of 150 - 300 s.

[0099] Preferably, the conditions for depositing the second hydrogenated silicon nitride layer include: introducing silane, ammonia, and hydrogen, with a reaction temperature of 400 - 500 °C, a power of 5000 - 6000 W, and a reaction time of 300 - 500 s.

[0100] Preferably, the conditions for depositing the third hydrogenated silicon nitride layer include: introducing silane, ammonia, and hydrogen, with a reaction temperature of 400 - 500 °C, a power of 4000 - 5000 W, and a reaction time of 500 - 800 s.

[0101] By using the above suitable deposition conditions to deposit the first hydrogenated silicon nitride layer, the second hydrogenated silicon nitride layer, and the third hydrogenated silicon nitride layer in the present invention, the film layer can be made more dense, which is more conducive to improving the passivation effect and ensuring the optical effect.

[0102] In some preferred embodiments of the present invention, in S6, the conditions for depositing the first hydrogenated silicon nitride layer, the second hydrogenated silicon nitride layer, and the third hydrogenated silicon nitride layer each independently further include: a silane flow rate of 1200 - 1800 sccm, an ammonia flow rate of 5000 - 10000 sccm, and a reaction pressure of 1500 - 3000 mtorr.

[0103] The corrosion rate of each corresponding hydrogenated silicon nitride layer in the present invention can be regulated by the ammonia - silicon ratio (i.e., the ratio of ammonia to silane), the hydrogen doping amount, and the power in the corresponding process conditions; the corrosion - resistant time can be regulated by the corrosion rate and the coating time.

[0104] Preferably in the present invention, the first hydrogenated silicon nitride layer, the second hydrogenated silicon nitride layer, and the third hydrogenated silicon nitride layer are deposited in a tube - type PECVD device.

[0105] In some preferred embodiments of the present invention, in S7, the alkali solution is a weak alkali solution, and the back - washing is carried out in the way of first cleaning with the weak alkali solution, then washing with water, and finally washing with an acid solution. Adopting this preferred back - washing scheme is more conducive to ensuring the interface cleanliness in the second semiconductor opening area while reducing the damage to the first semiconductor layer to improve the battery efficiency.

[0106] In some specific embodiments, the alkali solution can be a strong alkali solution with a mass concentration of 1% - 5%, and the alkali in the strong alkali solution is potassium hydroxide and / or sodium hydroxide.

[0107] Preferably, the weak alkaline solution is a mixed aqueous solution containing ammonia water and hydrogen peroxide. The mass concentration of ammonia water in the weak alkaline solution is 2% - 5%, and the mass concentration of hydrogen peroxide is 3% - 5%. Using the weak alkaline solution with this preferred composition is more conducive to controlling the corrosion depth and reducing the damage to the first semiconductor layer.

[0108] Preferably, the mass concentration of hydrofluoric acid in the acid solution is 1% - 10%.

[0109] Using the weak alkaline solution and the acid solution with the above suitable compositions of the present invention is more conducive to ensuring an appropriate corrosion rate and improving the film layer uniformity, effectively avoiding the probability of pores easily generated due to uneven corrosion, and further improving the battery conversion efficiency.

[0110] In some preferred embodiments of the present invention, the conditions for backwashing include: the treatment temperature is 20°C - 40°C.

[0111] Preferably, the treatment time of the acid solution is 0.5 - 2 min, which is more conducive to obtaining a clean interface and reducing the influence on the antireflection effect of the front antireflection layer.

[0112] Preferably, the treatment time of the weak alkaline solution is 0.1 - 2 min, which is more conducive to ensuring that while removing the damaged layer in the second semiconductor opening area, the damage to the first semiconductor layer is reduced.

[0113] In some preferred embodiments of the present invention, the manufacturing method of the back contact battery further includes:

[0114] S9. Etch openings on a part of the second semiconductor layer on the back of the silicon wafer to form a first semiconductor opening area arranged at intervals with the second semiconductor opening area, and then clean;

[0115] S10. Deposit a conductive film layer on the back obtained in S9;

[0116] S11. Etch openings on a part of the conductive film layer located between the first semiconductor opening area and the second semiconductor opening area to form isolation grooves;

[0117] S12. Form metal electrodes on the outer surfaces of the corresponding conductive film layers in the areas where the first semiconductor opening area and the second semiconductor opening area are located, respectively.

[0118] In the third aspect, the present invention provides a back contact battery, which is obtained by the manufacturing method of the back contact battery described in the second aspect.

[0119] In the fourth aspect, the present invention provides a photovoltaic module, which includes the back contact battery having a specific antireflection layer structure described in the first aspect, or includes the back contact battery described in the third aspect.

[0120] Embodiments of the present invention will be described in detail below. They are exemplary and are only used to explain the present invention, and should not be construed as a limitation of the present invention.

[0121] Embodiment 1

[0122] A back-contact battery is manufactured as follows:

[0123] S1. As shown in Figure 1 , the N-type monocrystalline silicon wafer 1 is polished and cleaned on both sides.

[0124] S2. As shown in Figure 2 , a first semiconductor layer and a mask layer 4 are formed on the back surface of the silicon wafer 1. The mask layer 4 is silicon nitride with a thickness of 80 nm. The first semiconductor layer includes a tunneling oxide layer 2 and an N-type doped polysilicon layer. The first semiconductor layer is in-situ doped by tube-type PECVD. The process includes: in the first stage, silane and nitrous oxide are introduced. The flow rate of silane is 2000 sccm, and the flow rate of nitrous oxide is 9000 sccm. Glow discharge is turned on, and a tunneling oxide layer 2 with a thickness of 1.5 nm is formed through chemical reaction. The reaction temperature in the first stage is 400 °C, the reaction pressure is 800 mtorr, and the time is 30 s. Then it enters the second stage. In the second stage, silane, phosphine, and hydrogen are introduced. The flow rate of silane is 2000 sccm, the flow rate of the mixed gas of hydrogen carrying phosphine (the flow rate ratio of hydrogen to phosphine is 49:1) is 3000 sccm, and the flow rate of hydrogen introduced alone is 8000 sccm. Glow discharge is turned on, and an N-type doped amorphous silicon layer 3 with a thickness of 200 nm is formed through chemical reaction. The reaction temperature in the second stage is 400 °C, the reaction time is 900 s, and the reaction pressure is 1000 mtorr.

[0125] S3. Openings are etched on the back surface of the silicon wafer 1 to form a second semiconductor opening area. The width W2 of the second semiconductor opening area is 0.4 mm, and the mask layer 4, the tunneling oxide layer 2, and the N-type doped amorphous silicon layer 3 in the second semiconductor opening area are etched away.

[0126] S4. As shown in Figure 3 , through texturing cleaning, the remaining mask layer 4, tunneling oxide layer 2, and N-type doped amorphous silicon layer 3 in the second semiconductor opening area are removed. At the same time, a textured surface is formed on the light-receiving surface of the silicon wafer 1 and the second semiconductor opening area. After that, it is cleaned with hydrofluoric acid to remove the mask layer 4 outside the second semiconductor opening area on the back surface of the silicon wafer 1.

[0127] S5. As shown in Figure 3 , the first semiconductor layer after texturing cleaning is subjected to oxidation annealing to convert the N-type doped amorphous silicon layer 3 into an effective doping concentration of 1e19 cm -3The N-type doped polysilicon layer is formed while an oxide layer 5 is formed on the light-receiving surface. The oxidation annealing conditions are as follows: the annealing pressure is 200 mbar, the annealing temperature is 920 °C, the oxygen flow rate is 2000 sccm, the nitrogen flow rate is 5000 sccm, and the annealing time is 30 min. The thickness of the oxide layer 5 is 4 nm.

[0128] S6. As Figure 4 shown, on the outer surface of the oxide layer 5 on the light-receiving surface of the silicon wafer 1, a first hydrogenated silicon nitride layer 6-1, a second hydrogenated silicon nitride layer 6-2, and a third hydrogenated silicon nitride layer 6-3 are sequentially deposited to form an antireflection layer. The deposition process of the antireflection layer is as follows:

[0129] In the first stage, silane, ammonia, and hydrogen are introduced, and glow discharge is started. Through chemical reactions, the first hydrogenated silicon nitride layer 6-1 is formed. The reaction temperature in the first stage is 400 °C, the silane flow rate is 1300 sccm, the ammonia flow rate is 8000 sccm, the hydrogen flow rate is 1000 sccm, the reaction time is 200 s, the reaction pressure is 2000 mtorr, the power is 6000 W, the thickness of the first hydrogenated silicon nitride layer 6-1 is 15 nm, and the effective hydrogen doping concentration is 1.73×10 19 cm -3 ;

[0130] In the second stage, silane, ammonia, and hydrogen are introduced, and glow discharge is started. Through chemical reactions, the second hydrogenated silicon nitride layer 6-2 is formed. The reaction temperature of the second hydrogenated silicon nitride layer 6-2 is 420 °C, the silane flow rate is 1300 sccm, the ammonia flow rate is 8000 sccm, the hydrogen flow rate is 3000 sccm, the reaction time is 400 s, the reaction pressure is 2000 mtorr, the power is 5000 W, the thickness of the second hydrogenated silicon nitride layer 6-2 is 40 nm, and the effective hydrogen doping concentration is 4.46×10 19 cm -3 ;

[0131] In the third stage, silane, ammonia, and hydrogen are introduced, and glow discharge is started. Through chemical reactions, the third hydrogenated silicon nitride layer 6-3 is formed. The reaction temperature of the third hydrogenated silicon nitride layer 6-3 is 500 °C, the silane flow rate is 1300 sccm, the ammonia flow rate is 8000 sccm, the hydrogen flow rate is 5000 sccm, the reaction time is 600 s, the reaction pressure is 2000 mtorr, the power is 4000 W, the thickness of the third hydrogenated silicon nitride layer 6-3 is 70 nm, and the effective hydrogen doping concentration is 7.43×10 19 cm -3 .

[0132] After calculation, the thickness ratio of the first hydrogenated silicon nitride layer 6-1, the second hydrogenated silicon nitride layer 6-2, and the third hydrogenated silicon nitride layer 6-3 is 1:2.67:4.67, and the ratio of their effective hydrogen doping concentrations is 1:2.578:4.29.

[0133] After testing, the etching rates of the first hydrogenated silicon nitride layer 6-1, the second hydrogenated silicon nitride layer 6-2, and the third hydrogenated silicon nitride layer 6-3 are 0.20 nm / s, 0.18 nm / s, and 0.13 nm / s respectively. The corrosion resistance time of the first hydrogenated silicon nitride layer 6-1 is 75 s. The ratio of the corrosion resistance times of the first hydrogenated silicon nitride layer 6-1, the second hydrogenated silicon nitride layer 6-2, and the third hydrogenated silicon nitride layer 6-3 is 1:2.96:7.71. Among them, the etching rate is obtained by etching the corresponding hydrogenated silicon nitride layer with a 5% hydrofluoric acid solution, and the corrosion resistance time is the time required to completely remove the corresponding hydrogenated silicon nitride layer with a 5% hydrofluoric acid solution.

[0134] S7. Backwashing:

[0135] The backwashing solution is carried out in a combination of a weak base solution and an acid solution. The weak base solution is a mixed solution of ammonia water with a mass concentration of 3% and hydrogen peroxide with a mass concentration of 4%. The acid solution is a 5% HF solution. The processing time of the silicon wafer in the HF solution is 1.3 min, the processing temperature is 20 °C, and the processing time of the weak base solution is 0.5 min.

[0136] After calculation, the ratio of the corrosion resistance time of the third hydrogenated silicon nitride layer 6-3 to the acid solution treatment time is approximately 7:1.

[0137] S8. As Figure 5 shown, a second semiconductor layer is deposited on the back surface of the silicon wafer 1. The second semiconductor layer includes an intrinsic amorphous silicon layer 7 and a P-type doped amorphous silicon layer 8. The thickness of the intrinsic amorphous silicon layer 7 is 10 nm, the thickness of the P-type doped amorphous silicon layer 8 is 13 nm, and the boron doping concentration is 3e19 cm -3 .

[0138] S9. As Figure 5 shown, an opening is etched on the back surface of the silicon wafer 1 to form a first semiconductor opening region arranged at intervals with the second semiconductor opening region, and then it is cleaned. The width W1 of the first semiconductor opening region is 0.2 mm.

[0139] S10. As Figure 6 shown, a transparent conductive film layer 9 is deposited on the back surface of the silicon wafer 1.

[0140] S11. An isolation groove is formed on the transparent conductive film layer 9 between the second semiconductor opening region and the first semiconductor opening region;

[0141] S12. As Figure 7 shown, a first metal electrode is formed on the transparent conductive film layer 9 corresponding to the first semiconductor opening region, and a second metal electrode is correspondingly formed on the transparent conductive film layer 9 corresponding to the second semiconductor opening region.

[0142] Example 2

[0143] The method of Reference Example 1 was followed, except that the effective hydrogen doping concentration of the second hydrogen-doped silicon nitride layer was adjusted to 5.2×10 19 cm -3 , such that the ratio of the effective hydrogen doping concentrations of the first and second hydrogen-doped silicon nitride layers was 1:3. To meet this effective hydrogen doping concentration, the hydrogen flow rate introduced during the deposition of the second hydrogen-doped silicon nitride layer was adjusted to 3500 sccm. In this solution, the corrosion rate of the second hydrogen-doped silicon nitride layer was 0.9 times that of the original Example 1, and the corrosion resistance time was 1.1 times that of the original Example 1.

[0144] Example 3

[0145] The method of Reference Example 1 was followed, except that the thickness of the third hydrogen-doped silicon nitride layer was adjusted to 80 nm, such that the ratio of the thicknesses of the first and third hydrogen-doped silicon nitride layers was 1:5.3. To meet this thickness, the deposition time of the third hydrogen-doped silicon nitride layer was adjusted to 686 s. In this solution, the corrosion rate of the third hydrogen-doped silicon nitride layer remained unchanged, and the ratio of the corrosion resistance time to that of the original Example 1 was 8:7.

[0146] Example 4

[0147] The method of Reference Example 1 was followed, except that the thickness of the oxide layer was adjusted to 5 nm, such that the ratio of the sum of the thicknesses of the first, second, and third hydrogen-doped silicon nitride layers to the thickness of the oxide layer was 25:1; to meet the thickness of the oxide layer, the oxidation annealing process parameters were adjusted to extend the annealing time to 1 h.

[0148] Example 5

[0149] The method of Reference Example 1 was followed, except that the backwashing process was adjusted by replacing the weak base solution with a strong base solution of potassium hydroxide with a mass concentration of 3%.

[0150] Example 6

[0151] The method of Reference Example 1 was followed, except that the passivation structure was a heterojunction. Specifically, the first semiconductor layer was an intrinsic amorphous silicon layer and a first doped amorphous silicon layer. Accordingly, the oxidation annealing temperature was controlled to 850°C. The thicknesses of both the intrinsic amorphous silicon layer and the N-type first doped amorphous silicon layer were 10 nm, and the effective doping concentration of the first doped amorphous silicon layer was 1e19 cm -3 .

[0152] Comparative Example 1

[0153] It is carried out according to the method of Example 1, except that in S6, it is replaced by sequentially depositing an N-type polysilicon layer (with a thickness of 10 nm) and a silicon nitride antireflection layer (the thickness of the silicon nitride antireflection layer is equal to the sum of the thicknesses of the first hydrogenated silicon nitride layer, the second hydrogenated silicon nitride layer, and the third hydrogenated silicon nitride layer in Example 1) on the outer surface of the oxide layer. The corrosion rate of the silicon nitride antireflection layer is 0.16 nm / s, and the corrosion-resistant time is 781 s.

[0154] Comparative Example 2

[0155] It is carried out according to the method of Example 1, except that in S6, the thicknesses of the first hydrogenated silicon nitride layer, the second hydrogenated silicon nitride layer, and the third hydrogenated silicon nitride layer are the same and the sum of the three thicknesses remains unchanged. Among them, the corrosion rates of the first hydrogenated silicon nitride layer, the second hydrogenated silicon nitride layer, and the third hydrogenated silicon nitride layer remain unchanged, and the ratio of the corrosion-resistant times is 1:1.1:1.5. To meet this thickness change, the deposition time of the corresponding hydrogenated silicon nitride layer needs to be modified to obtain the thickness of the desired target film layer.

[0156] Comparative Example 3

[0157] It is carried out according to the method of Example 1, except that in S6, the effective hydrogen doping concentrations of the first hydrogenated silicon nitride layer, the second hydrogenated silicon nitride layer, and the third hydrogenated silicon nitride layer are the same and are 6×10 19 cm -3 , among which the corrosion rates of the second hydrogenated silicon nitride layer and the third hydrogenated silicon nitride layer are the same as that of the first hydrogenated silicon nitride layer, and the ratio of the corrosion-resistant times of the first hydrogenated silicon nitride layer, the second hydrogenated silicon nitride layer, and the third hydrogenated silicon nitride layer is 1:2.7:4.7. To meet this effective hydrogen doping concentration, the hydrogen flow rates incorporated during the deposition of the first hydrogenated silicon nitride layer, the second hydrogenated silicon nitride layer, and the third hydrogenated silicon nitride layer need to be controlled to be 4000 sccm.

[0158] Comparative Example 4

[0159] It is carried out according to the method of Example 1, except that in S7, the treatment time of the acid solution is 2.275 min. After calculation, the ratio of the corrosion-resistant time of the third hydrogenated silicon nitride layer to the treatment time of the acid solution is about 4:1.

[0160] Test Example

[0161] The back contact batteries obtained from the above examples and comparative examples are subjected to performance tests, and the results are shown in Table 1.

[0162] Table 1

[0163]

[0164] From the above results, it can be seen that compared with the comparative example, adopting the embodiment scheme of the present invention can maximize the protection of the oxide layer while injecting more hydrogen, effectively passivating defects and impurities; at the same time, improve the density, achieve the optimal optical effect and passivation level, and improve the conversion efficiency of the battery.

[0165] Furthermore, according to Embodiment 1 and Embodiments 2-6, it can be seen that adopting the preferred battery structure scheme of the present invention is more conducive to improving the conversion efficiency of the battery.

[0166] The preferred embodiments of the present invention have been described in detail above. However, the present invention is not limited thereto. Within the scope of the technical concept of the present invention, various simple modifications can be made to the technical solution of the present invention, including any other suitable combination of each technical feature. These simple modifications and combinations should also be regarded as the content disclosed by the present invention and fall within the protection scope of the present invention.

Claims

1. A back-contact battery with a specific antireflection layer structure, comprising a silicon wafer, a first semiconductor layer and a second semiconductor layer alternately arranged on the back surface of the silicon wafer, and an oxide layer arranged on the light-receiving surface of the silicon wafer, characterized in that, It also includes a first hydrogenated silicon nitride layer, a second hydrogenated silicon nitride layer, and a third hydrogenated silicon nitride layer sequentially disposed on the outer surface of the oxide layer to form an antireflection layer; wherein, the effective hydrogen doping concentrations of the first hydrogenated silicon nitride layer, the second hydrogenated silicon nitride layer, and the third hydrogenated silicon nitride layer gradually increase, and the thicknesses gradually increase; and the etching rates of the first hydrogenated silicon nitride layer, the second hydrogenated silicon nitride layer, and the third hydrogenated silicon nitride layer are 0.20 nm / s - 0.23 nm / s, 0.16 nm / s - 0.20 nm / s, and 0.10 nm / s - 0.16 nm / s respectively, and the corrosion resistance times of the first hydrogenated silicon nitride layer, the second hydrogenated silicon nitride layer, and the third hydrogenated silicon nitride layer are in a ratio of 1:(2 - 4.5):(5 - 13.5), where the etching rate is obtained by etching the corresponding hydrogenated silicon nitride layer with a 5% hydrofluoric acid solution by mass concentration, and the corrosion resistance time is the time required for the corresponding hydrogenated silicon nitride layer to be completely removed by a 5% hydrofluoric acid solution by mass concentration.

2. The back-contact battery with a specific antireflection layer structure according to claim 1, characterized in that The ratio of the effective hydrogen doping concentrations of the first hydrogenated silicon nitride layer, the second hydrogenated silicon nitride layer, and the third hydrogenated silicon nitride layer is 1:(1.5 - 4):(2.5 - 6), and / or, The effective hydrogen doping concentrations of the first hydrogen-doped silicon nitride layer, the second hydrogen-doped silicon nitride layer, and the third hydrogen-doped silicon nitride layer are 1.5×10 19 cm -3 -4×10 19 cm -3 、4×10 19 cm -3 -6×10 19 cm -3 、7×10 19 cm -3 -9×10 19 cm -3 respectively.

3. The back contact battery with a specific antireflection layer structure according to claim 1, characterized in that, The ratio of the thicknesses of the first hydrogenated silicon nitride layer, the second hydrogenated silicon nitride layer, and the third hydrogenated silicon nitride layer is 1:(2 - 3):(4 - 6); and / or, The thickness of the first hydrogenated silicon nitride layer is 15 - 25 nm, the thickness of the second hydrogenated silicon nitride layer is 35 - 45 nm, and the thickness of the third hydrogenated silicon nitride layer is 60 - 90 nm.

4. The back-contact battery with a specific anti-reflection layer structure according to claim 1, characterized in that, The ratio of the sum of the thicknesses of the first hydrogenated silicon nitride layer, the second hydrogenated silicon nitride layer, and the third hydrogenated silicon nitride layer to the thickness of the oxide layer is (19 - 35):1, and / or, the thickness of the oxide layer is 3 - 5 nm.

5. The back contact battery having a specific antireflection layer structure according to claim 1, characterized in that, The corrosion resistance time of the first hydrogenated silicon nitride layer is 65 - 125 s; and / or, The first semiconductor layer includes a first passivation layer and a first doped silicon layer, the second semiconductor layer includes a second passivation layer and a second doped silicon layer, the first passivation layer and the second passivation layer are each independently a tunneling oxide layer or an intrinsic silicon layer; both ends of the second semiconductor layer extend outward to cover a part of the back surface of the adjacent first semiconductor layer, and a first semiconductor opening region that does not cover the second semiconductor layer is formed on the back surface of the first semiconductor layer, and a second semiconductor opening region is formed between adjacent first semiconductor layers. The second semiconductor opening region and the first semiconductor opening region are arranged at intervals, and the region between them is an interval region; in the interval region, a mask layer is provided or not provided between the first semiconductor layer and the second semiconductor layer; the back contact battery further includes a metal electrode and a conductive film layer laid on the outer surfaces of the first semiconductor layer and the second semiconductor layer, and an isolation groove is formed on a part of the conductive film layer located in the interval region; the metal electrode is provided on the outer surfaces of the conductive film layers corresponding to the second semiconductor opening region and the first semiconductor opening region respectively.

6. The back contact battery with a specific antireflection layer structure according to claim 1 or 5, characterized in that, The first semiconductor layer includes a tunneling oxide layer and a first doped polysilicon layer, and the second semiconductor layer includes an intrinsic silicon layer and a second doped silicon layer; the ratio of the sum of the thicknesses of the first hydrogenated silicon nitride layer, the second hydrogenated silicon nitride layer, and the third hydrogenated silicon nitride layer to the thicknesses of the intrinsic silicon layer and the tunneling oxide layer is (50 - 160):(3 - 15):1; and / or, The oxide layer is formed through an oxidation annealing process of the first semiconductor layer.

7. A manufacturing method of a back-contact battery, characterized in that, It includes the following steps: S1. Provide a double-sided polished silicon wafer; S2. Sequentially form the corresponding film layers of the first semiconductor layer and a mask layer on the back surface of the silicon wafer; no annealing is performed during the process of forming the corresponding film layers of the first semiconductor layer; S3. Etch an opening on the back surface obtained in S2 to form a second semiconductor opening region; S4. Through texturing and cleaning, and then select whether to perform the step of removing the mask layer outside the second semiconductor opening region on the back surface of the silicon wafer according to needs; S5. Perform oxidation annealing on the corresponding film layers of the first semiconductor layer obtained in S4 to form the first semiconductor layer, and simultaneously form an oxide layer on the light-receiving surface of the silicon wafer during the oxidation annealing process; S6. Sequentially deposit a first hydrogenated silicon nitride layer, a second hydrogenated silicon nitride layer, and a third hydrogenated silicon nitride layer on the outer surface of the oxide layer on the light-receiving surface of the silicon wafer to form an antireflection layer; During this period, control the gradually increasing hydrogen gas flow rate and deposition time corresponding to the doping of the first hydrogenated silicon nitride layer, the second hydrogenated silicon nitride layer, and the third hydrogenated silicon nitride layer. Among them, the effective hydrogen doping concentration and thickness of the first hydrogenated silicon nitride layer, the second hydrogenated silicon nitride layer, and the third hydrogenated silicon nitride layer gradually increase; and control the etching rates of the obtained first hydrogenated silicon nitride layer, second hydrogenated silicon nitride layer, and third hydrogenated silicon nitride layer to be 0.20 nm / s - 0.23 nm / s, 0.16 nm / s - 0.20 nm / s, and 0.10 nm / s - 0.16 nm / s respectively, and the corrosion resistance times of the first hydrogenated silicon nitride layer, second hydrogenated silicon nitride layer, and third hydrogenated silicon nitride layer are in a ratio of 1:(2 - 4.5):(5 - 13.5). Among them, the etching rate is obtained by etching the corresponding hydrogenated silicon nitride layer with a 5% hydrofluoric acid solution by mass concentration, and the corrosion resistance time is the time required for the corresponding hydrogenated silicon nitride layer to be completely removed by a 5% hydrofluoric acid solution by mass concentration; S7. Then perform backwashing. The backwashing solution includes an alkaline solution and an acid solution containing hydrofluoric acid. During this period, control the ratio of the corrosion resistance time of the third hydrogenated silicon nitride layer to the treatment time of the acid solution to be (6 - 12):1; S8. Deposit the second semiconductor layer on the back surface obtained in S7.

8. The manufacturing method of the back-contact battery according to claim 7, characterized in that, In S6, the hydrogen gas flow rate corresponding to the deposition of the first hydrogenated silicon nitride layer is 1000 - 2000 sccm, the hydrogen gas flow rate corresponding to the deposition of the second hydrogenated silicon nitride layer is 3000 - 4000 sccm, and the hydrogen gas flow rate corresponding to the deposition of the third hydrogenated silicon nitride layer is 5000 - 6000 sccm; and / or, The conditions for depositing the first hydrogenated silicon nitride layer include: introducing silane, ammonia, and hydrogen, with a reaction temperature of 400 - 450 °C, a power of 6000 - 7000 W, and a reaction time of 150 - 300 s; the conditions for depositing the second hydrogenated silicon nitride layer include: introducing silane, ammonia, and hydrogen, with a reaction temperature of 400 - 500 °C, a power of 5000 - 6000 W, and a reaction time of 300 - 500 s; the conditions for depositing the third hydrogenated silicon nitride layer include: introducing silane, ammonia, and hydrogen, with a reaction temperature of 400 - 500 °C, a power of 4000 - 5000 W, and a reaction time of 500 - 800 s.

9. The manufacturing method of the back-contact battery according to claim 7 or 8, characterized in that, In S6, the conditions for depositing the first hydrogenated silicon nitride layer, the second hydrogenated silicon nitride layer, and the third hydrogenated silicon nitride layer each independently further include: a silane flow rate of 1200 - 1800 sccm, an ammonia flow rate of 5000 - 10000 sccm, and a reaction pressure of 1500 - 3000 mtorr; and / or, The conditions for oxidation annealing in S5 include: an annealing temperature of 850 - 950 °C, an annealing pressure of 100 mbar - 500 mbar, introducing oxygen and nitrogen, an oxygen flow rate of 1000 - 3000 sccm, a nitrogen flow rate of 3000 - 10000 sccm, and an annealing time of 10 - 60 min.

10. The manufacturing method of the back-contact battery according to claim 7, characterized in that, In S7, the alkali solution is a weak alkali solution, and the backwashing is carried out in the manner of first cleaning with the weak alkali solution, then cleaning with water, and finally cleaning with an acid solution; wherein, the weak alkali solution is a mixed aqueous solution containing ammonia water and hydrogen peroxide, the mass concentration of ammonia water in the weak alkali solution is 2% - 5%, the mass concentration of hydrogen peroxide is 3% - 5%, and the mass concentration of hydrofluoric acid in the acid solution is 1% - 10%; and / or, the conditions for backwashing include: a treatment temperature of 20 °C - 40 °C, an acid solution treatment time of 0.5 - 2 min, and a weak alkali solution treatment time of 0.1 - 2 min.

11. The manufacturing method of the back contact battery according to claim 7, characterized in that, The manufacturing method of the back contact battery further includes: S9. Etch openings on a part of the second semiconductor layer on the back of the silicon wafer to form a first semiconductor opening area arranged at intervals with the second semiconductor opening area, and then clean; S10. Deposit a conductive film layer on the back obtained in S9; S11. Etch openings on a part of the conductive film layer located between the first semiconductor opening area and the second semiconductor opening area to form isolation grooves; S12. Form metal electrodes on the outer surfaces of the corresponding conductive film layers in the areas where the first semiconductor opening area and the second semiconductor opening area are located.

12. A back contact battery, characterized in that, It is obtained by the manufacturing method of the back contact battery according to any one of claims 7 - 11.

13. A photovoltaic module, characterized in that, It includes a back contact battery having a specific antireflection layer structure according to any one of claims 1 - 6, or includes the back contact battery according to claim 12.

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