Semiconductor light emitting device and method of manufacturing same

Abstract

A semiconductor light emitting device includes: a substrate including a first material; a plurality of protrusions; a buffer layer on the substrate and the plurality of protrusions; an intermediate layer on the buffer layer; and a light emitting stack on the intermediate layer. Each of the plurality of protrusions includes: a lower pattern including the same material as the first material of the substrate; and a feature pattern disposed on the lower pattern and including a second material different from the first material of the substrate. The intermediate layer includes silicon nitride (SiN).

Description

[0001] Cross - reference to related applications

[0002] This application claims the benefit of priority of Korean Patent Application No. 10 - 2023 - 0172728, filed on December 1, 2023, and Korean Patent Application No. 10 - 2024 - 0008283, filed on January 18, 2024, with the Korean Intellectual Property Office, the disclosures of which are incorporated herein by reference in their entireties. Technical field

[0003] The present disclosure generally relates to semiconductor light - emitting devices, and more particularly, to a semiconductor light - emitting device including a feature pattern having an increased light extraction efficiency. Background art

[0004] The demand for using semiconductor light - emitting devices in various lighting devices (such as, but not limited to, vehicle headlights, indoor lighting fixtures, etc.) may increase. For example, an intelligent lighting system may have been proposed, which can individually control light - emitting device chips to achieve various lighting modes according to the surrounding conditions when using a light source module that may include multiple light - emitting device chips. Therefore, further improvement in semiconductor light - emitting device technology is needed because the demand for intelligent lighting systems may be restricted by the light extraction efficiency of semiconductor light - emitting devices. Improvements are given herein. These improvements may also be applicable to other lighting technologies. Summary of the invention

[0005] One or more example embodiments of the present disclosure provide a semiconductor light - emitting device having an increased light extraction efficiency when compared with related semiconductor light - emitting devices.

[0006] According to an aspect of the present disclosure, a semiconductor light - emitting device includes: a substrate including a first material; a plurality of protrusions; a buffer layer on the substrate and the plurality of protrusions; an intermediate layer on the buffer layer; and a light - emitting stack on the intermediate layer. Each of the plurality of protrusions includes: a lower pattern including the same material as the first material of the substrate; and a feature pattern disposed on the lower pattern and including a second material different from the first material of the substrate. The intermediate layer includes silicon nitride (SiN).

[0007] According to one aspect of the present disclosure, a semiconductor light-emitting device includes: a substrate including a first material; a plurality of protrusions; a buffer layer on the substrate and the plurality of protrusions; an intermediate layer on the buffer layer; and a light-emitting stack including a first-conductivity-type semiconductor layer, an active layer, and a second-conductivity-type semiconductor layer sequentially disposed on the intermediate layer. Each of the plurality of protrusions includes: a lower pattern including the same material as the first material of the substrate; and a feature pattern disposed on the lower pattern and including a second material different from the first material of the substrate. The intermediate layer includes silicon nitride (SiN). The feature pattern includes at least one of silicon oxide (SiO x )、silicon oxynitride (SiO x N y ) and magnesium fluoride (MgF 2 ).

[0008] According to one aspect of the present disclosure, a semiconductor light-emitting device includes: a substrate including a first material; a plurality of protrusions; a buffer layer on the substrate and the plurality of protrusions; an intermediate layer on the buffer layer; and a light-emitting stack including a first-conductivity-type semiconductor layer, an active layer, and a second-conductivity-type semiconductor layer sequentially disposed on the intermediate layer. Each of the plurality of protrusions includes: a lower pattern including the same material as the first material of the substrate; and a feature pattern on the lower pattern and including a second material different from the first material of the substrate. The intermediate layer includes silicon nitride (SiN). The buffer layer includes at least one of aluminum nitride (AlN), gallium nitride

[0009] (GaN), indium nitride (InN), indium gallium nitride (InGaN), aluminum gallium nitride (AlGaN), indium aluminum gallium nitride (InAlGaN), and aluminum indium nitride (Al InN). The feature pattern includes at least one of silicon oxide (SiO x )、silicon oxynitride (SiO x N y ) and magnesium fluoride (MgF 2 ). The plurality of protrusions are arranged in a hexagonal pattern.

[0010] Additional aspects may be set forth in part in the description which follows, and in part will be obvious from the description, and / or may be learned by practice of the presented embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above and other aspects, features, and advantages of certain embodiments of the present disclosure will become more apparent from the following description taken in conjunction with the drawings, in which:[[]]

[0012] Figure 1 is a cross-sectional view showing a semiconductor light-emitting device according to an embodiment;

[0013] Figure 2is according to an embodiment Figure 1 An enlarged view of a partial CX1;

[0014] Figure 3 is a schematic plan layout diagram of protrusions of a semiconductor light-emitting device according to an embodiment;

[0015] Figure 4 is a cross-sectional view showing a semiconductor light-emitting device according to an embodiment;

[0016] Figure 5 is a cross-sectional view showing a semiconductor light-emitting device according to an embodiment;

[0017] Figure 6 is a cross-sectional view showing a semiconductor light-emitting device according to an embodiment;

[0018] Figures 7 to 15 is a cross-sectional view showing a method of manufacturing a semiconductor light-emitting device according to an embodiment;

[0019] Figure 16A and Figure 16B are respectively cross-sectional views showing protrusions and a first conductive type semiconductor layer in a crystal growth process according to a comparative example and an example by scanning electron microscopy (SEM)

[0020] images;

[0021] Figure 17 is a graph showing transmission electron microscope-energy dispersive spectrometer (TEM-EDS) observation results of a semiconductor light-emitting device according to an embodiment;

[0022] Figure 18 is a cross-sectional view showing a light source module including a semiconductor light-emitting device according to an embodiment;

[0023] Figures 19 to 22 is a perspective view schematically showing a lighting device including a semiconductor light-emitting device according to an embodiment;

[0024] Figure 23 is a schematic diagram showing an indoor lighting control network system including a semiconductor light-emitting device according to an embodiment;

[0025] Figure 24 is a schematic diagram showing a network system including a semiconductor light-emitting device according to an embodiment. Detailed Description

[0026] The following description with reference to the accompanying drawings is provided to assist in a comprehensive understanding of embodiments of the present disclosure defined by the claims and their equivalents. Various specific details are included to aid understanding, but these are considered to be merely exemplary. Thus, those of ordinary skill in the art will recognize that various changes and modifications to the embodiments described herein can be made without departing from the scope and spirit of the present disclosure. Additionally, descriptions of well-known functions and structures are omitted for clarity and conciseness.

[0027] Regarding the description of the accompanying drawings, like reference numerals may be used to represent like or related elements. It will be understood that, unless the relevant context clearly indicates otherwise, the singular form of a noun corresponding to an item may include one or more things. As used herein, each phrase such as "A or B", "at least one of A and B", "at least one of A or B", "A, B, or C", "at least one of A, B, and C", and "at least one of A, B, or C" may include any possible combination of the items enumerated together in the corresponding phrase. As used herein, terms such as "first" and "second" or "1st" and "2nd" may be used simply to distinguish corresponding components from each other, rather than to limit the components in other respects (e.g., importance or order). It will be understood that if an element (e.g., a first element) is referred to as (with or without the terms "operatively" or "communicatively") "coupled with", "coupled to", "connected with", or "connected to" another element (e.g., a second element), it means that the element may be coupled to the other element directly (e.g., wired), wirelessly, or via a third element.

[0028] It will be understood that when an element or layer is referred to as "above", "on", "over", "below", "beneath", "under", "connected to", or "coupled to" another element or layer, the element or layer may be directly above, on, over, below, beneath, under, directly connected to, or directly coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as "directly above", "on", "over", "below", "beneath", "under", "directly connected to", or "directly coupled to" another element or layer, there are no intervening elements or layers.

[0029] The terms "upper", "middle", "lower", etc. may be replaced by terms such as "first", "second", "third" for describing the relative positions of components. The terms "first", "second", "third" may be used to describe various components, but the components are not limited by these terms. A "first component" may be referred to as a "second component". Alternatively or additionally, the terms "first", "second", "third", etc. may be used to distinguish components from each other, and do not limit the present disclosure. For example, the terms "first", "second", "third", etc. may not necessarily involve any form of order or numerical meaning.

[0030] As used herein, when an element or layer is referred to as "covering" another element or layer, "overlapping" with another element or layer, or "surrounding" another element or layer, the element or layer may cover at least a portion of the other element or layer, where the portion may include a part of the other element or may include the entire other element. Similarly, when an element or layer is referred to as "penetrating" another element or layer, the element or layer may penetrate at least a portion of the other element or layer, where the portion may include a part of the other element or may include the entire dimension (e.g., length, width, depth) of the other element.

[0031] References throughout this disclosure to "one embodiment", "an embodiment", "example embodiment" or similar language may indicate that a particular feature, structure, or characteristic described in connection with the indicated embodiment is included in at least one embodiment of the present solution. Thus, the phrases "in one embodiment", "in an embodiment", "in an example embodiment" and similar language throughout this disclosure may, but do not necessarily, all refer to the same embodiment. The embodiments described herein are example embodiments, and thus, the present disclosure is not limited thereto and may be implemented in various other forms.

[0032] As used herein, the terms "AlGaN", "Al x In y Ga z N", "AlInN", "AlN", "Al 2 O 3 ", "BCl 3 ", "CF 4 ", "GaInO", "GaN", "InAlGaN", "In x Al y Ga (1-x-y) N", "InGaN", "In x Ga 1-x N", "InN", "InSnO", "LiAlO 2 ", "LiGaO 2 ", "MgAl 2 O 4”, “MgF 2 ”, “MgO”, “SF 6 ”, “SiC”, “SiN”, “SnO”, “SiO x ”, “SiO x N y ”, “ZnInO”, “Zn (1-x) Mg x O”, “ZnSnO”, “ZrInSnO”, etc. may each refer to a material made of the elements included in each term, rather than a chemical formula representing a stoichiometric relationship.

[0033] Hereinafter, various embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0034] Figure 1 is a cross-sectional view showing a semiconductor light-emitting device according to an embodiment. Figure 2 is according to an embodiment of Figure 1 an enlarged view of a partial CX1. Figure 3 is a schematic plan layout view of a protrusion of a semiconductor light-emitting device according to an embodiment.

[0035] Referring to Figure 1 , the semiconductor light-emitting device 100 may include a substrate 110, a protrusion 120, a buffer layer 130, an intermediate layer 140, a light-emitting stack 150, a transparent electrode layer 160, a first electrode 172, and a second electrode 174.

[0036] In some embodiments, the substrate 110 may include, but is not limited to, sapphire (Al 2 O 3 ), silicon carbide (SiC), silicon (Si), magnesium aluminate (MgAl 2 O 4 ), magnesium oxide (MgO), lithium aluminate (LiAlO 2 ), lithium gallium oxide (LiGaO 2 ), and gallium nitride (GaN), etc. In some embodiments, the substrate 110 may be a transparent substrate and include, for example, sapphire (Al 2 O 3 ).

[0037] In some embodiments, the protrusion 120 may be disposed on the upper surface of the substrate 110. The protrusion 120 may include a lower pattern P1 connected to the substrate 110 and protruding from the substrate 110, and a feature pattern P2 disposed on the lower pattern P1 and formed of a material different from that of the lower pattern P1.

[0038] The lower pattern P1 may be integrally connected to the substrate 110 and may be formed of the same material as the substrate 110. For example, the lower pattern P1 may include, but is not limited to, sapphire (Al2 O 3 )), silicon carbide (SiC), silicon (Si), magnesium aluminate (MgAl 2 O 4 ), magnesium oxide (MgO), lithium aluminate (LiAlO 2 ), lithium gallium oxide (LiGaO 2 ), and at least one of gallium nitride (GaN).

[0039] The lower pattern P1 can be formed by removing a part of the substrate 110. In the etching process of forming the feature pattern P2 on the substrate 110, a part of the substrate 110 can be removed together. Therefore, the part of the substrate 110 under the feature pattern P2 (for example, the part of the substrate 110 covered by the feature pattern P2 and retained without being removed) can be referred to as the lower pattern P1.

[0040] In some embodiments, the feature pattern P2 can be formed of a material having a refractive index lower than that of the substrate 110. In some embodiments, the feature pattern P2 can have a refractive index of 1 to 1.7. In some embodiments, the feature pattern P2 can include, but is not limited to, silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), and magnesium fluoride (MgF 2 ), and at least one of them.

[0041] In some embodiments, the bottom surface of the feature pattern P2 can be in contact with the upper surface of the lower pattern P1 and can have a flat profile, and the width of the upper side of the feature pattern P2 can gradually decrease in the direction away from the upper surface of the lower pattern P1. In some embodiments, the feature pattern P2 can have a hemispherical shape. In some other embodiments, the feature pattern P2 can have a conical shape.

[0042] The lower pattern P1 can have a first height h1 from the upper surface of the substrate 110. For example, the first height h1 can be in the range of about 200 nanometers (nm) to about 400 nm. However, the present disclosure is not limited in this regard, and the first height h1 can be less than 200 nm or greater than 400 nm. The first height h1 can correspond to the depth at which the substrate 110 is etched. For example, it is the distance in the vertical direction Z between the upper surface of the lower pattern P1 and the upper surface of the substrate 110. The feature pattern P2 can have a second height h2, and the second height h2 can be greater than the first height h1. For example, the second height h2 can be in the range of about 200 nm to about 2 micrometers (μm). However, the present disclosure is not limited in this regard, and the second height h2 can be less than 200 nm or greater than 2 μm.

[0043] In some embodiments, the ratio of the second height h2 of the feature pattern P2 to the total height of the protrusion 120 may be in the range of about 0.5 to about 0.9. However, the present disclosure is not limited in this regard, and the ratio of the second height h2 of the feature pattern P2 to the total height of the protrusion 120 may be less than 0.5 or greater than 0.9. For example, the total height of the protrusion 120 may be the sum of the first height h1 of the lower pattern P1 and the second height h2 of the feature pattern P2, and the second height h2 of the feature pattern P2 may be in the range of about 50% to about 90% of the total height of the protrusion 120.

[0044] In some embodiments, the protrusions 120 may be arranged at fixed intervals over the entire area of the substrate 110 in a plan view. For example, as Figure 3 shown, the protrusions 120 may be arranged in a hexagonal or honeycomb arrangement in a plan view. Each protrusion 120 may have a first width w1, and the protrusions 120 may be separated from each other by a first distance d1 in the first horizontal direction X and / or in a diagonal direction. In some embodiments, the first width w1 of the protrusion 120 may be in the range of about 200 nm to about 5 μm, and the first distance d1 may be in the range of about 100 nm to about 5 μm. In some embodiments, the first distance d1 may be 0.5 times to 10 times the first width w1. That is, the ratio of the first distance d1 to the first width w1 may be in the range of 0.5 to 10. However, the present disclosure is not limited in this regard, and the first distance d1 and the first width w1 may have other values and / or ratios other than those discussed above.

[0045] The buffer layer 130 may be on the upper surface of the substrate 110 and on the upper surface of the protrusion 120. The buffer layer 130 may be formed in a conformal shape covering the upper surface of the protrusion 120, and may be formed to have a substantially uniform and / or the same thickness on the sidewall of the lower pattern P1 and the upper surface of the feature pattern P2, for example.

[0046] The buffer layer 130 may include a first portion 130_1 having a flat upper surface on the upper surface of the substrate 110 and a second portion 130_2 that protrudes convexly and covers the upper surface of the protrusion 120. For example, the second portion 130_2 of the buffer layer 130 may be in contact with the upper surface of the feature pattern P2 and the sidewall of the lower pattern P1.

[0047] In some embodiments, the buffer layer 130 may include, but is not limited to, at least one of aluminum nitride (AlN), gallium nitride (GaN), indium nitride (InN), indium gallium nitride (InGaN), aluminum gallium nitride (AlGaN), indium aluminum gallium nitride (InAlGaN), and aluminum indium nitride (AlInN). The buffer layer 130 may have a first thickness t1. For example, the first thickness t1 may be in the range of about 5 nm to about 30 nm. However, the present disclosure is not limited in this regard, and the first thickness t1 may be less than 5 nm or greater than 30 nm. In some embodiments, the buffer layer 130 may be formed at a temperature of about 500 degrees Celsius (°C) to about 600 °C and may include multiple layers having different compositions.

[0048] The intermediate layer 140 may be on the buffer layer 130. The intermediate layer 140 may be conformally disposed on the upper surface of the substrate 110 and on the upper surface of the protrusion 120. In some embodiments, the intermediate layer 140 may include, but is not limited to, silicon nitride (SiN). For example, the intermediate layer 140 may have a second thickness t2, and the second thickness t2 may be in the range of about to about 1 nm. However, the present disclosure is not limited in this regard, and the second thickness t2 may be less than or greater than 1 nm.

[0049] In some embodiments, the intermediate layer 140 may be formed by forming a single layer or forming five (5) or fewer material layers (e.g., five (5) or fewer single layers) on the surface of the buffer layer 130 via an atomic layer deposition (ALD) process. In some embodiments, the intermediate layer 140 may be formed by forming ten (10) or fewer material layers (e.g., ten (10) or fewer single layers) on the surface of the buffer layer 130 via an ALD process. In some embodiments, a single layer of silicon nitride (SiN) may be formed by continuously supplying a silicon (Si) precursor, purging the silicon (Si) precursor, supplying a reactant including nitrogen (N), and purging the reactant in an ALD process. In some embodiments, the intermediate layer 140 may be formed by repeating the unit deposition cycle several times to dozens of times, and the unit deposition cycle consists of supplying a silicon (Si) precursor, purging the silicon (Si) precursor, supplying a reactant including nitrogen (N), and purging the reactant.

[0050] In some embodiments, when the intermediate layer 140 is formed to have a relatively small second thickness t2, the intermediate layer 140 may not be clearly identified by observation tools such as, but not limited to, a scanning electron microscope (SEM) or a transmission electron microscope (TEM). For example, the interface between the intermediate layer 140 and the buffer layer 130 and / or the interface between the intermediate layer 140 and the light-emitting stack 150 may not be clearly identified. However, in such a case, the presence of silicon (Si) atoms and nitrogen (N) atoms included in the intermediate layer 140 can be examined by analysis tools such as, but not limited to, a transmission electron microscope - energy dispersive spectrometer (TEM-EDS), an SEM - energy dispersive spectrometer (SEM-EDS), or a secondary ion mass spectrometer (SIMS).

[0051] In some embodiments, the light-emitting stack 150 on the intermediate layer 140 may cover the protrusion 120. The light-emitting stack 150 may include a first-conductive-type semiconductor layer 152, an active layer 154, and a second-conductive-type semiconductor layer 156.

[0052] In some embodiments, the first-conductive-type semiconductor layer 152 may be and / or may include a nitride semiconductor having an n-type component (e.g., indium aluminum gallium nitride In x Al y Ga (1-x-y) N, where 0 ≤ x < 1, 0 ≤ y < 1, and 0 ≤ x + y < 1), and wherein, for example, the n-type impurity may be silicon (Si). As another example, the first-conductive-type semiconductor layer 152 may include gallium nitride (GaN) containing an n-type impurity.

[0053] In some embodiments, the first-conductive-type semiconductor layer 152 may include a first-conductive-type semiconductor contact layer and a current diffusion layer. The impurity concentration of the first-conductive-type semiconductor contact layer may be in the range of about 2×10 18 cm -3 to about 9×10 19 cm -3 . However, the present disclosure is not limited thereto. The thickness of the first-conductive-type semiconductor contact layer may be about 1 μm to about 5 μm. However, the present disclosure is not limited thereto. The current diffusion layer may have a different composition or may have a structure in which multiple indium aluminum gallium nitride (In x Al y Ga (1-x-y) N) layers having different impurity contents are alternately stacked. For example, the current diffusion layer may have an n-type superlattice structure in which n-type gallium nitride (GaN) layers and / or aluminum indium gallium nitride (Al x In y Ga zN, where 0 ≤ x, y, z ≤ 1 and x + y + z ≠ 0) layers are alternately stacked. The impurity concentration of the current diffusion layer can be about 2 × 10 18 cm -3 to about 9 × 10 19 cm -3 . However, the present disclosure is not limited thereto.

[0054] The active layer 154 can be disposed between the first conductive type semiconductor layer 152 and the second conductive type semiconductor layer 156. When the semiconductor light emitting device 100 is driven, the active layer 154 can emit light with a preset energy through the recombination of electrons and holes. The active layer 154 can have a multi-quantum well (MQW) structure, in which quantum well layers and quantum barrier layers are alternately stacked. For example, the quantum well layers and the quantum barrier layers can each include indium aluminum gallium nitride (In x Al y Ga (1-x-y) N) with different compositions. As another example, the quantum well layer can include indium gallium nitride (In x Ga 1-x N, where 0 ≤ x ≤ 1), and the quantum barrier layer can include gallium nitride (GaN) or aluminum gallium nitride (AlGaN). The thicknesses of the quantum well layer and the quantum barrier layer can each be in the range of about 1 nm to about 50 nm. In an embodiment, the active layer 154 can have a single quantum well structure, and is not limited to the multi-quantum well structure.

[0055] The second conductive type semiconductor layer 156 can be a nitride semiconductor layer having a composition of p-type indium aluminum gallium nitride (In x Al y Ga (1-x-y) N), for example, the p-type impurity can be magnesium (Mg). However, the present disclosure is not limited thereto.

[0056] In some embodiments, the second conductive type semiconductor layer 156 can include an electron blocking layer, a low-concentration p-type gallium nitride (GaN) layer, and a high-concentration p-type gallium nitride (GaN) layer that can be stacked vertically. For example, the electron blocking layer can have a structure in which multiple indium aluminum gallium nitride (In x Al y Ga (1-x-y) N) layers (each layer having a thickness of about 5 nm to about 100 nm) are alternately stacked, or can be a single layer including aluminum gallium nitride (Al y Ga (1-y) N, where 0 < y ≤ 1). The energy band gap of the electron blocking layer can decrease as the distance from the active layer 154 increases. For example, the aluminum (Al) composition of the electron blocking layer can decrease as the distance from the active layer 154 increases.

[0057] The transparent electrode layer 160 may be on the light-emitting stack 150. The transparent electrode layer 160 may be above the upper surface of the first-conductive-type semiconductor layer 152. In some embodiments, the transparent electrode layer 160 may also be on the upper surface of the second-conductive-type semiconductor layer 156. For example, the transparent electrode layer 160 may be a transparent conductive oxide layer or a nitride layer, and may include, but is not limited to, indium tin oxide (InSnO), zinc-doped indium tin oxide (ZnInSnO), indium zinc oxide (ZnInO), gallium indium oxide (GaInO), zinc tin oxide (ZnSnO), fluorine-doped tin oxide (F-doped SnO), aluminum-doped zinc oxide (Al-doped ZnO), gallium-doped zinc oxide (Ga-doped ZnO), tin-doped indium (In 4 Sn 3 O 12 ) and magnesium zinc oxide (Zn (1-x) Mg x O, where 0 ≤ x ≤ 1), and at least one of them. In some embodiments, the transparent electrode layer 160 may further include graphene (C).

[0058] The first electrode 172 may be on the upper surface of the first-conductive-type semiconductor layer 152, and the second electrode 174 may be on the upper surface of the second-conductive-type semiconductor layer 156. The first electrode 172 may include, but is not limited to, at least one of silver (Ag), nickel (Ni), aluminum (Al), chromium (Cr), rhodium (Rh), palladium (Pd), iridium (Ir), ruthenium (Ru), magnesium (Mg), zinc (Zn), platinum (Pt), and gold (Au). The second electrode 174 may have a reflective electrode structure. The second electrode 174 may include, but is not limited to, at least one of silver (Ag), nickel (Ni), aluminum (Al), chromium (Cr), rhodium (Rh), palladium (Pd), iridium (Ir), ruthenium (Ru), magnesium (Mg), zinc (Zn), platinum (Pt), and gold (Au). In some embodiments, the second electrode 174 may have a bilayer structure such as nickel / silver (Ni / Ag), zinc / silver (Zn / Ag), nickel / aluminum (Ni / Al), zinc / aluminum (Zn / Al), palladium / silver (Pd / Ag), palladium / aluminum (Pd / Al), iridium / silver (Ir / Ag), iridium / gold (Ir / Au), platinum / aluminum (Pt / Al), or platinum / silver (Pt / Ag).

[0059] According to some embodiments, the protrusion 120 may be on the upper surface of the substrate 110, and the characteristic pattern P2 of the protrusion 120 may be formed of a material having a refractive index lower than that of the substrate 110. Therefore, the light extraction efficiency of the semiconductor light-emitting device 100 may be improved as compared with related semiconductor light-emitting devices.

[0060] In addition, since the intermediate layer 140 is between the buffer layer 130 and the light-emitting stack 150, abnormal crystal growth on the inclined surface of the protrusion 120 (e.g., on the inclined side surface of the buffer layer 130 disposed on the inclined surface of the protrusion 120) can be potentially reduced and / or prevented. Accordingly, the light-emitting stack 150 can have an improved crystal quality, and thus, the semiconductor light-emitting device 100 can have improved optical characteristics when compared with related semiconductor light-emitting devices.

[0061] Figure 4 FIG. 4 is a cross-sectional view showing a semiconductor light-emitting device 100A according to an embodiment.

[0062] The semiconductor light-emitting device 100A may include the semiconductor light-emitting device 100 described above with reference to Figures 1 to 3 and / or may be similar to the semiconductor light-emitting device 100 described above with reference to Figures 1 to 3 in many aspects and may include additional features not mentioned above. Accordingly, for the sake of brevity, a repetitive description of the semiconductor light-emitting device 100 described above with reference to Figures 1 to 3 may be omitted.

[0063] Referring to Figure 4 , the substrate 110 may provide a light extraction surface, and the semiconductor light-emitting device 100A may be provided in a flip-chip form. As used herein, one surface of the substrate 110 on which the protrusion 120 is not formed may be referred to as the upper surface of the substrate 110, and one surface of the substrate 110 on which the protrusion 120 is formed may be referred to as the bottom surface of the substrate 110. The protrusion 120 may be disposed on the bottom surface of the substrate 110, and the buffer layer 130 and the intermediate layer 140 covering the protrusion 120 may be above the bottom surface of the substrate 110. The light-emitting stack 150 may be on the bottom surface of the substrate 110, and the protrusion 120, the buffer layer 130, and the intermediate layer 140 may be between the substrate 110 and the light-emitting stack 150. The first electrode 172 and the second electrode 174 may be respectively connected to the first conductivity type semiconductor layer 152 and the second conductivity type semiconductor layer 156 of the light-emitting stack 150. The first electrode 172 and the second electrode 174 may be attached to a package substrate such that the upper surface of the substrate 110 or the light extraction surface of the substrate 110 faces upward, and thus, a flip-chip type semiconductor light-emitting device 100A may be provided.

[0064] Figure 5 FIG. 5 is a cross-sectional view showing a semiconductor light-emitting device 100B according to an embodiment.

[0065] The semiconductor light-emitting device 100B may include the semiconductor light-emitting devices 100 and 100A described above with reference to Figures 1 to 4 and / or may be similar to the semiconductor light-emitting devices 100 and 100A described above with reference to Figures 1 to 4The described semiconductor light-emitting devices 100 and 100A are similar and may include additional features not mentioned above. Thus, for the sake of brevity, the repeated descriptions of the semiconductor light-emitting devices 100 and 100A referred to above may be omitted. Figures 1 to 4 The repeated descriptions of the semiconductor light-emitting devices 100 and 100A.

[0066] Referring to Figure 5 , the semiconductor light-emitting device 100B may include a substrate 110, a protrusion 120, a buffer layer 130, an intermediate layer 140, and a light-emitting stack 150.

[0067] The substrate 110 may have a light extraction surface, and the semiconductor light-emitting device 100B may be provided in a flip-chip form. As used herein, one surface of the substrate 110 on which the protrusion 120 is not formed may be referred to as the upper surface of the substrate 110, and one surface of the substrate 110 on which the protrusion 120 is formed may be referred to as the bottom surface of the substrate 110. The protrusion 120 may be disposed on the bottom surface of the substrate 110, and the buffer layer 130 and the intermediate layer 140 covering the protrusion 120 may be disposed on the bottom surface of the substrate 110. The light-emitting stack 150 may be above the bottom surface of the substrate 110, and the protrusion 120, the buffer layer 130, and the intermediate layer 140 may be between the substrate 110 and the light-emitting stack 150.

[0068] The light-emitting stack 150 may include a plurality of openings E1. The plurality of openings E1 may penetrate the second-conductive-type semiconductor layer 156 and the active layer 154 to expose the surface of the first-conductive-type semiconductor layer 152. An insulating spacer 186 may be on the inner wall of each of the plurality of openings E1. A first electrode 172A in each of the plurality of openings E1 may be on the surface of the first-conductive-type semiconductor layer 152, and a first pad electrode 182 fills the interior of the plurality of openings E1 and is electrically connected to the first electrode 172A. A second electrode 174A may be on the bottom surface of the second-conductive-type semiconductor layer 156, and a second pad electrode 184 may be on the second electrode 174A. The first pad electrode 182 and the second pad electrode 184 may be attached to a package substrate such that the upper surface of the substrate 110 or the light extraction surface of the substrate 110 faces upward. Thus, a flip-chip type semiconductor light-emitting device 100B may be provided.

[0069] Figure 6 is a cross-sectional view showing a semiconductor light-emitting device 100C according to an embodiment.

[0070] The semiconductor light-emitting device 100C may include the semiconductor light-emitting devices 100, 100A, and 100B described above and / or may be similar to the semiconductor light-emitting devices 100, 100A, and 100B described above in many aspects and may include additional features not mentioned above. Thus, for the sake of brevity, the above references Figures 1 to 5 The descriptions of the semiconductor light-emitting devices 100, 100A, and 100B may be omitted. Figures 1 to 5 The descriptions of the semiconductor light-emitting devices 100, 100A, and 100B may be omitted.Figures 1 to 5 Repeated description of the described semiconductor light-emitting devices 100, 100A, and 100B.

[0071] Referring to Figure 6 , the protrusion 110P can be defined on the substrate 110, and the protrusion 110P can be integrally connected to the substrate 110. The protrusion 110P can be formed by etching a part of the substrate 110. For example, the protrusion 110P can include, but is not limited to, sapphire (Al 2 O 3 ), silicon carbide (SiC), silicon (Si), magnesium aluminate (MgAl 2 O 4 ), magnesium oxide (MgO), lithium aluminate (LiAlO 2 ), lithium gallium oxide (LiGaO 2 ), and gallium nitride (GaN). The buffer layer 130 and the intermediate layer 140 can be disposed on the surface of the protrusion 110P.

[0072] Figures 7 to 15 is a cross-sectional view showing a method of manufacturing the semiconductor light-emitting device 100 according to an embodiment.

[0073] Referring to Figure 7 , a feature layer 120L can be formed on the substrate 110. The substrate 110 can include, but is not limited to, sapphire (Al 2 O 3 ), silicon carbide (SiC), silicon (Si), magnesium aluminate (MgAl 2 O 4 ), magnesium oxide (MgO), lithium aluminate (LiAlO 2 ), lithium gallium oxide (LiGaO 2 ), and gallium nitride (GaN). In some embodiments, the feature layer 120L can be formed of a material having a refractive index different from that of the substrate 110. In some embodiments, the feature layer 120L can have a refractive index of about 1.0 to about 1.7. For example, the feature layer 120L can include at least one of silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), and magnesium fluoride (MgF 2 ). In some embodiments, the feature layer 120L can be formed by a chemical vapor deposition process, a physical vapor deposition process, an atomic layer deposition process, or the like.

[0074] Referring to Figure 8 , a photoresist pattern 210 can be formed on the feature layer 120L.

[0075] In some embodiments, the photoresist pattern 210 may be formed by coating the feature layer 120L with a photoresist film and then performing an exposure and development process on the photoresist film. In some embodiments, the photoresist pattern 210 may be formed by performing a reflow process at a preset temperature. In such embodiments, the photoresist pattern 210 may have a shape that protrudes upwardly convexly, or may have a hemispherical shape.

[0076] Referring Figure 9 , the feature pattern P2 may be formed from the feature layer 120L by etching the feature layer 120L using the photoresist pattern 210 as an etch mask (e.g., by a dry etching process). In some embodiments, the shape of the photoresist pattern 210 may be transferred to the feature pattern P2 during the etching process, and thus, the feature pattern P2 may be formed to have a shape corresponding to the convex protruding shape of the photoresist pattern 210. In some embodiments, the feature pattern P2 may have a hemispherical shape or a conical shape.

[0077] In some embodiments, an etching gas such as carbon tetrafluoride (CF 4 ), sulfur hexafluoride (SF 6 ), chlorine gas (Cl 2 ), boron trichloride (BCl 3 ), argon (Ar) or nitrogen (N) may be used to perform the dry etching process for forming the feature pattern P2.

[0078] A portion of the substrate 110 may be further removed during the etching process for forming the feature pattern P2 or in another etching process after the etching process for forming the feature pattern P2, and thus, the lower pattern P1 may be formed under the feature pattern P2. The lower pattern P1 may be covered by the feature pattern P2 and may indicate the portion of the substrate 110 that remains unremoved during the etching process. After the etching process, the upper surface of the substrate 110 may be retracted or recessed and disposed at a vertical level lower than the upper surface of the lower pattern P1.

[0079] In an embodiment, the lower pattern P1 and the feature pattern P2 on the lower pattern P1 may be referred to as the protrusion 120. For example, the protrusions 120 may be arranged in a hexagonal pattern as Figure 3 shown.

[0080] Referring Figure 10 , a buffer layer 130 may be formed over the substrate 110 and the protrusions 120.

[0081] In some embodiments, the buffer layer 130 may include, but is not limited to, at least one of aluminum nitride (AlN), gallium nitride (GaN), indium nitride (InN), indium gallium nitride (InGaN), aluminum gallium nitride (AlGaN), indium aluminum gallium nitride (InAlGaN), and aluminum indium nitride (AlInN). In some embodiments, the buffer layer 130 may be formed at a temperature of about 500 °C to about 600 °C by a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process.

[0082] The buffer layer 130 may include a first portion 130_1 having a flat upper surface and disposed on the upper surface of the substrate 110, and a second portion 130_2 that protrudes convexly and covers the upper surface of the protrusion 120. For example, the second portion 130_2 of the buffer layer 130 may be in contact with the upper surface of the feature pattern P2 and the sidewalls of the lower pattern P1.

[0083] In some embodiments, the buffer layer 130 may have a first thickness t1. For example, the first thickness t1 may be in the range of about 5 nm to about 30 nm. However, the present disclosure is not limited thereto.

[0084] Referring to Figure 11 , an intermediate layer 140 may be formed on the buffer layer 130.

[0085] In some embodiments, the intermediate layer 140 may be formed of silicon nitride (SiN). For example, the intermediate layer 140 may have a second thickness t2, and the second thickness t2 may be in the range of about to about 1 nm. However, the present disclosure is not limited thereto. The intermediate layer 140 may be conformally disposed on the first portion 130_1 and the second portion 130_2 of the buffer layer 130.

[0086] In some embodiments, the intermediate layer 140 may be formed by forming a single layer or forming five (5) or fewer material layers on the surface of the buffer layer 130 via an ALD process. In some embodiments, the intermediate layer 140 may be formed by forming ten (10) or fewer material layers on the surface of the buffer layer 130 via an ALD process. In some embodiments, a single layer of silicon nitride (SiN) may be formed by continuously supplying a silicon (Si) precursor, purging the silicon (Si) precursor, supplying a reactant including nitrogen (N), and purging the reactant in an ALD process. In some embodiments, the intermediate layer 140 may be formed by repeating several or dozens of unit deposition cycles, which consist of supplying a silicon (Si) precursor, purging the silicon (Si) precursor, supplying a reactant including nitrogen (N), and purging the reactant.

[0087] Referring to Figure 12 and Figure 13 , a first conductivity type semiconductor layer 152 may be grown on the upper surface of the intermediate layer 140. AsFigure 12 As shown, on the first portion 130_1 of the buffer layer 130 and on the intermediate layer 140 disposed on the first portion 130_1 of the buffer layer 130, the first-conductivity-type semiconductor layer 152 can nucleate and grow epitaxially. On the second portion 130_2 of the buffer layer 130 and on the intermediate layer 140 disposed on the second portion 130_2 of the buffer layer 130, the first-conductivity-type semiconductor layer 152 may not nucleate.

[0088] In a related method of manufacturing a semiconductor light-emitting device in which the intermediate layer 140 may not be formed, a pseudo-plane on which single crystal growth can be performed may be on the inclined surface (e.g., the second portion 130_2) of the buffer layer 130. Therefore, nucleation may occur on the inclined surface of the buffer layer 130. Thus, due to the grains nucleating on the inclined surface of the buffer layer 130, the crystal quality of the first-conductivity-type semiconductor layer 152 may be reduced.

[0089] In some embodiments, since the intermediate layer 140 is on the inclined surface of the buffer layer 130 (e.g., on the second portion 130_2 of the buffer layer 130), the first-conductivity-type semiconductor layer 152 does not nucleate on the inclined surface, and since the first-conductivity-type semiconductor layer 152 only nucleates on the flat upper surface of the buffer layer 130 (i.e., on the first portion 130_1 of the buffer layer 130) (on the intermediate layer 140 on the buffer layer 130), the crystal quality of the first-conductivity-type semiconductor layer 152 can potentially be improved when compared with related semiconductor light-emitting devices.

[0090] As Figure 13 shown, the first-conductivity-type semiconductor layer 152 can be grown laterally by an epitaxial lateral overgrowth process. Therefore, the first-conductivity-type semiconductor layer 152 can be formed to have a thickness large enough to completely cover the protrusion 120 and can have a flat top surface.

[0091] Since the first-conductivity-type semiconductor layer 152 grows epitaxially and laterally over the upper surface of the first portion 130_1 of the buffer layer 130, dislocation defects caused by the difference in lattice constants between the substrate 110 and the first-conductivity-type semiconductor layer 152 do not propagate upward. Therefore, when compared with related semiconductor light-emitting devices, the dislocation density in the first-conductivity-type semiconductor layer 152 can be reduced, and the crystal quality can potentially be improved.

[0092] Referring to Figure 14 , a light-emitting stack 150 can be formed by sequentially forming an active layer 154 and a second-conductivity-type semiconductor layer 156 on the first-conductivity-type semiconductor layer 152.

[0093] Referring to Figure 15, a part of the etchable light-emitting stack 150 may be etched to expose the upper surface of the first-conductive-type semiconductor layer 152. Thereafter, a first electrode 172 may be formed on the upper surface of the first-conductive-type semiconductor layer 152, and a transparent electrode layer 160 and a second electrode 174 may be formed on the upper surface of the second-conductive-type semiconductor layer 156.

[0094] The semiconductor light-emitting device 100 may be manufactured by performing the process described above with reference to Figures 7 to 15 the description.

[0095] According to the method of manufacturing a semiconductor light-emitting device, according to an embodiment, the intermediate layer 140 may prevent abnormal crystal growth on the inclined surface of the protrusion 120 during the epitaxial growth process of the light-emitting stack 150. Therefore, when compared with related semiconductor light-emitting devices, the crystallinity of the light-emitting stack 150 may be potentially improved, and the semiconductor light-emitting device 100 may have potentially improved light extraction efficiency.

[0096] Figure 16A and Figure 16B are SEM images showing the protrusion and the first-conductive-type semiconductor layer in the crystal growth process according to a comparative example and an example, respectively.

[0097] In a related method of manufacturing a semiconductor light-emitting device according to a comparative example, a buffer layer 130 may be formed on the protrusion 120, an intermediate layer may not be formed on the buffer layer 130, and an epitaxial growth process of forming the first-conductive-type semiconductor layer 152 on the buffer layer 130 may be performed. Figure 16A shows the planar shapes of the first-conductive-type semiconductor layer 152 and the protrusion 120 when the first-conductive-type semiconductor layer 152 grows to have a preset thickness in a state where the buffer layer 130 is formed on the protrusion 120.

[0098] Referring to Figure 16A , in a related method of manufacturing a semiconductor light-emitting device according to a comparative example, microcrystalline debris DB such as nucleation seeds or nucleation crystals may be observed to be formed on the inclined surface of the protrusion 120 (e.g., on the second portion 130_2 of the buffer layer 130). Since the inclined surface of the protrusion 120 serves as a pseudo-crystal plane for crystal growth and causes abnormal crystal growth on the inclined surface of the protrusion 120, the microcrystalline debris DB may be formed. The microcrystalline debris DB may cause dislocations to occur in the first-conductive-type semiconductor layer 152, and thus, the crystal quality of the first-conductive-type semiconductor layer 152 may be reduced.

[0099] Aspects of the present disclosure provide a method of manufacturing a semiconductor light emitting device 100 according to an example, in which a buffer layer 130 may be formed on a protrusion 120, an intermediate layer 140 may be formed on the buffer layer 130, and an epitaxial growth process of forming a first conductive type semiconductor layer 152 on the intermediate layer 140 may be performed. Figure 16B Shows the planar shapes of the first conductive type semiconductor layer 152 and the protrusion 120 when the first conductive type semiconductor layer 152 grows to have a preset thickness in a state where the buffer layer 130 and the intermediate layer 140 are formed on the protrusion 120.

[0100] Referring Figure 16B , microcrystalline debris DB such as nucleation seeds or nucleation crystals is not formed on the inclined surface of the protrusion 120 (e.g., on the second portion 130_2 of the buffer layer 130). Instead, it can be observed that the inclined surface of the protrusion 120 (e.g., the upper surface of the intermediate layer 140 disposed on the second portion 130_2 of the buffer layer 130) remains a smooth and clean surface. Therefore, the intermediate layer 140 can prevent and / or reduce the occurrence of crystal defects such as dislocations in the first conductive type semiconductor layer 152. Thus, the crystal quality of the first conductive type semiconductor layer 152 can be improved when compared with related semiconductor light emitting devices.

[0101] Table 1 below shows the results of X-ray diffraction analysis diagrams of the first conductive type semiconductor layer 152 obtained by a method of manufacturing a semiconductor light emitting device according to a comparative example and a method of manufacturing a semiconductor light emitting device according to an example. Specifically, the full width at half maximum (FWHM) of the (002) peak in the X-ray diffraction analysis diagram of the first conductive type semiconductor layer 152 is compared. The full width at half maximum can indicate the peak width at a point where the intensity is half of the maximum intensity at the (002) peak. As shown in Table 1, the full width at half maximum of the (002) peak according to the comparative example is 150 arcseconds. In contrast, the full width at half maximum of the (002) peak according to the example is 144 arcseconds. Thus, the crystallinity is improved when compared with the comparative example.

[0102] In the manufacturing method according to an embodiment, even when the intermediate layer 140 is formed of silicon nitride (SiN) on the buffer layer 130 to have a preset thickness, the intermediate layer 140 can be formed to be relatively thin and does not interfere with the crystal growth of the first conductive type semiconductor layer 152. Specifically, factors that cause defects (such as abnormal growth on the inclined surface) can be prevented and / or reduced. Thus, the first conductive type semiconductor layer 152 can have improved crystal quality when compared with related semiconductor light emitting devices.

[0103] Table 1: X-ray diffraction analysis

[0104]

[0105] Figure 17 is a graph showing the TEM-EDS observation results of a semiconductor light-emitting device according to an embodiment.

[0106] Referring to Figure 17 , a relatively thin intermediate layer 140 may be between the first conductive type semiconductor layer 152 and the buffer layer 130, and as a result of elemental composition analysis measured by TEM-EDS, it can be seen that a relatively large content of silicon (Si) element is observed at the position corresponding to the intermediate layer 140.

[0107] Figure 18 is a perspective view schematically showing a lighting device including a semiconductor light-emitting device according to an embodiment.

[0108] Referring to Figure 18 , the headlight module 2020 may be installed in the headlight unit 2010 of a vehicle, the side mirror light module 2040 may be installed in the outside mirror unit 2030, and the taillight module 2060 may be installed in the taillight unit 2050. At least one of the headlight module 2020, the side mirror light module 2040, and the taillight module 2060 may be a light source module including at least one of the semiconductor light-emitting devices 100, 100A, 100B, and 100C described above with reference to Figures 1 to 15 .

[0109] Figure 19 is a schematic perspective view of a board lighting device including a semiconductor light-emitting device according to an embodiment.

[0110] Referring to Figure 19 , the board lighting device 2100 may include a light source module 2110, a power supply 2120, and a housing 2130.

[0111] The light source module 2110 may include a light-emitting device array as a light source, and may include at least one of the semiconductor light-emitting devices 100, 100A, 100B, and 100C described above with reference to Figures 1 to 15 as a light source. The light source module 2110 may have an overall planar shape.

[0112] The power supply 2120 may supply power to the light source module 2110. The housing 2130 may have an accommodation space to accommodate the light source module 2110 and the power supply device 2120 therein, and may have one side formed in a hexahedron shape, but is not limited thereto. The light source module 2110 may be arranged to emit light through an open side of the housing 2130.

[0113] Figure 20 is a schematic exploded perspective view of a lighting device including a semiconductor light-emitting device according to an embodiment.

[0114] Referring to Figure 20, the lighting device 2200 may include a socket 2210, a power supply unit 2220, a heat dissipation unit 2230, a light source module 2240, and an optical unit 2250.

[0115] The socket 2210 can replace an existing lighting device. Electric power supplied to the lighting device 2200 can be applied through the socket 2210. The power supply unit 2220 may include a first power unit 2221 and a second power unit 2222 that are to be assembled integrally. The heat dissipation unit 2230 may include an internal heat dissipation unit 2231 and an external heat dissipation unit 2232. The internal heat dissipation unit 2231 can be directly connected to the light source module 2240 and / or the power supply unit 2220, and heat can be transferred from the internal heat dissipation unit 2231 to the external heat dissipation unit 2232. In an embodiment, the optical unit 2250 may include an internal optical unit and an external optical unit, and can evenly distribute the light emitted by the light source module 2240.

[0116] The light source module 2240 can receive power from the power supply unit 2220 and emit light to the optical unit 2250. The light source module 2240 may include one or more light emitting device packages 2241, a circuit board 2242, and a controller 2243. The controller 2243 can store driving information of the light emitting device packages 2241. Each of the light emitting device packages 2241 may include at least one of the semiconductor light emitting devices 100, 100A, 100B, and 100C described above with reference to Figures 1 to 15 description.

[0117] Figure 21 is an exploded perspective view schematically showing a bar-shaped lighting device including a semiconductor light emitting device according to an embodiment.

[0118] With reference to Figure 21 , the lighting device 2400 may include a heat dissipation member 2401, a cover 2427, a light source module 2421, a first socket 2405, and a second socket 2423. A plurality of heat dissipation fins 2450 and 2409 may be formed in an uneven shape on the inner surface and / or outer surface of the heat dissipation member 2401, and the heat dissipation fins 2450 and 2409 may be designed to have various shapes and spacings. A support member 2413 having a protruding shape may be formed inside the heat dissipation member 2401. The light source module 2421 may be fixed to the support member 2413. Locking claws 2411 may be formed at both ends of the heat dissipation member 2401.

[0119] Locking grooves 2429 may be formed in the cover 2427, and the locking claws 2411 of the heat dissipation member 2401 may be coupled to the locking grooves 2429 in a hook-coupling structure. The positions where the locking grooves 2429 and the locking claws 2411 are formed may change with each other.

[0120] The light source module 2421 may include a printed circuit board 2419, a light source 2417, and a controller 2415. The controller 2415 may store driving information of the light source 2417. Circuit leads for operating the light source 2417 may be formed in the printed circuit board 2419. Additionally, components for operating the light source 2417 may also be included in the printed circuit board 2419. The light source 2417 may include at least one of the semiconductor light-emitting devices 100, 100A, 100B, and 100C described above with reference to Figures 1 to 15 The at least one of the semiconductor light-emitting devices 100, 100A, 100B, and 100C described above with reference to

[0121] The first socket 2405 and the second socket 2423 are a pair of sockets and may be coupled to both ends of a cylindrical cover unit including a heat dissipation member 2401 and a cover 2427. For example, the first socket 2405 may include electrode terminals 2403 and a power supply 2407, and dummy terminals 2425 may be disposed in the second socket 2423. Additionally, an optical sensor and / or a communication module may be built into the first socket 2405 or the second socket 2423.

[0122] Figure 22 is an exploded perspective view schematically showing a lighting device including a semiconductor light-emitting device according to an embodiment.

[0123] Referring to Figure 22 According to the present embodiment, the difference between the lighting device 2500 and Figure 20 the lighting device 2200 shown is that a reflector 2310 and a communication module 2320 are included on the upper part of the light source module 2240. The reflector 2310 may reduce glare by evenly spreading the light from the light source to the sides and the rear.

[0124] The communication module 2320 may be mounted on the upper part of the reflector 2310, and home network communication may be achieved through the communication module 2320. For example, the communication module 2320 may include a wireless communication module using ZigBee, Wi-Fi (Wireless Fidelity), Li-Fi (Light Fidelity), etc., and may control the lighting of lighting devices installed inside and outside the home (such as turning on and off and brightness adjustment of lighting devices installed inside and outside the home), or may control electronic devices installed inside and outside the home (such as a television (TV), a refrigerator, an air conditioner, and a door lock, a car, and a car system). The reflector 2310 and the communication module 2320 may be covered by a cover unit 2330.

[0125] Figure 23 is a schematic diagram showing an indoor lighting control network system including a semiconductor light-emitting device according to an embodiment.

[0126] Referring to Figure 23, the network system 3000 may include a complex intelligent lighting - network system, in which lighting technologies using light - emitting devices such as light - emitting diodes (LEDs), Internet of Things (IoT) technologies, and wireless communication technologies are combined with each other. The network system 3000 may be implemented by various lighting devices and wired and wireless communication devices, or may be implemented based on the IoT environment to collect and process various types of information and provide various types of information to users.

[0127] The LED lamp 3200 included in the network system 3000 may receive information about the surrounding environment from the gateway 3100, control the lighting of the LED lamp 3200 itself, and perform functions such as checking and controlling the operating states of multiple devices 3300 to 3800 included in the IoT environment based on functions such as visible - light communication of the LED lamp 3200. The LED lamp 3200 may include at least one of the semiconductor light - emitting devices 100, 100A, 100B, and 100C described above with reference to Figures 1 to 15 The LED lamp 3200 may be communicatively connected to the gateway 3100 through a wireless communication protocol (such as but not limited to WiFi, Zigbee, or LiFi), and may have at least one lamp communication module 3210 for this purpose.

[0128] When the network system 3000 is applied to a home, the multiple devices 3300 to 3800 may include household appliances 3300, digital door locks 3400, garage door locks 3500, lighting switches 3600 installed on walls, etc., routers 3700 for wireless communication network relay, and mobile devices 3800 such as smart phones, tablets, and laptop computers.

[0129] In the network system 3000, the LED lamp 3200 may check the operating states of the multiple devices 3300 to 3800 through a wireless communication network (such as Zigbee, WiFi, LiFi, etc.) installed in the home, or may automatically adjust the illuminance of the LED lamp 3200 itself according to the surrounding environment and situation. In addition, the multiple devices 3300 to 3800 included in the network system 3000 may also be controlled using visible light emitted from the LED lamp 3200 through LiFi communication.

[0130] In an embodiment, the LED lamp 3200 may automatically adjust the illumination of the LED lamp 3200 based on the ambient information transmitted from the gateway 3100 through the lamp communication module 3210 or the ambient information collected from sensors mounted on the LED lamp 3200. For example, the illumination brightness of the LED lamp 3200 may be automatically adjusted according to the type of program being broadcast on the television 3310 or the brightness of the screen. To this end, the LED lamp 3200 may receive the operation information of the television 3310 from the lamp communication module 3210 connected to the gateway 3100. The lamp communication module 3210 may be integrated with the sensors and / or controllers included in the LED lamp 3200.

[0131] For example, while no one is at home, after a period of time has passed since the digital door lock 3400 has been locked, by turning off the LED lamps 3200 that may be on, power waste may potentially be reduced and / or prevented. Alternatively or additionally, in a state where a security mode is set through the mobile device 3800 or the like, when the digital door lock 3400 is locked while no one is at home, the LED lamps 3200 may also be maintained in the on state.

[0132] The operation of the LED lamp 3200 may also be controlled based on the ambient information collected by various sensors connected to the network system 3000. For example, when the network system 3000 is installed in a building, lighting devices, position sensors, and communication modules that may be installed in the building and combined with each other may collect the position information of people in the building and turn on and / or off the lighting devices and / or provide the collected information in real time. Thus, facilities may be effectively managed, and idle space may be effectively utilized.

[0133] Figure 24 It is a schematic diagram showing a network system including a semiconductor light-emitting device according to an embodiment.

[0134] Figure 24 An embodiment of a network system 4000 applied to an open space is shown. The network system 4000 may include a communication connection device 4100, a plurality of lighting fixtures (e.g., a first lighting fixture 4120 and a second lighting fixture 4150) installed at a preset interval and communicatively connected to the communication connection device 4100, a server 4160, a computer 4170 for controlling the server 4160, a communication base station 4180, a communication network 4190 for connecting communicable devices to each other, and a mobile device 4200.

[0135] A plurality of lighting fixtures 4120 and 4150 can be installed in an open outdoor space (such as but not limited to a street or a park), and can respectively include intelligent engines (for example, a first intelligent engine 4130 and a second intelligent engine 4140). The first intelligent engine 4130 and the second intelligent engine 4140 can include a light-emitting device for emitting light, a driver for driving the light-emitting device, a sensor for collecting information about the surrounding environment, a communication module, etc. The light-emitting device included in the first intelligent engine 4130 or the second intelligent engine 4140 can include at least one of the semiconductor light-emitting devices 100, 100A, 100B, and 100C described above with reference to Figures 1 to 15 at least one of the semiconductor light-emitting devices 100, 100A, 100B, and 100C described above with reference to

[0136] The first intelligent engine 4130 and the second intelligent engine 4140 can communicate with other surrounding devices according to the communication protocols of the communication module (such as but not limited to WiFi, Zigbee, and LiFi). The first intelligent engine 4130 can be communicatively connected to the second intelligent engine 4140, and WiFi extension technology (such as, for example, WiFi Mesh) can be used for communication between the first intelligent engine 4130 and the second intelligent engine 4140. The first intelligent engine 4130 can be connected to the communication connection device 4100 and / or connected to the communication network 4190 through wired / wireless communication.

[0137] The communication connection device 4100 can include an access point (AP), and the access point (AP) can perform wired or wireless communication and can serve as a medium for communication between the communication network 4190 and other devices. The communication connection device 4100 can be connected to the communication network 4190 through at least one of wired communication and wireless communication, and can be mechanically stored, for example, in the first lighting fixture 4120 or the second lighting fixture 4150.

[0138] The communication connection device 4100 can be connected to the mobile device 4200 through a communication protocol such as but not limited to WiFi. A user of the mobile device 4200 can receive the surrounding environment information that can be collected by the plurality of intelligent engines 4130 and 4140 through the communication connection device 4100 of the intelligent engine 4130 connected to the adjacent surrounding lighting fixture 4120. The surrounding environment information can include but not limited to surrounding traffic information, weather information, etc. The mobile device 4200 can also be connected to the communication network 4190 in a wireless cellular communication manner (such as but not limited to the third-generation (3G) network, the fourth-generation (4G) network, the fifth-generation (5G) network, etc.) through the communication base station 4180.

[0139] In an embodiment, a server 4160 connected to a communication network 4190 may receive information collected by a first smart engine 4130 and a second smart engine 4140 respectively installed on a first lighting fixture 4120 and a second lighting fixture 4150, and simultaneously monitor the operating states of the first lighting fixture 4120 and the second lighting fixture 4150. The server 4160 may be connected to a computer 4170 that can provide a management system, and the computer 4170 may execute software that can monitor and manage the operating states of the first smart engine 4130 and the second smart engine 4140.

[0140] A semiconductor light emitting device according to an embodiment may include protrusions disposed on a substrate, and may include a buffer layer and an intermediate layer covering the protrusions. The intermediate layer may prevent abnormal crystal growth on the inclined surfaces of the protrusions during the epitaxial growth process of the light emitting stack. Therefore, when compared with related semiconductor light emitting devices, the crystallinity of the light emitting stack may be improved, and the semiconductor light emitting device may also have improved light extraction efficiency.

[0141] As described above, embodiments are disclosed in the drawings and the specification. Although certain terms are used to describe the embodiments in this disclosure, this is only for the purpose of describing the technical concept of this disclosure, rather than for limiting the meaning or scope of this disclosure set forth in the claims. Therefore, those skilled in the art will understand that various modifications and other equivalent embodiments can be obtained therefrom. Therefore, the true technical protection scope of this disclosure should be determined by the technical concept of the appended claims.

[0142] Although the present disclosure has been specifically shown and described with reference to embodiments of the present disclosure, it will be understood that various changes in form and detail may be made herein without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor light emitting device, comprising: a substrate comprising a first material; a plurality of protrusions, each protrusion of the plurality of protrusions comprising: a lower pattern comprising the same material as the first material of the substrate; and a feature pattern disposed on the lower pattern and comprising a second material different from the first material of the substrate; a buffer layer on the substrate and the plurality of protrusions; an intermediate layer on the buffer layer; and A light-emitting stack, which is on the intermediate layer, Wherein, the intermediate layer comprises silicon nitride.

2. The semiconductor light emitting device according to claim 1, wherein: The intermediate layer is conformally disposed on the upper surface of the substrate and on the side surfaces and upper surfaces of the plurality of protrusions.

3. The semiconductor light emitting device according to claim 1, wherein: The intermediate layer has a thickness of 1 angstrom to 1 nanometer.

4. The semiconductor light emitting device according to claim 1, wherein: The buffer layer includes at least one of aluminum nitride, gallium nitride, indium nitride, indium gallium nitride, aluminum gallium nitride, indium aluminum gallium nitride, and aluminum indium nitride, and Wherein, the buffer layer has a thickness of 5 nanometers to 30 nanometers.

5. The semiconductor light emitting device according to claim 1, wherein: The second material of the feature pattern has a lower refractive index than the first material of the substrate.

6. The semiconductor light emitting device according to claim 1, wherein: The refractive index of the characteristic pattern is in the range of 1.0 to 1.

7.

7. The semiconductor light emitting device according to claim 1, wherein: The characteristic pattern includes at least one of silicon oxide, silicon oxynitride and magnesium fluoride.

8. The semiconductor light emitting device according to claim 1, wherein: The characteristic pattern has at least one of a hemispherical shape and a conical shape.

9. The semiconductor light emitting device according to claim 1, wherein: The first height of the lower pattern is less than or equal to the second height of the characteristic pattern.

10. The semiconductor light emitting device according to claim 9, wherein: The first height of the lower pattern is measured from the upper surface of the substrate at least partially surrounding each of the plurality of protrusions to the upper surface of the lower pattern, The second height of the characteristic pattern is measured from the upper surface of the lower pattern to the uppermost part of the characteristic pattern. wherein the first height of the lower pattern is in the range of 200 nanometers to 400 nanometers, and Wherein, the second height of the characteristic pattern is in the range of 200 nanometers to 2 micrometers.

11. The semiconductor light emitting device according to claim 10, wherein: A ratio of a second height of the feature pattern to a height of each of the plurality of protrusions is in a range of 0.5 to 0.

9.

12. The semiconductor light emitting device according to claim 1, wherein: The first material of the substrate includes at least one of sapphire, silicon carbide, silicon, magnesium aluminate, magnesium oxide, lithium aluminate, lithium gallium oxide, and gallium nitride.

13. The semiconductor light emitting device according to claim 1, wherein: The light emitting stack includes a first conductive type semiconductor layer, an active layer, and a second conductive type semiconductor layer sequentially disposed on the intermediate layer.

14. A semiconductor light emitting device, comprising: a substrate comprising a first material; a plurality of protrusions, each protrusion of the plurality of protrusions comprising: a lower pattern comprising the same material as the first material of the substrate; and a feature pattern disposed on the lower pattern and comprising a second material different from the first material of the substrate; a buffer layer on the substrate and the plurality of protrusions; an intermediate layer on the buffer layer; and a light emitting stack comprising a first conductive type semiconductor layer, an active layer and a second conductive type semiconductor layer sequentially disposed on the intermediate layer, Wherein, the intermediate layer comprises silicon nitride, and Wherein, the characteristic pattern includes at least one of silicon oxide, silicon oxynitride and magnesium fluoride.

15. The semiconductor light emitting device according to claim 14, wherein: The intermediate layer is conformally disposed on the upper surface of the substrate and on the side surfaces and upper surfaces of the plurality of protrusions.

16. The semiconductor light emitting device according to claim 14, wherein: The thickness of the intermediate layer is in the range of 1 angstrom to 1 nanometer, and Wherein, the thickness of the buffer layer is in the range of 5 nanometers to 30 nanometers.

17. The semiconductor light emitting device according to claim 14, wherein: The second material of the feature pattern has a refractive index lower than the refractive index of the first material of the substrate, and Wherein, the refractive index of the characteristic pattern is in the range of 1.0 to 1.

7.

18. The semiconductor light emitting device according to claim 14, wherein: The characteristic pattern has at least one of a hemispherical shape and a conical shape.

19. A semiconductor light emitting device, comprising: a substrate comprising a first material; a plurality of protrusions, each protrusion of the plurality of protrusions comprising: a lower pattern comprising the same material as the first material of the substrate; and a feature pattern on the lower pattern and comprising a second material different from the first material of the substrate; a buffer layer on the substrate and the plurality of protrusions; an intermediate layer on the buffer layer; and a light emitting stack comprising a first conductive type semiconductor layer, an active layer and a second conductive type semiconductor layer sequentially disposed on the intermediate layer, Wherein, the intermediate layer comprises silicon nitride, The buffer layer includes at least one of aluminum nitride, gallium nitride, indium nitride, indium gallium nitride, aluminum gallium nitride, indium aluminum gallium nitride and aluminum indium nitride. Wherein, the characteristic pattern comprises at least one of silicon oxide, silicon oxynitride and magnesium fluoride, and Wherein, the plurality of protrusions are arranged in a hexagonal shape.

20. The semiconductor light emitting device according to claim 19, wherein: The thickness of the intermediate layer is in the range of 1 angstrom to 1 nanometer, and Wherein, the thickness of the buffer layer is in the range of 5 nanometers to 30 nanometers.

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