Display method and display device

Abstract

The present disclosure provides a display method and a display device, and belongs to the technical field of display. The display method of the present disclosure, the physical resolution of the display panel is M1xN1; the display method comprises: a mainboard converts first original image data sent by a display card into first image data and sends the first image data to a timing controller; the resolution of the first image data is M2xN2; N2:N1=a:b<=1; the timing controller provides P clock signals to a gate drive circuit in the display panel and provides a data control signal to a source drive circuit; P=i*x*b; the gate drive circuit selects each row of sub-pixels of the display panel according to the P clock signals; the source drive circuit writes N2 rows of display data in the first image data into each row of sub-pixels in the scanning order according to the data control signal, except for the j*b row of sub-pixels; the display data of the j*b row of sub-pixels is written into the display data of the b*j-1 row and the b*j+1 row of sub-pixels; j is a positive integer greater than or equal to 1, and b*j+1<=N1.

Description

TECHNICAL FIELD

[0001] The present disclosure belongs to the technical field of display, and particularly relates to a display method and a display device. BACKGROUND

[0002] The performance improvement of current e-sports display is mainly the synchronous improvement of resolution and refresh rate, so as to achieve better user experience; however, it is inevitable that the synchronous improvement of resolution and refresh rate will cause the rapid shortening of pixel charging, although the process of the panel can be adjusted, the design material (A-SI to Oxide) can be replaced, and the IC with stronger driving capacity can be used; however, the problem of insufficient charging will still be faced; at the same time, in order to support such high display specifications, the graphics card and the scaler board also need to be improved synchronously to show excellent display performance, which will increase the user's consumption and affect the market sales in this case. SUMMARY

[0003] The present disclosure aims to at least solve one of the technical problems existing in the prior art, and provides a display method and a display device.

[0004] The display method provided by the present disclosure is applied to a display device, and the display device includes a graphics card, a mainboard, a timing controller and a display panel; the physical resolution of the display panel is M1xN1; the display method includes:

[0005] The mainboard converts the first original image data sent by the graphics card into first image data and sends the first image data to the timing controller; the resolution of the first image data is M2xN2; N2:N1=a:b<=1;

[0006] The timing controller provides P clock signals to the gate drive circuit in the display panel and provides data control signals to the source drive circuit; P=i x b; i is a positive integer greater than or equal to 1; the gate drive circuit selects each row of sub-pixels of the display panel according to the P clock signals, and the source drive circuit writes N2 rows of display data in the first image data into each row of sub-pixels in the scanning order except the j x b row of sub-pixels according to the data control signals; the display data of the j x b row of sub-pixels is written into the display data of the b x j-1 row and the b x j+1 row of sub-pixels; j is a positive integer greater than or equal to 1, and b x j+1<=N1.

[0007] Wherein, the starting time of the effective level of the k+1th clock signal is earlier than the ending time of the effective level of the kth clock signal; K is 1 to P-1;

[0008] The phase difference of the start time of the active level of the adjacent clock signals in the P clock signals except the b×jth clock signal is 1H1, the phase difference of the start time of the active level of the b×jth and b×j-1th clock signals is A, the phase difference of the start time of the active level of the b×j+1th and b×jth clock signals is B, A+B=H1, and the H1 is the phase difference of the start time of the two adjacent active levels of the data control signal.

[0009] The phase difference of the start time of the active level of the b×jth and b×j-1th clock signals is H1 / 2, and the phase difference of the start time of the active level of the b×j+1th and b×jth clock signals is H1 / 2.

[0010] The clock signal provided by the timing controller to the gate drive circuit and the data control signal provided by the timing controller to the source drive circuit satisfy:

[0011] The termination time of the data signal written by the source drive circuit to the sub-pixel except the j×bth row of sub-pixels is earlier than the termination time of the active level of the gate drive signal loaded by the sub-pixel.

[0012] The clock signal provided by the timing controller to the gate drive circuit and the data control signal provided by the timing controller to the source drive circuit satisfy:

[0013] The phase difference of the termination time of the data signal written by the source drive circuit to the sub-pixel and the termination time of the active level of the gate drive signal loaded by the sub-pixel except the j×bth row of sub-pixels is H1 / 2, and the H1 is the phase difference of the start time of the two adjacent active levels of the data control signal.

[0014] The clock signal provided by the timing controller to the gate drive circuit satisfies that the time during which the gate drive signals loaded by the sub-pixels of the adjacent rows are simultaneously in the active level is not less than 2H1, and the H1 is the phase difference of the start time of the two adjacent active levels of the data control signal.

[0015] When a:b=3:4 and P=4i, the phase difference of the start time of the active level of each clock signal except the 4e th clock signal is 1H1 in turn, e is a positive integer from 1 to i, H1 is the phase difference of the start time of the two adjacent active levels of the data control signal, and the phase difference of the start time of the active level of the 4e th and 4e-1th clock signals is H1 / 2.

[0016] When a:b=2:3 and P=3i, the phase difference between the starting time of the active level of each clock signal except the third e clock signal is 1H1 in turn, e is a positive integer from 1 to i, H1 is the phase difference between the starting time of two adjacent active levels of the data control signal, and the phase difference between the starting time of the active level of the third e and third e-1 clock signals is H1 / 2.

[0017] The duty cycle of the active level of the clock signal is 50%, and the length of the active level of the clock signal is 3H1; and H1 is the phase difference between the starting time of two adjacent active levels of the data control signal.

[0018] The M1 is equal to the M2.

[0019] The display method further comprises:

[0020] The display card sends the received first original image data to the mainboard when the display mode selection instruction is the first display mode; the resolution of the first original image data is M3×N3; M3

[0021] The mainboard converts the first original image data sent by the display card into first image data, comprising:

[0022] The mainboard performs horizontal interpolation processing on the first original image data to obtain first image data.

[0023] The display method further comprises: receiving a display mode selection instruction, and when the display mode selection instruction is the second display mode, the display card sends the received second original image data to the mainboard;

[0024] The mainboard converts the second original image data into second image data; the resolution of the second image data is M4×N4; N4:N1=1:2; and the refresh frequency of the second image data is greater than that of the first image data.

[0025] The timing controller provides a plurality of clock signals to the gate drive circuit in the display panel and provides a data control signal to the source drive circuit;

[0026] The gate drive circuit selects each row of sub-pixels of the display panel according to the plurality of clock signals, and the source drive circuit writes the second image data into the sub-pixels located in the even rows row by row according to the data control signal, and writes the display data of two sub-pixels located in the even rows adjacent to the sub-pixels located in the odd rows for the sub-pixels located in the odd rows; or

[0027] The gate drive circuit selects each row of sub-pixels of the display panel according to the plurality of clock signals, and the source drive circuit writes the second image data into the sub-pixels in odd rows row by row according to the data control signal, and writes the display data of two sub-pixels in odd rows adjacent to the sub-pixels in even rows.

[0028] In the second display mode, the start time of the active level of the plurality of clock signals is sequentially different by 1H2, and H2 is half of the phase difference between the start times of two adjacent active levels of the data control signal.

[0029] In the second display mode, the length of the active level of the clock signal is 4H2, and the duty cycle of the active level of the clock signal is 50%; the plurality of clock signals satisfy that the length of time during which adjacent row sub-pixels are simultaneously turned on is 3H2.

[0030] An example of the display device provided by the present disclosure includes a graphics card, a mainboard, a gate drive circuit, a source drive circuit, and a display panel; the physical resolution of the display panel is M1xN1;

[0031] The mainboard is configured to convert first original image data sent by the graphics card into first image data and send the first image data to a timing controller; the resolution of the first image data is M2xN2; N2:N1=a:b<1;

[0032] The timing controller is configured to provide P clock signals to the gate drive circuit in the display panel and provide a data control signal to the source drive circuit; P=i×b; i is a positive integer greater than or equal to 1; the gate drive circuit selects each row of sub-pixels of the display panel according to the P clock signals, and the source drive circuit writes N2 rows of display data in the first image data into each row of sub-pixels except the j×b row in the scanning order according to the data control signal; the j×b row of sub-pixels is written with the display data of the (b×j-1)th row and the (b×j+1)th row of sub-pixels; j is a positive integer greater than or equal to 1, and b×j+1≤N1. BRIEF DESCRIPTION OF DRAWINGS

[0033] Figure 1 A schematic diagram of the display device provided by the present disclosure.

[0034] Figure 2A And Figure 2B An example structure diagram of the gate drive circuit provided by the present disclosure.

[0035] Figure 3 A signal timing diagram of a display method provided by the present disclosure.

[0036] Figure 4A flowchart of a display method of an embodiment of the present disclosure.

[0037] Figure 5 A timing diagram of a display method of an embodiment of the present disclosure.

[0038] Figure 6 A flowchart of a display method of an embodiment of the present disclosure.

[0039] Figure 7 A timing diagram of a display method of an embodiment of the present disclosure in a second display mode.

[0040] Figure 8 Another timing diagram of a display method of an embodiment of the present disclosure in a second display mode. DETAILED DESCRIPTION

[0041] In order for those skilled in the art to better understand the technical solutions of the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0042] Unless otherwise defined, technical terms or scientific terms used in the present disclosure shall have the ordinary meaning understood by a person skilled in the art to which the present disclosure pertains. The terms "first", "second", and similar terms used in the present disclosure do not denote any order, quantity, or importance, but are used to distinguish different components. Similarly, the terms "one", "a", or "the" and similar terms do not denote a quantity restriction, but mean that there is at least one. The terms "include", "comprise", and similar terms mean that the elements or objects before the terms encompass the elements or objects listed after the terms and their equivalents, and do not exclude other elements or objects. The terms "connect" or "connected" and similar terms do not mean a physical or mechanical connection, but can include an electrical connection, whether direct or indirect. The terms "upper", "lower", "left", "right", and the like are used only to represent relative positional relationships, and when the absolute positions of the described objects are changed, the relative positional relationships can also be changed accordingly.

[0043] Figure 1 A schematic diagram of a display device provided by an embodiment of the present disclosure; as shown in Figure 1 The display device 100 includes a display panel, which includes a plurality of sub-pixels arranged in an M1xN1 array, where N1 and M1 are both integers greater than 1.

[0044] The display device 100 can further include a gate drive circuit 10 connected to the plurality of sub-pixels. The gate drive circuit 10 can be configured to sequentially apply a gate signal to the plurality of sub-pixels along a first direction (e.g., a row direction) of the display panel. Figure 1The plurality of gate signal lines extending along the first direction (x direction) are respectively connected with the N1 rows of sub-pixels, for example, a first row of sub-pixels is connected with a first gate signal line to provide a first gate driving signal G1 to the first row of sub-pixels, a second row of sub-pixels is connected with a second gate signal line to provide a second gate driving signal G2 to the second row of sub-pixels, and so on. The first row of sub-pixels is turned on in response to receiving the first gate driving signal G1, the second row of sub-pixels is turned on in response to receiving the second gate driving signal G2, and so on.

[0045] In some embodiments, the gate driving circuit 10 can scan the N1 rows of sub-pixels one or more rows at a time. For example, the gate driving circuit 10 can scan one row of sub-pixels at a time, for example, sequentially generating N1 gate driving signals G1, G2, … GN to sequentially turn on the first row of sub-pixels, the second row of sub-pixels P, … the N1th row of sub-pixels P. The gate driving circuit 10 can also scan two or more rows of sub-pixels P at a time. For example, the gate driving circuit 10 can simultaneously generate a first gate driving signal G1 and a second gate driving signal G2 to simultaneously turn on the first row of sub-pixels and the second row of sub-pixels, and then the gate driving circuit 10 can simultaneously generate a third gate driving signal G3 and a fourth gate driving signal G4 to simultaneously turn on the third row of sub-pixels and the fourth row of sub-pixels, and so on. In some embodiments, the gate driving circuit 10 can scan the N1 rows of sub-pixels at least one row at a time to sequentially turn on sub-pixels of partial rows. For example, the gate driving circuit 10 can sequentially turn on odd rows of sub-pixels (for example, sequentially turn on the first row of sub-pixels, the third row of sub-pixels, the fifth row of sub-pixels, and so on), or sequentially turn on even rows of sub-pixels (for example, sequentially turn on the second row of sub-pixels, the fourth row of sub-pixels, the sixth row of sub-pixels, and so on).

[0046] The display device 100 can further include a source driving circuit 20 connected with the plurality of sub-pixels. For example, the source driving circuit 20 can be connected with the M1 columns of sub-pixels P through a plurality of data lines extending along the second direction (y direction). Figure 1 For example, the source driving circuit 20 can be connected with a first column of sub-pixels through a first data line to provide a first data signal D1 to the first column of sub-pixels, connected with a second column of sub-pixels through a second data line to provide a second data signal D2 to the second column of sub-pixels, and so on.

[0047] For example, when the first row of sub-pixels is turned on, the source driving circuit 20 can provide M1 data signals D11, D12, …, D1M for the first row of sub-pixels to the M1 sub-pixels of the first row through M1 data lines respectively; when the second row of sub-pixels is turned on, the source driving circuit 20 can provide M1 data signals D21, D22, …, D2M1 for the second row of sub-pixels to the M1 sub-pixels of the second row through multiple data lines respectively, and so on. Of course, embodiments of the present disclosure are not limited thereto, and will be described in further detail below.

[0048] In some embodiments, the display device 100 can further include a graphics card 50, a mainboard 40, and a timing controller 30, where the mainboard 40 can be a Scalar mainboard 40, the graphics card 50 is used for image formation, and the mainboard 40 is used for data transmission, for example, the graphics card 50 transmits image data to the mainboard 40, and the mainboard 40 sends the image data to the timing controller 30.

[0049] The timing controller 30 is connected with the gate driving circuit 10 and the source driving circuit 20, and can provide relevant control signals to the gate driving circuit 10 and the source driving circuit 20. For example, the timing controller 30 can provide a data control signal TP to the source driving circuit 20, and the source driving circuit 20 can output data signals for each row under the control of the data control signal TP. The timing controller 30 can also provide other control signals to the source driving circuit 20, including but not limited to a row data start signal, a data synchronization signal, a data inversion signal, and the like. The timing controller 30 can also provide various control signals to the gate driving circuit 10, including but not limited to a frame start signal and a clock signal required by the gate driving circuit 10. In the present disclosure, the effective level of each signal is taken as a high level, and the corresponding invalid level is taken as a low level.

[0050] Figure 2A and Figure 2B An example structure diagram of the gate driving circuit of an embodiment of the present disclosure is shown. As shown in Figure 2A and Figure 2B The gate driving circuit includes multiple cascaded shift registers GOA1, GOA2, …, GOAN. For example, for a super high definition (QHD: resolution 2560x1440) display panel, the number of horizontal pixels is 2560, and the number of vertical pixels is 1440. If multiple sub-pixels contained in each pixel are arranged horizontally, the display panel includes 1440 rows of sub-pixels. In the case that the display panel includes 1440 rows of sub-pixels and each shift register corresponds to a row of sub-pixels, the number of shift registers included in the gate driving circuit can be 1440.

[0051] Figure 2A First to ninth level shift register units GOA1 to GOA9 are shown. As shown inFigure 2A As shown, STV1 is a frame start signal, when the gate driving circuit connects 8 CLK, the input end Input of the first to fourth stage shift register units GOA1 to GOA4 can be connected with the frame start signal end STV1. After the fourth stage shift register unit GOA4, the input end Input of the nth stage shift register unit GOAn is connected with the output end of the n-4 stage shift register unit GOA(n-4), wherein 5≤n≤N. For example, the output of GOA1 is connected with the input of GOA5, the output of GOA2 is connected with the input of GOA6, the output of GOA3 is connected with the input of GOA7, the output of G4 is connected with the input of GOA8, the output of G5 is connected with the input of GOA9, and so on. The reset end RST of the nth stage shift register unit GOAn is connected with the output end OUT of the n+4 stage shift register unit GOA(n+4), wherein 1≤n≤N-4. Figure 2B The last stage shift register unit GOA1440 and the dummy shift register unit (Dummy GOA) are shown in FIG. 14B. As shown, the last 4 rows of GOA can be reset by 4 rows of Dummy GOA, for example, Dummy GOA1 (Dum1) resets GOA1437, Dummy GOA2 (Dum2) resets GOA1438, and so on, sequentially reset, and each Dummy GOA can be reset by STV1. Figure 2B As shown, the last 4 rows of GOA can be reset by 4 rows of Dummy GOA, for example, Dummy GOA1 (Dum1) resets GOA1437, Dummy GOA2 (Dum2) resets GOA1438, and so on, sequentially reset, and each Dummy GOA can be reset by STV1.

[0052] It should be noted that in the above example, only the reset end RST of the nth stage shift register unit GOAn is connected with the output end OUT of the n+4 stage shift register unit GOA(n+4) is taken as an example, in some examples, the reset end RST of the nth stage shift register unit GOAn can also be connected with the output end OUT of the n+4 stage shift register unit GOA(n+5), wherein 1≤n≤N-5. Correspondingly, the gate driving circuit includes 5 Dummy GOA, and the last 5 rows of GOA can be reset by 5 rows of Dummy GOA, for example, Dummy GOA1 (Dum1) resets GOA1436, Dummy GOA2 (Dum2) resets GOA1437, and so on, sequentially reset. That is, for the setting of Dummy GOA, the reset relationship between GOA can be flexibly set. Figure 2A and 2BThe shown gate driving circuit adopts 8 clock signals CLK1 to CLK8, wherein the clock signal end CLK of the first stage shift register unit GOA1 is connected to receive the first clock signal CLK1, the clock signal end CLK of the second stage shift register unit GOA2 is connected to receive the second clock signal CLK2, and so on, and the clock signal end CLK of the eighth stage shift register unit GOA8 is connected to receive the eighth clock signal CLK8. In a similar way, the ninth stage to the sixteenth stage shift register units GOA9 to GOA16 are respectively connected to receive the first to the eighth clock signals CLK1 to CLK8.

[0053] Each stage shift register unit GOA1, GOA2, …, GOAN can generate an output signal as a gate driving signal (or a gate scanning signal) at its output end OUT under the control of the signals at its clock signal end CLK and input end. For example, the first stage shift register unit GOA1 generates a first gate driving signal G1, the second stage shift register unit GOA2 generates a second gate driving signal G2, and so on. In a cascaded way, the gate driving signal generated by a stage shift register unit can be shifted relative to the gate driving signal generated by another stage shift register unit.

[0054] The above is only an example of the display device of the embodiments of the present disclosure, and the structure of the display device of the embodiments of the present disclosure is not limited thereto, and can have other structures as needed. For example, the display device can be a display device based on liquid crystal display (LCD) technology, or a display device based on organic light emitting diode (OLED) display technology. The gate driving circuit of the display device can adopt a different structure from that shown in the embodiments of the present disclosure. Figure 2A and 2B The shown cascaded way can be cascaded in a different way, for example, 10 or 12 clock signals can be used.

[0055] Figure 3 The signal timing diagram of a display method of the embodiments of the present disclosure; the following will be described by taking the display device of Figure 1 、 Figure 2A and Figure 2B as an example to illustrate the signal timing of Figure 3 . As shown in Figure 3 , during the display of each frame of image, under the control of the clock signals CLK1 to CLK8, the gate driving circuit 10 generates the first gate driving signal G1, the second gate driving signal G2, the third gate driving signal G3, the fourth gate driving signal G4, and so on in a preset time interval. The phase difference of the start time of the data signal written into two adjacent row sub-pixels is H. In Figure 3 , the effective level duration of each gate driving signal is, for example, 4H.

[0056] For the first row of sub-pixels, during time periods T1 to T4, the first gate driving signal G1 is high, so that the first row of sub-pixels is in an open state, wherein the time periods T1 to T4 are each H in length, that is, the first row of sub-pixels is open for 4H. At time period T4, a first high-level pulse of the data control signal TP arrives, thereby controlling the source driving circuit 20 to apply a data signal (also referred to as a first row data signal) DATA1 for the first row of sub-pixels to the first row of sub-pixels in the open state. The first row data signal DATA1 can include M1 data signals D11, D12, …, D1M for the first row of M1 sub-pixels, respectively, wherein the data signal D11 is provided to the first column of sub-pixels in the first row, the data signal D12 is provided to the second column of sub-pixels in the first row, and so on, and the data signal D1M is provided to the M1th column of sub-pixels in the first row.

[0057] Similarly, for the second row of sub-pixels, during time periods T2 to T5, the second gate driving signal G2 is high, so that the second row of sub-pixels is in an open state, wherein at time period T5, a second high-level pulse of the data control signal TP arrives, thereby controlling the source driving circuit 20 to apply a data signal (also referred to as a second row data signal) DATA2 for the second row of sub-pixels to the second row of sub-pixels in the open state. The second row data signal DATA2 can include M1 data signals D21, D22, …, D2M for the second row of M1 sub-pixels, respectively, wherein the data signal D21 is provided to the first column of sub-pixels in the second row, the data signal D22 is provided to the second column of sub-pixels in the second row, and so on, and the data signal D2M1 is provided to the M1th column of sub-pixels in the second row. This can be similarly applied to other rows of sub-pixels.

[0058] According to the above-described display of one frame of image, the refresh frequency of the QHD display panel is 180 Hz. If the refresh frequency of the QHD display panel is increased from 180 Hz to 240 Hz, that is, a 4 / 3-fold increase in refresh frequency is achieved. Specifically, when the graphics card 50 receives the original image data 2560*1440*180 Hz adjusted to 1920*1080*240 Hz, and outputs 2560*1080*240 Hz after Scalar processing by the mainboard 40, the image data received by the timing controller 30 appears to be 2560*1080*240, so the received bandwidth remains unchanged. In this way, the refresh frequency is increased from 180 Hz to 240 Hz; however, since the timing controller 30 actually receives display data for 1080 rows, while the physical number of rows of sub-pixels of the display panel is 1440, display data is missing on the display panel. To solve this problem, the present disclosure provides the following technical solutions.

[0059] The display method can also be applied to Figure 1 The display device has a physical resolution of M1xN1, as shown in the figure, and the display method comprises the following steps. Figure 4

[0060] S10, the mainboard 40 converts the first original image data sent by the graphics card 50 into first image data and sends it to the timing controller 30; the resolution of the first image data is M2xN2; N2:N1=a:b≤1.

[0061] Specifically, in the display method of the present embodiment, the refresh frequency of the first image data is higher than the normal refresh frequency of the display device, for example, the normal refresh frequency of the display panel is 180Hz, the refresh frequency of the first image data is 240Hz, the physical resolution of the display panel is M1xN1=2560x1440, and the resolution of the first image data is M2xN2=2560x1080. Correspondingly, N2:N1=3:4, i.e. a=3 and b=4.

[0062] S20, the timing controller 30 provides P clock signals to the gate drive circuit 10 in the display panel and provides data control signals to the source drive circuit 20; P=i×b; i is a positive integer greater than or equal to 1. The gate drive circuit 10 selects each row of sub-pixels of the display panel according to the P clock signals, and the source drive circuit 20 writes N2 rows of display data in the first image data into each row of sub-pixels according to the scanning order except for the j×b row of sub-pixels according to the data control signals; the j×b row of sub-pixels is written into the display data of the b×j-1 row and the b×j+1 row of sub-pixels; j is a positive integer greater than or equal to 1, and j×b+1≤N1.

[0063] That is, the data written into each row of sub-pixels in the display panel except for the j×b row is the real display data in the first image data, and the display data written into the j×b row of sub-pixels is the interpolation of the display data of the two rows of sub-pixels arranged adjacent to it, so that each sub-pixel on the display panel has display data written into it, and the j×b row of sub-pixels has the interpolation of the display data of the two rows of sub-pixels arranged adjacent to it, avoiding the problem that the display of the interpolation row of sub-pixels is too different from the display of the adjacent row of sub-pixels, causing display abnormalities.

[0064] ​Specifically, taking a=3, b=4 in step S10 as an example, if i takes 2, then P=8, that is, the timing controller 30 generates 8 clock signals, which are CLK1-CLK8. At this time, the 8 clock signals generated by the timing controller 30 and the data control signal can control each row of sub-pixels except the 3j+1th row of sub-pixels (for example, the 4th, 8th, 12th, and so on) to be written with real display data, and the 3j+1th row of sub-pixels is displayed by using the interpolation of the display data of the two rows of sub-pixels arranged above and below it, for example, the 4th row of sub-pixels is mixed charged by using the display data written in the 3rd row of sub-pixels and the 5th row of sub-pixels.

[0065] It should be noted that in the above example, the number of clock signals is not limited to 8, and can be an integer multiple of 4, for example, the number of clock signals can be 4, 8, 12, and so on. In addition, in the above example, only the resolution M2xN2=2560x1080 of the first image data is taken as an example, and 2560x1080 data is filled into a display panel with a physical resolution of M1xN1=2560x1440. If the resolution M2xN2=2560x1440 of the first image data is taken as an example, and 2560x1440 data is filled into a display panel with a physical resolution of M1xN1=3840x2160, at this time, N2:N1=2:3, that is, a=2, b=3, and the display data of the display panel needs to be filled every two rows, that is, the 3rd, 6th, 9th, and so on. row of sub-pixels needs to be mixed charged by using the display data of the sub-pixels arranged above and below it. Therefore, the number of clock signals generated by the timing controller 30 at this time needs to be a multiple of 3, such as 6, 9, 12 clock signals, and so on. Here, it is not necessary to enumerate one by one.

[0066] In some examples, the starting time of the high level of the k+1th clock signal is earlier than the ending time of the high level of the kth clock signal; K takes 1~P-1; the phase difference of the starting time of the effective level of the adjacent clock signals among the P clock signals except the b×jth clock signal is H1, the phase difference of the starting time of the effective level of the b×jth and b×j-1th clock signals is A, the phase difference of the starting time of the effective level of the b×j+1th and b×jth clock signals is B; A+B=H1; H1 is the phase difference of the starting time of the two adjacent effective levels of the data control signal. For example: the phase difference of the starting time of the high level of the b×jth and b×j-1th clock signals is H1 / 2, the phase difference of the starting time of the high level of the b×j+1th and b×jth clock signals is H1 / 2. Specifically, still taking a=3, b=4, i taking 2, P=8 as an example; the phase difference of the starting time of the effective level of the clock signals except the 4e clock signal is H1 in turn; e takes positive integer 1 and 2; H1 is the phase difference of the starting time of the two adjacent effective levels of the data control signal; the phase difference of the starting time of the effective level of the 4e and 4e-1 clock signals is H1 / 2. Of course, in the embodiment of the disclosure, the phase difference of the starting time of the high level of the b×jth and b×j-1th clock signals can also be H1 / 3, the phase difference of the starting time of the high level of the b×j+1th and b×jth clock signals is 2H1 / 3 and so on, which will not be enumerated one by one here.

[0067] Due to the clock signal determines the output of the gate drive circuit 10, in the output stage of the gate drive circuit 10, the clock signal is high, at this time the gate drive signal output by the gate drive circuit 10 is high, therefore, the starting time of the high level of the k+1th clock signal is earlier than the ending time of the high level of the kth clock signal, that is to say, the two rows of sub-pixels arranged adjacently have a period of time of being opened at the same time, and the pre-charging can be performed before the sub-pixel data is written, so that the charging efficiency of the sub-pixel is improved. In the embodiment of the present disclosure, except for the 4th and 8th clock signals, the phase difference between the starting time of the high level of the adjacent clock signals is H1 / 1, the phase difference between the starting time of the high level of the 4th and 3rd clock signals is H1 / 2, and the phase difference between the starting time of the high level of the 4th and 5th clock signals is H1 / 2; that is to say, the starting time of the high level signals of the first clock signal CLK1, the second clock signal CLK2, the third clock signal CLK3, the fifth clock signal CLK5, the sixth clock signal CLK6 and the seventh clock signal CLK7 is sequentially different by H1 / 1, the phase difference between the starting time of the high level of the fourth clock signal CLK4 and the third clock signal CLK3 is H1 / 2, and the phase difference between the starting time of the high level of the fifth clock signal CLK5 and the fourth clock signal CLK4 is H1 / 2, in this way, it is ensured that the 3j+1th row of sub-pixels is mixedly charged with the display data of the upper and lower rows of sub-pixels arranged adjacently.

[0068] In some examples, the clock signals provided by the timing controller 30 to the gate drive circuit 10 and the data control signals provided by the timing controller 30 to the source drive circuit 20 satisfy that, except for the j×bth row of sub-pixels, the ending time of the data signal written by the source drive circuit 20 to the sub-pixels is earlier than the ending time of the high level of the gate drive signal loaded by the sub-pixels. In this way, it is ensured that the j×bth row of sub-pixels is charged with the display data of the sub-pixels arranged adjacently.

[0069] In one example, the clock signals provided by the timing controller 30 to the gate drive circuit 10 and the data control signals provided by the timing controller 30 to the source drive circuit 20 satisfy that, except for the j×bth row of sub-pixels, the phase difference between the ending time of the data signal written by the source drive circuit 20 to the sub-pixels and the ending time of the high level of the gate drive signal loaded by the sub-pixels is H1 / 2, and H1 is the phase difference between the starting time of two adjacent high levels of the data control signal.

[0070] In some examples, the clock signals provided by the timing controller 30 to the gate driving circuit 10 satisfy: the time during which the gate driving signals loaded by the sub-pixels of adjacent rows are simultaneously at high level is not less than 2H1, H1 being the phase difference between the start times of two adjacent high levels of the data control signals. For example, the duty ratio of the high level signal of each clock signal is 50%, and the high level clock can be 3H1, and the corresponding low level time is also 3H1. At this time, the time during which the gate driving signals loaded by the sub-pixels of adjacent rows are simultaneously at high level is not less than 2H1.

[0071] In order to more clearly describe the display of the display panel on the received first image data in the embodiments of the present disclosure, it is assumed that the gate driving circuit 10 of the display panel is controlled by 8 clock signals. The display method of the embodiments of the present disclosure is described.

[0072] Referring to Figure 5 , the 8 clock signals CLK1-CLK8 provided by the timing controller 30 to the gate driving circuit 10, the duty ratio of the high level signal of each clock signal is 50%, and the high level clock can be 3H1, and the corresponding low level time is also 3H1. The start times of the high level signals of the first clock signal CLK1, the second clock signal CLK2, the third clock signal CLK3, the fifth clock signal CLK5, the sixth clock signal CLK6 and the seventh clock signal CLK7 are sequentially different by 1H1. The phase difference between the start times of the high levels of the fourth clock signal CLK4 and the third clock signal CLK3 is H1 / 2, and the phase difference between the start times of the high levels of the fifth clock signal CLK5 and the fourth clock signal CLK4 is H1 / 2. The phase difference between the start time of each data row of the data control signal written by the timing controller 30 to the source driving circuit 20 and the end time of the high level of the gate driving signal of the corresponding sub-pixel row is 3H1 / 4, and the phase difference between the end time of each data row of the data control signal written by the timing controller 30 to the source driving circuit 20 and the end time of the high level of the gate driving signal of the corresponding sub-pixel row is H1 / 2. In this case, the sub-pixel row 1 is charged by the data row 1, the sub-pixel row 2 is charged by the data row 2, the sub-pixel row 3 is charged by the data row 3, the sub-pixel 4 is charged by the data row 3 and 4, the sub-pixel row 5 is charged by the data row 4, the sub-pixel row 6 is charged by the data row 5, the sub-pixel row 7 is charged by the data row 6, the sub-pixel row 8 is charged by the data row 6 and 7, and so on.

[0073] In some examples, referring to Figure 6The display method in the embodiment of the present disclosure further includes receiving a display mode selection instruction before the above steps are executed, and when the display mode selection instruction is a first display mode, the graphics card 50 sends the received first original image data to the mainboard 40; the resolution of the first original image data is M3xN3; M3

[0074] It should be noted that the display device in the embodiment of the present disclosure supports multiple modes of display, for example: the display device includes a normal display mode, that is, the resolution of the image data is the same as the resolution of the display panel, at this time, each sub-pixel row and data row are one-to-one corresponding, and the display data written to each sub-pixel is real data. The display device includes a first display mode, when the display mode selection instruction of the user selecting the first display mode is received, the graphics card 50 sends the received first original image data to the mainboard 40; the resolution of the first original image data is M3xN3; M3

[0075] In some examples, with reference to Figure 6 The display method in the embodiment of the present disclosure not only includes the above steps, but also can include: receiving a display mode selection instruction, and when the display mode selection instruction is a second display mode, the graphics card 50 sends the received second original image data to the mainboard 40.

[0076] The mainboard 40 converts the second original image data into second image data; the resolution of the second image data is M4xN4; N4:N1=1:2; the refresh frequency of the second image data is greater than that of the first image data. For example, the resolution of the second image data is M4xN4=2560x720, and the refresh frequency is 360Hz.

[0077] The step of converting the second raw image data into the second image data by the mainboard 40 specifically includes that the mainboard 40 performs horizontal interpolation processing on the second raw image data to obtain the second image data. For example, the resolution of the second raw image data is 1280*720, and the refresh frequency is 360Hz. The mainboard 40 performs horizontal interpolation processing on the second raw image data to obtain the second image data, and the resolution of the second image data is 2560*720, and the refresh frequency is 360Hz.

[0078] The timing controller 30 provides a plurality of clock signals to the gate driving circuit 10 in the display panel, and provides a data control signal to the source driving circuit 20.

[0079] The gate driving circuit 10 selects each row of sub-pixels of the display panel according to the plurality of clock signals, and the source driving circuit 20 writes the second image data into the sub-pixels in the even rows line by line according to the data control signal, and writes the display data of two sub-pixels in the even rows adjacent to the sub-pixels in the odd rows for the sub-pixels in the odd rows; or the gate driving circuit 10 selects each row of sub-pixels of the display panel according to the plurality of clock signals, and the source driving circuit 20 writes the second image data into the sub-pixels in the odd rows line by line according to the data control signal, and writes the display data of two sub-pixels in the odd rows adjacent to the sub-pixels in the even rows for the sub-pixels in the even rows.

[0080] In the second display mode, the refresh frequency is higher than that of the first display mode, and is twice the refresh frequency in the normal display mode, and the data of the second image data in the second display mode is displayed on half of the rows of sub-pixels of the display panel. At this time, the data control signal generated by the timing controller 30 is controlled to make the source driving circuit 20 write the real data into the sub-pixels in the odd rows, and the sub-pixels in the even rows are mixedly charged by the upper and lower rows of sub-pixels, or the source driving circuit 20 writes the real data into the sub-pixels in the even rows, and the sub-pixels in the odd rows are mixedly charged by the upper and lower rows of sub-pixels. In this way, the loss of image quality can be reduced.

[0081] In some examples, in the second display mode, the starting time of the effective level of the plurality of clock signals is sequentially different by 1H2, H2 is half of the phase difference between the starting times of two adjacent effective levels of the data control signal. The length of the effective level of the clock signal is 4H2, and the duty cycle of the effective level of the clock signal is 50%; the plurality of clock signals satisfy that the adjacent rows of sub-pixels are simultaneously in the opening state for a length of 3H2.

[0082] In order to more clearly describe the display method in the second display mode of the present disclosure, the timing diagram shown in the following is specifically described. Figure 7

[0083] ​The timing controller 30 provides eight clock signals, CLK1-CLK8, to the gate drive circuit 10. Each of the clock signals has a duty cycle of 50%, and the high level clock signal has a duration of 4H2, and the corresponding low level clock signal also has a duration of 4H2. The first clock signal CLK1, the second clock signal CLK2, the third clock signal CLK3, the fourth clock signal CLK4, the fifth clock signal CLK5, the sixth clock signal CLK6, the seventh clock signal CLK7, and the eighth clock signal CLK8 have a phase difference of 1H2 between the start time of the high level signal. The phase difference between the start time of each data line of the data control signal written by the timing controller 30 to the source drive circuit 20 and the end time of the high level of the gate drive signal of the corresponding sub-pixel row (odd row) is 5H2 / 3, and the phase difference between the end time of each data line of the data control signal written by the timing controller 30 to the source drive circuit 20 and the end time of the high level of the gate drive signal of the corresponding sub-pixel row is 4H2 / 3. In this case, the sub-pixel row 1 is charged by the data line 1, the sub-pixel row 2 is charged by the data line 1 and the data line 2, the sub-pixel row 3 is charged by the data line 2, the sub-pixel row 4 is charged by the data line 2 and the data line 3, the sub-pixel row 5 is charged by the data line 3, the sub-pixel row 6 is charged by the data line 3 and the data line 4, the sub-pixel row 7 is charged by the data line 4, the sub-pixel row 8 is charged by the data line 4 and the data line 5, and so on. That is, the odd row sub-pixel is written with the real display data, and the even row sub-pixel is mixed with the display data of the adjacent upper and lower two rows of sub-pixels. Similarly, referring to Figure 8

[0084] Continuing to refer to Figure 1 ​The display card 50, the mainboard 40, the gate drive circuit 10, the source drive circuit 20 and the display panel are also provided in the embodiments of the present disclosure. The physical resolution of the display panel is M1xN1. The mainboard 40 is configured to convert the first original image data sent by the display card 50 into first image data and send the first image data to the timing controller 30. The resolution of the first image data is M2xN2. N2:N1=a:b<1. The timing controller 30 is configured to provide P clock signals to the gate drive circuit 10 in the display panel and provide a data control signal to the source drive circuit 20. P=i x b. i is a positive integer greater than or equal to 1. The gate drive circuit 10 selects each row of sub-pixels of the display panel according to the P clock signals. The source drive circuit 20 writes N2 rows of display data in the first image data into each row of sub-pixels according to the scanning order except for the j x b row of sub-pixels according to the data control signal. The display data of the j x b row of sub-pixels is written into the (b x j-1)th row and the (b x j+1)th row of sub-pixels. j is a positive integer greater than or equal to 1, and b x j+1≤N1.

[0085] The display device of the embodiments of the present disclosure can be any device such as a mobile phone, a tablet computer, a notebook computer, an e-book, a game console, a television, a digital photo frame, a navigator, etc. The display device of the embodiments of the present disclosure can also be any combination of display devices and hardware, and the embodiments of the present disclosure do not limit the display device.

[0086] It should be noted that, for the sake of clarity and simplicity, the embodiments of the present disclosure do not show all the constituent units of the electronic device 1. To achieve the necessary functions of the electronic device, those skilled in the art can provide and set other constituent units not shown according to specific needs, and the embodiments of the present disclosure do not limit this.

[0087] The related description and technical effects of the electronic device 1 can refer to the related description and technical effects of the frequency divider provided in the embodiments of the present disclosure, which will not be repeated here.

[0088] It can be understood that the above embodiments are only exemplary embodiments for illustrating the principles of the present application, and the present application is not limited thereto. Those skilled in the art can make various modifications and improvements without departing from the spirit and essence of the present application, and these modifications and improvements are also considered as the protection scope of the present application.

Claims

1. A display method applied to a display device, the display device comprising a graphics card, a motherboard, a timing controller, and a display panel; The physical resolution of the display panel is M1×N1; the display method includes: The motherboard converts the first raw image data sent by the graphics card into first image data and sends it to the timing controller; the resolution of the first image data is M2×N2; N2:N1=a:b<1; The timing controller provides P clock signals to the gate driving circuit in the display panel and data control signals to the source driving circuit; P = i × b; i is a positive integer greater than or equal to 1; the gate driving circuit selects each row of sub-pixels of the display panel according to the P clock signals, and the source driving circuit, according to the data control signals, writes the N2 row of display data in the first image data line by line according to the scanning order for each row of sub-pixels except for the j × b row; and writes the display data of the b × j-1 and b × j+1 row sub-pixels of the j × b row sub-pixels; j is a positive integer greater than or equal to 1, and b × j+1 ≤ N1; the refresh rate of the display device for the first image data is higher than the refresh rate when the display device displays image data with a resolution of M1 × N1; The display method further includes: The graphics card receives a display mode selection instruction, and when the display mode selection instruction is a first display mode, the graphics card sends the received first raw image data to the motherboard; the resolution of the first raw image data is M3×N3; M3 < M2; The motherboard converts the first raw image data sent by the graphics card into first image data, including: The motherboard performs horizontal interpolation on the first original image data to obtain the first image data.

2. The display method according to claim 1, wherein, The start time of the effective level of the (k+1)th clock signal is earlier than the end time of the effective level of the kth clock signal; K ranges from 1 to P-1. Of the P clock signals, except for the b×j-th clock signal, the phase difference between the start times of the effective levels of adjacent clock signals is 1H1, the phase difference between the start times of the effective levels of the b×j-th and b×j-1-th clock signals is A, and the phase difference between the start times of the effective levels of the b×j+1-th and b×j-th clock signals is B; A+B=H1; H1 is the phase difference between the start times of two adjacent effective levels of the data control signal.

3. The display method according to claim 1, wherein, The phase difference between the start times of the effective levels of the b×j-th and b×j-1-th clock signals is H1 / 2, and the phase difference between the start times of the effective levels of the b×j+1-th and b×j-th clock signals is H1 / 2.

4. The display method according to claim 1, wherein, The clock signal provided by the timing controller to the gate drive circuit and the data control signal provided to the source drive circuit satisfy the following: Except for the sub-pixels in the j×b row, the termination time of the data writing signal from the source driving circuit to the sub-pixel is earlier than the termination time of the effective level of the gate driving signal loaded on the sub-pixel.

5. The display method according to claim 4, wherein, The clock signal provided by the timing controller to the gate drive circuit and the data control signal provided to the source drive circuit satisfy the following: For sub-pixels except those in the j×b row, the phase difference between the termination time of the data signal written to the sub-pixel by the source driving circuit and the termination time of the effective level of the gate driving signal loaded on the sub-pixel is H1 / 2, where H1 is the phase difference between the start times of two adjacent effective levels of the data control signal.

6. The display method according to claim 1, wherein, The clock signal provided by the timing controller to the gate driving circuit satisfies the following condition: the time during which the gate driving signals loaded on the sub-pixels of adjacent rows are simultaneously at an effective level is not less than 2H1, where H1 is the phase difference between the start times of two adjacent effective levels of the data control signal.

7. The display method according to claim 1, wherein, When a:b = 3:4 and P = 4i; except for the 4e-th clock signal, the phase difference of the start time of the effective level of each of the other clock signals is 1H1; e is a positive integer from 1 to i; H1 is the phase difference of the start time of two adjacent effective levels of the data control signal; the phase difference of the start time of the effective level of the 4e-th and 4e-1-th clock signals is H1 / 2.

8. The display method according to claim 1, wherein, When a:b = 2:3 and P = 3i; except for the 3e-th clock signal, the phase difference of the start time of the effective level of each of the other clock signals is 1H1; e is a positive integer from 1 to i; H1 is the phase difference of the start time of two adjacent effective levels of the data control signal; the phase difference of the start time of the effective level of the 3e-th and 3e-1-th clock signals is H1 / 2.

9. The display method according to claim 1, wherein, The duty cycle of the effective level of the clock signal is 50%, and the duration of the effective level of the clock signal is 3H1; where H1 is the phase difference between the start times of two adjacent effective levels of the data control signal.

10. The display method according to any one of claims 1-9, wherein, M1 is equal to M2.

11. The display method according to claim 1, wherein, Also includes: The graphics card receives a display mode selection instruction, and when the display mode selection instruction is the second display mode, the graphics card sends the received second raw image data to the motherboard; The motherboard converts the second original image data into second image data; the resolution of the second image data is M4×N4; N4:N1=1:2; the refresh rate of the second image data is greater than the refresh rate of the first image data; The timing controller provides multiple clock signals to the gate driving circuit in the display panel and data control signals to the source driving circuit; The gate driving circuit selects each row of sub-pixels of the display panel according to the plurality of clock signals, and the source driving circuit writes the second image data line by line to the sub-pixels located in even-numbered rows according to the data control signal, and writes the display data of the two adjacent sub-pixels located in even-numbered rows to the sub-pixels in odd-numbered rows. or, The gate driving circuit selects each row of sub-pixels of the display panel according to the plurality of clock signals, and the source driving circuit writes the second image data line by line to the sub-pixels located in odd-numbered rows according to the data control signal, and writes the display data of the two adjacent sub-pixels located in odd-numbered rows to the sub-pixels in even-numbered rows.

12. The display method according to claim 11, wherein, In the second display mode, the start times of the effective levels of the plurality of clock signals are sequentially separated by 1H2, where H2 is half the phase difference between the start times of two adjacent effective levels of the data control signal.

13. The display method according to claim 12, wherein, In the second display mode, the effective level of the clock signal has a duration of 4H2, and the duty cycle of the effective level of the clock signal is 50%; the duration for which the multiple clock signals satisfy that adjacent row sub-pixels are simultaneously turned on is 3H2.

14. A display device comprising a graphics card, a motherboard, a gate driving circuit, a source driving circuit, and a display panel; wherein the physical resolution of the display panel is M1×N1; The motherboard is configured to convert the first raw image data sent by the graphics card into first image data and send it to the timing controller; the resolution of the first image data is M2×N2; N2:N1=a:b<1; The timing controller is configured to provide P clock signals to the gate driving circuit in the display panel and to provide data control signals to the source driving circuit. P = i × b; i is a positive integer greater than or equal to 1; the gate driving circuit selects each row of sub-pixels of the display panel according to the P clock signals, and the source driving circuit writes the N2 rows of display data in the first image data line by line according to the scanning order for each row of sub-pixels except for the j × b row according to the data control signal. Write the sub-pixel of row j×b into the display data of sub-pixels of rows b×j-1 and b×j+1; j is a positive integer greater than or equal to 1, and b×j+1≤N1; The graphics card is configured to receive a display mode selection instruction, and when the display mode selection instruction is a first display mode, the graphics card sends the received first raw image data to the motherboard; the resolution of the first raw image data is M3×N3; M3 < M2; The motherboard converts the first raw image data sent by the graphics card into first image data, including: the motherboard performs horizontal interpolation processing on the first raw image data to obtain the first image data.

Images