Signal frequency measurement system and method based on FPGA and DSP
Through the signal frequency measurement system based on FPGA and DSP, the problems of high algorithm complexity, heavy computing burden and insufficient measurement accuracy in the prior art are solved, and signal frequency measurement with high accuracy and strong anti-interference ability are achieved.
Patent Information
- Application Number
- CN202510245659.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-04
- Publication Date
- 2025-06-06
AI Technical Summary
The existing signal frequency measurement technology has problems such as high algorithm complexity, heavy computational burden and insufficient measurement accuracy.
The signal frequency measurement system based on FPGA and DSP is adopted, and real-time signal sampling, preliminary calculation and high-precision frequency calculation are realized through the coordinated work of the data conversion module, FPGA module and DSP module.
It realizes high-precision signal frequency measurement, simplifies the module structure design, improves anti-interference ability and measurement accuracy, and is suitable for measurements in different frequency ranges.
Smart Images
Figure CN120102970A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of electronic measurement technology, and in particular to a signal frequency measurement system and method based on FPGA and DSP. Background Art
[0002] Signal frequency measurement is an important indicator in the field of electronic measurement. Because it plays an important role in practical engineering applications, high-precision signal frequency measurement is particularly important.
[0003] Common signal frequency measurement techniques include Fourier transform method, direct measurement method and indirect measurement method, etc. These methods can be applied to signal frequency measurement in different scenarios due to their respective characteristics, but they also have some disadvantages and limitations.
[0004] Among them, the Fourier transform method is a global analysis of the signal in time, which has high computational complexity and has limitations in the analysis of local characteristics of the signal. The spectrum analysis effect of non-periodic and bursty signals is poor. The direct measurement method counts the number of pulses of the measured signal within a fixed time t, and the number of pulses per unit time is the required frequency. This method will produce an error of ±1 measured pulse, which has certain limitations in practical applications. It is suitable for high-frequency signal measurement, but the measurement error for low-frequency signals is large. The indirect measurement method is to measure the number of reference clocks within a period of the measured signal to obtain the period of the measured signal, and then convert it into frequency. It is suitable for measuring low-frequency signals, and the measurement speed is too slow.
[0005] In addition, traditional frequency measurement methods have problems such as high algorithm complexity, heavy computational burden, and insufficient measurement accuracy. Summary of the invention
[0006] The purpose of the present invention is to propose a signal frequency measurement system and method based on FPGA and DSP to solve the problems of high algorithm complexity, heavy calculation burden and insufficient measurement accuracy in the background technology.
[0007] On the one hand, the present invention proposes a signal frequency measurement system based on FPGA and DSP, including a data conversion module, an FPGA module, a DSP module, a communication interface and an output unit:
[0008] A data conversion module is used to perform AD conversion on the external signal to be tested;
[0009] The FPGA module is responsible for real-time sampling of the input signal after AD conversion, performing preliminary calculations, and then transmitting these processed signals to the DSP module;
[0010] The data input and output of the DSP module are managed through the interrupt control mechanism;
[0011] The output unit is used to display the frequency data processed by the DSP module;
[0012] The communication interface is used to realize the electrical connection between the data conversion module, the FPGA module, the DSP module and the output unit.
[0013] Preferably, the FPGA module includes an input port, a gate signal generator, a register, a counter and an output port.
[0014] Preferably, the input port is used to receive the system clock signal and the square wave signal to be tested; the gate signal generator generates a 1-second gate signal, counts the preset gate time through the counter, and switches the gate signal state when the value is reached; the register is used to eliminate the jitter of the square wave signal to ensure that the square wave signal is synchronized with the system clock; the counter includes a system clock cycle counter and a square wave cycle counter to be tested, which are respectively used to count the system clock cycle and the square wave cycle to be tested within the gate time; the output port outputs the system clock cycle count and the square wave cycle count within the gate through a 16-bit wide output port for subsequent processing by the DSP module.
[0015] Preferably, the DSP module includes a data receiving unit, an output processing unit and a cycle merging unit.
[0016] Preferably, the data receiving unit is used to receive the high and low 16 bits of the system clock cycle count within the gate and the square wave cycle count to be tested transmitted by the FPGA module; the output processing unit performs the final frequency calculation, merges to obtain the complete system clock cycle count within the gate, and calculates the frequency of the signal to be tested.
[0017] Preferably, the cycle merging formula is: the system clock cycle count in the gate = high 6 bits * 2 16 +Lower 16 bits.
[0018] Preferably, the frequency calculation formula is: signal frequency=system clock frequency*square wave cycle count to be measured / system clock cycle count within the gate.
[0019] On the other hand, the present invention provides a signal frequency measurement method based on FPGA and DSP, comprising the following steps:
[0020] S1, the external signal to be tested is input into the data conversion module, a digital signal is generated through AD conversion, and the digital signal is transmitted to the FPGA module through the data bus;
[0021] S2, FPGA module implements an internal frequency meter and outputs the counting result to the DSP module for the final frequency calculation;
[0022] S3, the DSP module performs the final frequency calculation on the counting result output by the FPGA module to obtain a high-precision frequency measurement result;
[0023] S4, DSP module transmits the calculated signal frequency to the host computer.
[0024] Compared with the prior art, the present invention has the following beneficial technical effects:
[0025] 1. The module structure is simple in design and can be easily integrated into existing power electronic systems without the need for complex wiring or hardware components.
[0026] 2. The DSP calculation process is simple and efficient, without the need for complex mathematical operations.
[0027] 3. The method has strong anti-interference ability. The algorithm adopts the counting principle and has no requirements on the harmonic conditions of the input signal. It can maintain stable measurement performance in a power electronic environment with large electromagnetic interference.
[0028] 4. High measurement accuracy, can achieve high-precision measurement of different frequency ranges. Using two 16-bit counters can expand the counting range, so that the number of cycles in a larger range can be counted, which can effectively avoid overflow and improve the accuracy of frequency measurement. BRIEF DESCRIPTION OF THE DRAWINGS
[0029] Figure 1 A schematic diagram of the structure of an embodiment of the present invention;
[0030] Figure 2 This is a schematic diagram of the frequency measurement principle;
[0031] Figure 3 This is the overall flow chart for frequency calculation;
[0032] Figure 4 for Figure 3 The internal processing logic of the FPGA part;
[0033] Figure 5 for Figure 3 The internal processing logic of the DSP part. DETAILED DESCRIPTION
[0034] Embodiment 1, as Figure 1 As shown, the present invention proposes a signal frequency measurement system based on FPGA and DSP, including a data conversion module, an FPGA module, a DSP module, a communication interface and an output unit, wherein the output unit is a host computer:
[0035] A data conversion module is used to perform AD conversion on the external signal to be tested;
[0036] The FPGA module is responsible for real-time sampling of the input signal after AD conversion and performing preliminary calculations to obtain the system clock cycle count within the gate and the square wave cycle count to be measured, and then transmits these processed signals to the DSP module for further processing;
[0037] The data input and output of the DSP module are managed through the interrupt control mechanism. When the FPGA module completes data preparation and writes data, it will send a read interrupt signal to the DSP module. After receiving the signal, the DSP module will perform a data read operation. Conversely, when the FPGA module is ready to read the data processed by the DSP module, it will send an interrupt request signal. The DSP module will then place the processed data on the communication bus for the FPGA module to read.
[0038] The output unit is used to display the frequency data processed by the DSP module;
[0039] The communication interface is used to realize the electrical connection between the data conversion module, the FPGA module, the DSP module and the output unit. Specifically, the data conversion module and the FPGA module are connected in a one-way data transmission manner, the FPGA module and the DSP module are connected in a two-way data transmission manner, and the DSP module and the output unit are connected in a one-way data transmission manner.
[0040] Embodiment 2, the present invention proposes a signal frequency measurement system based on FPGA and DSP. Compared with embodiment 1, this embodiment introduces the FPGA module and the DSP module in detail.
[0041] The FPGA module includes an input port, a gate signal generator, a register, a counter, and an output port. The input port is used to receive the system clock signal and the square wave signal to be tested; the gate signal generator generates a 1-second gate signal, counts the preset gate time through the counter, and switches the gate signal state when the value is reached; the register is used to eliminate the jitter of the square wave signal to ensure that the square wave signal is synchronized with the system clock; the counter includes a system clock cycle counter and a square wave cycle counter to be tested, which are used to count the system clock cycle and the square wave cycle to be tested within the gate time respectively; the output port outputs the system clock cycle count and the square wave cycle count within the gate through a 16-bit wide output port for subsequent processing by the DSP module.
[0042] The DSP module includes a data receiving unit, an output processing unit, and a cycle merging unit. The data receiving unit is used to receive the high and low 16 bits of the gate system clock cycle count and the square wave cycle count to be measured transmitted by the FPGA module; the output processing unit performs the final frequency calculation, merges to obtain the complete gate system clock cycle count, and calculates the frequency of the signal to be measured. Cycle merging formula: Gate system clock cycle count = high 6 bits * 2 16+ Low 16 bits; Frequency calculation formula: Signal frequency = system clock frequency * square wave cycle count to be measured / system clock cycle count in the gate.
[0043] Furthermore, the relative error of the equal-precision frequency measurement method has nothing to do with the frequency of the measured signal, but only with the gate time and the reference clock frequency, thus achieving equal-precision measurement of the entire test frequency band. The longer the gate time and the higher the reference clock frequency, the smaller the relative error of the frequency measurement.
[0044] In this embodiment, the gate time is adjusted to T, and the frequency calculation formula is: signal frequency = system clock frequency (50000) * square wave cycle count to be measured / system clock cycle count within the gate time T.
[0045] The detailed description is as follows with reference to the accompanying drawings:
[0046] Figure 1 This is a frequency measurement function block diagram. The system mainly includes: DSP processor, programmable logic device FPGA, AD analog-to-digital conversion module, output port (host computer), etc., wherein the DSP processor refers to the DSP module mentioned above, the programmable logic device FPGA refers to the FPGA module mentioned above, the AD analog-to-digital conversion module refers to the data conversion module mentioned above, and the output port refers to the output unit mentioned above, wherein the external signal to be measured is input into the AD analog-to-digital converter, converted into a digital signal by the AD analog-to-digital converter, and transmitted to the programmable logic device FPGA through the data bus; the programmable logic device FPGA is connected to the data processor DSP through the address bus and the data bus, based on which the signal is transmitted; the data processor DSP is connected to the host computer through the communication serial port to observe the final result. The digital signal to be measured enters the programmable logic device FPGA, and the combination of the programmable logic device FPGA and the DSP data processor is used to calculate the frequency of the signal to be measured. Among them, an internal frequency meter is implemented in the programmable logic device FPGA, which counts the signal to be measured and the system clock within the gate time by setting the gate, and outputs the counting result to the DSP data processor for the final frequency calculation. The DSP data processor has the characteristics of high calculation accuracy and fast calculation speed. It can calculate the counting results output by the programmable logic device FPGA to obtain high-precision frequency measurement results. The DSP processor sends the calculated signal frequency to the host computer, which is convenient for intuitive and clear observation of frequency measurement results.
[0047] Figure 2This is a schematic diagram of the frequency measurement principle. It mainly includes the system clock (time base signal), the measured signal, and the gate signal. The gate signal must be synchronized with the measured signal to obtain the actual gate signal. When the gate signal is high, the system clock and the measured signal are counted. Assuming that the system clock is 50MHz, the counting result is 10,000 system clock cycles and 5 measured signal cycles, then the measured signal frequency f0 = 50M*5 / 10000 = 25KHz.
[0048] Figure 3 This is the overall frequency measurement flow chart.
[0049] Figure 4 and Figure 5 They are the internal computing logic of FPGA programmable logic devices and DSP processors respectively.
[0050] The overall frequency calculation process is as follows:
[0051] Input the system clock and the signal to be measured, and synchronize the input signal: use four registers to eliminate the jitter of the square wave signal to ensure signal stability.
[0052] Gate signal generation: Use a counter to generate a 1-second gate signal. When the counter reaches the gate time count number, the gate signal flips.
[0053] Gate signal synchronization: The gate signal is synchronized with the square wave to ensure that a gate contains an integer number of square wave cycles. The actual gate signal is a delayed version of the gate signal and is used to capture the edge of the gate signal.
[0054] Gate start and gate end signals: define the gate start and gate end.
[0055] System clock cycle count: Count the number of system clock cycles during the gate time. When the gate starts, the counter starts counting and saves the count result when the gate ends.
[0056] Counting the number of cycles of the square wave to be tested: Count the number of cycles of the square wave to be tested during the gate time. When the gate starts, the counter is reset to 0, and then during the gate, each time the falling edge of the square wave is detected, the counter increases, and when the gate ends, the result is saved.
[0057] Output the number of cycles of the square wave to be measured within the gate time and the high 16 bits and low 16 bits of the system clock cycle within the gate time.
[0058] The cycle count result is sent to the DSP processor through the data bus to perform the final frequency calculation. The complete system clock cycle count within the gate is combined to calculate the frequency of the signal to be measured using the formula:
[0059] Signal frequency = system clock frequency (50000) * square wave cycle count to be measured / system clock cycle count within the gate.
[0060] The embodiments of the present invention are described in detail above with reference to the accompanying drawings, but the present invention is not limited thereto, and various changes can be made within the knowledge scope of technicians in the relevant technical field without departing from the purpose of the present invention.
Claims
1. A signal frequency measurement system based on FPGA and DSP, characterized in that: Including data conversion module, FPGA module, DSP module, communication interface and output unit: A data conversion module is used to perform AD conversion on the external signal to be tested; The FPGA module is responsible for real-time sampling of the input signal after AD conversion, performing preliminary calculations, and then transmitting these processed signals to the DSP module; The data input and output of the DSP module are managed through the interrupt control mechanism; The output unit is used to display the frequency data processed by the DSP module; The communication interface is used to realize the electrical connection between the data conversion module, the FPGA module, the DSP module and the output unit.
2. The signal frequency measurement system based on FPGA and DSP according to claim 1, characterized in that: The FPGA module includes input ports, gate signal generators, registers, counters, and output ports.
3. The signal frequency measurement system based on FPGA and DSP according to claim 2 is characterized in that: The input port is used to receive the system clock signal and the square wave signal to be tested; the gate signal generator generates a 1-second gate signal, counts the preset gate time through the counter, and switches the gate signal state when the value is reached; The register is used to eliminate the jitter of the square wave signal and ensure that the square wave signal is synchronized with the system clock; the counter includes a system clock cycle counter and a square wave cycle counter to be measured, which are used to count the system clock cycle and the square wave cycle to be measured within the gate time respectively; the output port outputs the system clock cycle count and the square wave cycle count within the gate through a 16-bit wide output port for subsequent processing by the DSP module.
4. The signal frequency measurement system based on FPGA and DSP according to claim 1, characterized in that: The DSP module includes a data receiving unit, an output processing unit and a cycle merging unit.
5. The signal frequency measurement system based on FPGA and DSP according to claim 4 is characterized in that: The data receiving unit is used to receive the high and low 16 bits of the gate system clock cycle count and the square wave cycle count to be measured transmitted by the FPGA module; the output processing unit performs the final frequency calculation, merges the complete gate system clock cycle count, and calculates the frequency of the signal to be measured.
6. The signal frequency measurement system based on FPGA and DSP according to claim 5, characterized in that: Cycle merging formula: System clock cycle count within the gate = high 6 bits * 2 16 +Lower 16 bits.
7. The signal frequency measurement system based on FPGA and DSP according to claim 5, characterized in that: Frequency calculation formula: Signal frequency = system clock frequency * square wave cycle count to be measured / system clock cycle count in the gate.
8. A signal frequency measurement method based on FPGA and DSP, using the signal frequency measurement system based on FPGA and DSP according to claim 7, characterized in that: The following steps are involved: S1, the external signal to be tested is input into the data conversion module, a digital signal is generated through AD conversion, and the digital signal is transmitted to the FPGA module through the data bus; S2, FPGA module implements an internal frequency meter and outputs the counting result to the DSP module for the final frequency calculation; S3, the DSP module performs the final frequency calculation on the counting result output by the FPGA module to obtain a high-precision frequency measurement result; S4, DSP module transmits the calculated signal frequency to the host computer.