Low power on-chip read circuit

Abstract

The application provides a low-power on-chip reading circuit. When a storage unit is in a conducting state, a first branch and a second branch are both conducting, so that a first target level corresponding to a reading state is generated at an output end of the on-chip reading circuit, and the state reading of the storage unit is realized. Meanwhile, a logic control module performs feedback control on a first switch and a second switch, and immediately disconnects the first switch and the second switch, so that there is no current in the first branch and the second branch. In this way, the first switch and the second switch are latch switches for completing high-level reading state, and it is ensured that, when the storage unit is conducting, the actual reading power consumption is feedback controlled according to the change of the reading state. Even if the reference current is designed to be too large, the reading time is not designed to be unreasonable (for example, the reading time is designed to be too long), and the power consumption is not generated. Therefore, the reading time is optimally controlled in power consumption, and the power consumption of the on-chip reading circuit is reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of storage reading, in particular to a low-power on-chip reading circuit. BACKGROUND

[0002] Traditional reading circuits usually compare a reference current Iref with the current output by a storage unit bitcell, as shown in the following formula: Figure 1 The size of the reference current Iref needs to be carefully selected. The production or erasing of a chip may cause differences in the current between the storage units bitcell. If the reference current is designed to be too small, it may cause errors in the reading state of some storage units bitcell. If the reference current is designed to be too large, it may cause unnecessary static power consumption. Therefore, a low-power on-chip reading circuit that is more inclusive in the selection of the reference current and does not cause excessive power consumption is needed. SUMMARY

[0003] The present application provides a low-power on-chip reading circuit that is more inclusive in the selection of the reference current.

[0004] A low-power on-chip reading circuit includes a switch control module, a current mirror, a first switch, a second switch, a reference current module, and a logic control module. The switch control module is connected to the first connection end of a driving tube and the first connection end of a load tube in the current mirror. The second connection end of the driving tube is connected to the first end of the first switch. The second connection end of the load tube is connected to the first end of the second switch and the input end of the logic control module. The second end of the first switch is connected to a storage unit. The second end of the second switch is connected to the reference current module. The control end of the first switch and the control end of the second switch are connected to the output end of the logic control module.

[0005] In a reading state, the switch control module is configured to output a first voltage to the driving tube and the load tube. If the storage unit is in an on state, the first branch in which the driving tube is located is turned on, and a loop current is generated based on the first voltage and mapped to the second branch in which the load tube is located. Before the reading state, the first switch and the second switch are in an on state.

[0006] The reference current module is configured to provide a reference current, so that the output end of the low-power on-chip reading circuit generates a first target level based on the comparison result of the reference current and the loop current. The output end of the low-power on-chip reading circuit and the input end of the logic control module are the same end.

[0007] The logic control module is further configured to disconnect the first switch and the second switch according to the first target level.

[0008] In one embodiment, if the storage unit is in the disconnected state, the first branch is not conductive, and the output end of the low-power on-chip reading circuit outputs a second target level.

[0009] In one embodiment, the low-power on-chip reading circuit further comprises:

[0010] a first inverter, an input end of the first inverter being connected with the second connection end of the load tube;

[0011] a latch module, an output end of the first inverter and an input end of the logic control module being connected with the latch module respectively.

[0012] In one embodiment, the switch control module is further connected with the output end of the first inverter and the latch module respectively, and is configured to output a second voltage to the latch module before the reading state, so that the first switch and the second switch enter the conductive state.

[0013] In one embodiment, the switch control module is further connected with the second connection end of the drive tube and the first end of the first switch respectively, and is configured to output a third voltage before the reading state.

[0014] In one embodiment, the switch control module is further configured to control to stop outputting the second voltage and the third voltage, and to output the first voltage to the drive tube and the load tube respectively.

[0015] In one embodiment, the switch control module comprises a switch tube S1A, a switch tube S1B and a switch tube S0; a first connection end of the switch tube S1A, a first connection end of the switch tube S1B and a first connection end of the switch tube S0 are connected with a power supply respectively; a second connection end of the switch tube S1A is connected with the second connection end of the drive tube and the first end of the first switch respectively; a second connection end of the switch tube S0 is connected with the first connection end of the drive tube and the first connection end of the load tube in the current mirror; a second connection end of the switch tube S1B is connected with the output end of the first inverter and the latch module respectively; a control end of the switch tube S1A, a control end of the switch tube S1B and a control end of the switch tube S0 are configured to receive a gate drive voltage respectively.

[0016] In one embodiment, the logic control module comprises: a first NAND gate, a second inverter and a third inverter; the input end of the second inverter is connected with the latch module, the output end of the second inverter is connected with the input end of the third inverter and the control end of the second switch respectively; the output end of the third inverter is connected with the first input end of the first NAND gate, the second input end of the first NAND gate is used for receiving a first reference signal, and the output end of the first NAND gate is connected with the control end of the first switch.

[0017] In one embodiment, the latch module comprises: a second NAND gate and a third NAND gate, the first input end of the second NAND gate is connected with the output end of the first inverter, the output end of the second NAND gate is connected with the input end of the logic control module and the first input end of the third NAND gate respectively; the second input end of the third NAND gate is used for receiving a second reference signal, and the output end of the third NAND gate is connected with the second input end of the second NAND gate.

[0018] In one embodiment, the low-power on-chip reading circuit further comprises: a plurality of fourth inverters, each of which is connected in cascade, and the input end of the first fourth inverter is connected with the output end of the second NAND gate; the output end of the last fourth inverter serves as the output end of the low-power on-chip reading circuit.

[0019] The above achieves voltage transmission by setting the switch control module, and then sets the first switch and the second switch in the on state before reading. In the reading state, if the storage unit is in the on state, the first branch and the second branch are both in the on state, and the first voltage transmitted to the current mirror based on the switch control module, the first branch will generate a loop current, and mirror to the second branch, so as to compare with the reference current provided by the reference current module, so as to generate a first target level corresponding to the read state at the output end of the on-chip reading circuit based on the comparison result, to realize the state reading of the storage unit. Subsequently, the logic control module will feedback control the first switch and the second switch, and when the output of the on-chip reading circuit is the first target level, the first switch and the second switch will be immediately disconnected, so that there is no current in the first branch and the second branch. In this way, the first switch and the second switch serve as latching switches for high-level reading state, ensuring that the actual reading power consumption is feedback controlled according to the change of the reading state when the storage unit is on. Even if the reference current is designed to be too large, it will not produce excessive power consumption due to unreasonable reading time design (for example, the reading time is designed to be too long), so that the reading time is optimized for power consumption control, and the power consumption of the on-chip reading circuit is reduced. BRIEF DESCRIPTION OF DRAWINGS

[0020] Figure 1 It is a circuit structure diagram of a conventional reading circuit of the present application;

[0021] Figure 2 A circuit structure diagram of a low-power on-chip reading circuit according to an embodiment of the present application;

[0022] Figure 3 A circuit structure diagram of a low-power on-chip reading circuit according to another embodiment of the present application;

[0023] Figure 4 A circuit structure diagram of a low-power on-chip reading circuit according to another embodiment of the present application;

[0024] Figure 5 A circuit structure diagram of a low-power on-chip reading circuit according to another embodiment of the present application;

[0025] Figure 6 A circuit structure diagram of a low-power on-chip reading circuit according to another embodiment of the present application;

[0026] Figure 7 A circuit structure diagram of a low-power on-chip reading circuit according to another embodiment of the present application. DETAILED DESCRIPTION

[0027] It should be understood that the specific embodiments described herein merely exemplify the application and do not limit the application.

[0028] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative effort fall within the scope of the present application.

[0029] It should be noted that all the directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present application are merely used to explain the relative position relationship, movement condition, etc. between components in a certain posture (as shown in the drawings), and if the certain posture changes, the directional indications also change accordingly. The connection can be direct connection or indirect connection.

[0030] In addition, the descriptions such as “first”, “second” and the like in the present application are merely for the purpose of description, and cannot be understood as indicating or implying the relative importance of the indicated technical features or implicitly indicating the number of the indicated technical features. Therefore, the features defined as “first”, “second” can explicitly or implicitly include at least one of the features. In addition, the technical solutions of various embodiments can be combined with each other, but it must be based on the fact that a person skilled in the art can realize it, and when the combination of technical solutions appears contradictory or unachievable, it should be considered that the combination of technical solutions does not exist, and is not within the scope of protection claimed by the present application.

[0031] Figure 2 This is a schematic diagram of a low-power on-chip readout circuit according to an embodiment, such as... Figure 2 As shown, a low-power on-chip readout circuit is characterized by comprising a switch control module 110, a current mirror 120, a first switch S2A, a second switch S2B, a reference current module 140, and a logic control module 130. The switch control module 110 is connected to the first connection terminal of the driving transistor PM1 and the first connection terminal of the load transistor PM2 in the current mirror 120, respectively. The second connection terminal of the driving transistor PM1 is connected to the first terminal of the first switch S2A, and the second connection terminal of the load transistor PM2 is connected to the first terminal of the second switch S2B and the input terminal of the logic control module 130, respectively. The second terminal of the first switch S2A is connected to a memory cell, and the second terminal of the second switch S2B is connected to the reference current module 140. The control terminals of the first switch S2A and the second switch S2B are respectively connected to the output terminals of the logic control module 130. In the read state, the switch control module 110 controls the output of a first voltage U1 to the driving transistor PM1 and the load transistor PM2 respectively. If the memory cell is in the on state, the first branch where the driving transistor PM1 is located is turned on, and a loop current is generated based on the first voltage U1, and the loop current is mapped to the second branch where the load transistor PM2 is located. Before the read state, the first switch S2A and the second switch S2B are in the on state. The reference current module 140 is used to provide a reference current so that the output terminal of the low-power on-chip read circuit generates a first target level based on the comparison result of the reference current and the loop current. The output terminal of the low-power on-chip read circuit and the input terminal of the logic control module 130 are the same terminal. The logic control module 130 is also used to disconnect the first switch S2A and the second switch S2B according to the first target level.

[0032] It can be understood that the switch control module 110 can be used to realize voltage transmission; when the first switch S2A and the second switch S2B are in the on state, the reference current module 140 provides a reference current to the third branch l3 to compare with the current on the second branch l2, thereby generating a comparison result at node A, and then generating a corresponding level signal at the output terminal out of the low-power chip read circuit. At the same time, the level signal is fed back to the logic control module 130, and then the logic control module 130 controls the first switch S2A and the second switch S2B.

[0033] Specifically, before reading, the first switch S2A and the second switch S2B are in the on state, and the reference current module 140 provides a reference current to the third branch l3. In the reading state, the storage unit can include two states of on and off. When in the on state, the first branch l1 and the second branch l2 are both on, and the first branch l1 generates a loop current under the action of the first voltage U1. The loop current is then mapped to the third branch l3 under the action of the current mirror 120 composed of the MOS PM1 and the MOS PM2, to compare at the node A, and generate a first target level based on the comparison result. In some embodiments, the reference current can be a small current, which can be smaller than the mirror current. Thus, the node A is at a high level. If the output end of the on-chip reading circuit is the same as the node A, then the first target level is at a high level.

[0034] Further, when the logic control module 130 receives the first target level, the first switch S2A and the second switch S2B are turned off, so that there is no current in the first branch l1 and the second branch l2, achieving the reduction of the power consumption of the on-chip reading circuit.

[0035] The number of storage units can be multiple, and one storage unit is selected for reading each time. Each storage unit can include multiple MOS transistors. Taking two MOS transistors as an example, the MOS NM1 is a floating gate structure, used to save the state of the storage unit. When on, it indicates that the read state is at a high level, and vice versa. The MOS NM2 is controlled by the drive signal WL to turn on to select the storage unit to be read. In addition, the reference current module 140 can include a current mirror circuit to provide a reference current by mirroring output.

[0036] The on-chip reading circuit realizes voltage transmission through the switch control module 110, and then sets the first switch S2A and the second switch S2B in the on state before reading. When the reading state changes, if the storage unit is in the on state, the first branch l1 and the second branch l2 are both in the on state, and based on the first voltage U1 transmitted to the current mirror 120 by the switch control module 110, the first branch l1 will generate a loop current and mirror to the second branch l2 to compare with the reference current provided by the reference current module 140, so as to generate a first target level corresponding to the read state at the output end of the on-chip reading circuit based on the comparison result, realize the state reading of the storage unit, and then the logic control module 130 will perform feedback control on the first switch S2A and the second switch S2B. When the output of the on-chip reading circuit is the first target level, the first switch S2A and the second switch S2B are immediately disconnected, so that there is no current in the first branch l1 and the second branch l2. In this way, the first switch S2A and the second switch S2B serve as latching switches for high-level reading state, ensuring that when the storage unit 101 is in the on state, the actual reading power consumption is feedback controlled according to the change of the reading state. Even if the reference current is designed to be too large, it will not cause excessive power consumption due to unreasonable reading time design (for example, reading time design is too long), so that the reading time is optimized for power consumption control, and the power consumption of the on-chip reading circuit is reduced.

[0037] In one embodiment, if the storage unit is in the off state, the first branch l1 is not in the on state, and the output end of the low-power on-chip reading circuit outputs a second target level.

[0038] It can be understood that in the reading state, the switch control module 110 is used to control the output of the first voltage U1 to the driving tube PM1 and the load tube PM2 respectively. If the storage unit is in the off state, the first branch l1 has no current, and the second branch l2 and the third branch l3 output a level corresponding to the reference current after current comparison, so that the output end of the on-chip reading circuit outputs a second target level. Wherein, the reference current can be a small current, which is greater than the mirror current (the mirror current is zero). In this way, the node A is at a low level. If the output end of the on-chip reading circuit outputs the same as the node A, the second target level is at a low level.

[0039] In one embodiment, as shown in Figure 3 The low-power on-chip reading circuit further includes a first inverter 152 and a latch module 160. The input end of the first inverter 152 is connected with the second connection end of the load tube PM2. The latch module 160 is connected with the output end of the first inverter 152 and the input end of the logic control module 130 respectively.

[0040] It is understandable that the latch module 160 can latch the level at node A, ensuring that when the first switch S2A and the second switch S2B are open, the output state will not be changed due to the floating node A being disturbed and flipped, thus increasing the reliability of the circuit.

[0041] The output of latch module 160 is opposite to its input. Therefore, the first inverter 152 can be configured to first invert the level at node A, and then latch it through latch module 160.

[0042] In one embodiment, such as Figure 3 As shown, the switch control module 110 is also connected to the output terminal of the first inverter 152 and the latch module 160 respectively, and is used to control the output of the second voltage U2 to the latch module 160 before reading the state, so that the first switch S2A and the second switch S2B enter the conduction state.

[0043] Specifically, before reading the state, the switch control module 110 controls the output of the second voltage U2 instead of the first voltage U1. Therefore, node B is at a high level, which becomes a low level after passing through the latch. After receiving the low level, the logic control module 130 controls the first switch S2A and the second switch S2B to turn on respectively.

[0044] In one embodiment, continue to refer to Figure 3 As shown, the switch control module 110 is also connected to the second connection terminal of the drive transistor PM1 and the first terminal of the first switch S2A, respectively, for controlling the output of the third voltage U3 before reading the state.

[0045] It is understandable that parasitic capacitors are set at nodes P and M. The third voltage U3 can be used to precharge the parasitic capacitors, thereby speeding up the reading process, reducing latency, and improving reading efficiency.

[0046] In some embodiments, the moment when the switch control module 110 controls the output of the third voltage U3 can be the same moment when the switch control module 110 controls the output of the second voltage U2. In this way, the process of pre-charging the parasitic capacitor and the process of controlling the initial state of the first switch S2A and the second switch S2B to be in the on state do not affect each other, and the time to enter the reading state can be shortened.

[0047] In one embodiment, the switch control module 110 is further configured to control the stopping of the output of the second voltage U2 and the third voltage U3, and to control the output of the first voltage U1 to the drive transistor PM1 and the load transistor PM2, respectively.

[0048] The timing of the switch control module 110 controlling the output of the third voltage U3 is the same as the timing of the switch control module 110 controlling the output of the second voltage U2. When the first switch S2A and the second switch S2B are in the conducting state and the parasitic capacitor has been fully charged, the switch control module 110 controls the stop of the output of the second voltage U2 and the third voltage U3, and controls the output of the first voltage U1 to the drive transistor PM1 and the load transistor PM2 respectively. At this time, even if the second voltage U2 is not present, the first switch S2A and the second switch S2B can still remain in the conducting state. Moreover, since the first voltage U1 is controlled to be output in advance, preparations can be made in advance for entering the reading state.

[0049] In one embodiment, such as Figure 4 As shown, the switch control module 110 includes: a switch transistor S1A, a switch transistor S1B, and a switch transistor S0; the first connection terminals of switch transistor S1A, switch transistor S1B, and switch transistor S0 are respectively connected to the power supply VDD; the second connection terminal of switch transistor S1A is respectively connected to the second connection terminal of drive transistor PM1 and the first terminal of the first switch S2A; the second connection terminal of switch transistor S0 is connected to the first connection terminal of drive transistor PM1 and the first connection terminal of load transistor PM2 in the current mirror 120; the second connection terminal of switch transistor S1B is respectively connected to the output terminal of the first inverter 152 and the latch module 160; the control terminals of switch transistor S1A, switch transistor S1B, and switch transistor S0 are respectively used to receive the gate drive voltage.

[0050] It is understood that the switch control module 110 may be equipped with three switching transistors, one end of each of which is connected to the power supply VDD. By controlling the opening and closing of the switches, the output voltage of the power supply VDD can be controlled, thereby providing the corresponding voltage to the subsequent circuits. The opening and closing state of each switching transistor is controlled by its gate drive voltage, which may be the same or different.

[0051] In one embodiment, such as Figure 5 As shown, the logic control module 130 includes: a first NAND gate 131, a second inverter 132, and a third inverter 133; the input terminal of the second inverter 132 is connected to the latch module 160, and the output terminal of the second inverter 132 is connected to the input terminal of the third inverter 133 and the control terminal of the second switch S2B respectively; the output terminal of the third inverter 133 is connected to the first input terminal of the first NAND gate 131, the second input terminal of the first NAND gate 131 is used to receive a first reference signal, and the output terminal of the first NAND gate 131 is connected to the control terminal of the first switch S2A.

[0052] In this configuration, to enable the first switch S2A and the second switch S2B to conduct, the first reference signal can be at a low level. In some embodiments, when the switch control module includes switches S1A, S1B, and S0, the second input terminal of the first NAND gate 131 can be connected to the gates of switches S1A and S1B, respectively. Thus, the level of the first reference signal is the same as the gate voltage of switches S1A and S1B. When switches S1A and S1B are conducting, the first reference signal is at a low level, and the first NAND gate 131 outputs a high level, enabling the first switch S2A. When switches S1A and S1B are de-energized, and switch S0 is activated, the first reference signal is at a high level, and the output of the first NAND gate 131 is determined by the level of its first input terminal.

[0053] In one embodiment, such as Figure 6 As shown, the latch module 160 includes a second NAND gate 161 and a third NAND gate 162. The first input terminal of the second NAND gate 161 is connected to the output terminal of the first inverter 152. The output terminal of the second NAND gate 161 is connected to the input terminal of the logic control module 130 and the first input terminal of the third NAND gate 162, respectively. The second input terminal of the third NAND gate 162 is used to receive a second reference signal, and the output terminal of the third NAND gate 162 is connected to the second input terminal of the second NAND gate 161.

[0054] In this configuration, the second reference signal can be low to enable the first and second switches to conduct. In some embodiments, when the switch control module includes switches S1A, S1B, and S0, the second input of the third NAND gate 161 can be connected to the gates of switches S1A and S1B, respectively. Thus, the level of the second reference signal is the same as the gate voltage of switches S1A and S1B. When switches S1A and S1B are conducting, the second reference signal is low, and the latch module 160 outputs a low level, enabling the second switch S2B to conduct. When switches S1A and S1B are de-energized and switch S0 is activated, the second reference signal is high, and the output of the latch module 160 is determined by the level of the first input of the second NAND gate 161.

[0055] In one embodiment, continue to refer to Figure 6 As shown, the low-power on-chip read circuit also includes: multiple fourth inverters 151, each fourth inverter 151 is cascaded, and the input terminal of the first fourth inverter 151 is connected to the output terminal of the second NAND gate 161; the output terminal of the last fourth inverter 151 serves as the output terminal of the low-power on-chip read circuit.

[0056] It is understandable that when the circuit is far from the terminal, the size of the output stage transistors can be appropriately increased to enhance the driving capability of the output.Figure 6 The illustration only shows the case where there are two fourth inverters 151; in practice, this is not the limitation.

[0057] Figure 7 This is a circuit diagram of a low-power on-chip readout circuit according to another embodiment of the present invention, as shown below. Figure 7 As shown, the low-power on-chip read circuit includes: a switch control module 110, a current mirror 120, a first switch S2A, a second switch S2B, a reference current module 140, a logic control module 130, a first inverter 152, a latch module 140, and multiple fourth inverters 151; wherein, the switch control module 110 includes: a switch transistor S1A, a switch transistor S1B, and a switch transistor S0; the logic control module 130 includes: a first NAND gate 131, a second inverter 132, and a third inverter 133; the latch module 160 includes: a second NAND gate 161 and a third NAND gate 162. The connection relationship and working principle of each component can be referred to the above embodiment. The following is a brief description of the entire working process of the on-chip read circuit with reference to Table 1.

[0058] Table 1

[0059] State bitcell WL S0 S1A S1B S2A S2B A B C out reset -- off off on on on on 0 1 0 0 read init -- off on off off on on 0 1 0 0 Read_0 off on on off off on on 0 1 0 0 Read_1 on on on off off on->off on->off 0->1 1->0 0->1 1

[0060] The entire reading process is divided into a pre-reading state and a reading state. The pre-reading state includes the initial state "reset" and the read-init state as shown in Table 1. In both states, WL is low, and the state of the memory cell is not read. In the initial state "reset", switch S0 is turned off, and switches S1A and S1B are turned on. As a result, the third voltage U3 charges the parasitic capacitance of node P. The level of node A remains at the initial low level. Under the action of the second voltage U2, node B is at a high level. After passing through the latching module, node C is also at a low level, and the output terminal "out" is also at a low level. After passing through the logic control module, two high levels are obtained respectively, thereby turning on the first switch S2A and the second switch S2B. Then it enters the read init state. In this state, switch S0 is turned on, switch S1A and switch S1B are turned off, and drive transistor PM1 and load transistor PM2 in the current mirror are both turned on. However, since no state reading is performed, there is no current in the first branch L1 and the third branch L3, and the reference current is a small current. Therefore, node A is at a low level. After passing through the first inverter 152, node B is at a high level, node C is still at a low level, and the first switch S2A and the second switch S2B are still turned on.

[0061] Further, the system enters the read state. In this state, the drive signal WL is high, and the memory cell is either on or off. When it is off (bitcell is off), corresponding to the read_0 state in Table 1, the first branch is not conducting, meaning there is no current. Under the influence of the reference current, node A is low, node B is high, node C is low, and the output is also low, consistent with the state of the memory cell. When the memory cell is on (bitcell is on), corresponding to the read_1 state in Table 1, the first branch l1 is conducting, and its current is mapped to the third branch l3, which is greater than the reference current on the second branch l2. Node A jumps to high, node B jumps to low, node C jumps to high, and the output is also high, consistent with the state of the memory cell.

[0062] The above description is only a preferred embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural changes made based on the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A low-power on-chip readout circuit, characterized in that, The system includes a switch control module, a current mirror, a first switch, a second switch, a reference current module, and a logic control module. The switch control module is connected to the first connection terminal of the driving transistor and the first connection terminal of the load transistor in the current mirror. The second connection terminal of the driving transistor is connected to the first terminal of the first switch. The second connection terminal of the load transistor is connected to the first terminal of the second switch and the input terminal of the logic control module. The second terminal of the first switch is connected to a storage unit, and the second terminal of the second switch is connected to the reference current module. The control terminals of the first switch and the second switch are respectively connected to the output terminal of the logic control module. In the read state, the switch control module is used to control the output of a first voltage to the driving transistor and the load transistor respectively. If the memory cell is in the on state, the first branch where the driving transistor is located is turned on, and a loop current is generated based on the first voltage, and the loop current is mapped to the second branch where the load transistor is located. Before the read state, the first switch and the second switch are in the on state. The reference current module is used to provide a reference current so that the output of the low-power on-chip readout circuit generates a first target level based on the comparison result of the reference current and the loop current; the output of the low-power on-chip readout circuit is the same as the input of the logic control module. The logic control module is also used to disconnect the first switch and the second switch according to the first target level.

2. The low-power on-chip readout circuit according to claim 1, characterized in that, If the storage unit is in an off state, the first branch is not conducting, and the output terminal of the low-power on-chip read circuit outputs the second target level.

3. The low-power on-chip readout circuit according to claim 1, characterized in that, The low-power on-chip readout circuit also includes: A first inverter, the input terminal of which is connected to the second connection terminal of the load transistor; The latch module is connected to the output of the first inverter and the input of the logic control module, respectively.

4. The low-power on-chip readout circuit according to claim 3, characterized in that, The switch control module is also connected to the output terminal of the first inverter and the latch module respectively, and is used to control the output of a second voltage to the latch module before the read state, so that the first switch and the second switch enter the conduction state.

5. The low-power on-chip readout circuit according to claim 4, characterized in that, The switch control module is also connected to the second connection terminal of the drive tube and the first terminal of the first switch, respectively, for controlling the output of a third voltage before the reading state.

6. The low-power on-chip readout circuit according to claim 5, characterized in that, The switch control module is also used to control the stopping of the output of the second voltage and the third voltage, and to control the output of the first voltage to the driving transistor and the load transistor respectively.

7. The low-power on-chip readout circuit according to claim 5, characterized in that, The switch control module includes: a switch transistor S1A, a switch transistor S1B, and a switch transistor S0; the first connection terminal of the switch transistor S1A, the first connection terminals of the switch transistors S1B and S0 are respectively connected to a power supply; the second connection terminal of the switch transistor S1A is respectively connected to the second connection terminal of the driving transistor and the first terminal of the first switch; the second connection terminal of the switch transistor S0 is connected to the first connection terminal of the driving transistor in the current mirror and the first connection terminal of the load transistor; the second connection terminal of the switch transistor S1B is respectively connected to the output terminal of the first inverter and the latch module; the control terminals of the switch transistors S1A, S1B, and S0 are respectively used to receive the gate drive voltage.

8. The low-power on-chip readout circuit according to claim 4, characterized in that, The logic control module includes: a first NAND gate, a second inverter, and a third inverter; the input terminal of the second inverter is connected to the latch module, and the output terminal of the second inverter is connected to the input terminal of the third inverter and the control terminal of the second switch, respectively; the output terminal of the third inverter is connected to the first input terminal of the first NAND gate, the second input terminal of the first NAND gate is used to receive a first reference signal, and the output terminal of the first NAND gate is connected to the control terminal of the first switch.

9. The low-power on-chip readout circuit according to claim 4, characterized in that, The latching module includes a second NAND gate and a third NAND gate. The first input terminal of the second NAND gate is connected to the output terminal of the first inverter. The output terminal of the second NAND gate is connected to the input terminal of the logic control module and the first input terminal of the third NAND gate, respectively. The second input terminal of the third NAND gate is used to receive a second reference signal. The output terminal of the third NAND gate is connected to the second input terminal of the second NAND gate.

10. The low-power on-chip readout circuit according to claim 9, characterized in that, The low-power on-chip readout circuit further includes: a plurality of fourth inverters, each of which is cascaded, and the input terminal of the first fourth inverter is connected to the output terminal of the second NAND gate; the output terminal of the last fourth inverter serves as the output terminal of the low-power on-chip readout circuit.

Images