A system for integrated circuit debugging

Abstract

A system for integrated circuit debugging is disclosed. The system includes: a finite state machine that determines the working state of the system based on the value of a test data register, where the working state includes a normal function mode and a Scandump mode; several scan chains, each scan chain including several functional registers. When the working state is the normal function mode, the above scan chains are respectively controlled by a corresponding scan test logic; when the working state is the Scandump mode, the above scan chains are connected in series into a whole chain, the first end of the whole chain is connected to the input port of the system, the scan enable pins of the functional registers on the whole chain are controlled by the enable signal of the system, and the clock pins are controlled by the clock signal of the system. When the enable signal is activated and there is a clock pulse in the clock signal, the data in each functional register is shifted out from the output port of the system through the second end of the whole chain. This system can achieve efficient and low-cost Scandump debugging.

Description

Technical Field

[0001] This application relates to the technical field of testability design, and particularly to a system for integrated circuit debugging. Background Art

[0002] Scandump is a solution for functional debugging of large system-on-chip (SoC). Its purpose is to shift out all the values of the chip's functional registers when a functional failure occurs in the chip. These chip register values can initialize the chip simulation model to facilitate designers in finding the cause of the failure. How to provide an efficient and low-cost Scandump debugging solution for debuggers is a technical problem to be solved urgently. Summary of the Invention

[0003] In view of this, this application discloses a system for integrated circuit debugging to solve the technical problems proposed above.

[0004] A system for integrated circuit debugging includes: a finite state machine configured to determine the working state of the system based on the values of at least one test data register, where the working state includes a normal function mode and a Scandump mode; a plurality of scan chains that can be connected in series, each scan chain including a plurality of function registers connected in series in sequence. When the working state is the normal function mode, the plurality of scan chains that can be connected in series are respectively controlled by a corresponding scan test logic; when the working state is the Scandump mode, the plurality of scan chains that can be connected in series are connected in series into a single chain. The first end of the single chain is adapted to obtain data through the input port of the system. The scan enable pins of all the function registers on the single chain are controlled by an enable signal in the system, and the clock pins of the function registers are controlled by a clock signal in the system. When the enable signal indicates that the enable is activated and there is a clock pulse in the clock signal, the data stored in each function register is shifted out from the output port of the system through the second end of the single chain.

[0005] Optionally, the system further includes a data marking module disposed between the second end of the single chain and the output port. The data marking module includes a plurality of registers connected in series in sequence. The plurality of registers are initialized according to the values of a preset array during power-on reset; when in the normal function mode, the plurality of registers maintain their initial values, and when in the Scandump mode, the values of the plurality of registers are shifted out from the output port to mark the data from the second end of the single chain.

[0006] Optionally, the preset array includes a first element. A plurality of sequentially connected registers includes a first register. The first register has a serial input (si) port, a data input (d) port, a scan enable (se) port, a set control (set) port, a clear control (clr) port, an output (q) port, and a clock port. The d port is connected to the q port. The se port receives an enable signal in the system. The clock pin receives a clock signal in the system. The si port receives data at the second end of the entire chain or is connected to the q port of the previous-stage register. The q port is connected to the si port of the next-stage register or serves as the output end of the data marking module to shift the data out from the output port of the system. The set port is connected to the output end of the first AND gate. The clr port is connected to the output end of the second AND gate. The first input end of the first AND gate and the first input end of the second AND gate both receive a reset signal from the system. The second input end of the first AND gate receives the first element. The second input end of the second AND gate receives the inverted value of the first element, so that the signals received by the set port and the clr port are different.

[0007] Optionally, the preset array has a unique mapping relationship with the entire chain, so that the debugger can determine the corresponding entire chain based on the value of the preset array.

[0008] Optionally, the number of a plurality of sequentially connected registers is greater than or equal to the number of elements in the preset array.

[0009] Optionally, when the system is a module-level system in an integrated circuit, the finite state machine includes a first test data register, and the first test data register is adapted to store a first value or a second value; when the value of the first test data register is the first value, the working state is the Scandump mode; when the value of the first test data register is the second value, the working state is the normal function mode.

[0010] Optionally, the module-level system further includes a sub-module system, and the sub-module system is arranged between the second end of the entire chain and the output port of the system. The sub-module system receives the clock signal and the enable signal of the module-level system.

[0011] Optionally, when the system is a top-level system in an integrated circuit, the finite state machine includes a first test data register and a second test data register, and the first test data register and the second test data register are adapted to store a first value or a second value; when the values of the first test data register and the second test data register are both the second value, the working state is the normal function mode; when the value of the first test data register or the value of the second test data register is the first value, the working state is the Scandump mode; wherein, the values of the first test data register and the second test data register are not both the first value at the same time.

[0012] Optionally, the top-level system further includes a module-level system, which is disposed between the second end of the entire chain and the output port of the system. The module-level system receives the clock signal and the enable signal of the top-level system.

[0013] Optionally, the top-level system includes a Test Access Port (TAP), which is connected to the entire chain, and the signals on the TAP are suitable for controlling the shift operation of the entire chain; when the value of the first test data register is the first value and the value of the second test data register is the second value, and when both the selection signal and the enable signal on the TAP are the first value, the clock gating in the top-level system is turned on, and the clock signal of the test clock (TCK) corresponding to the clock gating is input to the entire chain through the clock gating to enable the top-level system to start the shift operation; when the value of the first test data register is the second value and the value of the second test data register is the first value, the scan enable ports of each register are controlled by the Test Mode Select (TMS) pin, and the value of the Test Mode Select on the TAP is fixed to the second value to keep the state of the TAP in order when the entire chain is shifted; the first end of the entire chain originates from the Test Data Input (TDI) pin, the second end of the entire chain drives the Test Data Output (TDO) pin, and the output enable of the TDO pin is driven to the first value; the clock gating at the stage after TCK is turned on to enable TCK to drive the clock signal of the entire chain; in this case, the Automatic Test Pattern Generation tool located outside the top-level system is suitable for penetrating the entire chain and extracting the data of each register on the entire chain.

[0014] In summary, a system for integrated circuit debugging disclosed in the present application has at least the following beneficial effects: directly connecting the entire chain to the TAP in the Scandump mode, which can facilitate the generation of Scandump vectors during debugging; and directly accessing the entire chain through the TAP port to help the ATPG tool correctly penetrate the entire chain and extract the names and location information of each register on the entire chain, facilitating subsequent debuggers to identify registers and locate problems; the design of the data marking module enables debuggers to quickly find the data of a certain module among a large amount of register data; in addition, when in the Scandump mode, a large number of GPIOs are not used as the interface for data interaction between the chip and the outside world, so there is no need to design interface hardware separately, thus achieving the effect of cost savings. Description of the Drawings

[0015] The following briefly introduces the drawings used in the description of the embodiments of the present application.

[0016] Figure 1 It is a structural schematic diagram of a test circuit based on a scan chain provided by an embodiment of the present application.

[0017] Figure 2 It is a TAP state machine provided by an embodiment of the present application.

[0018] Figure 3 This is a structural schematic diagram of a system (module level) for integrated circuit debugging provided by an embodiment of the present application.

[0019] Figure 4 This is a structural schematic diagram of a data marking module provided by an embodiment of the present application.

[0020] Figure 5 This is another structural schematic diagram of a system (top layer) for integrated circuit debugging provided by an embodiment of the present application. Detailed implementation manners

[0021] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the specific implementation manners of the present application will be described below with reference to the accompanying drawings. The accompanying drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings, and other implementation manners can be obtained. Adjustments and improvements made without departing from the concept of the present application fall within the protection scope of the present application.

[0022] To make the drawings concise, only the parts related to the corresponding embodiments are schematically shown in each drawing, and they do not represent the actual structure of the product as a whole. In addition, to make the drawings concise and easy to understand, in some drawings, only some of the components with the same structure or function are schematically shown, and there may actually be more or fewer components with the same structure or function.

[0023] In the present application, unless otherwise clearly specified and limited, ordinal numbers such as "first", "second", etc. are only used to distinguish and describe related objects, and cannot be understood as indicating or implying the relative importance or order of the related objects; in addition, they do not represent the quantity of the related objects. "Multiple" includes two or more, and other quantifiers are similar. " / " is used to describe the relationship between related objects, which means the "or" relationship between related objects. "And / or" is used to describe the relationship between related objects, which includes any combination relationship between related objects. For example, "a and / or b" includes: "a alone", "b alone", or "a and b". "One or more" or "at least one" among multiple objects refers to any object or any combination of multiple objects. For example, "one or more of a1, a2, a3" or "at least one of a1, a2, a3" includes: "a1 alone", "a2 alone", "a3 alone", "a1 and a2", "a1 and a3", "a2 and a3", or "a1, a2 and a3".

[0024] Design for testability (DFT) of chips is a key technology in the modern microelectronic chip development process. It is used to introduce testable structures during the chip design stage, thereby significantly improving the efficiency and reliability of subsequent manufacturing tests, fault location, debugging and verification, and field applications. By introducing DFT technology, the test cost can be reduced, the product yield can be increased, and the debugging cycle can be accelerated, which is particularly suitable for large-scale integrated circuits such as complex SoCs and ASICs.

[0025] In digital circuits, the most common and mature DFT strategy is the test method based on "Scan Chain". This method inserts scan paths between registers to construct a dedicated scan chain structure, thereby providing high controllability and observability for each register. In this way, designers can not only control the initial state of the register through the scan input, but also accurately capture the response of the register after the test through the scan output, realizing a comprehensive test and visual analysis of the internal logic state. In addition, the scan chain can cooperate with the Automatic Test Pattern Generation (ATPG) tool and the Automatic Test Equipment (ATE) to achieve a high-coverage and low-cost structured test process, which is one of the indispensable test design means in current mainstream chip design. Exemplarily, please refer to Figure 1 , which shows a structural example diagram of a test circuit based on a scan chain provided by an embodiment of the present application. The registers in the circuit are connected in series into a scan chain through the si and so ports. When scan_en is 1, the ATPG tool loads and unloads test vector data for the scan chain through scan_in and scan_out.

[0026] TAP (Test Access Port) is the DFT test interface. The ports include TDI (Test Data Input), TMS (Test Mode Select), TCK (Test Clock), TRSTN (Test Reset), and TDO (Test Data Output). Through these ports, the control and observation of chip testing are realized. Please refer to Figure 2 , which shows a TAP state machine provided by an embodiment of the present application. The TAP controller mainly controls the registers and realizes Select-DR-Scan and Shift-DR for selecting the TDR (Test Data Register) chain to be shifted and shifting the TDR chain through a finite state machine with 16 states.

[0027] Scandump is a solution for debugging the functions of large system-on-chips. Its purpose is to shift out the values of all the functional registers of the chip when a functional failure occurs in the chip. These values of the chip registers can initialize the chip simulation model, facilitating the designers to find out the cause of the failure.

[0028] There are also some chip debugging solutions in the prior art. For example, to implement the Scandump solution functionally, all the registers are strung into a chain functionally, and the values of the registers in the chip are shifted out through interfaces such as SPI and IIC. However, this technical solution will result in: (1) The functional logic is more complex, thus affecting the area and power consumption of the chip. At the same time, additional IOs are also required for data reception; (2) The registers related to Scandump data reception (SPI and IIC interface logic) cannot participate in the Scandump shift either, resulting in incomplete Scandump coverage; (3) When a functional logic failure such as a deadlock causes the system to hang, the Scandump function may not necessarily be started correctly, posing a risk that Scandump cannot work. Another technical solution is to shift out the register data inside the chip through SCANIOs by using the existing scan test circuit while masking off the scan compression logic. This solution has the following disadvantages: (1) Scan tests usually use a large number of GPIOs as the interface for data interaction between the chip and the outside world. If these interfaces are used in Scan dump, separate interface hardware needs to be designed, resulting in a high cost; (2) During the process of switching from the functional mode to the Scan test mode when a failure occurs, unexpected clock pulses may appear on the clock pins of the registers, damaging the state of the chip.

[0029] In view of the above deficiencies in the prior art, the purpose of this application is to provide a highly efficient and low-cost Scandump debugging solution for the debuggers.

[0030] The present application discloses a system for integrated circuit debugging, including: a finite state machine configured to determine the working state of the system based on the values of at least one test data register, where the working state includes a normal function mode and a Scandump mode; several serially connectable scan chains, each scan chain including several function registers connected in series in sequence. When the working state is the normal function mode, the several serially connectable scan chains are respectively controlled by a corresponding scan test logic; when the working state is the Scandump mode, the several serially connectable scan chains are connected in series into an integral chain. The first end of the integral chain is adapted to obtain data through the input port of the system, and the scan enable pins of all the function registers located on the integral chain are controlled by an enable signal in the system, and the clock pins of the function registers are controlled by a clock signal in the system. When the enable signal indicates that the enable is activated and there is a clock pulse in the clock signal, the data stored in each function register is shifted out from the output port of the system through the second end of the integral chain.

[0031] The system for integrated circuit debugging disclosed in the present application (hereinafter simply referred to as the "system") can be applied to different areas of the integrated circuit. For example, the system can be a module-level system. The module-level system can be a certain module applied to the integrated circuit (such as a processor module, a memory control module, etc.), and the module-level system can also be a sub-module of a certain module applied to the integrated circuit (such as the control unit of the processor module, the ECC unit of the memory control module, etc.). Another example is that the system can be a top-level system, and the top-level system is applied to the top-level design of the integrated circuit and is higher than each of the above modules. The present application does not limit the application area of the system, and corresponding implementation manners will be given respectively according to different types of systems later. The number of test data registers TDR is at least one, and the system can determine the current working state of the system, that is, the normal working mode or the Scandump mode, according to the value of the test data register. In the Scandump mode, the data stored in the registers of the integrated circuit can be shifted out. The value of the test data register can be set to a first value and a second value. In the present application, the first value refers to 1, and the second value refers to 0. The several serially connectable scan chains refer to multiple scan chains that can be connected end to end. After these scan chains are connected end to end, an integral chain can be formed. The head of the first scan chain is used as the head of the integral chain (or the first end of the integral chain), and the tail of the last scan chain is used as the tail of the integral chain (or the second end of the integral chain). Each scan chain is formed by connecting several function registers in series. The implementation manner of the series connection can refer to Figure 1 and the number of function registers included in each scan chain is not fixed. For example, it can include hundreds of function registers. When the working state is the normal function mode, the several serially connectable scan chains are respectively controlled by a corresponding scan test logic, and the scan test logic is in Figure 3 and Figure 5It is represented as "SCAN" in a rectangular grid. Each scan chain has a corresponding scan test logic. When the working state is the Scandump mode, the above scan test logic no longer controls each scan chain. Instead, each scan chain is connected end to end to form a complete chain, and then the shift operation starts. The se pins of each functional register on the complete chain are controlled by the enable signal in the system, and the clk pins are controlled by the clock signal in the system. When the system is in the Scandump mode and there is a clock pulse on the clock signal in the system, the data stored in each functional register on the complete chain is output through the second end of the complete chain and shifted out through the output port of the system. In the above embodiments, when the system is in the Scandump mode, a large number of GPIOs are not used as the interface for data interaction between the chip and the outside world. Thus, there is no need to separately design interface hardware, which further achieves the effect of cost savings.

[0032] In some embodiments of the present application, when the system is a module-level system in an integrated circuit, the finite state machine includes a first test data register, and the first test data register is adapted to store a first value or a second value; when the value of the first test data register is the first value, the working state is the Scandump mode; when the value of the first test data register is the second value, the working state is the normal function mode.

[0033] Please refer to Figure 3 , which shows a structural example diagram of a system (module level) for integrated circuit debugging provided by an embodiment of the present application. Inside the module, a TDR register named scandump_mode is implemented. When scandump_mode = 0, the circuit maintains its original state, and the input and output of the scan chain, and the SE and CLK pins of the functional register are controlled by the SCAN test logic. When scandump_mode = 1, all the scan chains are strung into a complete chain, the se pin of the functional register is controlled by scandump_se, and the clk pin is controlled by scandump_clk. When scandump_se = 1 and there is a clock pulse on scandump_clk, the value of the functional register can be shifted out through the scandump_so port.

[0034] In the circuit implementation, the switching of the mode in the finite state machine is achieved through a multiplexer (mux). In Figure 3In [the system], when the system is in the normal working mode, the value of the first test data register is the second value, that is, scandump_mode = 0. At this time, the signals received by the control terminals of each mux in the system are also all 0, so that each component / part is controlled by the scan test logic. When the system is in the Scandump mode, the value of the first test data register is the first value, that is, scandump_mode = 1. At this time, the signals received by the control terminals of each mux in the system are also all 1, so that each scan chain is connected in series into a complete chain, and the first end of the complete chain receives scandump_in, and the second end of the complete chain outputs scandump_out. The se pins of each functional register on the complete chain receive the scandump_se signal, and the clk pins receive the scandump_clk signal. In some embodiments of the present application, the scandump_clk signal can be transmitted to the clk pins of each functional register after being processed by OCC. Among them, OCC is an on-chip clock controller (OCC), which is a module used to manage the internal clock resources of the chip. It receives inputs such as external clock input, reset signal, configuration control signal, etc., and outputs multiple on-chip clock signals after frequency division, gating or selection, so as to achieve flexible clock distribution, power consumption optimization and multi-clock domain management.

[0035] In some embodiments of the present application, the module-level system further includes a sub-module system, which is arranged between the second end of the complete chain and the output port of the system. The sub-module system receives the clock signal and the enable signal of the module-level system.

[0036] In Figure 3 [the system], the module-level system is block, and the sub-module system is sub_block. The internal circuit implementation of the sub-module system is similar to that of the module-level system, and the operation can refer to the above embodiments, which will not be elaborated in the present application. It should be noted that when there is a sub-module system in the module-level system, the scandump_se signal and the scandump_clk signal received by the module-level system will also be input into the sub-module system. Moreover, the sub-module system is arranged between the second end of the complete chain of the module-level system and the output end of the module-level system, and it receives the data from the second end of the complete chain.

[0037] In some embodiments of the present application, the system further includes a data marking module, which is disposed between the second end of the entire chain and the output port. The data marking module includes a plurality of registers connected in series in sequence. The plurality of registers are initialized according to the values of a preset array during power-on reset; when in the normal function mode, the plurality of registers maintain their initial values, and when in the Scandump mode, the values of the plurality of registers are shifted out from the output port to mark the data from the second end of the entire chain.

[0038] Please refer to Figure 4 , which shows a structural example diagram of a data marking module provided by an embodiment of the present application. The data marking module ( Figure 3 and Figure 5 denoted as scandump_id in

[0039] is disposed between the second end of the entire chain and the output port of the system. If the module-level system further includes a sub-module system, the data marking module is further disposed between the second end of the entire chain and the sub-module system; if the top-level system further includes a module-level system, the data marking module is further disposed between the second end of the entire chain and the module-level system.

[0040] In some actual application scenarios, the top-level system of an integrated circuit includes several module-level systems, and each module-level system includes several sub-module systems; there are several scan chains in each system. After entering the Scandump mode, the scan chains are concatenated into a complete chain, and the data of each complete chain on the entire integrated circuit will be shifted out, which will generate a large amount of data. For debuggers, how to efficiently locate the data they need is crucial. For example, if a debugger wants to obtain the data of the complete chain in the control unit of the processor module, he usually needs to spend a lot of time to determine the data in this target sub-module system among all the data, and the efficiency is very low. After introducing the data marking module, the complete chains in each system can be marked according to a preset array; in this way, the debugger can quickly find the data of the complete chain corresponding to the target system according to the value of the preset array of the target system, improving the work efficiency. Moreover, regardless of whether the top-level system includes module-level systems or the module-level systems include sub-module systems, the data marking module is directly connected to the second end of the complete chain, so that the value shifted out from the data marking module and the value shifted out from its corresponding complete chain are adjacent, ensuring the accuracy of the data. By setting different preset arrays for different systems, these systems can be effectively distinguished; that is to say, there is a unique mapping relationship between the preset array and its corresponding complete chain, which enables the debugger to determine the complete chain corresponding to it based on the value of the preset array. The size of the preset array can be determined according to the total number of various systems included in the integrated circuit, and this application does not limit this.

[0041] Please continue to refer to Figure 4 , in some embodiments of the present application, the preset array includes a first element, and several sequentially concatenated registers include a first register. The first register has a serial input (si) port, a data input (d) port, a scan enable (se) port, a set control (set) port, a clear control (clr) port, an output (q) port, and a clock port. The d port is connected to the q port. The se port receives the enable signal in the system, the clock pin receives the clock signal in the system, the si port receives the data at the second end of the complete chain or is connected to the q port of the previous-stage register. The q port is connected to the si port of the next-stage register or serves as the output end of the data marking module to shift out the data from the output port of the system. The set port is connected to the output end of the first AND gate, the clr port is connected to the output end of the second AND gate. The first input end of the first AND gate and the first input end of the second AND gate both receive the reset signal from the system. The second input end of the first AND gate receives the first element, and the second input end of the second AND gate receives the inverted value of the first element, so that the signals received by the set port and the clr port are different.

[0042] In Figure 4Among them, the elements of the preset array include id[0], id[1], id[2]... id[n - 1]. The value received by the se port of the register controls the selection of the input port of the register between the si port and the d port. When the system is in the normal working mode, the input port is the d port. At this time, since the d port is connected to the q port, the value in the register can be kept unchanged from the initial value. When the system is in the Scandump mode, the input port is the si port; at this time, the values in the register are shifted out in sequence. And, since the registers in the data marking module are connected in series with each other, they also appear in a chain form and are connected to the second end of the whole chain, so the registers in the data marking module can be regarded as an extension of the whole chain.

[0043] The values received by the set port and the clr port are complementary to each other so that these two ports can work properly. When power-on reset occurs, the value of the rst signal is 1. For any register, it can be seen from Figure 4 that the input terminals of the two AND logic gates it is connected to are different, that is, one AND logic gate receives the rst signal and the value of the first element, and the other AND logic gate receives the rst signal and the inverted value of the first element. With such a setting, the signals received by the set port and the clr port can be made different.

[0044] In some embodiments of the present application, the number of several sequentially connected registers is the same as the number of elements of the preset array. That is, each register in the data marking module stores one element of the preset array. Designing the number of registers as needed can effectively reduce the circuit scale, power consumption and cost, and is suitable for systems with limited resources and simple access modes. In some embodiments of the present application, the number of registers in the data marking module is greater than the number of elements in the preset array, that is, a redundant design is adopted. The redundant design of registers helps to implement fault tolerance mechanisms such as parity check, support the scandump debugging function, simplify the decoding logic, and improve the expandability and versatility of the module. During the debugging or testing phase, especially when using debugging techniques such as scandump, the redundant registers can be used to save multiple historical states of the data to support "freezing" or exporting the register content at a specific moment for fault backtracking and problem location. Since scandump usually samples and exports the internal state during the chip operation, the additional registers can provide non-intrusive data snapshot storage, avoiding interference with the normal logic flow due to debugging behavior, while improving the integrity and timing reducibility of the debugging information. This redundant structure is especially suitable for high-reliability and high-complexity chip debugging scenarios.

[0045] In some embodiments of the present application, when the system is the top-level system in an integrated circuit, the finite state machine includes a first test data register and a second test data register, and the first test data register and the second test data register are adapted to store a first value or a second value; when the values of both the first test data register and the second test data register are the second value, the operating state is the normal function mode; when the value of the first test data register or the value of the second test data register is the first value, the operating state is the Scandump mode; wherein, the values of the first test data register and the second test data register are not both the first value at the same time.

[0046] The top-level system further includes a module-level system, which is arranged between the second end of the entire chain and the output port of the system, and the module-level system receives the clock signal and the enable signal of the top-level system.

[0047] The top-level system includes a test access port (TAP), the TAP is connected to the entire chain, and the signals on the TAP are adapted to control the shift operation of the entire chain; when the value of the first test data register is the first value and the value of the second test data register is the second value, and when both the selection signal and the enable signal on the TAP are the first value, the clock gating in the top-level system is turned on, and the clock signal of the test clock (TCK) corresponding to the clock gating is input to the entire chain through the clock gating to enable the top-level system to start the shift operation; when the value of the first test data register is the second value and the value of the second test data register is the first value, the scan enable ports of each register are controlled by the test mode select (TMS) pin, and the value of the test mode select on the TAP is fixed to the second value to keep the state of the TAP orderly when the entire chain is shifting; the first end of the entire chain originates from the test data input (TDI) pin, the second end of the entire chain drives the test data output (TDO) pin, and the output enable of the TDO pin is driven to the first value; the clock gating at the stage after TCK is turned on to enable TCK to drive the clock signal of the entire chain; in this case, the automatic test vector generation tool located outside the top-level system is adapted to penetrate the entire chain and extract the data of each register on the entire chain.

[0048] Similar to the module-level system described in the above embodiments, the top-level system may also include a data marking module, that is Figure 5 the scandump_id in, which can be used to mark the chain in the top-level system, so as to facilitate the debugger to quickly find the data of the top-level system among a large amount of register data.

[0049] Please refer to Figure 5 , which shows a structural example diagram of another system (top-level) for integrated circuit debugging provided by the embodiments of the present application. Figure 5 The top-level system shown is the same as Figure 3The module-level systems shown have a certain similarity in overall structure. However, the top-level system also includes a TAP, so a circuit structure is designed additionally for the top-level system. As Figure 5 shown, two TDR registers (i.e., the first test data register and the second test data register) are implemented inside the top-level system, named scandump_tdr_mode and scandump_tapio_mode respectively. scandump_tdr_mode and scandump_tapio_mode generate the scandump_mode signal through an OR logic gate. When both scandump_tdr_mode and scandump_tapio_mode are 0, that is, when scandump_mode is 0, the working state of the system is the normal function mode. When any one of scandump_tdr_mode and scandump_tapio_mode is 1, that is, when scandump_mode is 1, the working state of the system is the Scandump mode. Moreover, the values of scandump_tdr_mode and scandump_tapio_mode are not both 1 at the same time to avoid system logic confusion.

[0050] The TAP additionally implements an idle tdr chain interface, as shown in Figure 5 the tdr2_sel, tdr2_shift_en, and tdr2_shift_out signals on the TAP in it, and connects the scandump chain to the TAP as the TDR chain.

[0051] When scandump_tdr_mode = 0 and scandump_tapio_mode = 0, the circuit maintains its original state. The input and output of the scan chain, and the SE and CLK pins of the functional register are controlled by the SCAN test logic, and the circuit can work normally in the function or SCAN mode.

[0052] When scandump_tdr_mode = 1 and scandump_tapio_mode = 0, scandump_mode = 1. All the scan chains at the top layer are strung together into a single scandump chain, similar to the implementation of module-level scandump. The scandump_id module and all module-level systems (blocks) are also strung onto the scandump chain. The SE pins of the registers on the chip's scandump chain will enter the shift mode only when tdr2_sel = 1 and tdr2_shift_en = 1. Similarly, for the clock pins of these registers, only when tdr2_sel = 1 and tdr2_shift_en = 1, the clock gater at the stage after TCK will be opened to allow the TCK signal to pass through. This clock gater can prevent the clock pulses on TCK from corrupting the values in the functional registers when configuring the TAP before the scandump shift operation. This mode is used to shift out the chip register values during actual scandump debugging.

[0053] When scandump_tdr_mode = 0 and scandump_tapio_mode = 1, scandump_mode = 1. The SE of the register is controlled by the TMS pin, and at the same time, the tms pin of the TAP is fixed to 0, which can prevent the state of the TAP from being messed up when the scandump chain is shifted. The head of the scandump chain comes from the TDI pin, the tail drives the TDO pin, and the OE (output enable) of the TDO pin is driven to 1. The ICG after TCK is also opened, and the clock of the scandump chain is driven by the TCK pin. In the current state, the scandump chain can be controlled through TAP IO (TCK, TMS, TDI, TDO), which is convenient for the ATPG tool to penetrate the scandump chain and report the various registers on the scandump chain, facilitating subsequent debuggers to identify. This mode is used to extract the data of each register on the chain for the ATPG tool.

[0054] In this way, the scandump chain is connected to the TAP as a TDR, which is convenient for generating scandump vectors during debugging; and all the registers on the scandump chain can be directly accessed through TAP IO, facilitating the ATPG tool to extract the data of all the registers on the scandump chain.

[0055] In the above embodiments, the descriptions of the respective embodiments each have their own focuses. For parts not described or recorded in detail in a certain embodiment, reference may be made to the relevant descriptions of other embodiments. In addition, the above embodiments can be freely combined as needed.

Claims

1. A system for integrated circuit debugging, characterized in that, Comprising: A finite state machine configured to determine an operating state of the system based on values of at least one test data register, the operating state including a normal function mode and a Scandump mode; A plurality of scan chains that can be cascaded, each scan chain including a plurality of function registers connected in series in sequence. When the operating state is the normal function mode, each of the plurality of scan chains that can be cascaded is controlled by a corresponding scan test logic respectively; when the operating state is the Scandump mode, the plurality of scan chains that can be cascaded are cascaded into an integral chain. A first end of the integral chain is adapted to obtain data through an input port of the system. Scan enable pins of all function registers located on the integral chain are controlled by an enable signal in the system, and clock pins of the function registers are controlled by a clock signal in the system. When the enable signal indicates that enabling is activated and there is a clock pulse in the clock signal, data stored in each of the function registers is shifted out from an output port of the system through a second end of the integral chain; A data marking module disposed between the second end of the integral chain and the output port, the data marking module including a plurality of registers connected in series in sequence, the plurality of registers being initialized according to values of a preset array during power-on reset; when in the normal function mode, the plurality of registers maintain their initial values, and when in the Scandump mode, values of the plurality of registers are shifted out from the output port to mark data from the second end of the integral chain; Wherein, the preset array includes a first element, the plurality of registers connected in series in sequence include a first register, the first register having a serial input si port, a data input d port, a scan enable se port, a set control set port, a clear control clr port, an output q port, and a clock port. The d port is connected to the q port, the se port receives the enable signal in the system, the clock pin receives the clock signal in the system, the si port receives data from the second end of the integral chain or is connected to the q port of the previous-stage register, the q port is connected to the si port of the next-stage register or serves as an output end of the data marking module to shift out data from the output port of the system. The set port is connected to an output end of a first AND gate, the clr port is connected to an output end of a second AND gate. A first input end of the first AND gate and a first input end of the second AND gate both receive a reset signal from the system, a second input end of the first AND gate receives the first element, and a second input end of the second AND gate receives an inverted value of the first element, so that signals received by the set port and the clr port are different.

2. The system for integrated circuit debugging according to claim 1, wherein The preset array has a unique mapping relationship with the integral chain, so that a debugger can determine the corresponding integral chain based on values of the preset array.

3. The system for integrated circuit debugging according to claim 1, wherein The number of the plurality of registers connected in series in sequence is greater than or equal to the number of elements of the preset array.

4. The system for integrated circuit debugging according to claim 1, characterized in that, When the system is a module-level system in an integrated circuit, the finite state machine includes a first test data register, and the first test data register is adapted to store a first value or a second value; When the value of the first test data register is the first value, the operating state is the Scandump mode; When the value of the first test data register is the second value, the operating state is the normal function mode.

5. The system for integrated circuit debugging according to claim 4, characterized in that, The module-level system further includes a sub-module system, the sub-module system is disposed between the second end of the entire chain and the output port of the system, and the sub-module system receives the clock signal and the enable signal of the module-level system.

6. The system for integrated circuit debugging according to claim 1, wherein When the system is a top-level system in an integrated circuit, the finite state machine includes a first test data register and a second test data register, and the first test data register and the second test data register are adapted to store a first value or a second value; When the values of the first test data register and the second test data register are both the second value, the operating state is the normal function mode; When the value of the first test data register or the value of the second test data register is the first value, the operating state is the Scandump mode; Wherein, the values of the first test data register and the second test data register are not both the first value at the same time.

7. The system for integrated circuit debugging according to claim 6, wherein, The top-level system further includes a module-level system, the module-level system is disposed between the second end of the entire chain and the output port of the system, and the module-level system receives the clock signal and the enable signal of the top-level system.

8. The system for integrated circuit debugging according to claim 6, wherein, The top-level system includes a test access port TAP, the TAP is connected to the entire chain, and the signals on the TAP are adapted to control the shift operation of the entire chain; When the value of the first test data register is the first value and the value of the second test data register is the second value, and when the selection signal and the enable signal on the TAP are both the first value, the clock gating in the top-level system is turned on, and the clock signal of the test clock TCK corresponding to the clock gating is input to the entire chain through the clock gating, so that the top-level system starts a shift operation; When the value of the first test data register is the second value and the value of the second test data register is the first value, the scan enable ports of each register are controlled by the test mode selection TMS pin, and the value of the test mode selection at the TAP is fixed to the second value, so that the state of the TAP remains orderly when the entire chain is shifted; the first end of the entire chain originates from the test data input TDI pin, the second end of the entire chain drives the test data output TDO pin, and the output enable of the TDO pin is driven to the first value; the clock gating at the stage after the TCK is turned on, so that the TCK drives the clock signal of the entire chain; in this case, the automatic test vector generation tool located outside the top-level system is adapted to penetrate the entire chain and extract the data of each register on the entire chain.

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