PCIe link burst interrupt processing method of NVMe controller

Abstract

The invention provides a PCIe link burst interrupt processing method of an NVMe controller, and a data monitoring processing unit is arranged between the NVMe controller and a PCIe interface and is used for monitoring a PCIe link between the NVMe controller and the PCIe interface. When the PCIe link is disconnected, the data monitoring processing unit generates corresponding compensation data for an uncompleted equipment host reading request, and returns the compensation data to the NVMe controller; when the data is written, a receiving signal of the PCIe interface is pulled up, data transmission to the PCIe interface is stopped, and all data sent to the equipment by the host is discarded by the data monitoring processing unit. According to the invention, a mode that hardware carries out data discarding and data compensation on the PCIe interface is adopted, and meanwhile, after all data are transmitted, a mode of soft resetting of the NVMe controller is adopted for processing, so that the situation that Reset occurs during transmission due to the fact that a hardware Reset NVMe mode is directly used, data transmission between the NVMe controller and the outside cannot be completed, and the data transmission efficiency is improved is avoided. And normal starting cannot be carried out after restarting.

Description

Technical Field

[0001] The present invention relates to the field of solid-state hard disk storage, and more specifically to a method for processing a PCIe link sudden interruption of an NVMe controller. Background Art

[0002] When the existing NVMe controller encounters a Linkdown error in the PCLe link and cannot complete data transmission, the hardware reset NVMe method is directly used to restore the NVMe controller. This method has a certain probability of encountering a reset (Reset) of the NVMe controller during data transmission, which causes the NVMe controller to be unable to complete data transmission with the outside. When the error processing is completed and the NVMe controller needs to be started again, it cannot start normally.

[0003] Another approach is to terminate data transmission inside the modules in the NVMe controller that transmit data to the host. However, this approach will cause most modules in the NVMe controller to be unable to directly enter the next data transmission after data transmission is interrupted, and complex software processing is required. The process is complicated and prone to subsequent problems, resulting in the inability to process data normally after the PCIe link is restored. Summary of the invention

[0004] The object of the present invention is to provide a NVMe controller PCIe Lindown processing method that can be normally started again while ensuring data transmission integrity.

[0005] According to one aspect of the present invention, a method for processing a PCIe link burst interruption of an NVMe controller is provided.

[0006] A data monitoring processing unit is provided between the NVMe controller and the PCIe interface, for monitoring a PCIe link between the NVMe controller and the PCIe interface;

[0007] When the PCIe link is interrupted suddenly:

[0008] For the unfinished device read host request data, the data monitoring processing unit generates corresponding compensation data and returns the compensation data to the NVMe controller;

[0009] For the device response host read data that has been sent to the NVMe controller before the sudden interruption and has not completed the response, discard it;

[0010] When the device writes host data, the data monitoring processing unit pulls up the receiving signal of the PCIe interface and stops transmitting data to the PCIe interface;

[0011] The monitoring processing unit discards all data sent from the host to the device.

[0012] In some embodiments, the data monitoring processing unit returns the data to the NVMe controller by taking over the data interface of the original host returning the read request.

[0013] In some implementations, when the PCIe link transmits data normally, the data monitoring processing unit adopts a transparent transmission method.

[0014] In some implementations, the transparent transmission method is to record the transmitted data information until the transmission is completed.

[0015] In some embodiments, after the data monitoring processing unit completes processing, the NVMe controller performs a soft restart.

[0016] In some embodiments, the soft restart is that the CPU of the host modifies all relevant registers of the NVMe controller to initial values.

[0017] In some implementations, the compensation data is all-0 data having the same size as the read data request.

[0018] In some embodiments, the data flow between the NVMe controller and the PCIe interface includes: a data flow of the device reading a host request, a data flow of the host responding to the device reading data, a data flow of the device writing to the host, a data flow of the host reading a device request, a data flow of the device responding to the host reading data, and a data flow of the host writing to the device.

[0019] The beneficial effect is as follows: the present invention adopts the method of hardware to discard data and compensate data in the PCIe interface, and after all data are transmitted by means of data discard and data compensation, that is, the data transmission inside the NVMe controller is completed, a soft reset of the NVMe controller is adopted to handle it, thereby avoiding the direct use of hardware to reset the NVMe controller, which causes a reset during transmission, and further causes the NVMe controller to be unable to complete the data transmission with the external device, and unable to start normally again. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 A schematic diagram of a method for processing a PCIe link sudden interruption of an NVMe controller without disconnection according to an embodiment of the present invention;

[0021] Figure 2 A schematic diagram of a PCIe link sudden interrupt processing method of an NVMe controller according to an embodiment of the present invention. DETAILED DESCRIPTION

[0022] The present invention will be further described below in conjunction with the accompanying drawings.

[0023] Figure 1-Figure 2 The present invention schematically shows a method for processing a PCIe link sudden interruption (Linkdown) of an NVMe controller 1. Figure 1 and Figure 2 As shown, a data monitoring processing unit 2 is added between the NVMe controller 1 and the PCIe interface 3. The data monitoring processing unit 2 monitors the data flow between the NVMe controller 1 and the PCIe interface 3, and monitors whether the PCIe link is disconnected.

[0024] When the PCIe link is not disconnected (Linkdown), the data monitoring processing unit 2 adopts a transparent transmission method to Figure 1 The six data streams in the unit pass through the unit, while continuously recording the transmitted data information until the data transmission is completed. The six data streams between the NVMe controller 1 and the PCIe interface 3 include the data stream of the device reading the host request, the data stream of the host responding to the device reading data, the data stream of the device writing to the host, the data stream of the host reading the device request, the data stream of the device responding to the host reading request, and the host writing the device data stream.

[0025] When the PCIe link is disconnected (Linkdown), the data monitoring processing unit 2 takes over all data streams and processes the data transmission according to the recorded data transmission information to ensure the integrity of all data transmission. After all data is processed, the NVMe controller 1 performs a soft reset (Reset) to complete the entire error handling process.

[0026] The specific processing process is as follows:

[0027] like Figure 1 As shown, during the normal data transmission phase, when the PCIe link is not disconnected, the data monitoring processing unit 2 records the output transmission information but does not interfere with the data transmission.

[0028] like Figure 2 As shown, when the PCIe link is disconnected (Linkdown), data transmission cannot be completed. The data monitoring processing unit 2 senses the high disconnect signal, cuts off the data transmission between the NVMe controller 1 and the PCIe interface 3, and takes over all data transmission paths.

[0029] The data monitoring processing unit 2 performs corresponding processing on the data transmission.

[0030] For the unfinished device read host request data, the corresponding compensation data is returned;

[0031] Discard the data written by the device to the host and the data responded to the host's read request;

[0032] All data sent from the host to the device will be discarded.

[0033] Specifically,

[0034] The data monitoring processing unit 2 generates corresponding compensation data according to the monitored incomplete device read host request data. For example, if it monitors that a 512B read data request is not completed, the data monitoring processing unit 2 automatically generates a 512B full 0 data, and returns the compensation data to the initiator NVMe controller 1 of the read request through the data interface that takes over the original host to return the read request. In this way, the initiator NVMe controller 1 receives a complete data response to prevent the NVMe controller 1 from getting stuck.

[0035] For the device writing host data, the data monitoring processing unit 2 takes over the PCIe interface 3 of the receiver of the write data, the data receiving signal is always pulled high, and the data stops being transmitted to the PCIe interface 3. By pulling the receiving signal high, the data monitoring processing unit 2 can simulate or ensure that the PCIe interface 3 of the receiver is in a state that can accept the write data request from the NVMe controller 1, thereby ensuring that all write data requests issued by the NVMe controller 1 can be completed, and further ensuring that the NVMe controller 1 of the initiator of the write data will not be stuck.

[0036] Regarding the device responding to the host reading data, since there may be some host read device requests that have been sent to the device before the sudden interruption (linkdown) occurs, and the device's return action of responding to the host read request is not completed before the sudden interruption (linkdown) occurs, this part of the data is discarded after the sudden interruption (linkdown) occurs to ensure that the device's return to the host read request will not be stuck, thereby ensuring that the NVMe controller 1 is in a normal state.

[0037] The host read device request data and the host write device request data will be discarded after the sudden interruption (linkdown) to ensure that the host access after the sudden interruption (linkdown) will not reach the NVMe controller 1, reducing the amount of data that the NVMe controller 1 needs to process, and ensuring that the NVMe controller 1 can quickly process the received instructions. The host response device read request data will also be discarded in the data monitoring processing unit 2. By using the compensation data provided by the data monitoring processing unit 2, it can be ensured that all the data required for the device read request can be collected, ensuring the normal operation of the NVMe controller 1.

[0038] After the above steps, the data transmission between NVMe controller 1 and PCIe interface 3 can be completed within NVMe controller 1, ensuring the integrity of data transmission. NVMe controller 1 waits for all data transmissions to be completed. Then reset the entire NVMe controller 1 by means of soft reset. The specific implementation is that the host CPU modifies all the relevant registers of NVMe controller 1 to the initial values, and the processing of PCIe link sudden interruption (Linkdown) is completed.

[0039] The above are only some embodiments of the present invention, which are only used to illustrate the technical solutions of the present invention, but not to limit them. For those skilled in the art, without departing from the creative concept of the present invention, the technical solutions recorded in the above embodiments are modified, or some or all of the technical features are replaced by equivalents, which all belong to the protection scope of the present invention.

Claims

1. A PCIe link burst interrupt processing method for an NVMe controller, characterized in that: A data monitoring processing unit is provided between the NVMe controller and the PCIe interface, for monitoring a PCIe link between the NVMe controller and the PCIe interface; When the PCIe link is interrupted suddenly: For the unfinished device read host request data, the data monitoring processing unit generates corresponding compensation data and returns the compensation data to the NVMe controller; For the device response host read data that has been sent to the NVMe controller before the sudden interruption and has not completed the response, discard it; When the device writes host data, the data monitoring processing unit pulls up the receiving signal of the PCIe interface and stops transmitting data to the PCIe interface; The monitoring processing unit discards all data sent from the host to the device.

2. The PCIe link burst interrupt processing method of the NVMe controller according to claim 1, wherein: The data monitoring processing unit returns the data to the NVMe controller by taking over the data interface of the original host return read request.

3. The PCIe link burst interrupt processing method of the NVMe controller according to claim 1, wherein: When the PCIe link transmits data normally, the data monitoring processing unit adopts a transparent transmission method.

4. The PCIe link burst interrupt processing method of the NVMe controller according to claim 3, characterized in that: The transparent transmission method is to record the transmitted data information until the transmission is completed.

5. The PCIe link burst interrupt processing method of the NVMe controller according to claim 1, characterized in that: After the data monitoring processing unit completes the processing, the NVMe controller performs a soft restart.

6. The PCIe link burst interrupt processing method of the NVMe controller according to claim 5, characterized in that: The soft restart is that the CPU of the host modifies all relevant registers of the NVMe controller to initial values.

7. The PCIe link burst interrupt processing method of the NVMe controller according to claim 1, characterized in that: The compensation data is all-0 data having the same size as the read data request.

8. The NVMe controller PCIe lindown processing method according to claim 1, characterized in that: The data flow between the NVMe controller and the PCIe interface includes: a data flow of the device reading a host request, a data flow of the host responding to the device reading data, a data flow of the device writing to the host, a data flow of the host reading a device request, a data flow of the device responding to the host reading data, and a data flow of the host writing to the device.

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