Method and device for supporting chip interconnection extensible low-speed peripheral interruption

Abstract

The invention discloses a method and a device for supporting chip interconnection extensible low-speed peripheral interruption. The method comprises the following steps: extending an address space of a low-speed peripheral interruption register; the number of supported low-speed peripheral interrupts is configured through a low-speed peripheral interrupt register, and the low-speed peripheral interrupts managed by each chip are set; chip connection is configured through a low-speed peripheral interrupt register, and routing configuration information of the chip is generated; when an interrupt controller in the chip detects an interrupt request, the interrupt controller processes the interrupt request after detecting the interrupt request and distributes the interrupt request to a corresponding processor core according to routing configuration information; and the processor core calls the interrupt processing program for processing and returns interrupt confirmation. The invention aims to support the arbitrary configuration of the number of low-speed peripheral interrupts so as to meet the processing requirements of the low-speed peripheral interrupts of different system architectures, and has the advantages of low hardware implementation complexity, small area overhead and high cost performance.

Description

Technical Field

[0001] The present invention relates to the technical field of multi-chip integration based on multi-chip components, and in particular to a method and device for supporting chip interconnection and scalable slow peripheral interruption. Background Art

[0002] Over the past 50 years, the semiconductor industry has been advancing along the pace of Moore's Law. The density of transistors has continued to increase, gradually reaching the tens of billions level, bringing great challenges to density and cost. As Moore's Law approaches its limit, traditional monolithic semiconductor devices can no longer meet the performance or functional requirements of certain computing-intensive and workload-heavy applications. Multi-chip systems are becoming a solution to go beyond Moore's Law and solve complex systemic challenges, expanding system functions faster and reducing risks in an economical and efficient way, achieving higher throughput with lower power consumption, and helping to meet the rapidly growing demand for processing power. At the same time, the multi-chip module technology that came into being is a new generation of microelectronic packaging and assembly technology developed on the basis of printed circuit boards and surface mount technology to adapt to the development direction of short, small, light, thin, high-speed, high-performance, high-reliability, and low-cost modern electronic systems. It is a powerful means to achieve system integration. With the development of multi-chip systems, the number of mounted external devices is also increasing. Traditional interrupt controllers do not support the adjustment of slow peripheral interrupts. Changing the number of slow peripheral interrupts requires changing the hardware logic, which consumes a lot of time, manpower and resources. How to expand slow peripheral interrupts while controlling the chip area size and time and manpower costs, and realize the processing of slow peripheral interrupts between chips in the multi-chip system has become a difficult problem. Summary of the invention

[0003] Technical problem to be solved by the present invention: In view of the above-mentioned problems in the prior art, a method and device for supporting chip interconnection and expandable slow peripheral interrupts are provided. The present invention aims to support arbitrary configuration of the number of slow peripheral interrupts to meet the slow peripheral interrupt processing requirements of different system architectures, and has the advantages of low hardware implementation complexity, small area overhead, and high cost performance.

[0004] In order to solve the above technical problems, the technical solution adopted by the present invention is: A method for supporting chip interconnection and scalable slow peripheral interruption, comprising the following steps: S1, expands the address space of slow peripheral interrupt registers; S2, configure the number of slow peripheral interrupts supported through the slow peripheral interrupt register, and set the slow peripheral interrupts managed by each chip; S3, configuring the chip connection through the slow peripheral interrupt register and generating the routing configuration information of the chip; S4, when the interrupt controller in the chip detects an interrupt request, the interrupt controller processes the interrupt request and dispatches it to the corresponding processor core according to the routing configuration information; S5, the processor core calls the interrupt handler to process and returns the interrupt confirmation.

[0005] Optionally, when the address space of the slow peripheral interrupt register is expanded in step S1, the expanded slow peripheral interrupt register defines a group of registers that specify the chip connection relationship, and the group of registers includes: chip internal registers, each chip Chip corresponds to a chip internal register, and the register is used to describe the chip number used to identify the cross-chip routing during cross-chip transmission, the starting value of the slow peripheral interrupt group managed by the chip Chip, the number of slow peripheral interrupt groups managed by the chip Chip, and the power-on status of the chip Chip; chip management register, a multi-chip system has only one chip management register, and the register is used to describe the chip Chip responsible for managing consistency and the connection completion status of each chip Chip; chip status register, a multi-chip system has only one chip status register, which is used to describe the consistency status of the routing table.

[0006] Optionally, when the address space of the slow peripheral interrupt register is expanded in step S1, the expanded slow peripheral interrupt register defines a 32-bit slow peripheral interrupt quantity register, and step S2 includes: S2.1, configure the number of slow peripheral interrupts in the 32-bit slow peripheral interrupt number register; S2.2, configure the total number of slow peripheral interrupt groups according to the number of slow peripheral interrupts; S2.3, determining the bit width of the slow peripheral interrupt signal according to the total number of slow peripheral interrupt groups, and the bit width of the slow peripheral interrupt signal is less than a preset threshold value num, num = (num 1 ×32) / num 2 , where num 1 The total number of slow peripheral interrupt groups, num 2 is the number of chips; if the multi-chip system formed by interconnecting the chips is a homogeneous multi-chip system, the bit width of the slow peripheral interrupt signal of each chip is the same; otherwise, the bit width of the slow peripheral interrupt signal of some or all chips is different; S2.4, setting the slow peripheral interrupt managed by each chip Chip, including: assigning an interrupt number to the slow peripheral interrupt, the interrupt controller manages the slow peripheral interrupt in groups, each slow peripheral interrupt group contains 32 slow peripheral interrupts, and defines the starting value of the slow peripheral interrupt group and the number of slow peripheral interrupt groups for each chip Chip. The slow peripheral interrupt is allocated to a specific chip Chip in groups, indicating the interval of the slow peripheral interrupt number managed by the chip Chip, and completing the correspondence between the interrupt number and the slow peripheral interrupt line.

[0007] Optionally, step S3 includes: S3.1, configure the chip management register, designate a chip to be responsible for managing the consistency of the routing table, and the routing table is stored inside each chip as a carrier of routing configuration information; S3.2, configure the chip internal registers of the chip responsible for managing consistency, including specifying the chip number used to identify the cross-chip routing when the chip is transmitted across chips, the starting value of the slow peripheral interrupt group, the number of slow peripheral interrupt groups, and set the chip to the power-on state; S3.3, the interrupt controller saves the configuration information of the slow peripheral interrupt group to the routing table of the chip responsible for managing consistency, and updates the routing table status to a consistent state, which can be confirmed by reading the chip status register; S3.4, for the chip responsible for managing consistency, the chip needs to be connected, and the internal registers of the chip that needs to be connected are configured, including specifying the chip number used to identify the cross-chip routing when the chip is transmitted across chips, the starting value of the slow peripheral interrupt group, and the number of slow peripheral interrupt groups, and setting the chip to the power-on state. At this time, the routing table is in an unconnected state; S3.5, the interrupt controller saves the interrupt information of the slow peripheral that needs to be connected to the chip that has not yet been connected in the routing table responsible for managing the consistency chip. At this time, the routing table is in an updating state; S3.6, the chip responsible for managing consistency sends the routing table information to the chip that needs to be connected. The chip that needs to be connected creates a copy of the routing table and updates the routing table to be in a consistent state and indicates it in the chip status register. At this time, the connection between the two chips is completed and indicated in the chip management register. S3.7, repeat steps S3.4-S3.6 until all chips except the chip responsible for managing consistency are connected to the chip responsible for managing consistency.

[0008] Optionally, the routing configuration information in step S4 includes: A slow peripheral interrupt group, used to record the slow peripheral interrupt group information described in the slow peripheral interrupt, and the slow peripheral interrupt group information is used to set the security and non-security attributes of the slow peripheral interrupt; Slow peripheral interrupt enable, used to indicate the enable status of slow peripheral interrupt; Slow peripheral interrupt routing, used to indicate which processor core the slow peripheral interrupt is sent to for processing; Slow peripheral interrupt priority, used to indicate the priority level of slow peripheral interrupt processing; Slow peripheral interrupt trigger mode, used to indicate whether the slow peripheral interrupt is level triggered or edge triggered; The routing configuration information is stored in a random access memory inside the interrupt controller of the chip Chip by writing the slow peripheral interrupt register. The random access memory is also used to store the state information of the slow peripheral interrupt processing.

[0009] Optionally, in step S4, when the interrupt controller in the chip detects an interrupt request, the interrupt request is initiated in two slow peripheral interrupt initiation modes: direct connection and software writing. The direct connection initiation mode is that the slow peripheral directly connected to the chip initiates an interrupt request, and the software writing mode is to initiate an interrupt request from any chip that has been connected, and the interrupt controller of the chip obtains the configuration information of the slow peripheral interrupt and sends it to the corresponding chip for processing; and the interrupt controller processes the interrupt request of the direct connection initiation mode including: S101, obtaining configuration information of a slow peripheral interrupt group of the chip Chip, and obtaining the interval of slow peripheral interrupt numbers managed by the chip Chip; S102, initiating a direct slow peripheral interrupt and pulling the corresponding slow peripheral interrupt line high; S103, adding the starting value of the slow peripheral interrupt group managed by the chip Chip to the number of the corresponding slow peripheral interrupt line as the interrupt number of the slow peripheral interrupt directly connected to the chip Chip; S104, if the interrupt number of the slow peripheral interrupt is within the interval of the slow peripheral interrupt numbers managed by the chip, the interrupt is set to a suspended state, the random access memory is read to obtain the routing configuration information of the slow peripheral interrupt, and the next step is jumped; otherwise, an error is reported, the process ends and exits; S105, judging whether the slow peripheral interrupt priority of the slow peripheral interrupt has the highest priority and whether the slow peripheral interrupt enable is enabled according to the routing configuration information, and when the slow peripheral interrupt priority of the slow peripheral interrupt has the highest priority and the slow peripheral interrupt enable is enabled, sending the interrupt to the designated processor core according to the slow peripheral interrupt route, and marking the state information of the slow peripheral interrupt as a slow peripheral interrupt pending state in the random access memory; After step S5, the interrupt controller also includes marking the state information of the slow peripheral interrupt as the slow peripheral interrupt active state in the random access memory after receiving the interrupt confirmation, and regularly clearing the slow peripheral interrupt in the slow peripheral interrupt active state.

[0010] Optionally, the method further includes adjusting the correspondence between consecutive slow peripheral interrupt numbers and slow peripheral interrupt lines by configuring the internal registers of the chip in units of slow peripheral interrupt groups to achieve slow peripheral interrupt group migration: initiating a slow peripheral interrupt group migration request from any connected chip Chip, requesting the configuration to adjust the internal registers of the slow peripheral interrupt chip Chip, and changing the starting value and number of slow peripheral interrupt groups managed by the chip Chip; updating the routing table and the routing table copy: if the slow peripheral interrupt group migration request is sent to the chip Chip responsible for consistency management, The chip responsible for consistency management updates the routing table and then sends a request to update the routing table copies of the remaining chips; if the slow peripheral interrupt group reallocation request is sent to a chip that is not responsible for consistency management, then this chip updates its copy of the routing table and then sends a request to the chip responsible for consistency management to update the routing table. The chip responsible for consistency management then notifies the remaining chips to update their routing table copies. After the slow peripheral interrupt migration configuration is completed, the configuration information of the migrated slow peripheral interrupt stored in the random access memory is reset to the initial value.

[0011] In addition, the present invention also provides a device that supports chip interconnection and expandable slow peripheral interrupts, including a microprocessor, multiple slow peripheral interfaces, and two random access memories. The microprocessor includes multiple chips, each chip includes an interrupt controller, an on-chip network, multiple processor cores and a high-speed interconnection interface; the interrupt controller is connected to multiple slow peripherals, and the interrupt controller is connected to multiple processor cores through the on-chip network. Multiple chips in the same socket or different sockets are connected through the high-speed interconnection interface; the two random access memories, one is a fixed random access memory, which is used to store configuration information of slow peripheral interrupt numbers within a fixed interval, and the other is a real-time random access memory, which is used to store configuration information of slow peripheral interrupt numbers outside the fixed interval, and the real-time random access memory uses a least recently used algorithm LRU to select a storage row that has not been accessed for a long time in the recent period as a replacement row when updating the configuration information, and the interrupt controller is programmed or configured to execute the method for supporting chip interconnection and expandable slow peripheral interrupts.

[0012] In addition, the present invention also provides a device for supporting chip interconnection and scalable slow peripheral interruption, comprising a microprocessor and a memory connected to each other, wherein the microprocessor is programmed or configured to execute the method for supporting chip interconnection and scalable slow peripheral interruption.

[0013] In addition, the present invention also provides a computer-readable storage medium, in which a computer program is stored. The computer program is used to be programmed or configured by a microprocessor to execute the method for supporting chip interconnection and scalable slow peripheral interruption.

[0014] Compared with the prior art, the present invention mainly has the following advantages: the present invention includes setting the number of slow peripheral interrupts in a register configurable manner, the corresponding slow peripheral interrupt register address space is expanded, and the interrupt bit width and random access memory space in the interrupt controller are also adjusted accordingly to update the configuration information of the slow peripheral interrupt, thereby ensuring that any slow peripheral interrupt can be initiated by reading the configuration information, so that the slow peripheral interrupt is sent to the set processor core for processing according to the routing information, and at the same time, the global consistency of the configuration is achieved by migrating the slow peripheral configuration information between different chips, and the processor core further calls the interrupt handler to process the interrupt and return the interrupt confirmation. The traditional interrupt controller does not support the adjustment of slow peripheral interrupts, and changing the number of slow peripheral interrupts requires changing the hardware logic, which consumes a lot of time, manpower and resources. The present invention can realize the expandable number of slow peripheral interrupts under the interconnection of multiple chips through software configuration without modifying the hardware logic to meet the interrupt processing requirements of the slow peripheral update iteration, and realize higher reuse of the chip architecture. The device has the advantages of low hardware implementation complexity, small area overhead and high cost performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 Schematic diagram of the basic flow of the method of the embodiment of the present invention.

[0016] Figure 2 Schematic diagram of a slow peripheral interrupt quantity register in an embodiment of the present invention.

[0017] Figure 3 Schematic diagram of the state change of the routing table in an embodiment of the present invention.

[0018] Figure 4 The figure is a schematic diagram of the processing flow of directly connected slow peripheral interrupt in an embodiment of the present invention.

[0019] Figure 5 Schematic diagram of the slow peripheral interrupt migration process in an embodiment of the present invention.

[0020] Figure 6 Schematic diagram of routing table copy update in an embodiment of the present invention.

[0021] Figure 7 Schematic diagram of the topological structure of the device according to the embodiment of the present invention. DETAILED DESCRIPTION

[0022] like Figure 1 As shown, the method for supporting chip interconnection and scalable slow peripheral interruption in this embodiment includes the following steps: S1, expands the address space of slow peripheral interrupt registers; S2, configure the number of slow peripheral interrupts supported through the slow peripheral interrupt register, and set the slow peripheral interrupts managed by each chip; S3, configuring the chip connection through the slow peripheral interrupt register and generating the routing configuration information of the chip; S4, when the interrupt controller in the chip detects an interrupt request, the interrupt controller processes the interrupt request and dispatches it to the corresponding processor core according to the routing configuration information. For example, when the corresponding processor core crosses the chip, the interrupt controller dispatches it to the corresponding processor core through the on-chip network and the high-speed interconnection interface according to the routing configuration information; S5, the processor core calls the interrupt handler to process and returns the interrupt confirmation.

[0023] In order to realize the interrupt communication between chips and the management of slow peripheral interrupts, when the address space of the slow peripheral interrupt register is expanded in step S1 of this embodiment, the expanded slow peripheral interrupt register defines a group of registers that specify the chip connection relationship, and the group of registers includes: chip internal registers, each chip Chip corresponds to a chip internal register, and the register is used to describe the chip number used to identify the cross-chip routing during cross-chip transmission, the starting value of the slow peripheral interrupt group managed by the chip Chip, the number of slow peripheral interrupt groups managed by the chip Chip, and the power-on status of the chip Chip; chip management register, a multi-chip system has only one chip management register, and the register is used to describe the chip Chip responsible for managing consistency and the connection completion status of each chip Chip; chip status register, a multi-chip system has only one chip status register, which is used to describe the consistency status of the routing table.

[0024] From the hardware level, the method of this embodiment directly connects each slow peripheral interrupt to the interrupt controller, and controls the number of directly connected slow peripheral interrupts by the bit width of the slow peripheral interrupt signal. For homogeneous multi-chip systems, the bit width of the slow peripheral interrupt signal of each chip is the same. From the software level, the slow peripheral interrupt is assigned an interrupt number, and the interrupt controller manages the slow peripheral interrupts in groups. Each slow peripheral interrupt group contains 32 slow peripheral interrupts. The starting value of the slow peripheral interrupt group and the number of slow peripheral interrupt groups are defined for each chip. The slow peripheral interrupts are assigned to specific chips in groups, indicating the interval of the slow peripheral interrupt numbers managed by the chip, and completing the correspondence between the interrupt number and the slow peripheral interrupt line. In order to realize the configuration of any slow peripheral interrupt, when the address space of the slow peripheral interrupt register is expanded in step S1 of this embodiment, the expanded slow peripheral interrupt register defines a 32-bit slow peripheral interrupt number register, such as Figure 2 As shown, the register field is num, which is used to identify the number of slow peripheral interrupts. Step S2 includes: S2.1, configure the number of slow peripheral interrupts in the 32-bit slow peripheral interrupt number register; S2.2, configure the total number of slow peripheral interrupt groups according to the number of slow peripheral interrupts; S2.3, determining the bit width of the slow peripheral interrupt signal according to the total number of slow peripheral interrupt groups, and the bit width of the slow peripheral interrupt signal is less than a preset threshold value num, num = (num 1 ×32) / num 2 , where num 1 The total number of slow peripheral interrupt groups, num 2 is the number of chips; if the multi-chip system formed by interconnecting the chips is a homogeneous multi-chip system, the bit width of the slow peripheral interrupt signal of each chip is the same; otherwise, the bit width of the slow peripheral interrupt signal of some or all chips is different; S2.4, setting the slow peripheral interrupt managed by each chip Chip, including: assigning an interrupt number to the slow peripheral interrupt, the interrupt controller manages the slow peripheral interrupt in groups, each slow peripheral interrupt group contains 32 slow peripheral interrupts, and defines the starting value of the slow peripheral interrupt group and the number of slow peripheral interrupt groups for each chip Chip. The slow peripheral interrupt is allocated to a specific chip Chip in groups, indicating the interval of the slow peripheral interrupt number managed by the chip Chip, and completing the correspondence between the interrupt number and the slow peripheral interrupt line.

[0025] Step S3 of this embodiment includes: S3.1, configure the chip management register, designate a chip to be responsible for managing the consistency of the routing table, and the routing table is stored inside each chip as a carrier of routing configuration information; S3.2, configure the chip internal registers of the chip responsible for managing consistency, including specifying the chip number used to identify the cross-chip routing when the chip is transmitted across chips, the starting value of the slow peripheral interrupt group, the number of slow peripheral interrupt groups, and set the chip to the power-on state; S3.3, the interrupt controller saves the configuration information of the slow peripheral interrupt group to the routing table of the chip responsible for managing consistency, and updates the routing table status to a consistent state, which can be confirmed by reading the chip status register; S3.4, for the chip responsible for managing consistency, the chip needs to be connected, and the internal registers of the chip that needs to be connected are configured, including specifying the chip number used to identify the cross-chip routing when the chip is transmitted across chips, the starting value of the slow peripheral interrupt group, and the number of slow peripheral interrupt groups, and setting the chip to the power-on state. At this time, the routing table is in an unconnected state; S3.5, the interrupt controller saves the interrupt information of the slow peripheral that needs to be connected to the chip that has not yet been connected in the routing table responsible for managing the consistency chip. At this time, the routing table is in an updating state; S3.6, the chip responsible for managing consistency sends the routing table information to the chip that needs to be connected. The chip that needs to be connected creates a copy of the routing table and updates the routing table to a consistent state and indicates it in the read chip status register. At this time, the connection between the two chips is completed and indicated in the read chip management register; the schematic diagram of the routing table state change is as follows Figure 3 As shown, there are three states, namely, the unconnected state, the updated state and the consistent state. The unconnected state is entered after power-on reset. In the unconnected state, if the internal register value of the chip is saved to the routing table of the chip Chip that manages consistency, the update state is entered; in the update state, if the chip Chip1 that needs to be connected establishes a copy of the routing table, the consistent state is entered; in the consistent state, if the chip router of another chip Chip2 that needs to be connected is configured, the unconnected state is entered; S3.7, repeat steps S3.4-S3.6 until all chips except the chip responsible for managing consistency are connected to the chip responsible for managing consistency.

[0026] The routing configuration information in step S4 of this embodiment includes: A slow peripheral interrupt group, used to record the slow peripheral interrupt group information described in the slow peripheral interrupt, and the slow peripheral interrupt group information is used to set the security and non-security attributes of the slow peripheral interrupt; Slow peripheral interrupt enable, used to indicate the enable status of slow peripheral interrupt; Slow peripheral interrupt routing, used to indicate which processor core the slow peripheral interrupt is sent to for processing; Slow peripheral interrupt priority, used to indicate the priority level of slow peripheral interrupt processing; Slow peripheral interrupt trigger mode, used to indicate whether the slow peripheral interrupt is level triggered or edge triggered; The routing configuration information is stored in a random access memory inside the interrupt controller of the chip by writing a slow peripheral interrupt register, and the random access memory is also used to store the state information of the slow peripheral interrupt processing. As an optional implementation, the fields and lengths of the routing configuration information in this embodiment are set as shown in Table 1.

[0027] Table 1: Fields and lengths of routing configuration information

[0028] In Table 1, the length of the routing configuration information is 32 bits in total, [6:0] represents bits 1 to 7, [18:7] represents bits 8 to 19,

[19] represents bit 20, and so on. The slow peripheral interrupt ECC check can be used to determine whether the slow peripheral interrupt is correct. If the slow peripheral interrupt is incorrect, no response is made or an error message is returned.

[0029] In step S4 of this embodiment, when the interrupt controller in the chip detects an interrupt request, there are two ways to initiate the interrupt request: direct connection and software writing. The direct connection initiation method is that the slow peripheral directly connected to the chip initiates the interrupt request, and the software writing method is to initiate the interrupt request from any chip that has been connected, and the interrupt controller of the chip obtains the configuration information of the slow peripheral interrupt and sends it to the corresponding chip for processing; Figure 4 The figure shows an example of an interrupt request of the interrupt controller between Chip0 and Chip1 for the direct connection initiation mode. The processing of the interrupt request of the interrupt controller for the direct connection initiation mode includes: S101, obtaining configuration information of a slow peripheral interrupt group of the chip Chip, and obtaining the interval of slow peripheral interrupt numbers managed by the chip Chip; S102, initiating a direct slow peripheral interrupt and pulling the corresponding slow peripheral interrupt line high; S103, adding the starting value of the slow peripheral interrupt group managed by the chip Chip to the number of the corresponding slow peripheral interrupt line as the interrupt number of the slow peripheral interrupt directly connected to the chip Chip; S104, if the interrupt number of the slow peripheral interrupt is within the interval of the slow peripheral interrupt numbers managed by the chip, the interrupt is set to a suspended state, the random access memory is read to obtain the routing configuration information of the slow peripheral interrupt, and the next step is jumped; otherwise, an error is reported, the process ends and exits; S105, judging whether the slow peripheral interrupt priority of the slow peripheral interrupt has the highest priority and whether the slow peripheral interrupt enable is enabled according to the routing configuration information, and when the slow peripheral interrupt priority of the slow peripheral interrupt has the highest priority and the slow peripheral interrupt enable is enabled, sending the interrupt to the designated processor core according to the slow peripheral interrupt route, and marking the state information of the slow peripheral interrupt as a slow peripheral interrupt pending state in the random access memory; After step S5, the interrupt controller also includes marking the state information of the slow peripheral interrupt as the slow peripheral interrupt active state in the random access memory after receiving the interrupt confirmation, and regularly clearing the slow peripheral interrupt in the slow peripheral interrupt active state.

[0030] In addition, the method of this embodiment also includes taking the slow peripheral interrupt group as a unit, and adjusting the correspondence between the continuous slow peripheral interrupt numbers and the slow peripheral interrupt connection lines by configuring the internal registers of the chip to achieve the migration of the slow peripheral interrupt group: initiating a slow peripheral interrupt group migration request from any chip Chip that has been connected, requesting the configuration to adjust the chip internal registers of the slow peripheral interrupt chip Chip that needs to adjust, and changing the starting value and number of the slow peripheral interrupt group managed by the chip Chip; updating the routing table and the routing table copy, such as Figure 5 As shown, if the slow peripheral interrupt group migration request is sent to the chip responsible for consistency management, the chip responsible for consistency management updates the routing table and then sends a request to update the routing table copies of the remaining chips; if the slow peripheral interrupt group reallocation request is sent to the chip not responsible for consistency management, the chip updates the routing table copy and then sends a request to the chip responsible for consistency management to update the routing table, and then the chip responsible for consistency management notifies the remaining chips to update the routing table copies, as shown in FIG. Figure 6 As shown, after the slow peripheral interrupt migration configuration is completed, the configuration information of migrating the slow peripheral interrupt stored in the random access memory is reset to the initial value.

[0031] In summary, this embodiment discloses a method and device that supports chip interconnection and expandable slow peripheral interrupts. This embodiment includes setting the number of slow peripheral interrupts in a register-configurable manner, expanding the corresponding slow peripheral interrupt register address space, and adjusting the interrupt bit width and random access memory space in the interrupt controller to adapt to the configuration information of the slow peripheral interrupt, thereby ensuring that any slow peripheral interrupt can be initiated by reading the configuration information, and then sending the slow peripheral interrupt to the set processor core for processing according to the routing information. At the same time, the global consistency of configuration is achieved between different chips by migrating the slow peripheral configuration information. The processor core further calls the interrupt handler to handle the interrupt and returns an interrupt confirmation. Traditional interrupt controllers do not support the adjustment of slow peripheral interrupts. Changing the number of slow peripheral interrupts requires changing the hardware logic, which consumes a lot of time, manpower and resources. The method of this embodiment supports chip interconnection and scalable slow peripheral interrupts. It can realize the scalable number of slow peripheral interrupts under multi-chip chip interconnection through software configuration without modifying the hardware logic to meet the interrupt processing requirements of slow peripheral updates and iterations, thereby achieving higher reuse of chip architecture. The device has the advantages of low hardware implementation complexity, small area overhead and high cost performance.

[0032] In addition, if Figure 7 As shown, this embodiment also provides a device that supports chip interconnection and expandable slow peripheral interruption, including a microprocessor, multiple slow peripheral interfaces, and two random access memories. The microprocessor includes multiple chips, each chip includes an interrupt controller, an on-chip network, multiple processor cores and a high-speed interconnection interface; the interrupt controller is connected to multiple slow peripherals, and the interrupt controller is connected to multiple processor cores through the on-chip network. Multiple chips in the same socket or different sockets are connected through the high-speed interconnection interface; the two random access memories, one is a fixed random access memory, which is used to store configuration information of slow peripheral interrupt numbers within a fixed interval, and the other is a real-time random access memory, which is used to store configuration information of slow peripheral interrupt numbers outside the fixed interval, and the real-time random access memory adopts the least recently used algorithm LRU to select a storage row that has not been accessed for a long time in the recent period as a replacement row when updating the configuration information, and the interrupt controller is programmed or configured to execute the method for supporting chip interconnection and expandable slow peripheral interruption. Taking into account the chip area size, the real-time random access memory can update configuration information according to actual conditions. The device of this embodiment that supports chip interconnection and can expand slow peripheral interrupts adopts the least recently used algorithm (Least Recently Used, LRU), and selects a storage row that has not been accessed for a long time in the recent period as a replacement row based on the principle of locality of access.

[0033] In addition, the present invention also provides a device for supporting chip interconnection and scalable slow peripheral interruption, comprising a microprocessor and a memory connected to each other, wherein the microprocessor is programmed or configured to execute the method for supporting chip interconnection and scalable slow peripheral interruption.

[0034] In addition, the present invention also provides a computer-readable storage medium, in which a computer program is stored. The computer-readable storage medium is characterized in that the computer program is used to be programmed or configured by a microprocessor to execute the method of supporting chip interconnection and scalable slow peripheral interrupts.

[0035] Those skilled in the art should understand that the technical solution provided by the present invention may be in the form of a method, a system, or a computer program product. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present invention may take the form of a computer program product implemented on one or more computer-readable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes. The present invention is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the functions in the process. Figure 1 A process or multiple processes and / or boxes Figure 1 These computer program instructions can also be stored in a computer-readable memory that can guide a computer or other programmable data processing device to work in a specific way, so that the instructions stored in the computer-readable memory produce a product including an instruction device, which implements the functions specified in the process. Figure 1 A process or multiple processes and / or boxes Figure 1 These computer program instructions can also be loaded onto a computer or other programmable data processing device, so that a series of operation steps are executed on the computer or other programmable device to produce a computer-implemented process, so that the instructions executed on the computer or other programmable device provide for implementing the process in the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0036] The above is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above embodiments. All technical solutions under the concept of the present invention belong to the protection scope of the present invention. It should be pointed out that for ordinary technicians in this technical field, some improvements and modifications without departing from the principle of the present invention should also be regarded as the protection scope of the present invention.

Claims

1. A method for supporting chip interconnection and scalable slow peripheral interruption, characterized in that: The steps include: S1, expands the address space of slow peripheral interrupt registers; S2, configure the number of slow peripheral interrupts supported through the slow peripheral interrupt register, and set the slow peripheral interrupts managed by each chip; S3, configuring the chip connection through the slow peripheral interrupt register and generating the routing configuration information of the chip; S4, when the interrupt controller in the chip detects an interrupt request, the interrupt controller processes the interrupt request and dispatches it to the corresponding processor core according to the routing configuration information; S5, the processor core calls the interrupt handler to process and returns the interrupt confirmation.

2. The method for supporting chip interconnection and scalable slow peripheral interruption according to claim 1, characterized in that: When the address space of the slow peripheral interrupt register is expanded in step S1, the expanded slow peripheral interrupt register defines a group of registers that specify chip connection relationships, and the group of registers includes: chip internal registers, each chip corresponds to a chip internal register, and the register is used to describe the chip number used to identify cross-chip routing during cross-chip transmission, the starting value of the slow peripheral interrupt group managed by the chip, the number of slow peripheral interrupt groups managed by the chip, and the power-on status of the chip; a chip management register, a multi-chip system has only one chip management register, and the register is used to describe the chip responsible for managing consistency and the completion status of each chip connection; a chip status register, a multi-chip system has only one chip status register, which is used to describe the consistency status of the routing table.

3. The method for supporting chip interconnection and scalable slow peripheral interruption according to claim 1, characterized in that: When the address space of the slow peripheral interrupt register is expanded in step S1, the expanded slow peripheral interrupt register defines a 32-bit slow peripheral interrupt quantity register, and step S2 includes: S2.1, configure the number of slow peripheral interrupts in the 32-bit slow peripheral interrupt number register; S2.2, configure the total number of slow peripheral interrupt groups according to the number of slow peripheral interrupts; S2.3, determining the bit width of the slow peripheral interrupt signal according to the total number of slow peripheral interrupt groups, and the bit width of the slow peripheral interrupt signal is less than a preset threshold value num, num = (num1 × 32) / num2, where num1 is the total number of slow peripheral interrupt groups, and num2 is the number of chips; if the multi-chip system formed by chip interconnection is a homogeneous multi-chip system, the bit width of the slow peripheral interrupt signal of each chip is the same; otherwise, the bit width of the slow peripheral interrupt signal of some or all chips is different; S2.4, setting the slow peripheral interrupt managed by each chip, including: assigning an interrupt number to the slow peripheral interrupt, the interrupt controller manages the slow peripheral interrupt in groups, each slow peripheral interrupt group contains 32 slow peripheral interrupts, and defines the starting value of the slow peripheral interrupt group and the number of slow peripheral interrupt groups for each chip. The slow peripheral interrupt is allocated to a specific chip in groups, indicating the interval of the slow peripheral interrupt number managed by the chip, and completing the correspondence between the interrupt number and the slow peripheral interrupt line.

4. The method for supporting chip interconnection and scalable slow peripheral interruption according to claim 1, characterized in that: Step S3 includes: S3.1, configure the chip management register to designate a chip to be responsible for managing the consistency of the routing table. The routing table is stored inside each chip as a carrier of routing configuration information; S3.2, configure the chip internal registers of the chip responsible for managing consistency, including specifying the chip number used to identify the cross-chip routing when the chip is transmitted across chips, the starting value of the slow peripheral interrupt group, the number of slow peripheral interrupt groups, and set the chip to the power-on state; S3.3, the interrupt controller saves the slow peripheral interrupt group configuration information to the routing table of the chip responsible for managing consistency, and updates the routing table status to a consistent state, which can be confirmed by reading the chip status register; S3.4, for the chip responsible for managing consistency, the chip needs to be connected, and the internal registers of the chip to be connected are configured, including specifying the chip number used to identify the cross-chip routing when the chip is transmitted across chips, the starting value of the slow peripheral interrupt group, and the number of slow peripheral interrupt groups, and setting the chip to the power-on state. At this time, the routing table is in the unconnected state; S3.5, the interrupt controller saves the interrupt information of the slow peripheral that needs to be connected to the chip but has not yet been connected in the routing table responsible for managing the consistency chip. At this time, the routing table is in an updating state; S3.6, the chip responsible for managing consistency sends the routing table information to the chip that needs to be connected. The chip that needs to be connected creates a copy of the routing table and updates the routing table to be in a consistent state and indicates it in the read chip status register. At this time, the connection between the two chips is completed and indicated in the read chip management register; S3.7, repeat steps S3.4-S3.6 until all chips except the chip responsible for managing consistency are connected to the chip responsible for managing consistency.

5. The method for supporting chip interconnection and scalable slow peripheral interruption according to claim 1, characterized in that: The routing configuration information in step S4 includes: A slow peripheral interrupt group, used to record the slow peripheral interrupt group information described in the slow peripheral interrupt, and the slow peripheral interrupt group information is used to set the security and non-security attributes of the slow peripheral interrupt; Slow peripheral interrupt enable, used to indicate the enable status of slow peripheral interrupt; Slow peripheral interrupt routing, used to indicate which processor core the slow peripheral interrupt is sent to for processing; Slow peripheral interrupt priority, used to indicate the priority level of slow peripheral interrupt processing; Slow peripheral interrupt trigger mode, used to indicate whether the slow peripheral interrupt is level triggered or edge triggered; The routing configuration information is stored in a random access memory inside the interrupt controller of the chip by writing a slow peripheral interrupt register. The random access memory is also used to store status information of the slow peripheral interrupt processing.

6. The method for supporting chip interconnection and scalable slow peripheral interruption according to claim 5, characterized in that: In step S4, when the interrupt controller in the chip detects an interrupt request, there are two ways to initiate the interrupt request: direct connection and software writing. The direct connection initiation mode is that the slow peripheral directly connected to the chip initiates the interrupt request, and the software writing mode is to initiate the interrupt request from any connected chip, and the interrupt controller of the chip obtains the configuration information of the slow peripheral interrupt and sends it to the corresponding chip for processing; The interrupt controller processes the interrupt request initiated by the direct connection including: S101, obtaining configuration information of the slow peripheral interrupt group of the chip, and obtaining the interval of the slow peripheral interrupt number managed by the chip; S102, initiating a direct slow peripheral interrupt and pulling the corresponding slow peripheral interrupt line high; S103, adding the starting value of the slow peripheral interrupt group managed by the chip to the number of the corresponding slow peripheral interrupt line as the interrupt number of the slow peripheral interrupt directly connected to the chip; S104, if the interrupt number of the slow peripheral interrupt is within the interval of the slow peripheral interrupt numbers managed by the chip, the interrupt is set to a suspended state, the random access memory is read to obtain the routing configuration information of the slow peripheral interrupt, and the next step is jumped; otherwise, an error is reported, the process ends and exits; S105, judging whether the slow peripheral interrupt priority of the slow peripheral interrupt has the highest priority and whether the slow peripheral interrupt enable is enabled according to the routing configuration information, and when the slow peripheral interrupt priority of the slow peripheral interrupt has the highest priority and the slow peripheral interrupt enable is enabled, sending the interrupt to the designated processor core according to the slow peripheral interrupt route, and marking the state information of the slow peripheral interrupt as a slow peripheral interrupt pending state in the random access memory; After step S5, the interrupt controller also includes marking the state information of the slow peripheral interrupt as the slow peripheral interrupt active state in the random access memory after receiving the interrupt confirmation, and regularly clearing the slow peripheral interrupt in the slow peripheral interrupt active state.

7. The method for supporting chip interconnection and scalable slow peripheral interruption according to claim 5, characterized in that: It also includes adjusting the correspondence between consecutive slow peripheral interrupt numbers and slow peripheral interrupt lines by configuring the internal registers of the chip in units of slow peripheral interrupt groups to achieve slow peripheral interrupt group migration: initiating a slow peripheral interrupt group migration request from any chip that has been connected, requesting configuration to adjust the chip internal registers of the slow peripheral interrupt chip, and changing the starting value and number of slow peripheral interrupt groups managed by the chip; updating the routing table and routing table copies: if the slow peripheral interrupt group migration request is sent to the chip responsible for consistency management, the chip responsible for consistency management updates the routing table and then requests to update the routing table copies of the remaining chips; If the slow peripheral interrupt group reallocation request is sent to a chip that is not responsible for consistency management, then after this chip updates its copy of the routing table, it sends a request to the chip responsible for consistency management to update the routing table. The chip responsible for consistency management then notifies the remaining chips to update their copies of the routing table. After the slow peripheral interrupt migration configuration is completed, the configuration information of the migrated slow peripheral interrupt stored in the random access memory is reset to the initial value.

8. A device supporting chip interconnection and scalable slow peripheral interruption, comprising a microprocessor, a plurality of slow peripheral interfaces, and two random access memories, characterized in that: The microprocessor includes multiple chips, each chip includes an interrupt controller, an on-chip network, multiple processor cores and a high-speed interconnect interface; the interrupt controller is connected to multiple slow peripherals, and the interrupt controller is connected to multiple processor cores through the on-chip network, and multiple chips in the same slot or different slots are connected through a high-speed interconnect interface; the two random access memories, one is a fixed random access memory, used to store configuration information of slow peripheral interrupt numbers within a fixed interval, and the other is a real-time random access memory, used to store configuration information of slow peripheral interrupt numbers outside the fixed interval, and the real-time random access memory uses a least recently used algorithm to select a storage row that has not been accessed for a long time in the recent period as a replacement row when updating the configuration information, and the interrupt controller is programmed or configured to execute the method for supporting chip interconnection and scalable slow peripheral interrupts as described in any one of claims 1 to 7.

9. A device supporting chip interconnection and scalable slow peripheral interruption, comprising a microprocessor and a memory connected to each other, characterized in that: The microprocessor is programmed or configured to execute the method for supporting chip interconnection and scalable slow peripheral interruption as claimed in any one of claims 1 to 7.

10. A computer-readable storage medium having a computer program stored therein, characterized in that: The computer program is used to be programmed or configured by a microprocessor to execute the method for supporting chip interconnection and scalable slow peripheral interruption as claimed in any one of claims 1 to 7.

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