A method and device for supporting scalable slow peripheral interrupts for chip interconnection

Abstract

The present invention discloses a method and apparatus for supporting expandable slow peripheral interrupts for chip interconnection. The present invention includes expanding the address space of the slow peripheral interrupt register; configuring the number of supported slow peripheral interrupts through the slow peripheral interrupt register and setting the slow peripheral interrupts managed by each chip; configuring the chip connection and generating the routing configuration information of the chip through the slow peripheral interrupt register; when the interrupt controller in the chip detects an interrupt request, after detecting the interrupt request, the interrupt controller processes it and distributes it to the corresponding processor core according to the routing configuration information; the processor core calls the interrupt handling program to process it and returns an interrupt acknowledgment. The purpose of the present invention is to support arbitrarily configuring the number of slow peripheral interrupts to meet the slow peripheral interrupt handling requirements of different system architectures, and has the advantages of low hardware implementation complexity, small area overhead, and high cost performance.

Description

Technical Field

[0001] The present invention relates to the technical field of multi-chip integration based on multi-chip components, and particularly relates to a method and device for supporting scalable slow peripheral interrupts for chip interconnection. Background Art

[0002] In the past 50 years, the semiconductor industry has been advancing along the pace of Moore's Law. The density of transistors has been continuously increasing, gradually reaching the tens of billions level, bringing great challenges to density and cost. As Moore's Law approaches its limit, traditional single-chip semiconductor devices can no longer meet the performance or function requirements of certain computing density-intensive and workload-heavy applications. Multi-die systems are becoming a solution to transcend Moore's Law and address complex systematic challenges, expanding system functions faster in a cost-effective manner, reducing risks, achieving higher throughput with lower power consumption, and helping to meet the rapidly growing demand for processing power. At the same time, the emerging Multi-Chip Module technology is a new generation of microelectronic packaging and assembly technology developed on the basis of Printed Circuit Board and Surface Mount Technology to adapt to the development direction of modern electronic systems towards short, small, light, thin, high-speed, high-performance, high-reliability, and low-cost, and is a powerful means to achieve system integration. With the development of multi-die systems, the number of externally mounted devices is also increasing continuously. Traditional interrupt controllers do not support the adjustment of slow peripheral interrupts. Changing the number of slow peripheral interrupts requires changing the hardware logic, consuming a large amount of time, manpower, and resources. How to expand slow peripheral interrupts while controlling the chip area size and time and manpower costs, and achieve the processing of slow peripheral interrupts between different chips in a multi-die system has become a difficult problem. Summary of the Invention

[0003] The technical problem to be solved by the present invention: Aiming at the above problems of the prior art, a method and device for supporting scalable slow peripheral interrupts for chip interconnection are provided. The present invention aims to support arbitrarily configured numbers of slow peripheral interrupts to meet the slow peripheral interrupt processing requirements of different system architectures, and has the advantages of low hardware implementation complexity, small area overhead, and high cost performance.

[0004] To solve the above technical problems, the technical solution adopted by the present invention is as follows:

[0005] A method for supporting scalable slow peripheral interrupts for chip interconnection, comprising the following steps:

[0006] S1, expanding the address space of the slow peripheral interrupt register;

[0007] S2, Configure the number of slow peripheral interrupts supported by the slow peripheral interrupt register, and set the slow peripheral interrupts managed by each Chip;

[0008] S3, Configure the Chip connection and generate the routing configuration information of the Chip through the slow peripheral interrupt register;

[0009] S4, When the interrupt controller in the Chip detects an interrupt request, after the interrupt controller detects the interrupt request, it processes and dispatches it to the corresponding processor core according to the routing configuration information;

[0010] S5, The processor core calls the interrupt handler for processing and returns an interrupt acknowledgment.

[0011] Optionally, when expanding the address space of the slow peripheral interrupt register in step S1, the expanded slow peripheral interrupt register defines a set of registers specifying the Chip connection relationship. This set of registers includes: internal Chip registers, each Chip corresponds to an internal Chip register, which is used to describe the Chip number for identifying cross-chip routing during cross-chip transmission, the starting value of the slow peripheral interrupt group managed by the Chip, the number of slow peripheral interrupt groups managed by the Chip, and the power-on state of the Chip; Chip management register, there is only one Chip management register in a multi-Chip system, which is used to describe the Chip responsible for managing consistency and the connection completion status of each Chip; Chip status register, there is only one Chip status register in a multi-Chip system, which is used to describe the routing table consistency status.

[0012] Optionally, when expanding the address space of the slow peripheral interrupt register in step S1, the expanded slow peripheral interrupt register defines a 32-bit slow peripheral interrupt number register. Step S2 includes:

[0013] S2.1, Configure the number of slow peripheral interrupts of the 32-bit slow peripheral interrupt number register;

[0014] S2.2, Configure the total number of slow peripheral interrupt groups according to the number of slow peripheral interrupts;

[0015] S2.3, Determine the bit width of the slow peripheral interrupt signal according to the total number of slow peripheral interrupt groups, and the bit width of the slow peripheral interrupt signal is less than the preset threshold num, num = (num1 × 32) / num2, where num1 is the total number of slow peripheral interrupt groups and num2 is the number of Chips; if the multi-Chip system formed by Chip interconnection is a homogeneous multi-Chip system, the bit width of the slow peripheral interrupt signal of each Chip is the same; otherwise, the bit width of the slow peripheral interrupt signal of some or all Chips is different;

[0016] S2.4, Set the slow peripheral interrupts managed by each chip Chip, including: Assign an interrupt number to the slow peripheral interrupts. The interrupt controller manages the slow peripheral interrupts in groups. Each group of slow peripheral interrupts contains 32 slow peripheral interrupts. Define the starting value of the slow peripheral interrupt group and the number of slow peripheral interrupt groups for each chip Chip. Allocate the slow peripheral interrupts to a specific chip Chip in groups, representing the range of slow peripheral interrupt numbers managed by this chip Chip, and complete the correspondence between the interrupt numbers and the slow peripheral interrupt lines.

[0017] Optionally, step S3 includes:

[0018] S3.1, Configure the chip management register, and specify a chip Chip to be responsible for managing the routing table consistency. The routing table is stored inside each chip Chip as a carrier of routing configuration information;

[0019] S3.2, Configure the internal chip register of the chip Chip responsible for managing the consistency, including specifying the chip number, the starting value of the slow peripheral interrupt group, and the number of slow peripheral interrupt groups used to identify cross-chip routing during cross-chip transmission of this chip Chip, and set this chip Chip to the powered-on state;

[0020] S3.3, The interrupt controller saves the slow peripheral interrupt group configuration information to the routing table of the chip Chip responsible for managing the consistency, and updates the routing table status to the consistency state, which can be confirmed by reading the chip status register;

[0021] S3.4, For the chip Chip that needs to be connected to the chip Chip responsible for managing the consistency, configure the internal chip register of the chip Chip that needs to be connected, including specifying the chip number, the starting value of the slow peripheral interrupt group, and the number of slow peripheral interrupt groups used to identify cross-chip routing during cross-chip transmission of this chip Chip, and set this chip Chip to the powered-on state. At this time, the routing table is in the unconnected state;

[0022] S3.5, The interrupt controller saves the slow peripheral interrupt information of the chip Chip that needs to be connected but not yet connected in the routing table of the chip Chip responsible for managing the consistency. At this time, the routing table is in the updated state;

[0023] S3.6, The chip Chip responsible for managing the consistency sends the routing table information to the chip Chip that needs to be connected. The chip Chip that needs to be connected establishes a copy of the routing table, and updates the routing table to the consistency state and indicates it in the read chip status register. At this time, the connection between the two chips Chip is completed and indicated in the read chip management register;

[0024] S3.7. Repeat steps S3.4 - S3.6 until all chips Chip except the chip Chip responsible for managing consistency are completely connected to the chip Chip responsible for managing consistency.

[0025] Optionally, the routing configuration information in step S4 includes:

[0026] Slow peripheral interrupt grouping, used to record the slow peripheral interrupt group information described by the slow peripheral interrupt. The slow peripheral interrupt group information is used to set the secure and non - secure attributes of the slow peripheral interrupt;

[0027] Slow peripheral interrupt enable, used to indicate the enable state of the slow peripheral interrupt;

[0028] Slow peripheral interrupt routing, used to indicate which processor core the slow peripheral interrupt is sent to for processing;

[0029] Slow peripheral interrupt priority, used to indicate the priority level of slow peripheral interrupt processing;

[0030] Slow peripheral interrupt trigger mode, used to indicate whether the slow peripheral interrupt is level - triggered or edge - triggered;

[0031] The routing configuration information is saved in the random - access memory inside the interrupt controller of the chip Chip by writing to the slow peripheral interrupt register. The random - access memory is also used to save the status information of slow peripheral interrupt processing.

[0032] Optionally, when the interrupt controller in the chip Chip detects an interrupt request in step S4, there are two slow peripheral interrupt initiation methods for the interrupt request: direct connection and software write. Among them, the direct - connection initiation method is that the slow peripherals directly connected to the chip Chip initiate an interrupt request, and the software write is to initiate an interrupt request from any chip Chip that has been completely connected. And the interrupt controller of this chip Chip obtains the configuration information of this slow peripheral interrupt and sends it to the corresponding chip Chip for processing; and the processing of the interrupt request with the direct - connection initiation method by the interrupt controller includes:

[0033] S101. Obtain the configuration information of the slow peripheral interrupt group of this chip Chip to get the range of the slow peripheral interrupt numbers managed by this chip Chip;

[0034] S102. Initiate a direct - connection slow peripheral interrupt and pull up the corresponding slow peripheral interrupt line;

[0035] S103. Add the starting value of the slow peripheral interrupt group managed by the chip Chip and the number of the corresponding slow peripheral interrupt line as the interrupt number of the direct - connection slow peripheral interrupt of this chip Chip;

[0036] S104. If the interrupt number of the slow peripheral interrupt is within the range of the slow peripheral interrupt numbers managed by the chip Chip, then the interrupt is set to the pending state, read the random access memory to obtain the routing configuration information of the slow peripheral interrupt, and jump to the next step; otherwise, report an error, end and exit.

[0037] S105. Determine whether the slow peripheral interrupt priority of the slow peripheral interrupt has the highest priority and whether the slow peripheral interrupt enable is enabled according to the routing configuration information. And when the slow peripheral interrupt priority of the slow peripheral interrupt has the highest priority and the slow peripheral interrupt enable is enabled, send it to the specified processor core according to the slow peripheral interrupt routing, and mark the status information of the slow peripheral interrupt in the random access memory as the slow peripheral interrupt pending state.

[0038] After step S5, it further includes that after the interrupt controller receives the interrupt confirmation, it marks the status information of the slow peripheral interrupt in the random access memory as the slow peripheral interrupt active state, and periodically clears the slow peripheral interrupt with the slow peripheral interrupt active state of the slow peripheral interrupt active state.

[0039] Optionally, it further includes taking the slow peripheral interrupt group as a unit. The corresponding relationship between the consecutive slow peripheral interrupt numbers and the slow peripheral interrupt connections is adjusted by configuring the internal registers of the chip to achieve the slow peripheral interrupt group migration: initiate a slow peripheral interrupt group migration request from any chip Chip that has been connected. Request to configure the internal registers of the chip Chip that needs to adjust the slow peripheral interrupt, and change the starting value and number of groups of the slow peripheral interrupt group managed by this chip Chip; update the routing table and the routing table copy: if the slow peripheral interrupt group migration request is sent to the chip Chip responsible for consistency management, then the chip Chip responsible for consistency management updates the routing table and then sends a request to update the routing table copies of the other chips Chip; if the slow peripheral interrupt group reallocation request is sent to a chip Chip that is not responsible for consistency management, then after this chip Chip updates the copy of the routing table, it sends a request to update the routing table to the chip Chip responsible for consistency management, and then the chip Chip responsible for consistency management notifies the other chips Chip to update the routing table copies. After the slow peripheral interrupt migration configuration is completed, the configuration information of the migrated slow peripheral interrupt in the random access memory is reset to the initial value.

[0040] In addition, the present invention also provides a device for supporting scalable slow peripheral interrupts for chip interconnection, including a microprocessor, a plurality of slow peripheral interfaces, and two random access memories. The microprocessor includes a plurality of chips Chip, and each chip Chip includes an interrupt controller, a network-on-chip, a plurality of processor cores, and a high-speed interconnection interface. The interrupt controller is connected to a plurality of slow peripherals, and the interrupt controller is connected to a plurality of processor cores through the network-on-chip. A plurality of chips Chip in the same socket Socket or different sockets Socket are connected through the high-speed interconnection interface. The two random access memories, one is a fixed random access memory for storing configuration information of slow peripheral interrupt numbers within a fixed range, and the other is a real-time random access memory for storing configuration information of slow peripheral interrupt numbers outside the fixed range. The real-time random access memory uses the least recently used algorithm LRU to select the storage row that has not been accessed for a long time recently as the replacement row when updating the configuration information. The interrupt controller is programmed or configured to execute the method for supporting scalable slow peripheral interrupts for chip interconnection.

[0041] In addition, the present invention also provides a device for supporting scalable slow peripheral interrupts for chip interconnection, including a microprocessor and a memory connected to each other. The microprocessor is programmed or configured to execute the method for supporting scalable slow peripheral interrupts for chip interconnection.

[0042] In addition, the present invention also provides a computer-readable storage medium, in which a computer program is stored. The computer program is used to be programmed or configured by a microprocessor to execute the method for supporting scalable slow peripheral interrupts for chip interconnection.

[0043] Compared with the prior art, the present invention mainly has the following advantages: The present invention includes setting the number of slow peripheral interrupts in a register-configurable manner. Accordingly, the address space of the slow peripheral interrupt register is expanded, and the interrupt bit width and the random access memory space in the interrupt controller are also adjusted to update the configuration information of the slow peripheral interrupts. Furthermore, it is ensured that any slow peripheral interrupt initiation can read the configuration information, and thus the slow peripheral interrupts can be sent to the set processor core for processing according to the routing information. At the same time, the global consistency of the configuration is achieved by migrating the slow peripheral configuration information between different chips (Chips). The processor core further calls the interrupt handler to process the interrupt and returns an interrupt acknowledgment. The traditional interrupt controller does not support the adjustment of slow peripheral interrupts. Changing the number of slow peripheral interrupts requires modifying the hardware logic, consuming a large amount of time, manpower, and resources. The present invention can, without modifying the hardware logic, realize an expandable number of slow peripheral interrupts under multi-chip (Chip) interconnection through software configuration to meet the interrupt processing requirements of the slow peripheral update and iteration, and achieve higher reuse of the Chip architecture. This device has the advantages of low hardware implementation complexity, small area overhead, and high cost performance. Description of the Drawings

[0044] Figure 1 It is a schematic diagram of the basic process of the method according to the embodiment of the present invention.

[0045] Figure 2 It is a schematic diagram of the slow peripheral interrupt number register in the embodiment of the present invention.

[0046] Figure 3 It is a schematic diagram of the change of the routing table status in the embodiment of the present invention.

[0047] Figure 4 It is a schematic diagram of the processing flow of the directly connected slow peripheral interrupts in the embodiment of the present invention.

[0048] Figure 5 It is a schematic diagram of the slow peripheral interrupt migration process in the embodiment of the present invention.

[0049] Figure 6 It is a schematic diagram of the update of the routing table copy in the embodiment of the present invention.

[0050] Figure 7 It is a schematic diagram of the topological structure of the device according to the embodiment of the present invention. Detailed Embodiment

[0051] As Figure 1 shown, the method for supporting expandable slow peripheral interrupts for chip interconnection in this embodiment includes the following steps:

[0052] S1, expand the address space of the slow peripheral interrupt register;

[0053] S2, Configure the number of slow peripheral interrupts supported by the slow peripheral interrupt register and set the slow peripheral interrupts managed by each Chip;

[0054] S3, Configure the Chip connection through the slow peripheral interrupt register and generate the routing configuration information of the Chip;

[0055] S4, When the interrupt controller in the Chip detects an interrupt request, after detecting the interrupt request, the interrupt controller processes it and dispatches it to the corresponding processor core according to the routing configuration information. For example, in the case where the corresponding processor core crosses Chips, it is dispatched to the corresponding processor core through the on-chip network and high-speed interconnect interface according to the routing configuration information;

[0056] S5, The processor core calls the interrupt handler for processing and returns an interrupt acknowledgment.

[0057] To achieve interrupt communication between Chips and management of slow peripheral interrupts, when expanding the address space of the slow peripheral interrupt register in step S1 of this embodiment, the expanded slow peripheral interrupt register defines a set of registers specifying Chip connection relationships. This set of registers includes: internal Chip registers, each Chip corresponds to an internal Chip register, which is used to describe the Chip number for identifying cross-chip routing during cross-chip transmission, the starting value of the slow peripheral interrupt group managed by the Chip, the number of slow peripheral interrupt groups managed by the Chip, and the power-on state of the Chip; Chip management register, there is only one Chip management register in a multi-Chip system, which is used to describe the Chip responsible for management consistency and the connection completion status of each Chip; Chip status register, there is only one Chip status register in a multi-Chip system, which is used to describe the routing table consistency state.

[0058] In the method of this embodiment, at the hardware level, each slow peripheral interrupt is directly connected to the interrupt controller, and the number of directly connected slow peripheral interrupts is controlled by the bit width of the slow peripheral interrupt signal. For a homogeneous multi-Chip system, the bit width of the slow peripheral interrupt signal of each Chip is the same. At the software level, a slow peripheral interrupt is assigned an interrupt number, and the interrupt controller manages slow peripheral interrupts in groups. Each slow peripheral interrupt group contains 32 slow peripheral interrupts. For each Chip, the starting value of the slow peripheral interrupt group and the number of slow peripheral interrupt groups are defined, and the slow peripheral interrupts are allocated to a specific Chip in groups, indicating the range of slow peripheral interrupt numbers managed by the Chip, and the correspondence between the interrupt number and the slow peripheral interrupt line is completed. To achieve the configuration of any slow peripheral interrupt, when expanding the address space of the slow peripheral interrupt register in step S1 of this embodiment, the expanded slow peripheral interrupt register defines a 32-bit slow peripheral interrupt number register, such asFigure 2 As shown, the register field is num, which is used to identify the number of slow peripheral interrupts. Step S2 includes:

[0059] S2.1, Configure the number of slow peripheral interrupts of the 32-bit slow peripheral interrupt number register;

[0060] S2.2, Configure the total number of slow peripheral interrupt groups according to the number of slow peripheral interrupts;

[0061] S2.3, Determine the bit width of the slow peripheral interrupt signal according to the total number of slow peripheral interrupt groups, and the bit width of the slow peripheral interrupt signal is less than the preset threshold num, where num = (num1 × 32) / num2, num1 is the total number of slow peripheral interrupt groups, and num2 is the number of chips; if the multi-chip system formed by the interconnection of chips Chip is a homogeneous multi-chip system, the bit width of the slow peripheral interrupt signal of each chip Chip is the same; otherwise, the bit widths of the slow peripheral interrupt signals of some or all chips Chip are different;

[0062] S2.4, Set the slow peripheral interrupts managed by each chip Chip, including: Assign an interrupt number to the slow peripheral interrupt, the interrupt controller manages the slow peripheral interrupts in groups, each slow peripheral interrupt group contains 32 slow peripheral interrupts, define the starting value of the slow peripheral interrupt group and the number of slow peripheral interrupt groups for each chip Chip, and allocate the slow peripheral interrupts to a specific chip Chip in groups, indicating the range of slow peripheral interrupt numbers managed by the chip Chip, and complete the correspondence between the interrupt number and the slow peripheral interrupt line.

[0063] Step S3 of this embodiment includes:

[0064] S3.1, Configure the chip management register, and specify a chip Chip to be responsible for managing the routing table consistency. The routing table is stored inside each chip Chip as a carrier of routing configuration information;

[0065] S3.2, Configure the internal chip register of the chip Chip responsible for managing consistency, including specifying the chip number, the starting value of the slow peripheral interrupt group, and the number of slow peripheral interrupt groups used to identify cross-chip routing during cross-chip transmission of the chip Chip, and set the chip Chip to the power-on state;

[0066] S3.3, The interrupt controller saves the slow peripheral interrupt group configuration information to the routing table of the chip Chip responsible for managing consistency, and updates the routing table status to the consistency state and can be confirmed by reading the chip status register;

[0067] S3.4. For the chip Chip responsible for managing consistency, it is necessary to connect to the chip Chip, configure the internal registers of the chip that needs to be connected to the chip Chip, including specifying the chip number used to identify the cross-chip routing when the chip Chip performs cross-chip transmission, the starting value of the slow peripheral interrupt group, the number of slow peripheral interrupt groups, and set the chip Chip to the power-on state. At this time, the routing table is in an unconnected state;

[0068] S3.5. The interrupt controller saves the slow peripheral interrupt information that needs to be connected but not yet to the chip Chip in the routing table of the chip Chip responsible for managing consistency. At this time, the routing table is in an updated state;

[0069] S3.6. The chip Chip responsible for managing consistency sends the routing table information to the chip Chip that needs to be connected. The chip Chip that needs to be connected creates a copy of the routing table, and updates the routing table to the consistency state and indicates it in the read chip status register. At this time, the connection between the two chips Chip is completed and indicated in the read chip management register; The schematic diagram of the routing table state change is as Figure 3 shown, including a total of three states: unconnected state, updated state, and consistency state. After power-on reset, it enters the unconnected state. In the unconnected state, if the internal register value of the chip is saved to the routing table of the chip Chip responsible for managing consistency, it enters the updated state; In the updated state, if the chip Chip1 that needs to be connected creates a copy of the routing table, it enters the consistency state; In the consistency state, if the chip router of another chip Chip2 that needs to be connected is configured, it will enter the unconnected state;

[0070] S3.7. Repeat steps S3.4 - S3.6 until all chips Chip other than the chip Chip responsible for managing consistency are all connected to the chip Chip responsible for managing consistency.

[0071] The routing configuration information in step S4 of this embodiment includes:

[0072] Slow peripheral interrupt grouping, which is used to record the slow peripheral interrupt group information of the slow peripheral interrupt. The slow peripheral interrupt group information is used to set the security and non-security attributes of the slow peripheral interrupt;

[0073] Slow peripheral interrupt enable, which is used to indicate the enable state of the slow peripheral interrupt;

[0074] Slow peripheral interrupt routing, which is used to indicate which processor core the slow peripheral interrupt is sent to for processing;

[0075] Slow peripheral interrupt priority, which is used to indicate the priority level of slow peripheral interrupt processing;

[0076] The slow peripheral interrupt trigger mode is used to indicate whether the slow peripheral interrupt is level-triggered or edge-triggered;

[0077] The routing configuration information is stored in the random access memory inside the interrupt controller of the chip Chip by writing to the slow peripheral interrupt register. The random access memory is also used to store the status information of slow peripheral interrupt processing. As an alternative implementation, the fields and lengths of the routing configuration information in this embodiment are set as shown in Table 1.

[0078] Table 1: Fields and lengths of routing configuration information

[0079]

[0080] In Table 1, the total length of the routing configuration information is 32 bits. [6:0] represents bits 1 to 7, [18:7] represents bits 8 to 19,

[19] represents bit 20, and so on. Slow peripheral interrupt ECC check can be used to determine whether the slow peripheral interrupt is correct. If the slow peripheral interrupt is incorrect, no response is made or an error message is returned.

[0081] In step S4 of this embodiment, when the interrupt controller in the chip Chip detects an interrupt request, there are two slow peripheral interrupt initiation methods for the interrupt request: direct connection and software write. Among them, the direct connection initiation method is that the slow peripheral directly connected to the chip Chip initiates an interrupt request, and software write means initiating an interrupt request from any chip Chip that has been connected, and the interrupt controller of the chip Chip obtains the configuration information of the slow peripheral interrupt, and sends it to the corresponding chip Chip for processing; as Figure 4 shown is an example of the interrupt request of the direct connection initiation method by the interrupt controller between Chip0 and Chip1. The processing of the interrupt request of the direct connection initiation method by the interrupt controller includes:

[0082] S101, obtain the configuration information of the slow peripheral interrupt group of the chip Chip itself, and obtain the range of slow peripheral interrupt numbers managed by the chip Chip;

[0083] S102, initiate a direct connection slow peripheral interrupt, and pull up the corresponding slow peripheral interrupt line;

[0084] S103, add the starting value of the slow peripheral interrupt group managed by the chip Chip and the number of the corresponding slow peripheral interrupt line as the interrupt number of the direct connection slow peripheral interrupt of the chip Chip;

[0085] S104. If the interrupt number of the slow peripheral interrupt is within the range of the slow peripheral interrupt numbers managed by the chip Chip, then this interrupt is set to the pending state, read the random access memory to obtain the routing configuration information of the slow peripheral interrupt, and jump to the next step; otherwise, report an error, end and exit.

[0086] S105. According to the routing configuration information, determine whether the slow peripheral interrupt priority of the slow peripheral interrupt has the highest priority and whether the slow peripheral interrupt enable is enabled. When the slow peripheral interrupt priority of the slow peripheral interrupt has the highest priority and the slow peripheral interrupt enable is enabled, send it to the specified processor core according to the slow peripheral interrupt routing, and mark the status information of this slow peripheral interrupt as the slow peripheral interrupt pending state in the random access memory.

[0087] After step S5, it further includes that after the interrupt controller receives the interrupt confirmation, mark the status information of this slow peripheral interrupt as the slow peripheral interrupt active state in the random access memory, and regularly clear the slow peripheral interrupt with the slow peripheral interrupt active state of the slow peripheral interrupt active state.

[0088] In addition, the method of this embodiment further includes taking the slow peripheral interrupt group as a unit, and the corresponding relationship between the consecutive slow peripheral interrupt numbers and the slow peripheral interrupt connection lines is adjusted by configuring the internal registers of the chip to achieve the slow peripheral interrupt group migration: initiate a slow peripheral interrupt group migration request from any chip Chip that has been connected, request to configure the internal registers of the chip Chip that needs to adjust the slow peripheral interrupt, and change the starting value and number of groups of the slow peripheral interrupt group managed by this chip Chip; update the routing table and the routing table copy. As Figure 5 shown, if the slow peripheral interrupt group migration request is sent to the chip Chip responsible for consistency management, then the chip Chip responsible for consistency management updates the routing table and then sends a request to update the routing table copies of the remaining chips Chip; if the slow peripheral interrupt group reallocation request is sent to a chip Chip that is not responsible for consistency management, then after this chip Chip updates the copy of the routing table, it sends a request to update the routing table to the chip Chip responsible for consistency management, and then the chip Chip responsible for consistency management notifies the remaining chips Chip to update the routing table copies. As Figure 6 shown, after the slow peripheral interrupt migration configuration is completed, the configuration information of the migrated slow peripheral interrupt in the random access memory is reset to the initial value.

[0089] In summary, this embodiment discloses a method and apparatus for supporting scalable slow peripheral interrupts for chip interconnect. This embodiment includes setting the number of slow peripheral interrupts in a register-configurable manner, expanding the corresponding address space of the slow peripheral interrupt register, and adjusting the interrupt bit width and random access memory space within the interrupt controller to adapt to the configuration information of the slow peripheral interrupts. Furthermore, it ensures that any slow peripheral interrupt initiation can send the slow peripheral interrupt to the set processor core for processing by reading the configuration information and then according to the routing information. At the same time, the global consistency of the configuration is achieved by migrating the slow peripheral configuration information between different chips Chip. The processor core further calls the interrupt handler to process the interrupt and returns an interrupt acknowledgment. Traditional interrupt controllers do not support the adjustment of slow peripheral interrupts. Changing the number of slow peripheral interrupts requires modifying the hardware logic, consuming a large amount of time, manpower, and resources. The method for supporting scalable slow peripheral interrupts for chip interconnect in this embodiment can, without modifying the hardware logic, achieve scalable slow peripheral interrupts with multiple chips Chip interconnected through software configuration to meet the interrupt processing requirements of slow peripheral updates and iterations, realizing higher reuse of the chip Chip architecture. This apparatus has the advantages of low hardware implementation complexity, small area overhead, and high cost performance.

[0090] In addition, as Figure 7 shown, this embodiment also provides an apparatus for supporting scalable slow peripheral interrupts for chip interconnect, including a microprocessor, multiple slow peripheral interfaces, and two random access memories. The microprocessor contains multiple chips Chip, and each chip Chip contains an interrupt controller, a network-on-chip, multiple processor cores, and a high-speed interconnect interface; the interrupt controller is connected to multiple slow peripherals, the interrupt controller is connected to multiple processor cores through the network-on-chip, and multiple chips Chip in the same socket Socket or different sockets Socket are connected through the high-speed interconnect interface; the two random access memories, one is a fixed random access memory for storing the configuration information of slow peripheral interrupt numbers within a fixed range, and the other is a real-time random access memory for storing the configuration information of slow peripheral interrupt numbers outside the fixed range. The real-time random access memory uses the least recently used (LRU) algorithm to select the storage row that has not been accessed for a long time recently as the replacement row when updating the configuration information. The interrupt controller is programmed or configured to execute the method for supporting scalable slow peripheral interrupts for chip interconnect. Considering the chip area size, the real-time random access memory can update the configuration information according to the actual situation. The apparatus for supporting scalable slow peripheral interrupts for chip interconnect in this embodiment uses the least recently used (LRU) algorithm and selects the storage row that has not been accessed for a long time recently as the replacement row based on the locality principle of access.

[0091] In addition, the present invention also provides an apparatus for supporting expandable slow peripheral interrupts for chip interconnection, including a microprocessor and a memory connected to each other, and the microprocessor is programmed or configured to execute the method for supporting expandable slow peripheral interrupts for chip interconnection.

[0092] In addition, the present invention also provides a computer-readable storage medium, in which a computer program is stored, and the feature is that the computer program is used to be programmed or configured by a microprocessor to execute the method for supporting expandable slow peripheral interrupts for chip interconnection.

[0093] Those skilled in the art should understand that the technical solution provided by the present invention can be in the form of a method, a system, or a computer program product. Therefore, the present invention can be implemented in the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present invention can be implemented in the form of a computer program product implemented on one or more computer-readable storage media (including but not limited to disk memories, CD-ROMs, optical memories, etc.) containing computer-usable program codes. The present invention is described with reference to the flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each flow and / or block in the flowchart and / or block diagram can be implemented by computer program instructions, and the combination of the flows and / or blocks in the flowchart and / or block diagram can also be implemented by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing devices to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing devices generate a device for realizing the functions specified in one process Figure 1 one process or multiple processes and / or blocks Figure 1 or multiple blocks specified in the flowchart and / or block diagram. These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer-readable memory generate a manufactured article including an instruction device, and the instruction device realizes the functions specified in one process Figure 1 one process or multiple processes and / or blocks Figure 1 or multiple blocks specified in the flowchart and / or block diagram. These computer program instructions can also be loaded onto a computer or other programmable data processing device, so that a series of operation steps are executed on the computer or other programmable device to generate a computer-implemented process, and thus the instructions executed on the computer or other programmable device provide steps for realizing the functions specified in one process Figure 1 one process or multiple processes and / or blocks Figure 1 or multiple blocks specified in the flowchart and / or block diagram.

[0094] The above are only the preferred embodiments of the present invention, and the protection scope of the present invention is not limited to the above embodiments. All technical solutions within the idea of the present invention belong to the protection scope of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements and refinements should also be regarded as within the protection scope of the present invention.

Claims

1. A method for supporting expandable slow peripheral interrupts for chip interconnection, characterized in that, including the following steps: S1, expand the address space of the slow peripheral interrupt register; S2, configure the number of supported slow peripheral interrupts through the slow peripheral interrupt register, and set the slow peripheral interrupts managed by each chip; S3, configure the connection of the chip through the slow peripheral interrupt register and generate the routing configuration information of the chip; S4, when the interrupt controller in the chip detects an interrupt request, after the interrupt controller detects the interrupt request, it processes and dispatches it to the corresponding processor core according to the routing configuration information; S5, the processor core calls the interrupt handler to process and returns an interrupt acknowledgment.

2. The method for supporting chip interconnection to expand slow peripheral interrupt according to claim 1, wherein When expanding the address space of the slow peripheral interrupt register in step S1, the expanded slow peripheral interrupt register defines a set of registers specifying the chip connection relationship. This set of registers includes: an internal chip register, each chip has a corresponding internal chip register, which is used to describe the chip number for identifying cross-chip routing during cross-chip transmission, the starting value of the slow peripheral interrupt group managed by the chip, the number of slow peripheral interrupt groups managed by the chip, and the power-on state of the chip; a chip management register, there is only one chip management register in a multi-chip system, which is used to describe the chip responsible for managing consistency and the completion status of the connection of each chip; a chip status register, there is only one chip status register in a multi-chip system, which is used to describe the consistency status of the routing table.

3. The method for supporting chip interconnection and scalable slow peripheral interrupt according to claim 1, wherein When expanding the address space of the slow peripheral interrupt register in step S1, the expanded slow peripheral interrupt register defines a 32-bit slow peripheral interrupt number register. Step S2 includes: S2.1, configure the number of slow peripheral interrupts of the 32-bit slow peripheral interrupt number register; S2.2, configure the total number of slow peripheral interrupt groups according to the number of slow peripheral interrupts; S2.3, determine the bit width of the slow peripheral interrupt signal according to the total number of slow peripheral interrupt groups, and the bit width of the slow peripheral interrupt signal is less than the preset threshold num, num = (num1 × 32) / num2, where num1 is the total number of slow peripheral interrupt groups and num2 is the number of chips; if the multi-chip system formed by chip interconnection is a homogeneous multi-chip system, the bit width of the slow peripheral interrupt signal of each chip is the same; otherwise, the bit width of the slow peripheral interrupt signal of some or all chips is different; S2.4, set the slow peripheral interrupts managed by each chip, including: assign an interrupt number to the slow peripheral interrupt, the interrupt controller manages the slow peripheral interrupts in groups, each slow peripheral interrupt group contains 32 slow peripheral interrupts, define the starting value of the slow peripheral interrupt group and the number of slow peripheral interrupt groups for each chip, and allocate the slow peripheral interrupts to specific chips in groups, indicating the range of the interrupt numbers of the slow peripheral interrupts managed by the chip, and complete the correspondence between the interrupt numbers and the slow peripheral interrupt lines.

4. The method for supporting chip interconnection and scalable slow peripheral interrupt according to claim 1, wherein Step S3 includes: S3.1, configure the chip management register, specify a chip to be responsible for managing the routing table consistency, and the routing table is stored inside each chip as the carrier of the routing configuration information; S3.2, configure the on-chip registers of the chip responsible for managing consistency, including specifying the chip number used to identify the cross-chip routing when the chip performs cross-chip transmission, the starting value of the slow peripheral interrupt group, the number of slow peripheral interrupt groups, and set the chip to the power-on state; S3.3, the interrupt controller saves the slow peripheral interrupt group configuration information into the routing table of the chip responsible for managing consistency, and updates the routing table status to the consistency state, which can be confirmed by reading the chip status register; S3.4, for the chips that need to be connected to the chip responsible for managing consistency, configure the on-chip registers of the chips that need to be connected, including specifying the chip number used to identify the cross-chip routing when the chip performs cross-chip transmission, the starting value of the slow peripheral interrupt group, the number of slow peripheral interrupt groups, and set the chip to the power-on state. At this time, the routing table is in the unconnected state; S3.5, the interrupt controller saves the slow peripheral interrupt information of the chips that need to be connected but not yet connected in the routing table of the chip responsible for managing consistency. At this time, the routing table is in the updated state; S3.6, the chip responsible for managing consistency sends the routing table information to the chips that need to be connected. The chips that need to be connected establish a copy of the routing table, and update the routing table to the consistency state and indicate it in the read chip status register. At this time, the connection of the two chips is completed and indicated in the read chip management register; S3.7, repeat steps S3.4 - S3.6 until all chips except the chip responsible for managing consistency are all connected to the chip responsible for managing consistency.

5. The method for supporting chip interconnection and scalable slow peripheral interrupt according to claim 1, wherein The routing configuration information in step S4 includes: Slow peripheral interrupt grouping, which is used to record the slow peripheral interrupt group information of the slow peripheral interrupt. The slow peripheral interrupt group information is used to set the security and non-security attributes of the slow peripheral interrupt; Slow peripheral interrupt enable, which is used to indicate the enable state of the slow peripheral interrupt; Slow peripheral interrupt routing, which is used to indicate which processor core the slow peripheral interrupt is sent to for processing; Slow peripheral interrupt priority, which is used to indicate the priority level of slow peripheral interrupt processing; Slow peripheral interrupt trigger mode, which is used to indicate whether the slow peripheral interrupt is level-triggered or edge-triggered; The routing configuration information is saved in the random access memory inside the interrupt controller of the chip by writing to the slow peripheral interrupt register. The random access memory is also used to save the status information of slow peripheral interrupt processing.

6. The method for supporting scalable slow peripheral interrupts for chip interconnection according to claim 5, wherein, In step S4, when the interrupt controller in the chip detects an interrupt request, there are two slow peripheral interrupt initiation methods for the interrupt request: direct connection and software write. Among them, the direct connection initiation method is that the slow peripherals directly connected to the chip initiate an interrupt request, and the software write is to initiate an interrupt request from any chip that has been connected. And the interrupt controller of this chip obtains the configuration information of the slow peripheral interrupt and sends it to the corresponding chip for processing; And the processing of the interrupt request in the direct connection initiation method by the interrupt controller includes: S101, obtain the configuration information of the slow peripheral interrupt group of this chip to get the range of the slow peripheral interrupt numbers managed by this chip; S102, initiate a direct connection slow peripheral interrupt and pull up the corresponding slow peripheral interrupt line; S103. Add the number of the corresponding slow peripheral interrupt line to the starting value of the slow peripheral interrupt group managed by the chip as the interrupt number of the slow peripheral interrupt directly connected to the chip; S104. If the interrupt number of the slow peripheral interrupt is within the range of the slow peripheral interrupt numbers managed by the chip, then set this interrupt to the pending state, read the random access memory to obtain the routing configuration information of the slow peripheral interrupt, and jump to the next step; otherwise, report an error, end, and exit; S105. Judge whether the slow peripheral interrupt priority of the slow peripheral interrupt has the highest priority and whether the slow peripheral interrupt enable is enabled according to the routing configuration information. When the slow peripheral interrupt priority of the slow peripheral interrupt has the highest priority and the slow peripheral interrupt enable is enabled, send it to the specified processor core according to the slow peripheral interrupt routing, and mark the status information of the slow peripheral interrupt as the slow peripheral interrupt pending state in the random access memory; After step S5, it further includes that after the interrupt controller receives the interrupt confirmation, it marks the status information of the slow peripheral interrupt as the slow peripheral interrupt active state in the random access memory, and periodically clears the slow peripheral interrupt with the slow peripheral interrupt active state of the slow peripheral interrupt active state.

7. The method for supporting chip interconnection and scalable slow peripheral interrupt according to claim 5, wherein, It also includes taking the slow peripheral interrupt group as a unit. The correspondence between the consecutive slow peripheral interrupt numbers and the slow peripheral interrupt connections is adjusted by configuring the internal registers of the chip to realize the slow peripheral interrupt group migration: initiate a slow peripheral interrupt group migration request from any chip that has been connected, request to configure the internal registers of the chip that needs to adjust the slow peripheral interrupt chip, and change the starting value and the number of groups of the slow peripheral interrupt group managed by this chip; update the routing table and the routing table copy: if the slow peripheral interrupt group migration request is sent to the chip responsible for consistency management, then the chip responsible for consistency management updates the routing table and then sends a request to update the routing table copies of the other chips; If the slow peripheral interrupt group reallocation request is sent to a chip that is not responsible for consistency management, after this chip updates the copy of the routing table, it sends a request to update the routing table to the chip responsible for consistency management, and then the chip responsible for consistency management notifies the other chips to update the routing table copies. After the slow peripheral interrupt migration configuration is completed, the configuration information of the migrated slow peripheral interrupt in the random access memory is reset to the initial value.

8. A device for supporting scalable slow peripheral interrupts for chip interconnection, comprising a microprocessor, a plurality of slow peripheral interfaces, and two random access memories, characterized in that, The microprocessor includes multiple chips, each chip includes an interrupt controller, a network-on-chip, multiple processor cores, and a high-speed interconnect interface; the interrupt controller is connected to multiple slow peripherals, the interrupt controller is connected to multiple processor cores through the network-on-chip, and multiple chips in the same slot or different slots are connected through the high-speed interconnect interface; the two random access memories, one is a fixed random access memory for storing the configuration information of the slow peripheral interrupt numbers within a fixed range, and the other is a real-time random access memory for storing the configuration information of the slow peripheral interrupt numbers outside the fixed range, and the real-time random access memory adopts the least recently used algorithm to select the storage row that has not been accessed for a long time recently as the replacement row when updating the configuration information, and the interrupt controller is programmed or configured to execute the method for supporting chip-interconnected extensible slow peripheral interrupts described in any one of claims 1 to 7.

9. A device for supporting scalable slow peripheral interrupts for chip interconnect, including a microprocessor and a memory connected to each other, characterized in that, The microprocessor is programmed or configured to execute the method for supporting chip-interconnected extensible slow peripheral interrupts described in any one of claims 1 to 7.

10. A computer-readable storage medium storing a computer program therein, characterized in that, The computer program is used to be programmed or configured by the microprocessor to execute the method for supporting chip-interconnected extensible slow peripheral interrupts described in any one of claims 1 to 7.

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