Shifting register unit, driving method thereof, display driving circuit and display device

Abstract

The invention provides a shift register unit, a driving method thereof, a display driving circuit and a display device, and belongs to the technical field of display. The shift register unit comprises an input circuit, an output circuit and an output control circuit. Wherein the input circuit and the output control circuit can be matched with each other so as to control the output circuit to output a display driving signal to the pixels and drive the pixels to emit light. The display driving signal output by the output circuit is the direct-current power supply signal, so that compared with an output clock signal serving as the display driving signal, the driving capability of the shift register unit is improved, and the display effect is improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a shift register unit and a driving method thereof, a display driving circuit, and a display device. Background Art

[0002] At present, the gate drive on array (GOA) technology is often used to integrate the display drive circuit on the display panel to facilitate the design of a narrow frame. The display drive circuit is, for example, a gate drive circuit that transmits a gate drive signal to pixels in the display panel. This is also called a Gate GOA circuit.

[0003] In the related art, the Gate GOA circuit includes a plurality of cascaded GOA units, also known as shift register units. Each GOA unit is respectively connected to a control terminal, a clock terminal and an output terminal, and the output terminal is used to connect to a pixel in a display panel and to control the on-off of the clock terminal and the output terminal based on a control signal provided by the control terminal, so as to output a clock signal to the pixel via the output terminal as a gate drive signal to drive the pixel to emit light.

[0004] However, affected by various factors (eg, signals provided by connected terminals), the driving capability of the shift register unit in the related art is relatively poor. Summary of the invention

[0005] Provided are a shift register unit and a driving method thereof, a display driving circuit, and a display device, which can solve the problem of poor driving capability of the shift register unit in the related art. The technical solution is as follows:

[0006] In one aspect, a shift register unit is provided, the shift register unit comprising:

[0007] an input circuit, connected to the first clock terminal, the second clock terminal, the first power terminal, the input terminal, the first node, and the second node, respectively, and used to control the potential of the first node in response to a first clock signal provided by the first clock terminal, a second clock signal provided by the second clock terminal, an input signal provided by the input terminal, a first power signal provided by the first power terminal, and a potential of the second node;

[0008] a first output control circuit, connected to the first clock terminal, the third clock terminal, the second power terminal, the first node and the second node respectively, and used to control the potential of the second node in response to the first clock signal, the third clock signal provided by the third clock terminal, the second power signal provided by the second power terminal and the potential of the first node;

[0009] a second output control circuit, connected to the target control terminal, the third power terminal, the first node, the second node and the third node respectively, and used to control the potential of the third node in response to a control signal provided by the target control terminal, a third power signal provided by the third power terminal, the potential of the first node and the potential of the second node;

[0010] The output circuit is connected to the second node, the third node, the fourth power supply terminal, the fifth power supply terminal and the output terminal respectively, and is used to control the on-off connection between the fourth power supply terminal and the output terminal in response to the potential of the second node and the potential of the third node, and to control the on-off connection between the fifth power supply terminal and the output terminal, so as to output a display driving signal through the output terminal.

[0011] Optionally, the target control end includes: a sixth power supply end or a fourth clock end, and the fourth clock signal provided by the fourth clock end has the same timing as the third clock signal, and the pulse width of the fourth clock signal is less than or equal to the pulse width of the third clock signal.

[0012] Optionally, at least one of the fifth power terminal and the sixth power terminal is shared with the second power terminal; and / or at least one of the third power terminal and the fourth power terminal is shared with the first power terminal.

[0013] Optionally, the input circuit comprises:

[0014] a first input subcircuit, connected to the first clock terminal, the input terminal and the first node respectively, and used to control the connection and disconnection between the input terminal and the first node in response to the first clock signal, so as to control the potential of the first node;

[0015] a second input subcircuit, connected to the first node, the second node, the second clock terminal, the first power terminal and the fourth node respectively, and used to control the connection and disconnection between the second clock terminal and the fourth node in response to the potential of the first node, and to control the connection and disconnection between the first power terminal and the fourth node in response to the potential of the second node, so as to control the potential of the fourth node;

[0016] The third input sub-circuit is connected to the fourth node and the first node respectively, and is used to adjust the potential of the first node based on the potential of the fourth node to control the potential of the first node.

[0017] Optionally, the first input subcircuit includes: a first transistor; the second input subcircuit includes: a second transistor and a third transistor; the third input subcircuit includes: a first capacitor;

[0018] The gate of the first transistor is connected to the first clock terminal, the first electrode of the first transistor is connected to the input terminal, and the second electrode of the first transistor is connected to the first node;

[0019] The gate of the second transistor is connected to the first node, the first electrode of the second transistor is connected to the second clock terminal, and the second electrode of the second transistor is connected to the fourth node;

[0020] The gate of the third transistor is connected to the second node, the first electrode of the third transistor is connected to the first power supply terminal, and the second electrode of the third transistor is connected to the fourth node;

[0021] The first capacitor is connected between the fourth node and the first node.

[0022] Optionally, the first output control circuit includes:

[0023] a first control subcircuit, connected to the first clock terminal, the second power terminal and the second node respectively, and used to control the connection and disconnection between the second power terminal and the second node in response to the first clock signal, so as to control the potential of the second node;

[0024] The second control subcircuit is connected to the first node, the third clock terminal and the second node respectively, and is used to control the connection and disconnection of the third clock terminal and the second node in response to the potential of the first node to control the potential of the second node.

[0025] Optionally, the first control subcircuit includes: a fourth transistor; the second control subcircuit includes: a fifth transistor;

[0026] The gate of the fourth transistor is connected to the first clock terminal, the first electrode of the fourth transistor is connected to the second power supply terminal, and the second electrode of the fourth transistor is connected to the second node;

[0027] A gate of the fifth transistor is connected to the first node, a first electrode of the fifth transistor is connected to the third clock terminal, and a second electrode of the fifth transistor is connected to the second node.

[0028] Optionally, the second output control circuit includes:

[0029] a third control subcircuit, connected to the target control terminal, the first node and the third node respectively, and used to control the connection and disconnection of the first node and the third node in response to the control signal, so as to control the potential of the third node;

[0030] The fourth control subcircuit is respectively connected to the second node, the third power supply terminal and the third node, and is used to control the connection and disconnection of the third power supply terminal and the third node in response to the potential of the second node to control the potential of the third node.

[0031] Optionally, the third control subcircuit includes: a sixth transistor; the fourth control subcircuit includes: a seventh transistor;

[0032] The gate of the sixth transistor is connected to the target control terminal, the first electrode of the sixth transistor is connected to the first node, and the second electrode of the sixth transistor is connected to the third node;

[0033] The gate of the seventh transistor is connected to the second node, the first electrode of the seventh transistor is connected to the third power supply terminal, and the second electrode of the seventh transistor is connected to the third node;

[0034] When the absolute value of the difference between the potential of the control signal and the potential of the first node is greater than the threshold voltage of the sixth transistor, the sixth transistor is turned on.

[0035] Optionally, the output circuit includes:

[0036] a first output subcircuit, connected to the second node, the fourth power supply terminal and the output terminal respectively, and used to control the on-off of the fourth power supply terminal and the output terminal in response to the potential of the second node, so as to output the fourth power supply signal provided by the fourth power supply terminal as the display driving signal through the output terminal, and also adjust the potential of the second node based on the first power supply signal;

[0037] The second output sub-circuit is respectively connected to the third node, the fifth power supply terminal and the output terminal, and is used to control the connection and disconnection of the fifth power supply terminal and the output terminal in response to the potential of the third node, so as to output the fifth power supply signal provided by the fifth power supply terminal through the output terminal as the display drive signal.

[0038] Optionally, the first output sub-circuit includes: an eighth transistor and a second capacitor; the second output sub-circuit includes: a ninth transistor;

[0039] The gate of the eighth transistor is connected to the second node, the first electrode of the eighth transistor is connected to the fourth power supply terminal, and the second electrode of the eighth transistor is connected to the output terminal;

[0040] The gate of the ninth transistor is connected to the third node, the first electrode of the ninth transistor is connected to the fifth power supply terminal, and the second electrode of the ninth transistor is connected to the output terminal;

[0041] The second capacitor is connected between the fourth power supply terminal and the second node.

[0042] Optionally, the first node includes: a first sub-node and a second sub-node; the input circuit is connected to the first sub-node and the second sub-node respectively, the first output control circuit is connected to the first sub-node, and the second output control circuit is connected to the second sub-node; the shift register unit further includes:

[0043] The isolation circuit is connected to the seventh power supply terminal, the first sub-node and the second sub-node respectively, and is used to control the connection and disconnection of the first sub-node and the second sub-node in response to a seventh power supply signal provided by the seventh power supply terminal.

[0044] Optionally, the seventh power supply terminal is shared with the second power supply terminal; the isolation circuit comprises: a tenth transistor;

[0045] A gate of the tenth transistor is connected to the seventh power supply terminal, a first electrode of the tenth transistor is connected to the first sub-node, and a second electrode of the tenth transistor is connected to the second sub-node.

[0046] On the other hand, a driving method of a shift register unit is provided, for driving the shift register unit as described in the above aspect; the method comprises:

[0047] In the first stage, the input circuit controls the potential of the first node to be the first potential in response to the first clock signal provided by the first clock terminal, the second clock signal provided by the second clock terminal, the input signal provided by the input terminal, the first power signal provided by the first power terminal and the potential of the second node; the first output control circuit controls the potential of the second node to be the first potential in response to the first clock signal, the third clock signal provided by the third clock terminal, the second power signal provided by the second power terminal and the potential of the first node; the second output control circuit controls the potential of the third node to be the second potential in response to the control signal provided by the target control terminal, the third power signal provided by the third power terminal, the potential of the first node and the potential of the second node; the output circuit controls the fourth power terminal to be connected to the output terminal in response to the potential of the second node and the potential of the third node, and controls the fifth power terminal to be disconnected from the output terminal, so as to output the fourth power signal provided by the fourth power terminal as the display driving signal through the output terminal;

[0048] In the second stage, the input circuit controls the potential of the first node to be the first potential in response to the first clock signal, the second clock signal, the input signal, the first power supply signal and the potential of the second node; the first output control circuit controls the potential of the second node to be the second potential in response to the first clock signal, the third clock signal, the second power supply signal and the potential of the first node; the second output control circuit controls the potential of the third node to be the first potential in response to the control signal, the third power supply signal, the potential of the first node and the potential of the second node; the output circuit controls the fourth power supply terminal to be disconnected from the output terminal and controls the fifth power supply terminal to be connected to the output terminal in response to the potential of the second node and the potential of the third node, so as to output the fifth power supply signal provided by the fifth power supply terminal through the output terminal as a display drive signal.

[0049] In yet another aspect, a display driving circuit is provided, comprising: a plurality of cascaded shift register units as described in the above aspect.

[0050] In another aspect, a display device is provided, the display device comprising: a display panel, and the display driving circuit as described in the above another aspect; the display panel comprises a plurality of pixels;

[0051] The display driving circuit is connected to the plurality of pixels via an output terminal and is used to transmit display driving signals to the plurality of pixels to drive the plurality of pixels to emit light.

[0052] In summary, the beneficial effects brought about by the technical solution provided by this application may at least include:

[0053] A shift register unit and a driving method thereof, a display driving circuit, and a display device are provided. The shift register unit includes an input circuit, an output circuit, and an output control circuit. The input circuit and the output control circuit can cooperate with each other to control the output circuit to output a display driving signal to a pixel to drive the pixel to emit light. Since the display driving signal output by the output circuit is a DC power supply signal, compared with outputting a clock signal as a display driving signal, it is beneficial to improve the driving capability of the shift register unit and enhance the display effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0055] Figure 1 is a schematic block diagram of the structure of a shift register unit provided in an embodiment of the present application;

[0056] Figure 2 is a schematic block diagram of the structure of another shift register unit provided in an embodiment of the present application;

[0057] Figure 3 is a schematic diagram of a circuit structure of a shift register unit provided in an embodiment of the present application;

[0058] Figure 4 is a schematic diagram of the circuit structure of another shift register unit provided in an embodiment of the present application;

[0059] Figure 5 is a circuit structure diagram of another shift register unit provided in an embodiment of the present application;

[0060] Figure 6 It is a flowchart of a driving method of a shift register unit provided in an embodiment of the present application;

[0061] Figure 7 It is a signal timing diagram of a shift register unit provided in an embodiment of the present application;

[0062] Figure 8 is a signal timing diagram of another shift register unit provided in an embodiment of the present application;

[0063] Fig. 9 is a schematic block diagram of the structure of a display driving circuit provided in an embodiment of the present application;

[0064] Fig.10 It is a schematic block diagram of the structure of a display device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0065] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0066] It should be noted that the transistor used in the embodiment of the present application may be a thin film transistor (TFT) or a field effect transistor or other devices with the same characteristics. The field effect transistor may be a metal oxide semiconductor (MOS) field effect transistor, also known as a MOS transistor. Moreover, according to the role in the circuit, the transistor used in the embodiment of the present application is mainly a switching transistor. Since the source and drain of the switching transistor used here are symmetrical, the source and drain are interchangeable. In the embodiment of the present application, the source may be referred to as the first electrode and the drain may be referred to as the second electrode. According to the form in the accompanying drawings, the middle end of the transistor is defined as the control electrode, which may also be referred to as the gate, the signal input end is the source electrode, and the signal output signal end is the drain electrode. In addition, the switching transistor used in the embodiment of the present application may include any one of a P-type transistor and an N-type transistor, wherein the P-type transistor is turned on when the gate is at a low potential and is turned off when the gate is at a high potential; the N-type transistor is turned on when the gate is at a high potential and is turned off when the gate is at a low potential. In addition, multiple signals in each embodiment of the present application correspond to a first potential and a second potential. The first potential may refer to an effective potential, and the second potential may refer to an invalid potential. Moreover, the first potential and the second potential only represent that the potential of the signal has two state quantities, and do not represent that the first potential or the second potential has a specific value in the full text.

[0067] At present, in most display screens, such as active matrix organic light-emitting diode (AMOLED) display screens, the GOA units in the Gate GOA circuits use P-type transistors (such as PMOS tubes) to output clock signals to output low voltages row by row to drive the pixels as loads to emit light. However, when the load is large, it is not conducive to improving the driving ability of the GOA unit; and when the clock signal frequency is high, driving the pixels is not conducive to saving the power consumption of the GOA unit.

[0068] Based on this, an embodiment of the present application provides a GOA unit, which can achieve continuous low-voltage output row by row through a PMOS tube, thereby improving the driving ability of the GOA unit and enhancing the display effect. It is understandable that the GOA unit with a low output voltage mentioned here is used to connect the PMOS tube in the pixel. In some embodiments, the GOA unit can also be used to connect the NMOS tube in the pixel, in which case the GOA unit can achieve continuous high-voltage output row by row.

[0069] Figure 1 is a schematic block diagram of the structure of a shift register unit provided in an embodiment of the present application. Figure 1As shown, the shift register unit includes: an input circuit 01 , a first output control circuit 02 , a second output control circuit 03 and an output circuit 04 .

[0070] The input circuit 01 is connected to the first clock terminal CK1, the second clock terminal CK2, the first power supply terminal V1, the input terminal IN, the first node N1 and the second node N2 respectively. In addition, the input circuit 01 is used to control the potential of the first node N1 in response to the first clock signal provided by the first clock terminal CK1, the second clock signal provided by the second clock terminal CK2, the input signal provided by the input terminal IN, the first power supply signal provided by the first power supply terminal V1 and the potential of the second node N2.

[0071] For example, when the potential of the first clock signal provided by the first clock terminal CK1 is the first potential, the input circuit 01 can control the input terminal IN to be connected with the first node N1, so that the input signal provided by the input terminal IN is transmitted to the first node N1, that is, the potential of the first node N1 is controlled to be the potential of the input signal. When the potential of the first clock signal provided by the first clock terminal CK1 is the second potential, the input circuit 01 can control the input terminal IN to be disconnected from the first node N1. When the potential of the second node N2 is the first potential, the input circuit 01 can control the potential of the second node N2 based on the first power supply signal provided by the first power supply terminal V1. When the potential of the second node N2 is the second potential, the input circuit 01 can control the potential of the second node N2 not based on the first power supply signal provided by the first power supply terminal V1. Similarly, when the potential of the first node N1 is the first potential, the input circuit 01 can control the potential of the second node N2 based on the second clock signal provided by the second clock terminal CK2. When the potential of the first node N1 is the second potential, the input circuit 01 can control the potential of the second node N2 not based on the second clock signal provided by the second clock terminal CK2.

[0072] As described above, the first potential refers to the effective potential, and the second potential refers to the invalid potential. Moreover, for a P-type transistor, the effective potential is a lower potential relative to the invalid potential; for an N-type transistor, the effective potential is a higher potential relative to the invalid potential.

[0073] Optionally, the input terminal IN of the n-th shift register unit can be connected to the output terminal OUT of the cascaded ni-th shift register unit to receive the input signal provided by the output terminal of the ni-th shift register unit. Of course, the input terminal IN of the first-stage (i.e., the first-stage) shift register unit can be connected to a separate start signal terminal STV to receive the input signal provided by the start signal terminal STV. Wherein, n and i are both positive integers, and n is less than or equal to the total number of cascaded multi-stage shift register units, and i is less than n.

[0074] The first output control circuit 02 is connected to the first clock terminal CK1, the third clock terminal CK3, the second power supply terminal V2, the first node N1 and the second node N2 respectively. In addition, the first output control circuit 02 is used to control the potential of the second node N2 in response to the first clock signal, the third clock signal provided by the third clock terminal CK3, the second power supply signal provided by the second power supply terminal V2 and the potential of the first node N1.

[0075] For example, the first output control circuit 02 can control the second power supply terminal V2 to be turned on with the second node N2 when the potential of the first clock signal is the first potential, so that the second power supply signal provided by the second power supply terminal V2 is transmitted to the second node N2, that is, the potential of the second node N2 is controlled to be the potential of the second power supply signal. The first output control circuit 02 can control the second power supply terminal V2 to be disconnected from the second node N2 when the potential of the first clock signal is the second potential. The first output control circuit 02 can control the third clock terminal CK3 to be turned on with the second node N2 when the potential of the first node N1 is the first potential, so that the third clock signal provided by the third clock terminal CK3 is transmitted to the second node N2, that is, the potential of the second node N2 is controlled to be the potential of the third clock signal. The first output control circuit 02 can control the third clock terminal CK3 to be disconnected from the second node N2 when the potential of the first node N1 is the second potential.

[0076] The second output control circuit 03 is connected to the target control terminal V0, the third power supply terminal V3, the first node N1, the second node N2 and the third node N3 respectively. In addition, the second output control circuit 03 is used to control the potential of the third node N3 in response to the control signal provided by the target control terminal V0, the third power supply signal provided by the third power supply terminal V3, the potential of the first node N1 and the potential of the second node N2.

[0077] For example, when the potential of the control signal provided by the target control terminal V0 is the first potential, the second output control circuit 03 can control the first node N1 to be connected with the third node N3, so that the signal transmitted to the first node N1 is further transmitted to the third node N3, that is, the potential of the third node N3 is controlled to be the potential of the first node N1. When the potential of the control signal provided by the target control terminal V0 is the second potential, the second output control circuit 03 can control the first node N1 to be disconnected from the third node N3. When the potential of the second node N2 is the first potential, the second output control circuit 03 can control the third power supply terminal V3 to be connected with the third node N3, so that the third power supply signal provided by the third power supply terminal V3 is transmitted to the third node N3, that is, the potential of the third node N3 is controlled to be the potential of the third power supply signal. When the potential of the second node N2 is the second potential, the second output control circuit 03 can control the third power supply terminal V3 to be disconnected from the third node N3.

[0078] The output circuit 04 is connected to the second node N2, the third node N3, the fourth power supply terminal V4, the fifth power supply terminal V5 and the output terminal OUT respectively. In addition, the output circuit 04 is used to control the on-off of the fourth power supply terminal V4 and the output terminal OUT in response to the potential of the second node N2 and the potential of the third node N3, and to control the on-off of the fifth power supply terminal V5 and the output terminal OUT, so as to output the display driving signal through the output terminal OUT.

[0079] For example, the output circuit 04 can control the fourth power supply terminal V4 to be turned on with the output terminal OUT when the potential of the second node N2 is the first potential, so that the fourth power supply signal provided by the fourth power supply terminal V4 is transmitted to the output terminal OUT, that is, the fourth power supply signal is output as a display drive signal through the output terminal OUT. The output circuit 04 can control the fourth power supply terminal V4 to be disconnected from the output terminal OUT when the potential of the second node N2 is the second potential. The output circuit 04 can control the fifth power supply terminal V5 to be turned on with the output terminal OUT when the potential of the third node N3 is the first potential, so that the fifth power supply signal provided by the fifth power supply terminal V5 is transmitted to the output terminal OUT, that is, the fifth power supply signal is output as a display drive signal through the output terminal OUT. The output circuit 04 can control the fifth power supply terminal V5 to be disconnected from the output terminal OUT when the potential of the third node N3 is the second potential.

[0080] Optionally, the display drive signal may be the gate drive signal described above, and accordingly, the output terminal OUT may be connected to the pixel via a gate line. For example, the output terminal OUT may be connected to a PMOS tube in the pixel via a gate line, and output a P-type gate drive signal Gate-P to the PMOS tube. Of course, in some other embodiments, the display drive signal may also be a signal required by other pixels such as a light emitting control signal or a reset control signal.

[0081] Optionally, the first clock signal provided by the first clock terminal CK1, the second clock signal provided by the second clock terminal CK2, and the third clock signal provided by the third clock terminal CK3 may all be periodic pulse signals.

[0082] Optionally, the first power terminal V1, the second power terminal V2, the third power terminal V3, the fourth power terminal V4 and the fifth power terminal V5 can all be DC power terminals that provide DC power signals. The potential of the first power signal provided by the first power terminal V1, the potential of the third power signal provided by the third power terminal V3, and the potential of the fourth power signal provided by the fourth power terminal V4 can all be high potentials; the potential of the second power signal provided by the second power terminal V2 and the potential of the fifth power signal provided by the fifth power terminal V5 can all be low potentials. Here, high potential and low potential are relative. In addition, in the embodiment of the present application, the power terminal that provides a high potential power signal can be referred to as a pull-up power terminal VGH, and the power terminal that provides a low potential power signal can be referred to as a pull-down power terminal VGL.

[0083] In summary, an embodiment of the present application provides a shift register unit. The shift register unit includes an input circuit, an output circuit, and an output control circuit. The input circuit and the output control circuit can cooperate with each other to control the output circuit to output a display drive signal to a pixel to drive the pixel to emit light. Since the display drive signal output by the output circuit is a DC power supply signal, compared with outputting a clock signal as a display drive signal, it is beneficial to improve the driving capability of the shift register unit and enhance the display effect.

[0084] Optionally, Figure 2 FIG. 2 shows a schematic block diagram of another structure of a shift register unit. Figure 2 First, it can be seen that the target control terminal V0 recorded in the embodiment of the present application may include: the sixth power terminal V6 or the fourth clock terminal CK4. Moreover, the fourth clock signal provided by the fourth clock terminal CK4 has the same timing as the third clock signal, and the pulse width of the fourth clock signal is less than or equal to the pulse width of the third clock signal.

[0085] That is, combined Figure 1 , the sixth power supply terminal V6 or the fourth clock terminal CK4 can be used as the target control terminal V0. And it can be understood that when the sixth power supply terminal V6 is used as the target control terminal V0, the control signal provided by the target control terminal V0 is the sixth power supply signal provided by the sixth power supply terminal V6. When the fourth clock terminal CK4 is used as the target control terminal V0, the control signal provided by the target control terminal V0 is the fourth clock signal provided by the fourth clock terminal CK4.

[0086] It can also be understood that the timing of the fourth clock signal and the third clock signal is the same means: in each clock cycle, the rising edge of the fourth clock signal and the rising edge of the third clock signal come at the same time, and the falling edge of the fourth clock signal and the falling edge of the third clock signal come at the same time. The rising edge is the transition edge from low potential to high potential; the falling edge is the transition edge from high potential to low potential. The pulse width of the fourth clock signal is less than or equal to the pulse width of the third clock signal, which means that the duration of the potential of the fourth clock signal at a high potential can be located within the duration of the potential of the third clock signal at a high potential. The high potential duration of the fourth clock signal is either consistent with the high potential duration of the third clock signal; or some margin is left on the left and right. This setting is mainly considered to be in the output stage, either controlling the potential of the second node N2 to be an effective potential, or controlling the potential of the third node N3 to be an effective potential, so that the output circuit 04 controls the fourth power supply terminal V4 or the fifth power supply terminal V5 to be turned on with the output terminal OUT, ensuring the reliable output of the output circuit 04.

[0087] Optionally, like other power supply terminals described above, the sixth power supply terminal V6 may also be a DC power supply terminal that provides a DC power supply signal. Moreover, the potential of the sixth power supply signal provided by the sixth power supply terminal V6 may be a low potential. Of course, in some embodiments, the potential of the sixth power supply signal provided by the sixth power supply terminal V6 may also be a high potential. On this basis, based on the transistor turn-on principle, if the transistor connected to the target control terminal V0 is an N-type transistor, and the potential of the sixth power supply signal provided by the sixth power supply terminal V6 is a low potential, then the turn-on condition of the N-type transistor should satisfy: the difference between the potential of the sixth power supply signal and the potential of the first node N1 is greater than the threshold voltage Vth of the N-type transistor. If the transistor connected to the target control terminal V0 is a P-type transistor, and the potential of the sixth power supply signal provided by the sixth power supply terminal V6 is a high potential, then the turn-on condition of the N-type transistor should satisfy: the difference between the potential of the sixth power supply signal and the potential of the first node N1 is less than the threshold voltage Vth of the N-type transistor. That is, no matter whether the transistor connected to the target control terminal V0 is an N-type transistor or a P-type transistor, when the absolute value of the difference between the potential of the sixth power supply signal and the potential of the first node N1 is greater than the threshold voltage Vth of the transistor, the transistor can be turned on. Of course, when the target control terminal V0 is the fourth clock terminal CK4, the turn-on condition of the transistor is the same and will not be repeated.

[0088] Optionally, at least one of the fifth power supply terminal V5 and the sixth power supply terminal V6 can be shared with the second power supply terminal V2; and / or, at least one of the third power supply terminal V3 and the fourth power supply terminal V4 can be shared with the first power supply terminal V1. It can be understood that sharing multiple power supply terminals also simplifies the multiple power supply terminals into one power supply terminal. In this way, wiring can be simplified, cost can be saved, and a narrow frame design is conducive.

[0089] For example, refer to Figure 2 The third power supply terminal V3 and the fourth power supply terminal V4 shown therein are both shared with the first power supply terminal V1, and are the same pull-up power supply terminal VGH1. The fifth power supply terminal V5 shown therein is shared with the second power supply terminal V2, and are the same pull-down power supply terminal VGL1. And the sixth power supply terminal V6 shown therein can be shared with the second power supply terminal V2, and be the same pull-down power supply terminal VGL1; or, it can also be independent of the second power supply terminal V2, and be another pull-down power supply terminal VGL2; or, it can also be the fourth clock terminal CK4.

[0090] Optionally, continue to refer to Figure 2 It can also be seen that the input circuit 01 may include: a first input sub-circuit 011 , a second input sub-circuit 012 , and a third input sub-circuit 013 .

[0091] The first input subcircuit 011 can be connected to the first clock terminal CK1, the input terminal IN and the first node N1 respectively, and can be used to control the connection between the input terminal IN and the first node N1 in response to the first clock signal to control the potential of the first node N1.

[0092] For example, when the potential of the first clock signal is the first potential, the first input sub-circuit 011 can control the input terminal IN to be connected to the first node N1, so that the input signal provided by the input terminal IN is transmitted to the first node N1, and the potential of the first node N1 is controlled to be the potential of the input signal. And, when the potential of the first clock signal is the second potential, the first input sub-circuit 011 can control the input terminal IN to be disconnected from the first node N1. That is, the first input sub-circuit 011 can control the potential of the first node N1 by controlling the connection between the input terminal IN and the first node N1.

[0093] The second input sub-circuit 012 can be connected to the first node N1, the second node N2, the second clock terminal CK2, the first power supply terminal V1 and the fourth node N4 respectively. In addition, the second input sub-circuit 012 can be used to control the connection and disconnection between the second clock terminal CK2 and the fourth node N4 in response to the potential of the first node N1, and control the connection and disconnection between the first power supply terminal V1 and the fourth node N4 in response to the potential of the second node N2, so as to control the potential of the fourth node N4.

[0094] For example, when the potential of the first node N1 is the first potential, the second input sub-circuit 012 can control the second clock terminal CK2 to be connected to the fourth node N4, so that the second clock signal provided by the second clock terminal CK2 is transmitted to the fourth node N4, and the potential of the fourth node N4 is controlled to be the potential of the second clock signal. When the potential of the first node N1 is the second potential, the second input sub-circuit 012 can control the second clock terminal CK2 to be disconnected from the fourth node N4. Similarly, when the potential of the second node N2 is the first potential, the second input sub-circuit 012 can control the first power supply terminal V1 to be connected to the fourth node N4, so that the first power supply signal provided by the first power supply terminal V1 is transmitted to the fourth node N4, and the potential of the fourth node N4 is controlled to be the potential of the first power supply signal. When the potential of the second node N2 is the second potential, the second input sub-circuit 012 can control the first power supply terminal V1 to be disconnected from the fourth node N4. That is, the second input sub-circuit 012 can control the connection and disconnection between each signal terminal of the second clock terminal CK2 and the first power terminal V1 and the fourth node N4 to control the potential of the fourth node N4.

[0095] The third input sub-circuit 013 may be connected to the fourth node N4 and the first node N1 respectively, and may be used to adjust the potential of the first node N1 based on the potential of the fourth node N4 to control the potential of the first node N1.

[0096] For example, the third input subcircuit 013 can adjust the potential of the first node N1 based on the potential of the fourth node N4 through coupling, thereby controlling the potential of the first node N1. That is, the potential of the first node N1 can be indirectly controlled by the third input subcircuit 013 based on the potential of the fourth node N4.

[0097] Optionally, continue to refer to Figure 2 It can also be seen that the first output control circuit 02 may include: a first control subcircuit 021 and a second control subcircuit 022 .

[0098] The first control subcircuit 021 can be connected to the first clock terminal CK1, the second power terminal V2 and the second node N2 respectively, and can be used to control the connection between the second power terminal V2 and the second node N2 in response to the first clock signal to control the potential of the second node N2.

[0099] For example, when the potential of the first clock signal is the first potential, the first control subcircuit 021 can control the second power supply terminal V2 to be connected to the second node N2, so that the second power supply signal provided by the second power supply terminal V2 is transmitted to the second node N2, and the potential of the second node N2 is controlled to be the potential of the second power supply signal. And, when the potential of the first clock signal is the second potential, the first control subcircuit 021 can control the second power supply terminal V2 to be disconnected from the second node N2. That is, the first control subcircuit 021 can control the potential of the second node N2 by controlling the connection and disconnection of the second power supply terminal V2 and the second node N2.

[0100] The second control subcircuit 022 can be connected to the first node N1, the third clock terminal CK3 and the second node N2 respectively. In addition, the second control subcircuit 022 can be used to control the connection between the third clock terminal CK3 and the second node N2 in response to the potential of the first node N1, so as to control the potential of the second node N2.

[0101] For example, when the potential of the first node N1 is the first potential, the second control subcircuit 022 can control the third clock terminal CK3 to be connected to the second node N2, so that the third clock signal provided by the third clock terminal CK3 is transmitted to the second node N2, and the potential of the second node N2 is controlled to be the potential of the third clock signal. Also, when the potential of the first node N1 is the second potential, the second control subcircuit 022 can control the third clock terminal CK3 to be disconnected from the second node N2. That is, the second control subcircuit 022 can also control the potential of the second node N2 by controlling the connection and disconnection of the third clock terminal CK3 and the second node N2.

[0102] Optionally, continue to refer to Figure 2 It can also be seen that the second output control circuit 03 may include: a third control subcircuit 031 and a fourth control subcircuit 032 .

[0103] The third control subcircuit 031 can be connected to the target control terminal V0, the first node N1 and the third node N3 respectively, and can be used to control the connection between the first node N1 and the third node N3 in response to a control signal to control the potential of the third node N3.

[0104] For example, when the potential of the control signal is the first potential, the third control subcircuit 031 can control the first node N1 and the third node N3 to be turned on, so that the signal transmitted to the first node N1 is further transmitted to the third node N3, and the potential of the third node N3 is controlled to be the potential of the first node N1. And, when the potential of the control signal is the second potential, the third control subcircuit 031 can control the first node N1 to be disconnected from the third node N3. That is, the third control subcircuit 031 can control the potential of the third node N3 by controlling the on-off of the first node N1 and the third node N3.

[0105] The fourth control subcircuit 032 can be connected to the second node N2, the third power supply terminal V3 and the third node N3 respectively. In addition, the fourth control subcircuit 032 can be used to control the connection and disconnection between the third power supply terminal V3 and the third node N3 in response to the potential of the second node N2, so as to control the potential of the third node N3.

[0106] For example, when the potential of the second node N2 is the first potential, the fourth control subcircuit 032 can control the third power supply terminal V3 to be connected to the third node N3, so that the third power signal provided by the third power supply terminal V3 is transmitted to the third node N3, and the potential of the third node N3 is controlled to be the potential of the third power signal. And, when the potential of the second node N2 is the second potential, the fourth control subcircuit 032 can control the third power supply terminal V3 to be disconnected from the third node N3. That is, the fourth control subcircuit 032 can also control the potential of the third node N3 by controlling the connection and disconnection of the third power supply terminal V3 and the third node N3.

[0107] Optionally, continue to refer to Figure 2 It can also be seen that the output circuit 04 may include: a first output sub-circuit 041 and a second output sub-circuit 042 .

[0108] The first output sub-circuit 041 can be connected to the second node N2, the fourth power supply terminal V4 and the output terminal OUT respectively. In addition, the first output sub-circuit 041 can be used to control the on-off of the fourth power supply terminal V4 and the output terminal OUT in response to the potential of the second node N2, so as to output the fourth power supply signal provided by the fourth power supply terminal V4 as the display driving signal through the output terminal OUT, and can also adjust the potential of the second node N2 based on the fourth power supply signal.

[0109] For example, when the potential of the second node N2 is the first potential, the first output sub-circuit 041 controls the fourth power supply terminal V4 to be connected with the output terminal OUT, so that the fourth power supply signal provided by the fourth power supply terminal V4 is transmitted to the output terminal OUT, and the fourth power supply signal is output as a display drive signal via the output terminal OUT. Also, the first output sub-circuit 041 can control the fourth power supply terminal V4 to be disconnected from the output terminal OUT when the potential of the second node N2 is the second potential. That is, the first output sub-circuit 041 can output the display drive signal by controlling the connection and disconnection of the fourth power supply terminal V4 and the output terminal OUT. In addition, the first output sub-circuit 041 can also adjust the potential of the second node N2 based on the fourth power supply signal through coupling.

[0110] The second output sub-circuit 042 can be connected to the third node N3, the fifth power supply terminal V5 and the output terminal OUT respectively. In addition, the second output sub-circuit 042 can be used to control the connection and disconnection of the fifth power supply terminal V5 and the output terminal OUT in response to the potential of the third node N3, so as to output the fifth power supply signal provided by the fifth power supply terminal V5 through the output terminal OUT as a display driving signal.

[0111] For example, the second output sub-circuit 042 can control the fifth power supply terminal V5 to be connected to the output terminal OUT when the potential of the third node N3 is the first potential, so that the fifth power supply signal provided by the fifth power supply terminal V5 is transmitted to the output terminal OUT, and the fifth power supply signal is output as the display driving signal through the output terminal OUT. And, the second output sub-circuit 042 can control the fifth power supply terminal V5 to be disconnected from the output terminal OUT when the potential of the third node N3 is the second potential. That is, the second output sub-circuit 042 can also output the display driving signal by controlling the on and off of the fifth power supply terminal V5 and the output terminal OUT.

[0112] Optionally, continue to refer to Figure 2 It can also be seen that the first node N1 may include: a first subnode N11 and a second subnode N12. The input circuit 01 may be connected to the first subnode N11 and the second subnode N12 respectively, the first output control circuit 02 may be connected to the first subnode N11, and the second output control circuit 03 may be connected to the second subnode N12.

[0113] That is, the first node N1 can be divided into two sub-nodes. In addition, in the input circuit 01, the first input sub-circuit 011 can be connected to the first sub-node N11, and the second input sub-circuit 012 and the third input sub-circuit 013 can be connected to the second sub-node N12. Correspondingly, the first input sub-circuit 011 can be in response to the first clock signal to control the on-off of the input terminal IN and the first sub-node N11. The second input sub-circuit 012 can be in response to the potential of the second sub-node N12 to control the on-off of the second clock terminal CK2 and the fourth node N4. The third input sub-circuit 013 can be based on the potential of the fourth node N4 to adjust the potential of the second sub-node N12. Similarly, in the case where the first output control circuit 02 is connected to the first sub-node N11, the second control sub-circuit 022 can be in response to the potential of the first sub-node N11 to control the on-off of the third clock terminal CK3 and the second node N2. When the second output control circuit 03 is connected to the second sub-node N12, the third control sub-circuit 031 may control the connection between the second sub-node N12 and the third node N3 in response to a control signal.

[0114] On this basis, continue to refer to Figure 2 It can also be seen that the shift register unit recorded in the embodiment of the present application may further include: an isolation circuit 05 .

[0115] The isolation circuit 05 can be connected to the seventh power terminal V7, the first subnode N11 and the second subnode N12 respectively. In addition, the isolation circuit 05 can be used to control the connection and disconnection of the first subnode N11 and the second subnode N12 in response to the seventh power signal provided by the seventh power terminal V7.

[0116] Optionally, like the other power supply terminals described above, the seventh power supply terminal V7 may also be a DC power supply terminal that provides a DC power supply signal. Furthermore, the potential of the seventh power supply signal provided by the seventh power supply terminal V7 may be a low potential, or may also be a high potential. The transistor included in the isolation circuit 05 may be a P-type transistor or an N-type transistor.

[0117] For example, in an embodiment of the present application, the transistor included in the isolation circuit 05 may be a P-type transistor. The potential of the seventh power supply signal provided by the seventh power supply terminal V7 may be a low potential. Moreover, the seventh power supply terminal V7 may be shared with the second power supply terminal V2 of the power supply signal of the same low potential, that is, the same pull-down power supply terminal VGL1. In this way, the isolation circuit 05 may control the first subnode N11 and the second subnode N12 to remain in the on state in response to the seventh power supply signal provided by the seventh power supply terminal V7, so that the signal transmitted to the first subnode N11 is further transmitted to the second subnode N12, and the potential of the second subnode N12 is controlled to be the same as the potential of the first subnode N11. In addition, by setting the isolation circuit 05 to isolate the first subnode N11 and the second subnode N12, leakage can be avoided, ensuring better potential stability of the node.

[0118] Optionally, in Figure 2 Based on this, taking the target control terminal V0 as an independent sixth power terminal V6 as an example, Figure 3 The circuit structure diagram of a shift register unit is schematically shown. Taking the target control terminal V0 as the sixth power terminal V6, and the sixth power terminal V6 is shared with the second power terminal V2 as an example, Figure 4 Another circuit structure diagram of a shift register unit is schematically shown. And, taking the sixth power supply terminal V6 as the fourth clock terminal CK4 as an example, Figure 5 A schematic diagram of the circuit structure of another shift register unit is shown schematically.

[0119] Combination Figures 3 to 5 It can be seen that the first input subcircuit 011 may include: a first transistor T1. The second input subcircuit 012 may include: a second transistor T2 and a third transistor T3. The third input subcircuit 013 may include: a first capacitor C1. The first control subcircuit 021 may include: a fourth transistor T4. The second control subcircuit 022 may include: a fifth transistor T5. The third control subcircuit 031 may include: a sixth transistor T6. The fourth control subcircuit 032 may include: a seventh transistor T7. The first output subcircuit 041 may include: an eighth transistor T8 and a second capacitor C2. The second output subcircuit 042 may include: a ninth transistor T9. The isolation circuit 05 may include: a tenth transistor T10.

[0120] The gate of the first transistor T1 may be connected to the first clock terminal CK1 , the first electrode of the first transistor T1 may be connected to the input terminal IN (eg, STV), and the second electrode of the first transistor T1 may be connected to the first node N1 .

[0121] A gate electrode of the second transistor T2 may be connected to the first node N1 , a first electrode of the second transistor T2 may be connected to the second clock terminal CK2 , and a second electrode of the second transistor T2 may be connected to the fourth node N4 .

[0122] A gate of the third transistor T3 may be connected to the second node N2 , a first electrode of the third transistor T3 may be connected to the first power supply terminal V1 , and a second electrode of the third transistor T3 may be connected to the fourth node N4 .

[0123] The first capacitor C1 may be connected between the fourth node N4 and the first node N1.

[0124] A gate of the fourth transistor T4 may be connected to the first clock terminal CK1 , a first electrode of the fourth transistor T4 may be connected to the second power supply terminal V2 , and a second electrode of the fourth transistor T4 may be connected to the second node N2 .

[0125] A gate of the fifth transistor T5 may be connected to the first node N1 , a first electrode of the fifth transistor T5 may be connected to the third clock terminal CK3 , and a second electrode of the fifth transistor T5 may be connected to the second node N2 .

[0126] A gate of the sixth transistor T6 may be connected to the target control terminal V0 , a first electrode of the sixth transistor T6 may be connected to the first node N1 , and a second electrode of the sixth transistor T6 may be connected to the third node N3 .

[0127] A gate electrode of the seventh transistor T7 may be connected to the second node N2 , a first electrode of the seventh transistor T7 may be connected to the third power supply terminal V3 , and a second electrode of the seventh transistor T7 may be connected to the third node N3 .

[0128] A gate of the eighth transistor T8 may be connected to the second node N2 , a first electrode of the eighth transistor T8 may be connected to the fourth power supply terminal V4 , and a second electrode of the eighth transistor T8 may be connected to the output terminal OUT.

[0129] A gate of the ninth transistor T9 may be connected to the third node N3 , a first electrode of the ninth transistor T9 may be connected to the fifth power supply terminal V5 , and a second electrode of the ninth transistor T9 may be connected to the output terminal OUT.

[0130] The second capacitor C2 may be connected between the fourth power terminal V4 and the second node N2.

[0131] A gate of the tenth transistor T10 may be connected to the seventh power supply terminal V7 , a first electrode of the tenth transistor T10 may be connected to the first subnode N11 , and a second electrode of the tenth transistor T10 may be connected to the second subnode N12 .

[0132] Furthermore, as described above, when the absolute value of the difference between the potential of the control signal and the potential of the first node N1 is greater than the threshold voltage Vth of the sixth transistor T6 , the sixth transistor T6 can be turned on.

[0133] It can be understood that, in combination with the foregoing records, on the basis of dividing the first node N1 into the first sub-node N11 and the second sub-node N12, the second electrode of the first transistor T1 and the gate of the fifth transistor T5 can both be connected to the first sub-node N11; the gate of the second transistor T2, the first electrode of the sixth transistor T6 and the first capacitor C1 can all be connected to the second sub-node N12.

[0134] It is also understandable that, combined with Figures 3 to 5 It can be known that the structure of the shift register unit provided in the embodiment of the present application can be a 10T2C structure, that is, it includes 10 transistors and 2 capacitors. In addition, one transistor (i.e., the sixth transistor T6) among the 10 transistors is an N-type transistor (e.g., an NPMOS tube), and nine transistors (i.e., each transistor other than the sixth transistor T6) are P-type transistors (e.g., a PMOS tube). Of course, in some embodiments, the shift register unit can also be other structures, such as a 9T2C structure. And, each transistor included in the shift register unit can be a P-type transistor or an N-type transistor. The embodiments of the present application do not limit this.

[0135] In summary, an embodiment of the present application provides a shift register unit. The shift register unit includes an input circuit, an output circuit, and an output control circuit. The input circuit and the output control circuit can cooperate with each other to control the output circuit to output a display drive signal to a pixel to drive the pixel to emit light. Since the display drive signal output by the output circuit is a DC power supply signal, compared with outputting a clock signal as a display drive signal, it is beneficial to improve the driving capability of the shift register unit and enhance the display effect.

[0136] The present application also provides a method for driving a shift register unit. The method is used to drive a shift register unit. Figures 1 to 5 Any of the shift register units shown. Figure 6 As shown, the method includes:

[0137] Step 601, in the first stage, the input circuit controls the potential of the first node to be the first potential in response to the first clock signal provided by the first clock terminal, the second clock signal provided by the second clock terminal, the input signal provided by the input terminal, the first power signal provided by the first power terminal and the potential of the second node. The first output control circuit controls the potential of the second node to be the first potential in response to the first clock signal, the third clock signal provided by the third clock terminal, the second power signal provided by the second power terminal and the potential of the first node. The second output control circuit controls the potential of the third node to be the second potential in response to the control signal provided by the target control terminal, the third power signal provided by the third power terminal, the potential of the first node and the potential of the second node. The output circuit controls the fourth power terminal to be turned on and off with the output terminal in response to the potential of the second node and the potential of the third node, and controls the fifth power terminal to be disconnected from the output terminal, so as to output the fourth power signal provided by the fourth power terminal through the output terminal as a display drive signal.

[0138] Step 602, the second stage, the input circuit controls the potential of the first node to be the first potential in response to the first clock signal, the second clock signal, the input signal, the first power supply signal and the potential of the second node, the first output control circuit controls the potential of the second node to be the second potential in response to the first clock signal, the third clock signal, the second power supply signal and the potential of the first node, the second output control circuit controls the potential of the third node to be the first potential in response to the control signal, the third power supply signal, the potential of the first node and the potential of the second node, the output circuit controls the fourth power supply terminal to be disconnected from the output terminal in response to the potential of the second node and the potential of the third node, and controls the fifth power supply terminal to be connected to the output terminal, so as to output the fifth power supply signal provided by the fifth power supply terminal through the output terminal as a display drive signal.

[0139] For example, Figure 3 Take the structure shown as an example, combined with Figure 7 A signal timing diagram of a shift register unit is shown, and the working principle of the shift register unit provided in the embodiment of the present application is described as follows:

[0140] It should be noted that, in any stage, as described above, the potential of the first power signal provided by the first power terminal V1 (i.e., VGH1) can be maintained at a high potential, and the potential of the second power signal provided by the second power terminal V2 (i.e., VGL1) can be maintained at a low potential. Since the third power terminal V3 and the fourth power terminal V4 are both shared with the first power terminal V1, the potential of the third power signal provided by the third power terminal V3 and the potential of the fourth power signal provided by the fourth power terminal V4 are also high potentials. And since the target control terminal V0 and the fifth power terminal V5 are both shared with the second power terminal V2, the potential of the control signal provided by the target control terminal V0 and the potential of the fifth power signal provided by the fifth power terminal V5 are also low potentials. On this basis, it can be seen that the tenth transistor T10 can remain turned on.

[0141] In the t01 stage, the potential of the input signal provided by the input terminal IN (such as STV), the potential of the first clock signal provided by the first clock terminal CK1, and the potential of the third clock signal provided by the third clock terminal CK3 are all high potentials, and the potential of the second clock signal provided by the second clock terminal CK2 is low potential. In addition, the potential of the second power supply signal provided by the second power supply terminal V2 remains at a low potential, the potential of the first subnode N11 and the potential of the second subnode N12 in the first node N1 are both maintained at the high potential of the previous stage, and the potential of the second node N2 remains at the low potential of the previous stage.

[0142] Accordingly, the first transistor T1 , the second transistor T2 , the fourth transistor T4 , the fifth transistor T5 and the sixth transistor T6 can all be controlled to be turned off; and the third transistor T3 , the seventh transistor T7 and the eighth transistor T8 can all be controlled to be turned on.

[0143] On this basis, the high-potential first power signal provided by the first power terminal V1 can be transmitted to the fourth node N4 through the turned-on third transistor T3, and the potential of the fourth node N4 can be controlled to be high. The high-potential third power signal provided by the third power terminal V3 can be transmitted to the third node N3 through the turned-on seventh transistor T7, and the potential of the third node N3 can be controlled to be high. Correspondingly, the ninth transistor T9 can also be controlled to be turned off. And the high-potential fourth power signal provided by the fourth power terminal V4 can be transmitted to the output terminal OUT through the turned-on eighth transistor T8. That is, in the t01 stage, the shift register unit can output a high-potential display drive signal through the output terminal OUT.

[0144] In the t02 stage, the potential of the second clock signal provided by the second clock terminal CK2 can be a high potential, and the potential of the input signal provided by the input terminal IN, the potential of the first clock signal provided by the first clock terminal CK1, and the potential of the third clock signal provided by the third clock terminal CK3 can all be low potentials.

[0145] Accordingly, first, the first transistor T1 and the fourth transistor T4 can be controlled to be turned on. Further, the low-potential input signal provided by the input terminal IN can be transmitted to the first subnode N11 and the second subnode N12 in sequence through the turned-on first transistor T1 and the tenth transistor T10, and the potential of the first subnode N11 and the potential of the second subnode N12 are controlled to be low potential. In addition, the low-potential second power supply signal provided by the second power supply terminal V2 can be transmitted to the second node N2 through the turned-on fourth transistor T4, and the potential of the second node N2 is controlled to be low potential.

[0146] Correspondingly, secondly, the second transistor T2, the third transistor T3, the fifth transistor T5, the seventh transistor T7 and the eighth transistor T8 can also be controlled to be turned on. Furthermore, the high-potential second clock signal provided by the second clock terminal CK2 can be transmitted to the fourth node N4 through the turned-on second transistor T2, and the high-potential first power signal provided by the first power terminal V1 can be transmitted to the fourth node N4 through the turned-on third transistor T3, and the potential of the fourth node N4 can be controlled to be high. On this basis, since the low-potential input signal will also be lost after passing through the first transistor T1, it is not enough to control the sixth transistor T6 to be turned on at this time. Moreover, such control is also to prepare for the coupling of the first capacitor C1 in the next stage. The low-potential third clock signal provided by the third clock terminal CK3 can also be transmitted to the second node N2 through the turned-on fifth transistor T5, and the potential of the second node N2 can be controlled to be low. The high-potential third power signal provided by the third power terminal V3 can also be transmitted to the third node N3 through the turned-on seventh transistor T7, and the potential of the third node N3 can be controlled to be high. Correspondingly, the ninth transistor T9 can also be controlled to be turned off. Furthermore, the high potential fourth power signal provided by the fourth power terminal V4 can continue to be transmitted to the output terminal OUT via the turned-on eighth transistor T8. That is, at stage t02, the shift register unit can continue to output a high potential display driving signal via the output terminal OUT.

[0147] In the t03 stage, similar to the t01 stage, the potential of the input signal provided by the input terminal IN, the potential of the first clock signal provided by the first clock terminal CK1, and the potential of the third clock signal provided by the third clock terminal CK3 are all high potentials, and the potential of the second clock signal provided by the second clock terminal CK2 is low potential. In addition, the potential of the first subnode N11 and the potential of the second subnode N12 can both be maintained at low potentials.

[0148] On this basis, first, the first transistor T1 and the fourth transistor T4 can be controlled to be turned off, and the second transistor T2 and the fifth transistor T5 can be controlled to be turned on. Furthermore, the low-potential second clock signal provided by the second clock terminal CK2 can be transmitted to the fourth node N4 through the turned-on second transistor T2, and the potential of the fourth node N4 can be controlled to be low. And the potential of the high-potential third clock signal provided by the third clock terminal CK3 can be transmitted to the second node N2 by the turned-on fifth transistor T5, and the potential of the second node N2 can be controlled to be high. At the same time, because the potential of the second clock signal provided by the second clock terminal CK2 has jumped from a high potential to a low potential, the potential of the second sub-node N12 can be greatly pulled down through the coupling effect of the first capacitor C1, and the potential of the second sub-node N12 can be controlled to be a sufficiently low low potential. At this time, the absolute value of the difference between the potential of the control signal provided by the target control terminal V0 and the potential of the second sub-node N12 can be greater than the threshold voltage Vth of the sixth transistor T6. Thus, the sixth transistor T6 can also be controlled to be turned on. Furthermore, the low potential signal transmitted to the second sub-node N12 can be further transmitted to the third node N3 via the turned-on sixth transistor T6 , so that the potential of the third node N3 is controlled to be a low potential.

[0149] Correspondingly, the third transistor T3, the seventh transistor T7 and the eighth transistor T8 can be controlled to be turned off, and the ninth transistor T9 can be controlled to be turned on. Furthermore, the low-potential fifth power supply signal provided by the fifth power supply terminal V5 can be transmitted to the output terminal OUT. That is, in the t03 stage, the shift register unit can output a low-potential display drive signal through the output terminal OUT.

[0150] In stage t04, the potential of the input signal provided by the input terminal IN and the potential of the second clock signal provided by the second clock terminal CK2 can both be high potentials, and the potential of the first clock signal provided by the first clock terminal CK1 and the potential of the third clock signal provided by the third clock terminal CK3 can both be low potentials.

[0151] On this basis, first, the first transistor T1 and the fourth transistor T4 can be controlled to be turned on. Then, the high-potential input signal provided by the input terminal IN can be transmitted to the first subnode N11 and the second subnode N12 in sequence through the turned-on first transistor T1 and the tenth transistor T10, and the potential of the first subnode N11 and the potential of the second subnode N12 are controlled to be high potential. In addition, the low-potential second power supply signal provided by the second power supply terminal V2 can be transmitted to the second node N2 through the turned-on fourth transistor T4, and the potential of the second node N2 is controlled to be low potential.

[0152] Correspondingly, secondly, the second transistor T2, the fifth transistor T5 and the sixth transistor T6 can be controlled to be turned off, and the third transistor T3, the seventh transistor T7 and the eighth transistor T8 can be controlled to be turned on. Furthermore, the high-potential first power signal provided by the first power supply terminal V1 can be transmitted to the fourth node N4 through the turned-on third transistor T3, and the potential of the fourth node N4 can be controlled to be high. The high-potential third power signal provided by the third power supply terminal V3 can be transmitted to the third node N3 through the turned-on seventh transistor T7, and the potential of the third node N3 can be controlled to be high. Correspondingly, the ninth transistor T9 can also be controlled to be turned off. And, the high-potential fourth power signal provided by the fourth power supply terminal V4 can also be transmitted to the output terminal OUT through the turned-on eighth transistor T8. That is, in the t04 stage, the shift register unit can output a high-potential display drive signal through the output terminal OUT again.

[0153] It can be understood that the t03 stage is the output stage. And, Figure 4 and Figure 5 The working process of the shift register unit of other circuit structures shown is similar, and will not be described one by one. Figure 8 It can be seen from the signal timing diagram of another shift register unit taking the target control terminal V0 as the fourth clock terminal CK4 as an example that the pulse widths of the fourth clock signal provided by the fourth clock terminal CK4 and the third clock signal provided by the third clock terminal CK3 are each reduced by some margins, that is, the pulse width of the fourth clock signal can be smaller than the pulse width of the third clock signal. Of course, as described above, the fourth clock signal can also be completely consistent with the third clock signal.

[0154] It can be understood that since the driving method of the shift register unit can have substantially the same technical effect as the shift register unit described in the previous embodiment, the technical effect of the driving method of the shift register unit will not be repeatedly shown here for the purpose of brevity.

[0155] The present application also provides a display driving circuit. Fig. 9 As shown, the display driving circuit includes: a plurality of cascaded Figures 1 to 5 Any of the shift register cells shown is also called a GOA cell.

[0156] For example, refer to Fig. 9 In the display driving circuit shown therein, every two adjacent GOA units are cascaded to each other through the output terminal OUT and the input terminal IN. Of course, this is only a schematic illustration.

[0157] It can be understood that, since the display driving circuit can have substantially the same technical effects as the shift register unit described in the previous embodiment, the technical effects of the display driving circuit will not be repeatedly described here for the purpose of brevity.

[0158] The present application also provides a display device. Fig.10 As shown, the display device includes: a display panel 100, and Fig. 9 The display driving circuit 000 is shown.

[0159] The display panel includes a plurality of pixels (not shown in the figure). The display driving circuit 000 is connected to the plurality of pixels via output terminals and is used to transmit display driving signals to the plurality of pixels to drive the plurality of pixels to emit light.

[0160] Optionally, Fig.10 The display driving circuit shown may be a gate driving circuit whose output terminal is connected to a P-type transistor in a pixel through a gate line, and is used to output a P-type gate driving signal Gate-P. Of course, this is only a schematic illustration.

[0161] Optionally, the display device described in the embodiments of the present application may be any product or component with a display function, such as an OLED display device or an AMOLED display device. Also, the display device may be any appropriate display device, including but not limited to any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, and an e-book.

[0162] Furthermore, it can be understood that since the display device can have substantially the same technical effects as the display driving circuit described in the previous embodiment, for the purpose of brevity, the technical effects of the display device will not be repeatedly described herein.

[0163] It should be noted that the terms used in the examples of this application are only used to explain the examples and are not intended to limit this application. Unless otherwise defined, the technical terms or scientific terms used in the embodiments of this application should be the common meanings understood by people with ordinary skills in the field to which this application belongs.

[0164] For example, the words "first", "second" or "third" and similar words used in the patent application specification and claims of this application do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one" or "a" do not indicate a quantitative limitation, but indicate the existence of at least one. Words such as "include" or "comprise" mean that the elements or objects appearing before "include" or "comprise" include the elements or objects listed after "include" or "comprise" and their equivalents, and do not exclude other elements or objects. "Up", "down", "left" or "right" are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly. "Connect" or "couple" refers to electrical connection. "And / or" means that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the objects associated with each other are in an "or" relationship.

[0165] The above description is only an optional embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A shift register unit, characterized in that: The shift register unit comprises: an input circuit, connected to the first clock terminal, the second clock terminal, the first power terminal, the input terminal, the first node, and the second node, respectively, and used to control the potential of the first node in response to a first clock signal provided by the first clock terminal, a second clock signal provided by the second clock terminal, an input signal provided by the input terminal, a first power signal provided by the first power terminal, and a potential of the second node; a first output control circuit, connected to the first clock terminal, the third clock terminal, the second power terminal, the first node and the second node respectively, and used to control the potential of the second node in response to the first clock signal, the third clock signal provided by the third clock terminal, the second power signal provided by the second power terminal and the potential of the first node; a second output control circuit, connected to the target control terminal, the third power terminal, the first node, the second node and the third node respectively, and used to control the potential of the third node in response to a control signal provided by the target control terminal, a third power signal provided by the third power terminal, the potential of the first node and the potential of the second node; The output circuit is connected to the second node, the third node, the fourth power supply terminal, the fifth power supply terminal and the output terminal respectively, and is used to control the on-off connection between the fourth power supply terminal and the output terminal in response to the potential of the second node and the potential of the third node, and to control the on-off connection between the fifth power supply terminal and the output terminal, so as to output a display driving signal through the output terminal.

2. The shift register unit according to claim 1, characterized in that: The target control end includes: a sixth power supply end or a fourth clock end, and the fourth clock signal provided by the fourth clock end has the same timing as the third clock signal, and the pulse width of the fourth clock signal is less than or equal to the pulse width of the third clock signal.

3. The shift register unit according to claim 2, characterized in that: At least one of the fifth power supply terminal and the sixth power supply terminal is shared with the second power supply terminal; and / or at least one of the third power supply terminal and the fourth power supply terminal is shared with the first power supply terminal.

4. The shift register unit according to any one of claims 1 to 3, characterized in that: The input circuit comprises: a first input subcircuit, connected to the first clock terminal, the input terminal and the first node respectively, and used to control the connection and disconnection between the input terminal and the first node in response to the first clock signal, so as to control the potential of the first node; a second input subcircuit, connected to the first node, the second node, the second clock terminal, the first power terminal and the fourth node respectively, and used to control the connection and disconnection between the second clock terminal and the fourth node in response to the potential of the first node, and to control the connection and disconnection between the first power terminal and the fourth node in response to the potential of the second node, so as to control the potential of the fourth node; The third input sub-circuit is connected to the fourth node and the first node respectively, and is used to adjust the potential of the first node based on the potential of the fourth node to control the potential of the first node.

5. The shift register unit according to claim 4, characterized in that: The first input subcircuit includes: a first transistor; the second input subcircuit includes: a second transistor and a third transistor; the third input subcircuit includes: a first capacitor; The gate of the first transistor is connected to the first clock terminal, the first electrode of the first transistor is connected to the input terminal, and the second electrode of the first transistor is connected to the first node; The gate of the second transistor is connected to the first node, the first electrode of the second transistor is connected to the second clock terminal, and the second electrode of the second transistor is connected to the fourth node; The gate of the third transistor is connected to the second node, the first electrode of the third transistor is connected to the first power supply terminal, and the second electrode of the third transistor is connected to the fourth node; The first capacitor is connected between the fourth node and the first node.

6. The shift register unit according to any one of claims 1 to 3, characterized in that: The first output control circuit comprises: a first control subcircuit, connected to the first clock terminal, the second power terminal and the second node respectively, and used to control the connection and disconnection between the second power terminal and the second node in response to the first clock signal, so as to control the potential of the second node; The second control subcircuit is connected to the first node, the third clock terminal and the second node respectively, and is used to control the connection and disconnection of the third clock terminal and the second node in response to the potential of the first node to control the potential of the second node.

7. The shift register unit according to claim 6, characterized in that: The first control subcircuit includes: a fourth transistor; the second control subcircuit includes: a fifth transistor; The gate of the fourth transistor is connected to the first clock terminal, the first electrode of the fourth transistor is connected to the second power supply terminal, and the second electrode of the fourth transistor is connected to the second node; A gate of the fifth transistor is connected to the first node, a first electrode of the fifth transistor is connected to the third clock terminal, and a second electrode of the fifth transistor is connected to the second node.

8. The shift register unit according to any one of claims 1 to 3, characterized in that: The second output control circuit comprises: a third control subcircuit, connected to the target control terminal, the first node and the third node respectively, and used to control the connection and disconnection of the first node and the third node in response to the control signal, so as to control the potential of the third node; The fourth control subcircuit is respectively connected to the second node, the third power supply terminal and the third node, and is used to control the connection and disconnection of the third power supply terminal and the third node in response to the potential of the second node to control the potential of the third node.

9. The shift register unit according to claim 8, characterized in that: The third control subcircuit includes: a sixth transistor; the fourth control subcircuit includes: a seventh transistor; The gate of the sixth transistor is connected to the target control terminal, the first electrode of the sixth transistor is connected to the first node, and the second electrode of the sixth transistor is connected to the third node; The gate of the seventh transistor is connected to the second node, the first electrode of the seventh transistor is connected to the third power supply terminal, and the second electrode of the seventh transistor is connected to the third node; When the absolute value of the difference between the potential of the control signal and the potential of the first node is greater than the threshold voltage of the sixth transistor, the sixth transistor is turned on.

10. The shift register unit according to any one of claims 1 to 3, characterized in that: The output circuit comprises: a first output subcircuit, connected to the second node, the fourth power supply terminal and the output terminal respectively, and used to control the on-off of the fourth power supply terminal and the output terminal in response to the potential of the second node, so as to output the fourth power supply signal provided by the fourth power supply terminal as the display driving signal through the output terminal, and also adjust the potential of the second node based on the first power supply signal; The second output sub-circuit is respectively connected to the third node, the fifth power supply terminal and the output terminal, and is used to control the connection and disconnection of the fifth power supply terminal and the output terminal in response to the potential of the third node, so as to output the fifth power supply signal provided by the fifth power supply terminal through the output terminal as the display drive signal.

11. The shift register unit according to claim 10, characterized in that: The first output sub-circuit includes: an eighth transistor and a second capacitor; the second output sub-circuit includes: a ninth transistor; The gate of the eighth transistor is connected to the second node, the first electrode of the eighth transistor is connected to the fourth power supply terminal, and the second electrode of the eighth transistor is connected to the output terminal; The gate of the ninth transistor is connected to the third node, the first electrode of the ninth transistor is connected to the fifth power supply terminal, and the second electrode of the ninth transistor is connected to the output terminal; The second capacitor is connected between the fourth power supply terminal and the second node.

12. The shift register unit according to any one of claims 1 to 3, characterized in that: The first node includes: a first sub-node and a second sub-node; the input circuit is connected to the first sub-node and the second sub-node respectively, the first output control circuit is connected to the first sub-node, and the second output control circuit is connected to the second sub-node; the shift register unit also includes: The isolation circuit is connected to the seventh power supply terminal, the first sub-node and the second sub-node respectively, and is used to control the connection and disconnection of the first sub-node and the second sub-node in response to a seventh power supply signal provided by the seventh power supply terminal.

13. The shift register unit according to claim 12, characterized in that: The seventh power supply terminal is shared with the second power supply terminal; the isolation circuit comprises: a tenth transistor; A gate of the tenth transistor is connected to the seventh power supply terminal, a first electrode of the tenth transistor is connected to the first sub-node, and a second electrode of the tenth transistor is connected to the second sub-node.

14. A method for driving a shift register unit, characterized in that: Used to drive the shift register unit according to any one of claims 1 to 13; the method comprises: In the first stage, the input circuit controls the potential of the first node to be the first potential in response to the first clock signal provided by the first clock terminal, the second clock signal provided by the second clock terminal, the input signal provided by the input terminal, the first power signal provided by the first power terminal and the potential of the second node; the first output control circuit controls the potential of the second node to be the first potential in response to the first clock signal, the third clock signal provided by the third clock terminal, the second power signal provided by the second power terminal and the potential of the first node; the second output control circuit controls the potential of the third node to be the second potential in response to the control signal provided by the target control terminal, the third power signal provided by the third power terminal, the potential of the first node and the potential of the second node; the output circuit controls the fourth power terminal to be connected to the output terminal in response to the potential of the second node and the potential of the third node, and controls the fifth power terminal to be disconnected from the output terminal, so as to output the fourth power signal provided by the fourth power terminal as the display driving signal through the output terminal; In the second stage, the input circuit controls the potential of the first node to be the first potential in response to the first clock signal, the second clock signal, the input signal, the first power supply signal and the potential of the second node; the first output control circuit controls the potential of the second node to be the second potential in response to the first clock signal, the third clock signal, the second power supply signal and the potential of the first node; the second output control circuit controls the potential of the third node to be the first potential in response to the control signal, the third power supply signal, the potential of the first node and the potential of the second node; the output circuit controls the fourth power supply terminal to be disconnected from the output terminal and controls the fifth power supply terminal to be connected to the output terminal in response to the potential of the second node and the potential of the third node, so as to output the fifth power supply signal provided by the fifth power supply terminal through the output terminal as a display drive signal.

15. A display driving circuit, characterized in that: The display driving circuit comprises: a plurality of cascaded shift register units according to any one of claims 1 to 13.

16. A display device, characterized in that: The display device comprises: a display panel, and a display driving circuit as claimed in claim 15; the display panel comprises a plurality of pixels; The display driving circuit is connected to the plurality of pixels via an output terminal and is used to transmit display driving signals to the plurality of pixels to drive the plurality of pixels to emit light.

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