Shift register, gate drive circuit and display device

Abstract

The invention provides a shift register, a gate drive circuit and a display device, belongs to the technical field of display, and can solve the problem that an existing display product is likely to have poor horizontal black lines. The shifting register comprises an input sub-circuit which is configured to respond to an input signal input by a signal input end and write the input signal into a pull-up node so as to charge the pull-up node; the output sub-circuit is configured to respond to the potential of the pull-up node and output a clock signal input by a clock signal end through a signal output end; the pull-up reset sub-circuit is configured to respond to a pull-up reset signal input by a pull-up reset signal end and reset the potential of the pull-up node through a non-working level signal input by a non-working level signal end; and the channel width of the thin film transistor in the pull-up reset sub-circuit is greater than that of the thin film transistor in the output sub-circuit.

Description

Technical Field

[0001] The present disclosure belongs to the field of display technology, and particularly relates to a shift register, a gate driving circuit and a display device. Background Art

[0002] In recent years, the development of displays has gradually shown a trend of high integration and low cost. One of the most important technologies is the mass production of the Gate Driver on Array (GOA) technology. The GOA technology integrates the gate drive circuit composed of thin film transistors (TFT) on the array substrate of the display panel to form a scan drive for the display panel, thereby eliminating the gate drive integrated circuit part. It can not only reduce product costs in terms of material cost and manufacturing process, but also achieve a beautiful design of symmetry on both sides and narrow frame of the display panel. Summary of the invention

[0003] The present disclosure aims to solve at least one of the technical problems existing in the prior art, and provides a shift register, a gate driving circuit and a display device.

[0004] In a first aspect, an embodiment of the present disclosure provides a shift register, the shift register comprising: an input subcircuit, an output subcircuit and a pull-up reset subcircuit;

[0005] The input subcircuit is connected to the signal input terminal and the pull-up node, and is configured to respond to the input signal input by the signal input terminal, and write the input signal to the pull-up node to charge the pull-up node; the output subcircuit is connected to the pull-up node, the clock signal input terminal and the signal output terminal, and is configured to respond to the potential of the pull-up node, and output the clock signal input by the clock signal terminal through the signal output terminal; the pull-up reset subcircuit is connected to the pull-up node, the pull-up reset signal terminal and the non-working level signal terminal, and is configured to respond to the pull-up reset signal input by the pull-up reset signal terminal, and reset the potential of the pull-up node through the non-working level signal input by the non-working level signal terminal;

[0006] The channel width of the thin film transistor in the pull-up reset subcircuit is greater than the channel width of the thin film transistor in the output subcircuit.

[0007] In some embodiments, the first electrode of the thin film transistor in the output subcircuit includes: a plurality of first extension portions and at least one second extension portion; the second electrode of the thin film transistor in the output subcircuit includes: a plurality of first U-shaped portions;

[0008] The first extension portion and the second extension portion extend into the corresponding opening of the first U-shaped portion respectively; at least one second extension portion is located on at least one side of the plurality of first extension portions;

[0009] The width of the second extending portion is greater than the width of the first extending portion.

[0010] In some embodiments, the first electrode of the thin film transistor in the pull-up reset subcircuit includes: a plurality of third extensions and at least one fourth extension; the second electrode of the thin film transistor in the pull-up reset subcircuit includes: a plurality of second U-shaped portions;

[0011] The third extension portion and the fourth extension portion extend into the corresponding opening of the second U-shaped portion respectively; at least one of the fourth extension portions is located on at least one side of the plurality of third extension portions;

[0012] The width of the fourth extending portion is greater than the width of the third extending portion.

[0013] In some embodiments, the input subcircuit includes: a first transistor; the pull-up reset subcircuit includes: a second transistor; the output subcircuit includes: a third transistor and a storage capacitor;

[0014] The control electrode of the first transistor and the first electrode are connected to the signal input terminal, and the second electrode is connected to the pull-up node; the control electrode of the second transistor is connected to the pull-up reset signal terminal, the first electrode is connected to the pull-up node, and the second electrode is connected to the non-working level signal terminal; the control electrode of the third transistor is connected to the pull-up node, the first electrode is connected to the clock signal terminal, and the second electrode is connected to the signal output terminal; one end of the storage capacitor is connected to the pull-up node, and the other end is connected to the signal output terminal.

[0015] In some embodiments, the shift register further comprises: a discharge subcircuit; the discharge subcircuit is connected to the frame start signal terminal, the non-working level signal terminal and the pull-up node, and is configured to respond to the frame start signal input by the frame start signal terminal, and discharge the pull-up node through the non-working level signal input by the non-working level signal terminal;

[0016] The channel width of the thin film transistor in the discharge sub-circuit is greater than the channel width of the thin film transistor in the output sub-circuit.

[0017] In some embodiments, the first electrode of the thin film transistor in the discharge sub-circuit includes: a plurality of fifth extensions and at least one sixth extension; the second electrode of the thin film transistor in the discharge sub-circuit includes: a plurality of third U-shaped portions;

[0018] The fifth extension portion and the sixth extension portion extend into the corresponding opening of the third U-shaped portion respectively; at least one sixth extension portion is located on at least one side of the plurality of fifth extension portions;

[0019] The width of the sixth extension portion is greater than the width of the fifth extension portion.

[0020] In some embodiments, the discharge subcircuit includes: a seventh transistor; the control electrode of the seventh transistor is connected to the frame start signal terminal, the first electrode is connected to the pull-up node, and the second electrode is connected to the non-working level signal terminal.

[0021] In some embodiments, the shift register further includes: a noise reduction subcircuit; the noise reduction subcircuit is connected to the pull-down node, the non-working level signal terminal and the pull-up node, and is configured to reduce the noise of the pull-up node through the non-working level signal input by the non-working level signal terminal in response to the potential of the pull-down node;

[0022] The channel width of the thin film transistor in the noise reduction sub-circuit is greater than the channel width of the thin film transistor in the output sub-circuit.

[0023] In some embodiments, the first electrode of the thin film transistor in the noise reduction sub-circuit includes: a plurality of seventh extension portions and at least one eighth extension portion; the second electrode of the thin film transistor in the noise reduction sub-circuit includes: a plurality of fourth U-shaped portions;

[0024] The seventh extension portion and the eighth extension portion extend into the corresponding opening of the fourth U-shaped portion respectively; at least one of the eighth extension portions is located on at least one side of the plurality of the seventh extension portions;

[0025] The width of the eighth extending portion is greater than the width of the seventh extending portion.

[0026] In some embodiments, the noise reduction sub-circuit includes: a tenth transistor; the control electrode of the tenth transistor is connected to the pull-down node, the first electrode is connected to the pull-up node, and the second electrode is connected to the non-working level signal terminal.

[0027] In some embodiments, a channel width of the thin film transistor in the input sub-circuit is greater than a channel width of the thin film transistor in the output sub-circuit.

[0028] In a second aspect, an embodiment of the present disclosure provides a gate driving circuit, wherein the gate driving circuit includes a plurality of cascaded shift registers as provided in the first aspect.

[0029] In a third aspect, an embodiment of the present disclosure provides a display device, comprising a gate driving circuit as provided in the second aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 A schematic diagram of the structure of an exemplary shift register.

[0031] Figure 2 for Figure 1 A schematic diagram of the local structure of a thin film transistor in a shift register is shown.

[0032] Figure 3 A schematic diagram of a partial structure of a thin film transistor in a shift register provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0033] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all of the embodiments. The components of the embodiments of the present disclosure generally described and shown in the drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present disclosure provided in the drawings is not intended to limit the scope of the present disclosure claimed for protection, but merely represents the selected embodiments of the present disclosure. Based on the embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present disclosure. In the absence of conflict, the various embodiments of the present disclosure and the various features in the embodiments can be combined with each other.

[0034] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, similar words such as "one", "one" or "the" do not indicate quantitative restrictions, but indicate that there is at least one. "Including" or "comprising" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects.

[0035] The "multiple or several" mentioned in this disclosure refers to two or more. "And / or" describes the association relationship of the associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the associated objects before and after are in an "or" relationship.

[0036] It should be noted that the transistors in the embodiments of the present disclosure may be thin film transistors or field effect transistors or other switching devices with the same characteristics. The thin film transistors may include oxide semiconductor thin film transistors, amorphous silicon thin film transistors or polycrystalline silicon thin film transistors, etc. The source and drain of the transistor may be symmetrical in structure, so the source and drain may be indistinguishable in physical structure. In the embodiments of the present disclosure, in order to distinguish transistors, except for the gate as the control electrode, one of the electrodes is directly described as the first electrode and the other electrode is directly described as the second electrode, so the first electrode and the second electrode of all or part of the transistors in the embodiments of the present disclosure can be interchangeable as needed.

[0037] It should be noted that the thin film transistor can be an N-type thin film transistor or a P-type thin film transistor; wherein, the N-type thin film transistor refers to the thin film transistor active layer being doped with N-type ions; and the P-type thin film transistor refers to the thin film transistor active layer being doped with P-type ions. The working level voltage of the N-type thin film transistor is a high level voltage, that is, when a high level voltage is input to the gate of the N-type thin film transistor, the source and the drain are turned on; the working level voltage of the P-type thin film transistor is a low level voltage, that is, when a low level voltage is input to the gate of the P-type thin film transistor, the source and the drain are turned on. In the embodiments disclosed herein, the N-type thin film transistor will be used as an example for explanation. It can be understood that the implementation principle of the P-type transistor is similar to that of the P-type transistor and will not be described in detail.

[0038] Among them, since the transistor used in the embodiment of the present disclosure is an N-type transistor, the working level signal in the embodiment of the present disclosure refers to a high level signal, and the non-working level signal is a low level signal; the corresponding working level end is a high level signal end, and the non-working level end is a low level signal end.

[0039] Usually, the display panel includes a plurality of gate lines and a plurality of data lines, and the gate lines and the data lines are cross-arranged to define a plurality of pixel areas, and each pixel area is provided with a pixel unit. The structure of the display panel is described by taking the extension direction of each gate line as the row direction and the extension direction of each data line as the column direction as an example. When the display panel is driven to display, a scanning signal can be written to the gate line row by row according to the picture to be displayed, and a data voltage signal can be written to each data line at the same time, so that the pixel units in the display panel are lit up row by row.

[0040] The scanning signal is provided by the gate driving circuit, and the data voltage signal is provided by the source driving circuit. In the related art, the gate driving circuit can be integrated into the gate driving chip, and the source driving circuit can be integrated into the source driving chip. At present, in order to reduce the number of chips and realize narrow frame or no frame, a GOA technology is provided to integrate the gate driving circuit on the array substrate. The gate driving circuit includes a plurality of cascaded shift registers integrated on the array substrate, each shift register is connected to the gate line one by one, and is used to provide a scanning signal for the gate line connected thereto.

[0041] In recent years, with the continuous development of display technology, the refresh rate of display products has also been continuously improved, especially the refresh rate of e-sports display products has developed from 100 Hz to 144Hz, 240Hz, 360Hz, etc. However, with the increase in refresh rate, the defect of horizontal black lines on the display screen is more frequent. In addition, the width of the horizontal black line defect is not fixed, and it is obvious on monochrome screens. The defect is aggravated as the refresh rate decreases. For example, compared with the display screen with a refresh rate of 60Hz, the horizontal black line defect phenomenon on the display screen with a refresh rate of 48Hz is significantly aggravated.

[0042] Figure 1 is a schematic diagram of an exemplary structure of a shift register, such as Figure 1 As shown, the shift register includes: an input subcircuit, an output subcircuit, and a pull-up reset subcircuit; wherein the input subcircuit is connected to the signal input terminal INPUT and the pull-up node PU, and is configured to respond to the input signal input by the signal input terminal INPUT, and write the input signal into the pull-up node PU to charge the pull-up node PU; the output subcircuit is connected to the pull-up node PU, the clock signal terminal CLK and the signal output terminal OUTPUT, and is configured to respond to the potential of the pull-up node PU, and output the clock signal input by the clock signal terminal CLK through the signal output terminal OUTPUT; the pull-up reset subcircuit is connected to the pull-up node PU, the pull-up reset signal terminal RESET_PU and the low-level signal terminal VGL, and is configured to respond to the pull-up reset signal input by the pull-up reset signal terminal RESET_PU, and reset the potential of the pull-up node PU through the low-level signal input by the low-level signal terminal VGL.

[0043] Specifically, Figure 1As shown, the input sub-circuit includes: a first transistor M1; the pull-up reset sub-circuit includes: a second transistor M2; the output sub-circuit includes: a third transistor M3 and a storage capacitor C; wherein, the gate and source of the first transistor M1 are connected to the signal input terminal INPUT, and the drain is connected to the pull-up node PU; the gate of the second transistor M2 is connected to the pull-up reset signal terminal RESET_PU, the source is connected to the pull-up node PU, and the drain is connected to the low-level signal terminal VGL; the gate of the third transistor M3 is connected to the pull-up node PU, the source is connected to the clock signal terminal CLK, and the drain is connected to the signal output terminal OUTPUT; one end of the storage capacitor C is connected to the pull-up node PU, and the other end is connected to the signal output terminal OUTPUT.

[0044] like Figure 1 As shown, the shift register further includes: a pull-down control subcircuit, a pull-down subcircuit, a noise reduction subcircuit, a discharge subcircuit and a cascade subcircuit; wherein the pull-down control subcircuit includes: a first pull-down control subcircuit and a second pull-down control subcircuit; the pull-down subcircuit includes: a first pull-down subcircuit and a second pull-down subcircuit; the noise reduction subcircuit includes: a first noise reduction subcircuit and a second noise reduction subcircuit. The first pull-down control subcircuit and the second pull-down control subcircuit have the same structure and function, and the two only work in time sharing; similarly, the first pull-down subcircuit and the second pull-down subcircuit have the same structure and function; the first noise reduction subcircuit and the second noise reduction subcircuit have the same structure and function.

[0045] The first pull-down control sub-circuit is connected to the first power supply voltage signal terminal VDDO and the first pull-down node PD1, and is configured to respond to the first power supply voltage input by the first power supply voltage signal terminal VDDO, input the first power supply voltage input by the first power supply voltage signal terminal VDDO to the first pull-down node PD1, so as to control the potential of the first pull-down node PD1; the second pull-down control sub-circuit is connected to the second power supply voltage signal terminal VDDE and the second pull-down node PD2, and is configured to respond to the second power supply voltage input by the second power supply voltage signal terminal VDDE, input the second power supply voltage input by the second power supply voltage signal terminal VDDE to the second pull-down node PD2, so as to control the potential of the second pull-down node PD2; the first pull-down sub-circuit is connected to the pull-up node PU, the low-level signal terminal VGL, the first pull-down node PD1 and the first pull-down control node PD_CN1, and is configured to respond to the potential of the pull-up node PU, and pull down the potential of the first pull-down node PD1 and the first pull-down control node PD_CN1 through the low-level signal input by the low-level signal terminal VGL; the second pull-down sub-circuit is connected to the pull-up node PU, the low-level signal terminal VGL, the first pull-down node PD1 and the first pull-down control node PD_CN1. The first noise reduction sub-circuit is connected to the first pull-down node PD1, the low-level signal terminal VGL, the pull-up node PU, the signal output terminal OUTPUT, and the cascade signal output terminal OUT_C, and is configured to respond to the potential of the first pull-down node PD1, and pull down the potential of the second pull-down node PD2 and the second pull-down control node PD_CN2 through the low-level signal input by the low-level signal terminal VGL. The low-level signal input from the signal terminal VGL reduces the noise of the pull-up node PU, the signal output terminal OUTPUT, and the cascade signal output terminal OUT_C; the second noise reduction sub-circuit is connected to the second pull-down node PD2, the low-level signal terminal VGL, the pull-up node PU, the signal output terminal OUTPUT, and the cascade signal output terminal OUT_C, and is configured to respond to the potential of the second pull-down node PD2, and reduce the noise of the pull-up node PU, the signal output terminal OUTPUT, and the cascade signal output terminal OUT_C ​​through the low-level signal input from the low-level signal terminal VGL. The discharge sub-circuit is connected to the frame start signal terminal STV, the low-level signal terminal VGL, and the pull-up node PU, and is configured to respond to the frame start signal input from the frame start signal terminal STV, and discharge the pull-up node PU through the low-level signal input from the low-level signal terminal VGL. The cascade subcircuit is connected to the pull-up node PU, the clock signal terminal CLK, and the cascade signal output terminal OUT_C, and is configured to output the clock signal input by the clock signal terminal CLK to other cascaded shift registers through the cascade signal output terminal OUT_C ​​in response to the potential of the pull-up node PU.

[0046] It should be noted that the signals output by the cascade signal output terminal OUT_C ​​and the signal output terminal OUTPUT are the same, except that two output terminals are set in the shift register unit, one is the signal output terminal OUTPUT connected to the gate line, and the other is the cascade signal output terminal OUT_C ​​used for cascading. The reason for setting the cascade sub-circuit separately is to reduce the load of the signal output terminal OUTPUT to avoid affecting the scanning signal output by the signal output terminal OUTPUT.

[0047] Specifically, Figure 1 As shown, the first pull-down control subcircuit and the second pull-down control subcircuit both include a fifth transistor and a ninth transistor; wherein the fifth transistor in the first pull-down control subcircuit and the second control subcircuit are represented by M5 and M5', respectively, and the ninth transistor is represented by M9 and M9', respectively. The first pull-down subcircuit and the second pull-down subcircuit both include a sixth transistor and an eighth transistor; wherein the sixth transistor in the first pull-down subcircuit and the second pull-down subcircuit are represented by M6 and M6', respectively, and the eighth transistor is represented by M8 and M8', respectively. The first noise reduction subcircuit and the second noise reduction subcircuit both include a tenth transistor, an eleventh transistor, and a twelfth transistor; wherein the tenth transistor in the first noise reduction subcircuit and the second noise reduction subcircuit are represented by M10 and M10', respectively, the eleventh transistor is represented by M11 and M11', respectively, and the twelfth transistor is represented by M12 and M12', respectively; the discharge subcircuit includes a seventh transistor M7.

[0048] Among them, the gate and source of the fifth transistor M5 are both connected to the first power supply voltage terminal VDDO, and the drain is connected to the first pull-down control node PD_CN1; the gate of the ninth transistor M9 is connected to the first pull-down control node PD_CN1, the source is connected to the first power supply voltage terminal VDDO, and the drain is connected to the first pull-down node PD1; the gate and source of the fifth transistor M5' are both connected to the second power supply voltage terminal VDDE, and the drain is connected to the second pull-down control node PD_CN2; the gate of the ninth transistor M9' is connected to the second pull-down control node PD_CN2, the source is connected to the second power supply voltage terminal VDDE, and the drain is connected to the first pull-down node PD1; the gate of the sixth transistor M6 is connected to the pull-up node PU, the source is connected to the first pull-down node PD1, and the drain is connected to the low-level signal terminal VGL; the gate of the eighth transistor M8 is connected to the pull-up node PU, the source is connected to the first pull-down control node PD_CN1, and the drain is connected to the low-level signal terminal VGL; the gate of the sixth transistor M6' is connected to the pull-up node PU , the source is connected to the second pull-down node PD2, and the drain is connected to the low-level signal terminal VGL; the gate of the eighth transistor M8' is connected to the pull-up node PU, the source is connected to the second pull-down control node PD_CN2, and the drain is connected to the low-level signal terminal; the gate of the tenth transistor M10 is connected to the first pull-down node PD1, the source is connected to the pull-up node PU, and the drain is connected to the low-level signal terminal VGL; the gate of the eleventh transistor M11 is connected to the first pull-down node PD1, the source is connected to the signal output terminal OUTPUT, and the drain is connected to the low-level signal terminal VGL; the gate of the tenth transistor M10' is connected to the second pull-down node PD2, the source is connected to the pull-up node PU, and the drain is connected to the low-level signal terminal VGL; the gate of the eleventh transistor M11' is connected to the second pull-down node PD2, the source is connected to the signal output terminal OUTPUT, and the drain is connected to the low-level signal terminal VGL; the gate of the seventh transistor M7 is connected to the frame start signal terminal STV, the source is connected to the pull-up node PU, and the drain is connected to the low-level signal terminal VGL. The cascade subcircuit includes a thirteenth transistor M13, the gate of the thirteenth transistor M13 is connected to the pull-up node PU, the source is connected to the clock signal terminal CLK, and the drain is connected to the cascade signal output terminal OUT_C. At the same time, a twelfth transistor is also provided in the first noise reduction subcircuit and the second noise reduction subcircuit, respectively represented by M12 and M12', for noise reduction of the signal output by the cascade signal output terminal OUT_C. The gate of the twelfth transistor M12 is connected to the first pull-down node PD1, the source is connected to the cascade signal output terminal OUT_C, and the drain is connected to the low-level signal terminal VGL; the gate of the twelfth transistor M12' is connected to the second pull-down node PD2, the source is connected to the cascade signal output terminal OUT_C, and the drain is connected to the low-level signal terminal VGL.

[0049] Among them, the fifth transistor M5 and the ninth transistor M9 form a first pull-down control subcircuit and the fifth transistor M5' and the ninth transistor M9' form a second pull-down control subcircuit and work in time sharing (that is, work in turns); correspondingly, since the first noise reduction subcircuit composed of the tenth transistor M10 and the eleventh transistor M11 and the second noise reduction subcircuit composed of the tenth transistor M10' and the eleventh transistor M11' are respectively controlled by the first pull-down control subcircuit and the second pull-down control subcircuit, the first noise reduction subcircuit and the second noise reduction subcircuit also work in time sharing. The working principles of the first pull-down control subcircuit and the second pull-down control subcircuit are the same, and the working principles of the first noise reduction subcircuit and the second noise reduction subcircuit are the same; therefore, the following only describes the working principle of the shift register when the first pull-down control subcircuit and the first noise reduction subcircuit are working. It should be noted here that Figure 1 In the circuit structure shown, some low-level signal terminals can be represented by VGL or LVGL. The low-level signal terminal LVGL can provide a signal with a lower potential than the lower-level signal terminal VGL, which can more fully lower the potential of the corresponding point.

[0050] In the input stage, a high-level signal is written into the signal input terminal INPUT, the first transistor M1 is turned on, the potential of the pull-up node PU is pulled up by the high-level signal, and the storage capacitor C is charged.

[0051] In the output stage, since the potential of the pull-up node PU is pulled high in the input stage, the third transistor M3 is turned on, and the high level signal input by the clock signal terminal CLK is output to the gate line connected to the shift register through the signal output terminal OUTPUT.

[0052] In the closing stage, the frame start signal terminal STV inputs a high-level signal, the seventh transistor M7 is turned on, and the pull-up node PU is discharged through the low-level signal input by the low-level signal terminal VGL to prevent the residual charge of the pull-up node PU from causing display abnormalities. The pull-up reset signal terminal RESET_PU inputs a high-level signal, the second transistor M2 is turned on, and the low-level signal input by the low-level signal terminal VGL pulls down the potential of the pull-up node PU to reset the pull-up node PU. Since the pull-up node PU is pulled down, the third transistor M3 is turned off, and the signal output terminal OUTPUT and the cascade signal output terminal OUT_C ​​no longer output high-level signals. At the same time, the first pull-down control node PD_CN1 and the pull-down node are both high-level signals, the tenth transistor M10 and the eleventh transistor M11 are turned on, and the outputs of the pull-up node PU, the signal output terminal OUTPUT, and the cascade signal output terminal OUT_C ​​are respectively denoised, until the next frame scan starts and the potential of the pull-up node PU is pulled up.

[0053] In actual applications, the voltage of each node in the sample was monitored and it was found that the voltage of the pull-up node PU in the bad sample (NG) was low in the output stage, the voltage was insufficient, and the voltage dropped from 41.6V to 30.5V, while the voltage of the pull-up node PU of the normal sample (OK) dropped from 44.6V to 35.1V in the output stage. The delay time of the voltage at the signal output terminal OUTPUT of the normal sample in the closing stage was 2.9μs, and the delay time of the voltage at the signal output terminal OUTPUT of the bad sample in the closing stage was 11.5μs. The delay time of the output voltage of the bad sample in the closing stage increased.

[0054] After research, it was found that the input subcircuit is responsible for inputting signals and pulling up the voltage of the pull-up node PU, while the pull-up reset subcircuit, discharge subcircuit and noise reduction subcircuit are responsible for pulling down the voltage of the pull-up node PU. Since the channel size of the thin film transistors in the input subcircuit, pull-up reset subcircuit, discharge subcircuit and noise reduction subcircuit of the defective sample is relatively small, the smaller the channel size, the greater the leakage current. According to the analysis of the voltage results of each node, in the output stage, due to the large leakage of the thin film transistors in the input subcircuit, pull-up reset subcircuit, discharge subcircuit and noise reduction subcircuit of the defective sample, the voltage of the pull-up node PU is reduced, and the voltage is insufficient. When the clock signal is output, the voltage of the pull-up node PU is low, resulting in a decrease in the output capacity of the thin film transistor in the output subcircuit, which in turn increases the delay time of the output voltage, and the data signal is mischarged, resulting in the appearance of horizontal black line defects.

[0055] Figure 2 for Figure 1 The schematic diagram of the local structure of the thin film transistor in the shift register shown in FIG. Figure 2 As shown, the source of the thin film transistor includes: a plurality of extensions 301; the drain includes: a plurality of U-shaped portions 302. The extensions 301 extend into the openings of the corresponding U-shaped portions 302. The thin film transistor also includes other structures such as a channel portion, Figure 2 Since the channel size of the thin film transistor in the shift register will cause the horizontal black line to be bad, it is necessary to measure and control the channel size of the thin film transistor. At the same time, in order to narrow the frame and reduce the load, the width of the extension part 301 of the thin film transistor is required to be smaller and smaller. When measuring the channel width of the thin film transistor, due to the influence of the extension part 301, there are many mismeasurements when monitoring the channel width, and the channel width of the thin film transistor cannot be accurately monitored.

[0056] In order to solve at least one of the above-mentioned technical problems, the embodiments of the present disclosure provide a shift register, a gate drive circuit and a display device. The shift register, the gate drive circuit and the display device provided by the embodiments of the present disclosure will be further described in detail below in combination with the accompanying drawings and specific implementation methods.

[0057] In a first aspect, an embodiment of the present disclosure provides a shift register, the circuit structure of the shift register is similar to Figure 1 The structure of the shift register shown is the same as Figure 1 As shown, the shift register includes: an input subcircuit, an output subcircuit, and a pull-up reset subcircuit; wherein the input subcircuit is connected to the signal input terminal INPUT and the pull-up node PU, and is configured to respond to the input signal input by the signal input terminal INPUT, and write the input signal to the pull-up node PU to charge the pull-up node PU; the output subcircuit is connected to the pull-up node PU, the clock signal terminal CLK and the signal output terminal OUTPUT, and is configured to respond to the potential of the pull-up node PU, and output the clock signal input by the clock signal terminal CLK through the signal output terminal OUTPUT; the pull-up reset subcircuit is connected to the pull-up node PU, the pull-up reset signal terminal RESET_PU and the low-level signal terminal VGL, and is configured to respond to the pull-up reset signal input by the pull-up reset signal terminal RESET_PU, and reset the potential of the pull-up node PU through the low-level signal input by the low-level signal terminal VGL. The channel width of the thin film transistor in the pull-up reset subcircuit is greater than the channel width of the thin film transistor in the output subcircuit.

[0058] It should be noted that the working principle of the shift register provided in the embodiment of the present disclosure is similar to the above Figure 1 The working principle of the shift register shown in is the same as that of the embodiment, and will not be described in detail here.

[0059] In the shift register provided by the embodiment of the present disclosure, the input subcircuit is responsible for inputting signals in the input stage and pulling up the voltage of the pull-up node PU, the pull-up reset subcircuit is responsible for lowering the voltage of the pull-up node PU in the output stage, and the output subcircuit is responsible for outputting the gate drive signal in the output stage. Since the channel width of the thin film transistor in the pull-up reset subcircuit is relatively large, for example, the channel width of the thin film transistor in the pull-up reset subcircuit is larger than the channel width of the thin film transistor in the output subcircuit, the leakage current of the thin film transistor in the pull-up reset subcircuit can be reduced, ensuring that the voltage of the pull-up node PU can be sufficiently maintained in the output stage, so that the voltage of the pull-up node PU is high enough in the off stage, avoiding the output capacity of the thin film transistor in the output subcircuit from decreasing, thereby reducing the delay time of the output voltage, and further preventing the data signal from being mischarged and causing poor horizontal black lines, so as to improve the display effect and enhance the user experience.

[0060] In some embodiments, Figure 3 A schematic diagram of a partial structure of a thin film transistor in a shift register provided in an embodiment of the present disclosure, such as Figure 3As shown, the thin film transistor can be a thin film transistor in an output sub-circuit, and the source electrode of the thin film transistor in the output sub-circuit includes: multiple first extension portions 3011 and at least one second extension portion 3012 (for example, 3 second extension portions); the second electrode of the thin film transistor in the output sub-circuit includes: multiple first U-shaped portions 3021; ​​the first extension portions 3011 and the second extension portions 3012 respectively extend into the openings of the corresponding first U-shaped portions 3021; ​​at least one second extension portion 3012 is located on at least one side of the multiple first extension portions 3011; the width of the second extension portion 3012 is greater than the width of the first extension portion 3011.

[0061] The channel size of the thin film transistor in the output subcircuit is very critical and affects the normal operation of the shift register. At the same time, the overall area of ​​the thin film transistor in the output subcircuit is large and easy to identify. Therefore, the thin film transistor in the output subcircuit can be used as a channel size monitoring unit to monitor the channel size of the thin film transistor in the shift register. Figure 3 In the embodiment, the source electrode of the thin film transistor in the output sub-circuit includes: a plurality of first extension portions 3011 and at least one second extension portion 3012; the second electrode of the thin film transistor in the output sub-circuit includes: a plurality of first U-shaped portions 3021; ​​the first extension portions 3011 and the second extension portions 3012 extend into the openings of the corresponding first U-shaped portions 3021 respectively; at least one second extension portion 3012 is located on at least one side of the plurality of first extension portions 3011 (for example, the edge of the overall region where the thin film transistor is located), Figure 3 Only the case where the second extension portion 3012 is located on the right side of the first extension portion 3011 is shown. Since the width of the second extension portion 3012 is greater than the width of the first extension portion 3011, the second extension portion 3012 is easily identified during the detection process. When the channel size of the thin film transistor is monitored, the second extension portion 3012 can be directly identified to avoid the influence of the second extension portion 3012 on the measurement of the channel size of the thin film transistor, thereby avoiding mismeasurement when monitoring the channel width, thereby improving the accuracy of monitoring the channel width of the thin film transistor and improving the stability of each thin film transistor in the shift register.

[0062] In some embodiments, the source of the thin film transistor in the pull-up reset subcircuit includes: multiple third extension portions and at least one fourth extension portion; the second electrode of the thin film transistor in the pull-up reset subcircuit includes: multiple second U-shaped portions; the third extension portion and the fourth extension portion respectively extend into the openings of the corresponding second U-shaped portions; at least one fourth extension portion is located on at least one side of the multiple third extension portions; and the width of the fourth extension portion is greater than the width of the third extension portion.

[0063] It should be noted that the structure of the third extension portion is Figure 3The structure of the first extension portion 3011 is the same as that of the fourth extension portion. Figure 3 The structure of the second extension portion 3012 is the same as that of the second U-shaped portion. Figure 3 The structure of the first U-shaped portion 3021 is the same as that of the first U-shaped portion 3021 in FIG. Figure 3 .

[0064] The channel size of the thin film transistor in the pull-up reset subcircuit affects the defect of the horizontal black line. The thin film transistor in the pull-up reset subcircuit can be used as a monitoring unit of the channel size to monitor the channel size of the thin film transistor in the shift register. The source of the thin film transistor in the pull-up reset subcircuit includes: multiple third extensions and at least one fourth extension; the drain of the thin film transistor in the pull-up reset subcircuit includes: multiple second U-shaped portions; the third extension and the fourth extension respectively extend into the opening of the corresponding second U-shaped portion; at least one fourth extension is located on at least one side of the multiple third extensions (for example, the edge of the overall area where the thin film transistor is located). Since the width of the fourth extension is greater than the width of the third extension, the fourth extension is easy to be identified during the detection process. When monitoring the channel size of the thin film transistor, the fourth extension can be directly identified to avoid the influence of the fourth extension on the measurement of the channel size of the thin film transistor, thereby avoiding mismeasurement when monitoring the channel width, thereby improving the accuracy of monitoring the channel width of the thin film transistor and improving the stability of each thin film transistor in the shift register.

[0065] Specifically, Figure 1 As shown, the output sub-circuit includes a first transistor M1; the pull-up reset sub-circuit includes a second transistor M2; the output sub-circuit includes a third transistor M3 and a storage capacitor C; wherein, the gate and source of the first transistor M1 are connected to the signal input terminal INPUT, and the drain is connected to the pull-up node PU; the gate of the second transistor M2 is connected to the pull-up reset signal terminal RESET_PU, the source is connected to the pull-up node PU, and the drain is connected to the low-level signal terminal VGL; the gate of the third transistor M3 is connected to the pull-up node PU, the source is connected to the clock signal terminal CLK, and the drain is connected to the signal output terminal OUTPUT; one end of the storage capacitor C is connected to the pull-up node PU, and the other end is connected to the signal output terminal OUTPUT; the channel width of the second transistor M2 is greater than the channel width of the third transistor M3.

[0066] For example, the difference between the channel width of the second transistor M2 and the channel width of the third transistor M3 is 0.1-1.0 μm, and specifically may be 0.5 μm.

[0067] For example, the width of the second extension portion 3012 in the third transistor M3 is greater than the width of the first extension portion 3011 , and the difference between the width of the second extension portion 3012 and the width of the first extension portion 3011 is 0.5-2 μm, and specifically may be 1.0 μm.

[0068] For example, the width of the fourth extension portion of the second transistor M2 is greater than the width of the third extension portion, and the difference between the width of the fourth extension portion and the width of the third extension portion is 0.5-2 μm, and specifically may be 1.0 μm.

[0069] In some embodiments, Figure 1 As shown, the shift register also includes: a discharge sub-circuit; the discharge sub-circuit is connected to the frame start signal terminal STV, the low-level signal terminal VGL and the pull-up node PU, and is configured to respond to the frame start signal input by the frame start signal terminal STV, and discharge the pull-up node PU through the low-level signal input by the low-level signal terminal VGL; the channel width of the thin film transistor in the discharge sub-circuit is greater than the channel width of the thin film transistor in the output sub-circuit.

[0070] The discharge subcircuit is responsible for lowering the voltage of the pull-up node PU in the output stage. Since the channel width of the thin film transistor in the discharge subcircuit is relatively large, for example, the channel width of the thin film transistor in the discharge subcircuit is greater than the channel width of the thin film transistor in the output subcircuit, the leakage current of the thin film transistor in the discharge subcircuit can be reduced, ensuring that the voltage of the pull-up node PU can be sufficiently maintained in the output stage, so that the voltage of the pull-up node PU is high enough in the off stage, avoiding the output capacity of the thin film transistor in the output subcircuit from decreasing, thereby reducing the delay time of the output voltage, and further preventing the data signal from being mischarged and causing poor horizontal black lines, so as to improve the display effect and enhance the user experience.

[0071] In some embodiments, the source of the thin film transistor in the discharge circuit includes: multiple fifth extension portions and at least one sixth extension portion; the drain of the thin film transistor in the discharge circuit includes: multiple third U-shaped portions; the fifth extension portion and the sixth extension portion respectively extend into the openings of the corresponding third U-shaped portions; at least one sixth extension portion is located on at least one side of the multiple fifth extension portions; and the width of the sixth extension portion is greater than the width of the fifth extension portion.

[0072] It should be noted that the structure of the fifth extension portion is Figure 3 The structure of the first extension portion 3011 is the same as that of the sixth extension portion. Figure 3 The structure of the second extension portion 3012 is the same as that of the third U-shaped portion. Figure 3 The structure of the first U-shaped portion 3021 is the same as that of the first U-shaped portion 3021 in FIG. Figure 3 .

[0073] The channel size of the thin film transistor in the discharge circuit affects the defect of the horizontal black line. The thin film transistor in the discharge circuit can be used as a monitoring unit of the channel size to monitor the channel size of the thin film transistor in the shift register. The source of the thin film transistor in the discharge circuit includes: a plurality of fifth extensions and at least one sixth extension; the drain of the thin film transistor in the discharge circuit includes: a plurality of third U-shaped portions; the fifth extension and the sixth extension respectively extend into the opening of the corresponding third U-shaped portion; at least one sixth extension is located on at least one side of the plurality of fifth extensions (for example, the edge of the overall area where the thin film transistor is located). Since the width of the sixth extension is greater than the width of the fifth extension, the sixth extension is easy to be identified during the detection process. When monitoring the channel size of the thin film transistor, the sixth extension can be directly identified to avoid the influence of the sixth extension on the measurement of the channel size of the thin film transistor, thereby avoiding mismeasurement when monitoring the channel width, thereby improving the accuracy of monitoring the channel width of the thin film transistor and improving the stability of each thin film transistor in the shift register.

[0074] Specifically, the discharge subcircuit includes: a seventh transistor M7; the gate of the seventh transistor M7 is connected to the frame start signal terminal STV, the source is connected to the pull-up node PU, and the drain is connected to the low level signal terminal VGL; the channel width of the seventh transistor M7 is greater than the channel width of the third transistor M3.

[0075] For example, the difference between the channel width of the seventh transistor M7 and the channel width of the third transistor M3 is 0.1-1.0 μm, and specifically may be 0.5 μm.

[0076] For example, the width of the sixth extension portion in the seventh transistor M7 is greater than the width of the fifth extension portion, and the difference between the width of the sixth extension portion and the width of the fifth extension portion is 0.5-2 μm, and may be specifically 1.0 μm.

[0077] In some embodiments, Figure 1 As shown, the shift register also includes: a noise reduction sub-circuit; the noise reduction sub-circuit is connected to the pull-down node PD (the first pull-down node PD1 or the second pull-down node PD2), the low-level signal terminal VGL and the pull-up node PU, and is configured to respond to the potential of the pull-down node PD (the first pull-down node PD1 or the second pull-down node PD2), and reduce the noise of the pull-up node PU through the low-level signal input by the low-level signal terminal; the channel width of the thin film transistor in the noise reduction sub-circuit is greater than the channel width of the thin film transistor in the output sub-circuit.

[0078] The noise reduction sub-circuit is responsible for lowering the voltage of the pull-up node PU in the output stage. Since the channel width of the thin film transistor in the noise reduction sub-circuit is relatively large, for example, the channel width of the thin film transistor in the noise reduction sub-circuit is greater than the channel width of the thin film transistor in the output sub-circuit, the leakage current of the thin film transistor in the noise reduction sub-circuit can be reduced, ensuring that the voltage of the pull-up node PU can be sufficiently maintained in the output stage, so that the voltage of the pull-up node PU is high enough in the shutdown stage, avoiding the output capacity of the thin film transistor in the output sub-circuit from decreasing, thereby reducing the delay time of the output voltage, and further preventing the data signal from being mischarged and causing poor horizontal black lines, so as to improve the display effect and enhance the user experience.

[0079] In some embodiments, the source of the thin film transistor in the noise reduction sub-circuit includes: multiple seventh extension portions and at least one eighth extension portion; the drain of the thin film transistor in the noise reduction sub-circuit includes: multiple fourth U-shaped portions; the seventh extension portion and the eighth extension portion respectively extend into the openings of the corresponding fourth U-shaped portions; at least one eighth extension portion is located on at least one side of the multiple seventh extension portions; and the width of the eighth extension portion is greater than the width of the seventh extension portion.

[0080] It should be noted that the structure of the seventh extension portion is similar to Figure 3 The structure of the first extension portion 3011 is the same as that of the eighth extension portion. Figure 3 The structure of the second extension portion 3012 is the same as that of the fourth U-shaped portion. Figure 3 The structure of the first U-shaped portion 3021 is the same as that of the first U-shaped portion 3021 in FIG. Figure 3 .

[0081] The channel size of the thin film transistor in the noise reduction subcircuit affects the defect of the horizontal black line. The thin film transistor in the noise reduction subcircuit can be used as a monitoring unit of the channel size to monitor the channel size of the thin film transistor in the shift register. The source of the thin film transistor in the noise reduction subcircuit includes: multiple seventh extensions and at least one eighth extension; the drain of the thin film transistor in the noise reduction subcircuit includes: multiple fourth U-shaped parts; the seventh extension and the eighth extension respectively extend into the opening of the corresponding fourth U-shaped part; at least one eighth extension is located on at least one side of the multiple seventh extensions (for example, the edge of the overall area where the thin film transistor is located). Since the width of the eighth extension is greater than the width of the seventh extension, the eighth extension is easy to be identified during the detection process. When monitoring the channel size of the thin film transistor, the eighth extension can be directly identified to avoid the influence of the eighth extension on the measurement of the channel size of the thin film transistor, thereby avoiding mismeasurement when monitoring the channel width, and further improving the accuracy of monitoring the channel width of the thin film transistor and improving the stability of each thin film transistor in the shift register.

[0082] Specifically, the noise reduction sub-circuit includes: a tenth transistor, which is represented by M10 and M10'; the gate of the tenth transistor M10 is connected to the first pull-down node PD1, the source is connected to the pull-up node PU, and the drain is connected to the low-level signal terminal VGL; the gate of the tenth transistor M10' is connected to the second pull-down node PD2, the source is connected to the pull-up node PU, and the drain is connected to the low-level signal terminal VGL; the channel width of the tenth transistor M10 / M10' is greater than the channel width of the third transistor M3.

[0083] For example, the difference between the channel width of the tenth transistor M10 / M10 ′ and the channel width of the third transistor M3 is 0.1-1.0 μm, and specifically may be 0.5 μm.

[0084] For example, the width of the eighth extension portion in the tenth transistor M10 / M10 ′ is greater than the width of the seventh extension portion, and the difference between the width of the eighth extension portion and the width of the seventh extension portion is 0.5-2 μm, and specifically may be 1.0 μm.

[0085] In some embodiments, a channel width of a thin film transistor in the input sub-circuit is greater than a channel width of a thin film transistor in the output sub-circuit.

[0086] The input subcircuit is responsible for inputting signals in the input stage and pulling up the voltage of the pull-up node PU. Since the channel width of the thin film transistor in the input subcircuit is relatively large, for example, the channel width of the thin film transistor in the input subcircuit is greater than the channel width of the thin film transistor in the output subcircuit, the leakage current of the thin film transistor in the input subcircuit can be reduced, ensuring that the voltage of the pull-up node PU can be sufficiently maintained in the output stage, so that the voltage of the pull-up node PU is high enough in the off stage, avoiding the output capacity of the thin film transistor in the output subcircuit from decreasing, thereby reducing the delay time of the output voltage, and further preventing the data signal from being mischarged and causing poor horizontal black lines, so as to improve the display effect and enhance the user experience.

[0087] For example, the difference between the channel width of the first transistor M1 and the channel width of the third transistor M3 is 0.1-1.0 μm, and specifically may be 0.5 μm.

[0088] It should be noted that, in addition to the above-mentioned sub-circuits, the shift register provided in the embodiment of the present disclosure also includes other sub-circuits, which can be specifically as follows: Figure 1 Of course, each sub-circuit in the shift register may also be a structure in the related art, which will not be described in detail here.

[0089] In a second aspect, an embodiment of the present disclosure provides a gate drive circuit, the gate drive circuit comprising a plurality of cascaded shift registers as provided in any of the above embodiments. For example, the number of stages of the shift register may be N stages, wherein the signal input terminal INPUT of the first stage shift register is connected to the frame start signal terminal STV; the signal input terminal INPUT of the i+1th stage shift register is connected to the cascade signal output terminal OUT_C ​​of the i-th stage shift register; N is a positive integer greater than 1, and i is a positive integer less than or equal to N.

[0090] The gate driving circuit provided in the embodiment of the present disclosure is configured to provide an on or off signal to the gate of the thin film transistor in each pixel driving circuit, so that the pixel driving circuit controls the light-emitting device to emit light.

[0091] It should be noted that the light-emitting devices involved in the embodiments of the present disclosure may include but are not limited to organic light-emitting diodes (OLED), quantum dot light-emitting diodes (QLED) or micro light-emitting diodes (MicroLED). Optionally, the light-emitting device is an OLED device.

[0092] For the description of the specific structure of the shift register, please refer to the detailed description of the shift register mentioned above, and the repeated parts will not be repeated here.

[0093] In a third aspect, an embodiment of the present disclosure provides a display device, which includes a gate drive circuit of any one of the above embodiments. The display device can be, for example, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a vehicle-mounted device, or any other product with a display function. Other essential components of the display device should be understood by a person of ordinary skill in the art, and will not be described in detail here, nor should they be used as a limitation to the present disclosure.

[0094] It should be noted that in the accompanying drawings, the sizes of layers and regions may be exaggerated for clarity of illustration. It is also understood that when an element or layer is referred to as being "on" another element or layer, it may be directly on the other element, or there may be an intermediate layer. In addition, it is understood that when an element or layer is referred to as being "under" another element or layer, it may be directly under the other element, or there may be more than one intermediate layer or element. In addition, it is also understood that when a layer or element is referred to as being "between" two layers or two elements, it may be the only layer between the two layers or two elements, or there may also be more than one intermediate layer or element. Similar reference numerals throughout the text indicate similar elements.

[0095] In the several embodiments provided in the present disclosure, it should be understood that the disclosed device can be implemented in other ways. For example, the device embodiments described above are only schematic, for example, the position of the components shown is only a logical functional position, and there may be other position arrangements in actual implementation.

[0096] It is to be understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of the present disclosure, but the present disclosure is not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and substance of the present disclosure, and these modifications and improvements are also considered to be within the scope of protection of the present disclosure.

Claims

1. A shift register, characterized in that: The shift register comprises: an input subcircuit, an output subcircuit and a pull-up reset subcircuit; The input subcircuit is connected to the signal input terminal and the pull-up node, and is configured to respond to the input signal input by the signal input terminal, and write the input signal to the pull-up node to charge the pull-up node; the output subcircuit is connected to the pull-up node, the clock signal input terminal and the signal output terminal, and is configured to respond to the potential of the pull-up node, and output the clock signal input by the clock signal terminal through the signal output terminal; the pull-up reset subcircuit is connected to the pull-up node, the pull-up reset signal terminal and the non-working level signal terminal, and is configured to respond to the pull-up reset signal input by the pull-up reset signal terminal, and reset the potential of the pull-up node through the non-working level signal input by the non-working level signal terminal; The channel width of the thin film transistor in the pull-up reset subcircuit is greater than the channel width of the thin film transistor in the output subcircuit.

2. The shift register according to claim 1, characterized in that: The first electrode of the thin film transistor in the output sub-circuit includes: a plurality of first extension portions and at least one second extension portion; the second electrode of the thin film transistor in the output sub-circuit includes: a plurality of first U-shaped portions; The first extension portion and the second extension portion extend into the corresponding opening of the first U-shaped portion respectively; at least one second extension portion is located on at least one side of the plurality of first extension portions; The width of the second extending portion is greater than the width of the first extending portion.

3. The shift register according to claim 1, characterized in that: The first electrode of the thin film transistor in the pull-up reset subcircuit includes: a plurality of third extension portions and at least one fourth extension portion; the second electrode of the thin film transistor in the pull-up reset subcircuit includes: a plurality of second U-shaped portions; The third extension portion and the fourth extension portion extend into the corresponding opening of the second U-shaped portion respectively; at least one of the fourth extension portions is located on at least one side of the plurality of third extension portions; The width of the fourth extending portion is greater than the width of the third extending portion.

4. The shift register according to claim 1, wherein: The input subcircuit includes: a first transistor; the pull-up reset subcircuit includes: a second transistor; the output subcircuit includes: a third transistor and a storage capacitor; The control electrode of the first transistor and the first electrode are connected to the signal input terminal, and the second electrode is connected to the pull-up node; the control electrode of the second transistor is connected to the pull-up reset signal terminal, the first electrode is connected to the pull-up node, and the second electrode is connected to the non-working level signal terminal; the control electrode of the third transistor is connected to the pull-up node, the first electrode is connected to the clock signal terminal, and the second electrode is connected to the signal output terminal; one end of the storage capacitor is connected to the pull-up node, and the other end is connected to the signal output terminal.

5. The shift register according to claim 1, characterized in that: The shift register further comprises: a discharge subcircuit; the discharge subcircuit is connected to the frame start signal terminal, the non-working level signal terminal and the pull-up node, and is configured to respond to the frame start signal input from the frame start signal terminal, and discharge the pull-up node through the non-working level signal input from the non-working level signal terminal; The channel width of the thin film transistor in the discharge sub-circuit is greater than the channel width of the thin film transistor in the output sub-circuit.

6. The shift register according to claim 5, characterized in that: The first electrode of the thin film transistor in the discharge sub-circuit comprises: a plurality of fifth extension portions and at least one sixth extension portion; the second electrode of the thin film transistor in the discharge sub-circuit comprises: a plurality of third U-shaped portions; The fifth extension portion and the sixth extension portion extend into the corresponding opening of the third U-shaped portion respectively; at least one sixth extension portion is located on at least one side of the plurality of fifth extension portions; The width of the sixth extension portion is greater than the width of the fifth extension portion.

7. The shift register according to claim 5, characterized in that: The discharge subcircuit comprises: a seventh transistor; the control electrode of the seventh transistor is connected to the frame start signal terminal, the first electrode is connected to the pull-up node, and the second electrode is connected to the non-working level signal terminal.

8. The shift register according to claim 1 or 5, characterized in that: The shift register further includes: a noise reduction subcircuit; the noise reduction subcircuit is connected to the pull-down node, the non-working level signal terminal and the pull-up node, and is configured to reduce the noise of the pull-up node through the non-working level signal input by the non-working level signal terminal in response to the potential of the pull-down node; The channel width of the thin film transistor in the noise reduction sub-circuit is greater than the channel width of the thin film transistor in the output sub-circuit.

9. The shift register according to claim 8, characterized in that: The first electrode of the thin film transistor in the noise reduction sub-circuit includes: a plurality of seventh extension portions and at least one eighth extension portion; the second electrode of the thin film transistor in the noise reduction sub-circuit includes: a plurality of fourth U-shaped portions; The seventh extension portion and the eighth extension portion extend into the corresponding opening of the fourth U-shaped portion respectively; at least one of the eighth extension portions is located on at least one side of the plurality of the seventh extension portions; The width of the eighth extending portion is greater than the width of the seventh extending portion.

10. The shift register according to claim 9, characterized in that: The noise reduction sub-circuit comprises: a tenth transistor; a control electrode of the tenth transistor is connected to a pull-down node, a first electrode is connected to a pull-up node, and a second electrode is connected to a non-working level signal terminal.

11. The shift register according to claim 1, characterized in that: A channel width of the thin film transistor in the input sub-circuit is greater than a channel width of the thin film transistor in the output sub-circuit.

12. A gate drive circuit, characterized in that: The gate driving circuit includes a plurality of shift registers according to any one of claims 1 to 11 connected in cascade.

13. A display device, characterized in that: The display device comprises the gate driving circuit as claimed in claim 12.

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