Shift register and driving method thereof, gate driving circuit and display device

Abstract

The embodiment of the invention provides a shift register and a driving method thereof, a gate driving circuit and a display device. The shift register comprises an input circuit used for providing a signal of an input power supply end for a pull-up node under the control of a signal input end; the first pull-down circuit is used for providing a signal of a third power supply end for the first pull-down node under the control of the pull-up node; the first pull-down control circuit is used for providing a signal of the first power supply end for the first auxiliary node under the control of the first power supply end; the suppression circuit is used for disconnecting the first auxiliary node and the first pull-down node based on a signal of a control signal end under the condition that the signal of the pull-up node is a starting signal; and the first output circuit is used for providing a signal of a clock signal end for a first output end under the control of the starting signal of the pull-up node. The shift register can bear high voltage.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a shift register and a driving method thereof, a gate driving circuit and a display device. Background Art

[0002] With the rapid development of electronic paper, users have put forward higher requirements for electronic paper products, such as high-quality full-color electronic paper. Full-color electronic paper (ACeP) is composed of four colors of ink particles (usually including yellow, cyan, magenta, and white). Its working principle is to apply an electric field and use the principle of positive and negative attraction to push the ink particles of the corresponding pigments to the display side for mixing to present a variety of colors (about 50,000 colors).

[0003] As the number of ink particles increases, the required driving voltage also increases. Related projects require that electronic paper products can withstand higher voltages, such as ±38V, but existing products are difficult to achieve. Summary of the invention

[0004] Embodiments of the present disclosure provide a shift register and a driving method thereof, a gate driving circuit and a display device to solve or alleviate one or more technical problems in the prior art.

[0005] As a first aspect of an embodiment of the present disclosure, an embodiment of the present disclosure provides a shift register, including:

[0006] An input circuit is coupled to the signal input terminal, the input power terminal and the pull-up node respectively, and is configured to provide the signal of the input power terminal to the pull-up node under the control of the signal of the signal input terminal;

[0007] A first pull-down circuit is coupled to the pull-up node, the third power supply terminal and the first pull-down node respectively, and is configured to provide a signal of the third power supply terminal to the first pull-down node under the control of a signal of the pull-up node;

[0008] A first pull-down control circuit is coupled to the first power supply terminal and the first auxiliary node respectively, and is configured to provide a signal of the first power supply terminal to the first auxiliary node under the control of a signal of the first power supply terminal;

[0009] an inhibition circuit, coupled to the control signal terminal, the first auxiliary node and the first pull-down node respectively, and configured to disconnect the first auxiliary node and the first pull-down node based on the signal of the control signal terminal when the signal of the pull-up node is an on signal;

[0010] A first output circuit is coupled to the pull-up node, the clock signal terminal and the first output terminal respectively, and is configured to provide a signal of the clock signal terminal to the first output terminal under the control of a start signal of the pull-up node;

[0011] The first output pull-down circuit is coupled to the first pull-down node, the fourth power supply terminal and the first output terminal respectively, and is configured to provide a signal of the fourth power supply terminal to the first output terminal under the control of the first pull-down node.

[0012] In some embodiments, the suppression circuit is further configured to, when the signal of the pull-up node is a shutdown signal, enable the first auxiliary node and the first pull-down node to be conductive based on the signal of the control signal terminal.

[0013] In some embodiments, the suppression circuit includes a nineteenth transistor, a gate of the nineteenth transistor is coupled to a control node, the control node is coupled to a control signal terminal, and a first electrode and a second electrode of the nineteenth transistor are coupled to a first auxiliary node and a first pull-down node, respectively.

[0014] In some embodiments, the suppression circuit further includes a state control subcircuit, the state control subcircuit being coupled to the control signal terminal, the first voltage signal, the second voltage signal, and the control node, respectively;

[0015] The state control subcircuit is configured to provide a first voltage signal to the control node based on the signal at the control signal terminal when the signal at the pull-up node is an on signal, so that the first electrode and the second electrode of the nineteenth transistor are disconnected; and / or,

[0016] The state control subcircuit is configured to provide a second voltage signal to the control node based on the signal of the control signal terminal when the signal of the pull-up node is a shutdown signal, so as to turn on the first electrode and the second electrode of the nineteenth transistor.

[0017] In some embodiments, the state control subcircuit satisfies at least one of the following:

[0018] The state control subcircuit includes a first control transistor, a gate of the first control transistor is coupled to the control signal terminal, a first electrode and a second electrode of the first control transistor are coupled to the first voltage signal and the control node respectively, and when the signal of the pull-up node is an on signal, the signal of the control signal terminal controls the first control transistor to be turned on;

[0019] The state control subcircuit includes a second control transistor, a gate of the second control transistor is coupled to the control signal terminal, a first electrode and a second electrode of the second control transistor are coupled to the second voltage signal and the control node respectively, and when the signal of the pull-up node is a shutdown signal, the signal of the control signal terminal controls the second control transistor to turn on.

[0020] In some embodiments, the first control transistor includes an NMOS and the second control transistor includes a PMOS.

[0021] In some embodiments,

[0022] The level state of the control signal terminal is the same as that of the pull-up node;

[0023] The signal at the control signal end includes a first preset signal and a second preset signal, and level states of the first preset signal and the second preset signal are opposite.

[0024] In some embodiments, the control signal terminal is coupled to the pull-up node.

[0025] In some embodiments, it also includes:

[0026] A second pull-down circuit is coupled to the pull-up node, the third power supply terminal, and the second pull-down node, respectively, and is configured to provide a signal of the third power supply terminal to the second pull-down node under the control of a signal of the pull-up node;

[0027] A second pull-down control circuit is coupled to the second power supply terminal and the second auxiliary node respectively, and is configured to provide a signal of the second power supply terminal to the second auxiliary node under the control of a signal of the second power supply terminal;

[0028] A second output pull-down circuit is coupled to the second pull-down node, the fourth power supply terminal and the first output terminal respectively, and is configured to provide a signal of the fourth power supply terminal to the first output terminal under the control of the second pull-down node;

[0029] The inhibition circuit is also coupled to the second auxiliary node and the second pull-down node, and is also configured to disconnect the second auxiliary node and the second pull-down node based on the signal at the control signal end when the signal at the pull-up node is an on signal; and / or, the inhibition circuit is also configured to turn on the second auxiliary node and the second pull-down node based on the signal at the control signal end when the signal at the pull-up node is a off signal.

[0030] In some embodiments, the suppression circuit includes a twenty-ninth transistor, the gate of the twenty-ninth transistor is coupled to the control node, the control node is connected to the control signal terminal, and the first electrode and the second electrode of the twenty-ninth transistor are coupled to the second auxiliary node and the second pull-down node respectively.

[0031] In some embodiments, at least one of the following is also included:

[0032] A first auxiliary pull-down circuit is coupled to the signal input terminal, the third power terminal and the first pull-down node respectively, and is configured to provide a signal from the third power terminal to the first pull-down node under the control of a signal from the signal input terminal;

[0033] A first noise reduction circuit is coupled to the first pull-down node, the third power supply terminal and the pull-up node respectively, and is configured to provide a signal of the third power supply terminal to the pull-up node under the control of a signal of the first pull-down node;

[0034] A second auxiliary pull-down circuit is coupled to the signal input terminal, the third power terminal and the second pull-down node respectively, and is configured to provide a signal from the third power terminal to the second pull-down node under the control of a signal from the signal input terminal;

[0035] A second noise reduction circuit is coupled to the second pull-down node, the third power supply terminal and the pull-up node respectively, and is configured to provide a signal of the third power supply terminal to the pull-up node under the control of a signal of the second pull-down node;

[0036] A row reset circuit is coupled to the row reset signal terminal, the third power supply terminal and the pull-up node respectively, and is configured to provide a signal from the third power supply terminal to the pull-up node under the control of a signal from the row reset signal terminal;

[0037] A frame reset circuit is coupled to the frame reset signal terminal, the third power terminal and the pull-up node respectively, and is configured to provide a signal from the third power terminal to the pull-up node under the control of a signal from the frame reset signal terminal;

[0038] The output reset circuit is coupled to the row reset signal terminal, the fourth power terminal and the first output terminal respectively, and is configured to provide a signal from the fourth power terminal to the first output terminal under the control of a signal from the row reset signal terminal.

[0039] In some embodiments, the voltage levels of the first power terminal and the second power terminal are opposite.

[0040] In some embodiments, at least one of the following is satisfied:

[0041] The input circuit comprises a first transistor, a gate of the first transistor is coupled to the signal input terminal, and a first electrode and a second electrode of the first transistor are respectively coupled to the input power supply terminal and the pull-up node;

[0042] The first pull-down circuit includes a sixteenth transistor, a gate of the sixteenth transistor is coupled to the pull-up node, and a first electrode and a second electrode of the sixteenth transistor are respectively coupled to the third power supply terminal and the first pull-down node;

[0043] The first pull-down control circuit includes a fifteenth transistor, a gate and a first electrode of the fifteenth transistor are coupled to the first power supply terminal, and a second electrode of the fifteenth transistor is coupled to the first auxiliary node;

[0044] The first auxiliary pull-down circuit includes a seventeenth transistor, a gate of the seventeenth transistor is coupled to the signal input terminal, and a first electrode and a second electrode of the seventeenth transistor are respectively coupled to the third power supply terminal and the first pull-down node;

[0045] The first noise reduction circuit includes an eighteenth transistor, a gate of the eighteenth transistor is coupled to the first pull-down node, and a first electrode and a second electrode of the eighteenth transistor are respectively coupled to the third power supply terminal and the pull-up node;

[0046] The second pull-down circuit includes a twenty-sixth transistor, a gate of the twenty-sixth transistor is coupled to the pull-up node, and a first electrode and a second electrode of the twenty-sixth transistor are respectively coupled to the third power supply terminal and the second pull-down node;

[0047] The second pull-down control circuit includes a twenty-fifth transistor, a gate and a first electrode of the twenty-fifth transistor are coupled to the second power supply terminal, and a second electrode of the twenty-fifth transistor is coupled to the second auxiliary node;

[0048] The second auxiliary pull-down circuit includes a twenty-seventh transistor, a gate of the twenty-seventh transistor is coupled to the signal input terminal, and a first electrode and a second electrode of the twenty-seventh transistor are coupled to the third power supply terminal and the second pull-down node respectively;

[0049] The second noise reduction circuit includes a twenty-eighth transistor, a gate of the twenty-eighth transistor is coupled to the second pull-down node, and a first electrode and a second electrode of the twenty-eighth transistor are respectively coupled to the third power supply terminal and the pull-up node;

[0050] The first output circuit includes a third transistor, a gate of the third transistor is coupled to the pull-up node, and a first electrode and a second electrode of the third transistor are respectively coupled to the clock signal terminal and the first output terminal;

[0051] The first output pull-down module includes an eleventh transistor, a gate of the eleventh transistor is coupled to the first pull-down node, and a first electrode and a second electrode of the eleventh transistor are respectively coupled to the fourth power supply terminal and the first output terminal;

[0052] The second output pull-down module includes a twenty-first transistor, a gate of the twenty-first transistor is coupled to the second pull-down node, and a first electrode and a second electrode of the twenty-first transistor are respectively coupled to the fourth power supply terminal and the first output terminal;

[0053] The row reset circuit comprises a second transistor, a gate of the second transistor is coupled to the row reset signal terminal, a first electrode and a second electrode of the second transistor are coupled to the third power supply terminal and the pull-up node respectively;

[0054] The frame reset circuit includes a seventh transistor, a gate of the seventh transistor is coupled to the frame reset signal terminal, and a first electrode and a second electrode of the seventh transistor are respectively coupled to the third power supply terminal and the pull-up node;

[0055] The output reset circuit comprises a fourth transistor, a gate of the fourth transistor is coupled to the row reset signal terminal, and a first electrode and a second electrode of the fourth transistor are respectively coupled to the fourth power supply terminal and the first output terminal.

[0056] As a second aspect of an embodiment of the present disclosure, an embodiment of the present disclosure provides a driving method of a shift register, which is applied to any shift register of the present disclosure, and the method includes:

[0057] In the first stage, a valid level signal is provided to the signal input terminal, and the input circuit provides a signal from the input power terminal to the pull-up node under the control of the valid level signal from the signal input terminal; the first pull-down circuit provides a signal from the third power terminal to the first pull-down node under the control of the signal from the pull-up node; and a first preset signal is provided to the control signal terminal, so that the first auxiliary node and the first pull-down node are disconnected;

[0058] In the second stage, a valid level signal is provided to the row reset signal terminal, and the row reset circuit provides a signal from the third power supply terminal to the pull-up node under the control of the valid level signal from the row reset signal terminal; the first pull-down control circuit provides a signal from the first power supply terminal to the first auxiliary node under the control of the signal from the first power supply terminal; and a second preset signal is provided to the control signal terminal, so that the first auxiliary node and the first pull-down node are turned on.

[0059] As a third aspect of an embodiment of the present disclosure, an embodiment of the present disclosure provides a gate driving circuit, comprising any shift register of the present disclosure.

[0060] As a fourth aspect of an embodiment of the present disclosure, an embodiment of the present disclosure provides a display device, including any shift register of the present disclosure or including a gate driving circuit of the present disclosure.

[0061] In the technical solution disclosed in the present invention, a suppression circuit is arranged between the first auxiliary node and the first pull-down node. When the pull-up node is an on signal, the suppression circuit disconnects the first auxiliary node and the first pull-down node based on the signal at the control signal end. That is to say, when the signal at the pull-up node is an on signal, the first auxiliary node and the first pull-down node are disconnected, thereby cutting off the connection between the first pull-down control circuit and the first pull-down circuit, and avoiding the first power supply end from forming a path through the first pull-down control circuit and the first pull-down circuit to the third power supply end. Therefore, in the present invention, when the pull-up node is an on signal, no static current will flow through the first pull-down control circuit and the first pull-down circuit, thereby preventing the forward bias of the devices in the first pull-down control circuit and the first pull-down circuit, and avoiding the characteristic deviation of the internal devices, so that the shift register can withstand a high voltage of, for example, ±38V.

[0062] The above summary is for illustrative purposes only and is not intended to be limiting in any way. In addition to the illustrative aspects, embodiments and features described above, further aspects, embodiments and features of the present disclosure will be readily apparent by reference to the accompanying drawings and the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0063] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the multiple drawings represent the same or similar parts or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings only depict some embodiments according to the present disclosure and should not be regarded as limiting the scope of the present disclosure.

[0064] Figure 1 A shift register in the related art;

[0065] Figure 2 is a circuit diagram of a shift register in an embodiment of the present disclosure;

[0066] Figure 3 is a circuit diagram of a shift register in another embodiment of the present disclosure;

[0067] Figure 4 is a circuit diagram of a shift register in yet another embodiment of the present disclosure;

[0068] Figure 5 is a circuit diagram of a shift register in another embodiment of the present disclosure;

[0069] Figure 6 for Figure 5 A timing diagram of the shift register shown;

[0070] Figure 7 is a schematic diagram of a gate driving circuit in an embodiment of the present disclosure;

[0071] Figure 8 is a schematic diagram of a gate driving circuit in a display panel according to an embodiment of the present disclosure;

[0072] Fig. 9 for Figure 8 A timing diagram of the middle gate drive circuit. DETAILED DESCRIPTION

[0073] In the following, only some exemplary embodiments are briefly described. As those skilled in the art will appreciate, the described embodiments may be modified in various ways without departing from the spirit or scope of the present disclosure. Therefore, the drawings and descriptions are considered to be exemplary and non-restrictive in nature.

[0074] The transistors used in all embodiments of the present invention can be thin film transistors or field effect transistors or other devices with the same characteristics. According to the role in the circuit, the transistors used in the embodiments of the present invention are mainly switching transistors. Since the source and drain of the switching transistor used here are symmetrical, the source and drain are interchangeable. In the embodiment of the present invention, the source (source electrode) is called the first electrode, the drain (drain electrode) is called the second electrode, or the drain can be called the first electrode and the source is called the second electrode. According to the form in the accompanying drawings, the middle end of the transistor is defined as the gate (also called the gate electrode), the signal input end is the source, and the signal output end is the drain. The switching transistor used in the embodiment of the present invention can be a P-type transistor (PMOS) or an N-type transistor (NMOS). The P-type transistor is turned on when the gate is at a low level and is turned off when the gate is at a high level; the N-type transistor is turned on when the gate is at a high level and is turned off when the gate is at a low level. In addition, multiple signals in each embodiment of the present invention correspond to a first potential and a second potential. The first potential and the second potential only represent two different potential state quantities of the signal, and do not represent that the first potential or the second potential in the full text has a specific value. In the embodiment of the present invention, the first potential is taken as an effective potential for description.

[0075] The coupling may include: direct physical contact between the two ends or indirect connection between the two ends (eg, connection between the two ends via a signal line). The embodiment of the present invention does not limit the coupling method between the two ends.

[0076] It is understandable that the electronic paper is also driven by a gate driving circuit, which includes a shift register that provides a row driving signal to the display area of ​​the electronic paper.

[0077] Figure 1 is a shift register in the related art, such as Figure 1 As shown, the thin film transistor (TFT) can be an oxide transistor. A shift register using conventional oxide transistors cannot withstand a high voltage of ±38V even if the process of the thin film transistor is adjusted.

[0078] The inventors have discovered that Figure 1 In the shift register shown, when the pull-up node PU is at a high level, the transistor M16 is turned on under the control of the high level of the pull-up node PU, so that a path is formed from the first power supply terminal VDD1→transistor M5A→transistor M6A→third power supply terminal VGL1, and a large static current flows through the path. The large static current exerts a large pressure on the transistor M15 / transistor M16, causing the characteristics of the transistor M15 / transistor M16 to shift, thereby making it unable to withstand the high voltage of ±38V. The same problem exists in the transistor M25 / transistor M26.

[0079] In order to solve the problem that the shift register cannot withstand high voltage, an embodiment of the present disclosure provides a shift register.

[0080] Figure 2 FIG. 1 is a circuit diagram of a shift register in an embodiment of the present disclosure, as shown in FIG. Figure 2 As shown, the shift register includes an input circuit 11 , a first pull-down circuit 12 , a first pull-down control circuit 13 , a suppression circuit 14 , a first output circuit 18 and a first output pull-down circuit 15 .

[0081] The input circuit 11 is coupled to the signal input terminal INPUT, the input power terminal VDD0 and the pull-up node PU respectively, and is configured to provide the signal of the input power terminal VDD0 to the pull-up node PU under the control of the signal of the signal input terminal INPUT. For example, when the signal input terminal INPUT is a valid level signal, the input circuit 11 provides the signal of the input power terminal VDD0 to the pull-up node PU under the control of the valid level signal of the signal input terminal INPUT, charges the pull-up node PU, and pulls the pull-up node PU to a high level; when the signal input terminal INPUT is an invalid level signal, the input circuit 11 disconnects the signal input terminal INPUT and the pull-up node PU.

[0082] The first pull-down circuit 12 is coupled to the pull-up node PU, the third power supply terminal VGL1 and the first pull-down node PD1 respectively, and is configured to provide the signal of the third power supply terminal VGL1 to the first pull-down node PD1 under the control of the signal of the pull-up node PU. For example, when the pull-up node PU is a valid level signal, such as a high level signal, the first pull-down circuit 12 is controlled by the high level signal of the pull-up node PU, and the first pull-down node PD1 is connected to the third power supply terminal VGL1, and the signal of the third power supply terminal VGL1 is provided to the first pull-down node PD1; when the pull-up node PU is an invalid level signal, such as a low level signal, the first pull-down circuit 12 disconnects the third power supply terminal VGL1 from the first pull-down node PD1.

[0083] The first pull-down control circuit 13 is coupled to the first power supply terminal VDD1 and the first auxiliary node N1, respectively, and is configured to provide the signal of the first power supply terminal VDD1 to the first auxiliary node N1 under the control of the signal of the first power supply terminal VDD1. In other words, the first pull-down control circuit 13, under the control of the signal of the first power supply terminal VDD1, makes the first auxiliary node N1 conductive with the first power supply terminal VDD1, so as to provide the signal of the first power supply terminal VDD1 to the first auxiliary node N1.

[0084] The suppression circuit 14 is coupled to the control signal terminal S, the first auxiliary node N1 and the first pull-down node PD1 respectively, and is configured to disconnect the first auxiliary node N1 and the first pull-down node PD1 based on the signal of the control signal terminal S when the signal of the pull-up node PU is an on signal. For a shift register using TFT, the on signal can be understood as an effective level signal, and when the pull-up node PU is connected to the gate of the TFT, the on signal can be understood as a signal that can control the first and second electrodes of the TFT to be turned on.

[0085] The first output circuit 18 is coupled to the pull-up node PU, the clock signal terminal CLK and the first output terminal Gout, respectively, and is configured to provide the signal of the clock signal terminal CLK to the first output terminal Gout under the control of the start signal of the pull-up node PU. For example, when the pull-up node PU is a start signal or a valid level signal such as a high level signal, the first output circuit 18 provides the signal of the clock signal terminal CLK to the first output terminal Gout under the control of the high level signal of the pull-up node PU, so that the first output terminal Gout can output the signal of the clock signal terminal CLK. Therefore, the "start signal" can also be understood as a signal that can control the first output circuit to make the clock signal terminal and the first output terminal conductive.

[0086] The first output pull-down circuit 15 is coupled to the first pull-down node PD1, the fourth power supply terminal VGL2 and the first output terminal Gout, respectively, and is configured to provide the signal of the fourth power supply terminal VGL2 to the first output terminal Gout under the control of the first pull-down node PD1. For example, when the first pull-down node PD1 is a valid level signal, the signal of the fourth power supply terminal VGL2 can be provided to the first output terminal Gout through the first output pull-down circuit 15, so that the first output terminal Gout can output the signal of the fourth power supply terminal VGL2.

[0087] like Figure 2 As shown, when the pull-up node PU is an on signal, the first pull-down circuit 12 provides the signal of the third power supply terminal VGL1 to the first pull-down node PD1 under the control of the on signal of the pull-up node PU; and the first pull-down control circuit 13 provides the signal of the first power supply terminal VDD1 to the first auxiliary node N1 under the control of the signal of the first power supply terminal VDD1. If the first auxiliary node N1 is directly connected to the first pull-down node PD1, then the first power supply terminal VDD1→the first pull-down control circuit 13→the first auxiliary node N1→the first pull-down node PD1→the first pull-down circuit 12→the third power supply terminal VGL1 can form a path, and a large static current flows through the path.

[0088] In the technical solution disclosed in the present invention, a suppression circuit 14 is provided between the first auxiliary node N1 and the first pull-down node PD1. When the pull-up node PU is an on signal, the suppression circuit 14 disconnects the first auxiliary node N1 and the first pull-down node PD1 based on the signal of the control signal terminal S. That is, when the signal of the pull-up node PU is an on signal, the first auxiliary node N1 and the first pull-down node PD1 are disconnected, thereby cutting off the connection between the first pull-down control circuit 13 and the first pull-down circuit 12, and preventing the first power supply terminal VDD1 from forming a path through the first pull-down control circuit 13 and the first pull-down circuit 12 to the third power supply terminal VGL1. Therefore, in the present invention, when the pull-up node PU is an on signal, no static current will flow through the first pull-down control circuit 13 and the first pull-down circuit 12, preventing the forward bias of the devices in the first pull-down control circuit 13 and the first pull-down circuit 12, and avoiding the characteristic deviation of the internal devices, so that the shift register can withstand a high voltage of, for example, ±38V.

[0089] It can be understood that in the display panel, the shift register generally includes two timing stages: the first stage and the second stage. The first stage can also be called the working stage. In the first stage, the pull-up node PU is an on signal, and the first output circuit 18 provides the signal of the clock signal terminal CLK to the first output terminal Gout under the control of the on signal of the pull-up node PU; the second stage can also be called the non-working stage. In the second stage, the pull-up node PU is an off signal, and the first output circuit 18 stops providing the signal of the clock signal terminal CLK to the first output terminal Gout under the control of the off signal of the pull-up node PU, and instead provides the signal of the fourth power supply terminal VGL2 to the first output terminal Gout by the first output pull-down circuit 15.

[0090] As the shift register timing phase changes, the signal of the pull-up node PU can be changed from an on signal to a off signal. Under the control of the off signal of the pull-up node PU, the first output circuit 18 stops providing the signal of the clock signal terminal CLK to the first output terminal Gout. In order to achieve that when the pull-up node PU is a shut-down signal, the first auxiliary node N1 is turned on with the first pull-down node PD1, the suppression circuit 14 can also be configured to make the first auxiliary node N1 and the first pull-down node PD1 turned on based on the signal of the control signal terminal S when the signal of the pull-up node PU is a shut-down signal. When the pull-up node PU is a shut-down signal, the first pull-down circuit 12 stops providing the signal of the third power supply terminal VGL1 to the first pull-down node PD1 under the control of the shut-down signal of the pull-up node PU, so that the signal of the first auxiliary node N1 can be transmitted to the first pull-down node PD1, so as to provide the signal of the first power supply terminal VDD1 to the first pull-down node PD1.

[0091] Figure 3FIG. 1 is a circuit diagram of a shift register in another embodiment of the present disclosure. Figure 3 As shown, the suppression circuit 14 may include a nineteenth transistor M19, a gate of which is coupled to a control node N3, and the control node N3 is coupled to the control signal terminal S. A first electrode and a second electrode of the nineteenth transistor M19 are respectively coupled to the first auxiliary node N1 and the first pull-down node PD1.

[0092] The signal at the control signal terminal S includes a first preset signal and a second preset signal, and the level states of the first preset signal and the second preset signal are opposite. When the first preset signal is a high level signal, the second preset signal is a low level signal; when the first preset signal is a low level signal, the second preset signal is a high level signal.

[0093] The control signal terminal S is coupled to the control node N3, and can provide the first preset signal and the second preset signal to the control node N3. When the pull-up node PU is an on signal, the control signal terminal S provides the first preset signal to the control node N3, and the nineteenth transistor M19 is cut off or turned off under the control of the first preset signal, so that the first electrode and the second electrode of the nineteenth transistor M19 are disconnected, thereby disconnecting the first auxiliary node N1 and the first pull-down node PD1.

[0094] When the pull-up node PU is a shutdown signal, the control signal terminal S provides a second preset signal to the control node N3, and the nineteenth transistor M19 is turned on under the control of the second preset signal, so that the first electrode and the second electrode of the nineteenth transistor M19 are turned on, thereby coupling the first auxiliary node N1 and the first pull-down node PD1.

[0095] In one example, the nineteenth transistor M19 may be a PMOS, the first preset signal may be a high level signal, and the nineteenth transistor M19 is cut off under the control of the high level signal; the second preset signal is a low level signal, and the nineteenth transistor M19 is turned on under the control of the low level signal.

[0096] In another example, the nineteenth transistor M19 may be an NMOS, the first preset signal may be a low level signal, and the nineteenth transistor M19 is cut off under the control of the high level signal; the second preset signal is a high level signal, and the nineteenth transistor M19 is turned on under the control of the high level signal.

[0097] In one embodiment, the level state of the control signal terminal S is the same as that of the pull-up node PU, that is, when the pull-up node PU is a high-level signal, the first preset signal of the control signal terminal S is also a high-level signal; when the pull-up node PU is a low-level signal, the second preset signal of the control signal terminal S is also a low-level signal. The high-level signal of the pull-up node PU may be equal to or unequal to the high-level signal of the control signal terminal S; the low-level signal of the pull-up node PU may be equal to or unequal to the low-level signal of the control signal terminal S.

[0098] In one embodiment, the control signal terminal S is coupled to the pull-up node PU, so that the signal at the control signal terminal S is the same as the signal at the pull-up node PU. Figure 3 In the embodiment, the nineteenth transistor M19 is a PMOS.

[0099] Figure 4 FIG. 1 is a circuit diagram of a shift register in another embodiment of the present disclosure. Figure 4 As shown, the suppression circuit 14 may further include a state control subcircuit 141. The state control subcircuit 141 is coupled to the control signal terminal S, the first voltage signal V1, the second voltage signal V2 and the control node N3 respectively.

[0100] The state control subcircuit 141 is configured to provide the first voltage signal V1 to the control node N3 based on the signal of the control signal terminal S when the signal of the pull-up node PU is an on signal, so that the first electrode and the second electrode of the nineteenth transistor M19 are disconnected. With respect to the nineteenth transistor M19, the first voltage signal V1 is an invalid level signal, and the nineteenth transistor M19 is turned off under the control of the first voltage signal V1, so that the first electrode and the second electrode of the nineteenth transistor M19 are disconnected, thereby disconnecting the first auxiliary node N1 and the first pull-down node PD1.

[0101] The state control subcircuit 141 is configured to provide the second voltage signal V2 to the control node N3 based on the signal of the control signal terminal S when the signal of the pull-up node PU is a shutdown signal, so that the first electrode and the second electrode of the nineteenth transistor M19 are turned on. Relative to the nineteenth transistor M19, the second voltage signal V2 is an effective level signal, and the nineteenth transistor M19 is turned on under the control of the second voltage signal V2, so that the first electrode and the second electrode of the nineteenth transistor M19 are turned on, and then the first auxiliary node N1 is turned on with the first pull-down node PD1.

[0102] If the control signal terminal S is directly coupled to the control node N3, the gate of the nineteenth transistor M19 needs to directly bear the voltage signal of the control signal terminal S, which may cause the gate of the nineteenth transistor M19 to bear an inappropriate voltage.

[0103] Figure 4 In the embodiment, by setting the state control subcircuit 141, the state control subcircuit 141 can selectively provide the first voltage signal V1 or the second voltage signal V2 to the control node N3 according to the signal of the control signal terminal S, so that the gate of the nineteenth transistor M19 bears the first voltage signal V1 or the second voltage signal V2. The first voltage signal V1 or the second voltage signal V2 can be set to a voltage value suitable for the nineteenth transistor M19, so as to avoid the gate of the nineteenth transistor M19 directly bearing the voltage signal of the control signal terminal S, which is conducive to ensuring the performance of the nineteenth transistor M19 and extending its service life.

[0104] like Figure 4 As shown, the state control subcircuit 141 may include a first control transistor M5, a gate of the first control transistor M5 is coupled to the control signal terminal S, and a first electrode and a second electrode of the first control transistor M5 are coupled to the first voltage signal V1 and the control node N3, respectively. In the case where the signal of the pull-up node PU is a turn-on signal, the signal of the control signal terminal S controls the first control transistor M5 to be turned on. For example, in the case where the signal of the pull-up node PU is a turn-on signal, the signal of the control signal terminal S is a first preset signal, and the first preset signal can control the first control transistor M5 to be turned on, and provide the first voltage signal V1 to the control node N3.

[0105] The state control subcircuit 141 may include a second control transistor M6, a gate of the second control transistor M6 is coupled to the control signal terminal S, and a first electrode and a second electrode of the second control transistor M6 are coupled to the second voltage signal V2 and the control node N3, respectively. In the case where the signal of the pull-up node PU is a shutdown signal, the signal of the control signal terminal S controls the second control transistor M6 to turn on. For example, in the case where the signal of the pull-up node PU is a shutdown signal, the signal of the control signal terminal S is a second preset signal, and the second preset signal can control the second transistor M2 to turn on and provide the second voltage signal V2 to the control node N3.

[0106] In order to prevent the first control transistor M5 and the second control transistor M6 from being turned on at the same time, the first voltage signal V1 can be an invalid level signal of the second control transistor M6, ensuring that the second control transistor M6 is turned off while the first control transistor M5 is turned on. The second voltage signal V2 can be an invalid level signal of the first control transistor M5, ensuring that the first control transistor M5 is turned off while the second control transistor M6 is turned on.

[0107] Exemplarily, in order to achieve opposite states of the first control transistor M5 and the second control transistor M6 , one of the first control transistor M5 and the second control transistor M6 may be a PMOS, and the other may be an NMOS.

[0108] When the level states of the control signal terminal S and the pull-up node PU are the same, for example, the control signal terminal S is coupled to the pull-up node PU. The first control transistor M5 includes an NMOS, and the second control transistor M6 includes a PMOS.

[0109] The type of the nineteenth transistor M19 can be determined according to the first voltage signal V1 and the second voltage signal V2. For example, if the first voltage signal V1 is a low level signal and the second voltage signal V2 is a high level signal, then the nineteenth transistor M19 can be an NMOS; if the first voltage signal V1 is a high level signal and the second voltage signal V2 is a low level signal, then the nineteenth transistor M19 can be a PMOS.

[0110] In one example, the first level signal can be provided by the fifth power supply terminal VGL3, that is, the fifth power supply terminal VGL3 provides a first level signal, which is a low level signal. The second level signal can be provided by the sixth power supply terminal VDD3, which is a high level signal.

[0111] In one embodiment, Figure 2-Figure 4 As shown, the shift register may further include a second pull-down circuit 22 , a second pull-down control circuit 23 and a second output pull-down circuit 25 .

[0112] The second pull-down circuit 22 is coupled to the pull-up node PU, the third power supply terminal VGL1, and the second pull-down node PD2, respectively, and is configured to provide the signal of the third power supply terminal VGL1 to the second pull-down node PD2 under the control of the signal of the pull-up node PU. For example, when the pull-up node PU is a valid level signal, such as a high level signal, the second pull-down circuit 22 is controlled by the high level signal of the pull-up node PU, and the second pull-down node PD2 is connected to the third power supply terminal VGL1, and the signal of the third power supply terminal VGL1 is provided to the second pull-down node PD2; when the pull-up node PU is an invalid level signal, such as a low level signal, the second pull-down circuit 22 disconnects the third power supply terminal VGL1 from the second pull-down node PD2.

[0113] The second pull-down control circuit 23 is coupled to the second power supply terminal VDD2 and the second auxiliary node N2 respectively, and is configured to provide a signal of the second power supply terminal VDD2 to the second auxiliary node N2 under the control of a signal of the second power supply terminal VDD2.

[0114] The second output pull-down circuit 25 is coupled to the second pull-down node PD2, the fourth power supply terminal VGL2 and the first output terminal Gout, respectively, and is configured to provide the signal of the fourth power supply terminal VGL2 to the first output terminal Gout under the control of the second pull-down node PD2. For example, when the second pull-down node PD2 is a valid level signal, the second output pull-down circuit 25 can provide the signal of the fourth power supply terminal VGL2 to the first output terminal Gout, so that the first output terminal Gout can output the signal of the fourth power supply terminal VGL2.

[0115] The suppression circuit 14 is also coupled to the second auxiliary node N2 and the second pull-down node PD2, and is further configured to disconnect the second auxiliary node N2 and the second pull-down node PD2 based on the signal of the control signal terminal S when the signal of the pull-up node PU is an on signal.

[0116] Exemplarily, the shift register may include a first module and a second module, the first module including a first pull-down control circuit 13, a first pull-down circuit 12 and a first output pull-down circuit 15, and the second module including a second pull-down control circuit 23, a second pull-down circuit 22 and a second output pull-down circuit 25. The first module and the second module may be used alternately in the operation of the shift register, or one of the first module and the second module may be selected for use. The functions of the two modules are the same or similar.

[0117] Referring to the foregoing, when the second pull-down control circuit 23 and the second pull-down circuit 22 are used, when the pull-up node PU is an on signal, no static current will flow through the second pull-down control circuit 23 and the second pull-down circuit 22, thereby preventing the forward bias of the devices in the second pull-down control circuit 23 and the second pull-down circuit 22, avoiding the characteristic deviation of the internal devices, and allowing the shift register to withstand high voltages such as ±38V.

[0118] The suppression circuit 14 is also configured to, when the signal of the pull-up node PU is a shutdown signal, turn on the second auxiliary node N2 and the second pull-down node PD2 based on the signal of the control signal terminal S. When the pull-up node PU is a shutdown signal, the second pull-down circuit 22 stops providing the signal of the third power supply terminal VGL1 to the second pull-down node PD2 under the control of the shutdown signal of the pull-up node PU, so that the signal of the second auxiliary node N2 can be transmitted to the second pull-down node PD2, so as to provide the signal of the second power supply terminal VDD2 to the second pull-down node PD2.

[0119] Corresponding to the nineteenth transistor M19, as Figure 3 and Figure 4As shown, the suppression circuit 14 may further include a twenty-ninth transistor M29, the gate of the twenty-ninth transistor M29 is coupled to the control node N3, the control node N3 is connected to the control signal terminal S, and the first electrode and the second electrode of the twenty-ninth transistor M29 are respectively coupled to the second auxiliary node N2 and the second pull-down node PD2. The twenty-ninth transistor M29 has the same function as the nineteenth transistor M19 in the previous text, and will not be repeated here.

[0120] like Figure 4 As shown, the shift register may further include a first auxiliary pull-down circuit 16 and a first noise reduction circuit 17. The first auxiliary pull-down circuit 16 is coupled to the signal input terminal INPUT, the third power supply terminal VGL1 and the first pull-down node PD1, respectively, and is configured to provide a signal of the third power supply terminal VGL1 to the first pull-down node PD1 under the control of a signal of the signal input terminal INPUT.

[0121] The first noise reduction circuit 17 is coupled to the first pull-down node PD1 , the third power supply terminal VGL1 and the pull-up node PU respectively, and is configured to provide a signal of the third power supply terminal VGL1 to the pull-up node PU under the control of the signal of the first pull-down node PD1 .

[0122] The shift register may further include a second auxiliary pull-down circuit 26 and a second noise reduction circuit 27. The second auxiliary pull-down circuit 26 is coupled to the signal input terminal INPUT, the third power supply terminal VGL1 and the second pull-down node PD2 respectively, and is configured to provide the signal of the third power supply terminal VGL1 to the second pull-down node PD2 under the control of the signal of the signal input terminal INPUT.

[0123] The second noise reduction circuit 27 is coupled to the second pull-down node PD2 , the third power supply terminal VGL1 and the pull-up node PU respectively, and is configured to provide a signal of the third power supply terminal VGL1 to the pull-up node PU under the control of the signal of the second pull-down node PD2 .

[0124] like Figure 4 As shown, the shift register may further include a row reset circuit 19. The row reset circuit 19 is coupled to the row reset signal terminal RST, the third power supply terminal VGL1 and the pull-up node PU respectively, and is configured to provide a signal of the third power supply terminal VGL1 to the pull-up node PU under the control of the signal of the row reset signal terminal RST. In the display panel, the row reset circuit 19 may provide a signal of the third power supply terminal VGL1 to the pull-up node PU after the corresponding row of pixels is displayed, so as to reset the pixels of the corresponding row.

[0125] like Figure 4As shown, the shift register may further include a frame reset circuit 20. The frame reset circuit 20 is coupled to the frame reset signal terminal TRST, the third power supply terminal VGL1 and the pull-up node PU respectively, and is configured to provide the signal of the third power supply terminal VGL1 to the pull-up node PU under the signal control of the frame reset signal terminal TRST. In the display panel, the frame reset circuit 20 can provide the signal of the third power supply terminal VGL1 to the pull-up node PU of all shift registers after a frame of picture ends, so as to reset the entire picture so as to display the next frame of picture.

[0126] like Figure 4 As shown, the shift register may further include an output reset circuit 21. The output reset circuit 21 is coupled to the row reset signal terminal RST, the fourth power supply terminal VGL2 and the first output terminal Gout respectively, and is configured to provide a signal of the fourth power supply terminal VGL2 to the first output terminal Gout under the control of the signal of the row reset signal terminal RST. In the display panel, the output reset circuit 21 may provide a signal of the fourth power supply terminal VGL2 to the first output terminal Gout of the corresponding shift register after the corresponding row of pixels is displayed, so as to reset the pixels of the row.

[0127] Exemplarily, the first module may further include a first auxiliary pull-down circuit 16 and a first noise reduction circuit 17, and the second module may further include a second auxiliary pull-down circuit 26 and a second noise reduction circuit 27. In order to achieve the alternating use of the first module and the second module, the level states of the first power supply terminal VDD1 and the second power supply terminal VDD2 are opposite. For example, when the first module is used, the first power supply terminal VDD1 is a working level signal, and the second power supply terminal VDD2 may be a common voltage signal Vcom; when the second module is used, the second power supply terminal VDD2 is a working level signal, and the first power supply terminal VDD1 may be a common voltage signal Vcom.

[0128] In one embodiment, the third power terminal VGL1 and the fourth power terminal VGL2 may be coupled.

[0129] Figure 5 FIG. 1 is a circuit diagram of a shift register in another embodiment of the present disclosure, as shown in FIG. Figure 5 As shown, the signal input terminal INPUT may be coupled to the input power terminal VDD0 , and the third power terminal VGL1 may be coupled to the fourth power terminal VGL2 .

[0130] In one embodiment, Figure 5As shown, the input circuit 11 may include a first transistor M1, a gate of the first transistor M1 is coupled to the signal input terminal INPUT, and a first electrode and a second electrode of the first transistor M1 are coupled to the input power supply terminal VDD0 and the pull-up node PU, respectively. The signal input terminal INPUT may be coupled to the input power supply terminal VDD0. When the signal input terminal INPUT provides a valid level signal, the first transistor M1 is turned on, and the signal of the signal input terminal INPUT is provided to the pull-up node PU, pulling the pull-up node PU high; when the signal input terminal INPUT provides an invalid level signal, the first transistor M1 is turned off or turned off.

[0131] The first pull-down circuit 12 may include a sixteenth transistor M16, a gate of the sixteenth transistor M16 is coupled to the pull-up node PU, and a first electrode and a second electrode of the sixteenth transistor M16 are coupled to the third power supply terminal VGL1 and the first pull-down node PD1, respectively. When the pull-up node PU is a valid level signal, the sixteenth transistor M16 is turned on, and the third power supply terminal VGL1 is turned on to the first pull-down node PD1; when the pull-up node PU is an invalid level signal, the sixteenth transistor M16 is turned off.

[0132] The first pull-down control circuit 13 may include a fifteenth transistor M15, a gate and a first electrode of the fifteenth transistor M15 are coupled to the first power supply terminal VDD1, and a second electrode of the fifteenth transistor M15 is coupled to the first auxiliary node N1. When the first power supply terminal VDD1 is a valid level signal, the fifteenth transistor M15 is turned on and provides the signal of the first power supply terminal VDD1 to the first auxiliary node N1. When the first module is not used, the first power supply terminal VDD1 is an invalid level signal, and the fifteenth transistor M15 is turned off.

[0133] The first auxiliary pull-down circuit 16 may include a seventeenth transistor M17, the gate of the seventeenth transistor M17 is coupled to the signal input terminal INPUT, and the first electrode and the second electrode of the seventeenth transistor M17 are coupled to the third power supply terminal VGL1 and the first pull-down node PD1, respectively. When the signal input terminal INPUT is a valid level signal, the pull-up node PU is pulled up, and at this time, it is necessary to ensure that the pull-down node is pulled down. By setting the first auxiliary pull-down circuit 16, the signal of the third power supply terminal VGL1 can be provided to the first pull-down node PD1 through the seventeenth transistor M17, and the first pull-down node PD1 is pulled down, ensuring that the pull-up node PU is pulled up and the pull-down node is pulled down at the same time.

[0134] The first noise reduction circuit 17 includes an eighteenth transistor M18, the gate of the eighteenth transistor M18 is coupled to the first pull-down node PD1, and the first electrode and the second electrode of the eighteenth transistor M18 are coupled to the third power supply terminal VGL1 and the pull-up node PU, respectively. In the second stage (non-working stage) of the shift register, the first pull-down node PD1 is a high-level signal. In order to prevent the pull-up node PU from having a high level, by setting the first noise reduction circuit 17, when the first pull-down node PD1 is a high-level signal, the eighteenth transistor M18 can provide a low-level signal of the third power supply terminal VGL1 to the pull-up node PU, thereby preventing the pull-up node PU from having a high level.

[0135] The second pull-down circuit 22 includes a twenty-sixth transistor M26 , a gate of the twenty-sixth transistor M26 is coupled to the pull-up node PU, and a first electrode and a second electrode of the twenty-sixth transistor M26 are coupled to the third power supply terminal VGL1 and the second pull-down node PD2 , respectively.

[0136] The second pull-down control circuit 23 includes a twenty-fifth transistor M25 , a gate and a first electrode of the twenty-fifth transistor M25 are coupled to the second power supply terminal VDD2 , and a second electrode of the twenty-fifth transistor M25 is coupled to the second auxiliary node N2 .

[0137] The second auxiliary pull-down circuit 26 includes a twenty-seventh transistor M27, a gate of the twenty-seventh transistor M27 is coupled to the signal input terminal INPUT, and a first electrode and a second electrode of the twenty-seventh transistor M27 are coupled to the third power supply terminal VGL1 and the second pull-down node PD2, respectively. The working principle of the second auxiliary pull-down circuit 26 is the same or similar to that of the first auxiliary pull-down circuit 16, and will not be repeated here.

[0138] The second noise reduction circuit 27 includes a 28th transistor M28, a gate of the 28th transistor M28 is coupled to the second pull-down node PD2, and a first electrode and a second electrode of the 28th transistor M28 are respectively coupled to the third power supply terminal VGL1 and the pull-up node PU. The working principle of the second noise reduction circuit 27 is the same or similar to that of the first noise reduction circuit 17, and will not be repeated here.

[0139] The first output circuit 18 includes a third transistor M3, the gate of the third transistor M3 is coupled to the pull-up node PU, and the first and second electrodes of the third transistor M3 are coupled to the clock signal terminal CLK and the first output terminal Gout, respectively. When the signal of the pull-up node PU is an on signal, the third transistor M3 is turned on and provides the signal of the clock signal terminal CLK to the first output terminal Gout. When the signal of the pull-up node PU is a shut-down signal, the third transistor M3 is turned off. The first output circuit 18 may also include a storage capacitor C, one end of the storage capacitor is coupled to the second electrode of the third transistor M3, and the other end is coupled to the pull-up node PU.

[0140] The first output pull-down module 15 includes an eleventh transistor M11, the gate of the eleventh transistor M11 is coupled to the first pull-down node PD1, and the first electrode and the second electrode of the eleventh transistor M11 are coupled to the fourth power supply terminal VGL2 and the first output terminal Gout, respectively. When the first pull-down node PD1 is an invalid level signal, the eleventh transistor M11 is turned off; when the first pull-down node PD1 is a valid level signal, the eleventh transistor M11 is turned on to provide the signal of the fourth power supply terminal VGL2 to the first output terminal Gout.

[0141] The second output pull-down module 25 includes a 21st transistor M21, a gate of the 21st transistor M21 is coupled to the second pull-down node PD2, and a first electrode and a second electrode of the 21st transistor M21 are coupled to the fourth power supply terminal VGL2 and the first output terminal Gout, respectively. When the second pull-down node PD2 is an invalid level signal, the 21st transistor M21 is turned off; when the second pull-down node PD2 is a valid level signal, the 21st transistor M21 is turned on to provide the signal of the fourth power supply terminal VGL2 to the first output terminal Gout.

[0142] The row reset circuit 19 includes a second transistor M2, a gate of the second transistor M2 is coupled to the row reset signal terminal RST, and a first electrode and a second electrode of the second transistor M2 are coupled to the third power supply terminal VGL1 and the pull-up node PU, respectively. When the row reset signal terminal RST is a valid level signal, the second transistor M2 is turned on, and the signal of the third power supply terminal VGL1 is provided to the pull-up node PU to reset the pull-up node PU; when the row reset signal terminal RST is an invalid level signal, the second transistor M2 is turned off.

[0143] The frame reset circuit 20 includes a seventh transistor M7, a gate of the seventh transistor M7 is coupled to the frame reset signal terminal TRST, and a first electrode and a second electrode of the seventh transistor M7 are coupled to the third power supply terminal VGL1 and the pull-up node PU, respectively. When the frame reset signal terminal TRST is a valid level signal, the seventh transistor M7 is turned on, and the signal of the third power supply terminal VGL1 is provided to the pull-up node PU to achieve frame reset; when the frame reset signal terminal TRST is an invalid level signal, the seventh transistor M7 is turned off.

[0144] The output reset circuit 21 includes a fourth transistor M4, a gate of the fourth transistor M4 is coupled to the row reset signal terminal RST, and a first electrode and a second electrode of the fourth transistor M4 are coupled to the fourth power supply terminal VGL2 and the first output terminal Gout, respectively. When the row reset signal terminal RST is a valid level signal, the fourth transistor M4 is turned on, and a signal of the third power supply terminal VGL1 is provided to the first output terminal Gout, so as to reset the first output terminal Gout; when the row reset signal terminal RST is an invalid level signal, the fourth transistor M4 is turned off.

[0145] In one embodiment, Figure 5 As shown, the shift register may further include a thirteenth transistor M13, a tenth transistor M10, and a twentieth transistor M20. The gate of the thirteenth transistor M13 is coupled to the pull-up node PU, and the first and second electrodes of the thirteenth transistor M13 are coupled to the clock signal terminal CLK and the second output terminal Out_C, respectively. The gate of the tenth transistor M10 is coupled to the first pull-down node PD1, and the first and second electrodes of the tenth transistor M10 are coupled to the second output terminal Out_C and the fourth power supply terminal VGL2, respectively. The gate of the twentieth transistor M20 is coupled to the second pull-down node PD2, and the first and second electrodes of the twentieth transistor M20 are coupled to the second output terminal Out_C and the fourth power supply terminal VGL2, respectively.

[0146] The first module may further include a tenth transistor M10, and the second module may further include a twentieth transistor M20.

[0147] In the gate driving circuit, the first output terminal Gout is connected to the signal input terminal INPUT of the next stage shift register, and the second output terminal Out_C is connected to the row reset signal terminal RST of the previous stage shift register.

[0148] exist Figure 5 In the embodiment, the first module includes a fifteenth transistor M15, a sixteenth transistor M16, a seventeenth transistor M17, and an eighteenth transistor M18, and the second module includes a twenty-fifth transistor M25, a twenty-sixth transistor M26, a twenty-seventh transistor M27, and a twenty-eighth transistor M28. The first module and the second module are used alternately.

[0149] It should be noted that Figure 5 FIG. 1 shows an exemplary structure of each circuit module or sub-circuit module. A person skilled in the art can understand that Figure 5 The structures shown in the figure can be simple structures of modules. Those skilled in the art can Figure 5 For example, the state control subcircuit 141 can adopt a structure of more than two thin film transistors connected in series, so that the state control subcircuit 141 can also achieve the same function as the state control subcircuit 141 when the structure is changed. Figure 3 to Figure 5 Therefore, each circuit module or sub-circuit module in the present disclosure is not limited to Figure 3 to Figure 5 Any structure shown may be used as long as the function can be achieved.

[0150] in addition, Figure 5The types of each transistor are shown exemplarily, for example, the first control transistor M5 is NMOS, the second control transistor M6 is PMOS, the nineteenth transistor M19 and the twenty-ninth transistor M29 are both NMOS, the first transistor M1 is NMOS, etc. It can be understood that the type of each transistor can be set according to the actual situation, and the type of the transistor can be set according to the specific control signal, as long as the function of the present disclosure can be realized. In an example, the NMOS type transistor in the shift register of the present disclosure can be an oxide transistor, that is, the material of the active layer includes an oxide semiconductor material, such as amorphous indium gallium zinc oxide material (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO) and other oxide semiconductor materials.

[0151] Figure 6 for Figure 5 A timing diagram of the shift register shown below is combined with Figure 5 and Figure 6 The working principle of the shift register of the embodiment of the present disclosure is described in detail. In the following, the first module is selected and the second module is idle, that is, the signal of the first power supply terminal VDD1 is a high level signal, the signal of the second power supply terminal VDD2 is Vcom, and the third power supply terminal VGL1 and the fourth power supply terminal VGL2 are both low level signals, and the effective level signal is explained as a high level signal.

[0152] In the first stage T1, an effective level signal is provided to the signal input terminal INPUT, the first transistor M1 is turned on under the control of the effective level signal, and a high level signal is provided to the pull-up node PU; the sixteenth transistor M16 provides a signal of the third power supply terminal VGL1 to the first pull-down node PD1 under the control of the high level signal of the pull-up node PU; the fifteenth transistor M15 provides a high level signal of the first power supply terminal VDD1 to the first auxiliary node N1 under the control of the high level signal of the first power supply terminal VDD1; at this time, since the control signal terminal S is coupled to the pull-up node PU, the control signal terminal S is also a high level signal, so that the first control transistor M5 is turned on, and the first voltage signal V1 of the fifth power supply terminal VGL3 is provided to the control node N3, and the first voltage signal V1 controls the nineteenth transistor M19 to be turned off, disconnecting the connection between the first auxiliary node N1 and the first pull-down node PD1. Therefore, in the first stage T1, no static current will flow through the fifteenth transistor M15 and the sixteenth transistor.

[0153] In the first stage T1, the third transistor M3 is turned on under the control of the high-level signal of the pull-up node PU, and provides the signal of the clock signal terminal CLK to the first output terminal Gout; when the clock signal terminal CLK is a high-level signal, due to the coupling effect, the level of the pull-up node PU is further increased, so that the third transistor M3 is fully turned on, and the high-level signal of the clock signal terminal CLK is provided to the first output terminal Gout to drive the corresponding row of pixels.

[0154] In the second stage T2, a valid level signal is provided to the row reset signal terminal RST, the second transistor M2 is turned on, and a signal of the third power supply terminal VGL1 is provided to the pull-up node PU, so that the pull-up node PU is reset to a low level signal; the sixteenth transistor M16 is turned off under the control of the low level signal of the pull-up node PU; the fifteenth transistor M15 is controlled by the high level signal of the first power supply terminal VDD1, and provides a high level signal of the first power supply terminal VDD1 to the first auxiliary node N1; at this time, since the control signal terminal S is coupled to the pull-up node PU, the control signal terminal S is also a low level signal, so that the second control transistor M6 is turned on, and the second voltage signal V2 of the sixth power supply terminal VDD3 is provided to the control node N3, and the second voltage signal V2 controls the nineteenth transistor M19 to be turned on, so that the first auxiliary node N1 is connected to the first pull-down node PD1, and the high level signal of the first auxiliary node N1 is transmitted to the first pull-down node PD1. Therefore, in the second stage T2, the first pull-down node PD1 is a high level signal.

[0155] The shift register may also include a third stage T0, which may be called a frame interval stage, i.e., an interval between two frames. In the third stage T0, the level signals of the first power supply terminal VDD1 and the second power supply terminal VDD2 are exchanged. For example, the signal of the first power supply terminal VDD1 is changed from a high level signal to Vcom, and the signal of the second power supply terminal VDD2 is changed from Vcom to a high level signal. Therefore, in the next frame, the shift register uses the second module. The first module and the second module are used alternately to extend the service life of the shift register.

[0156] An embodiment of the present disclosure further provides a shift register driving method, which is applied to the shift register in any embodiment of the present disclosure. The shift register driving method includes a first stage and a second stage.

[0157] In the first stage, a valid level signal is provided to the signal input terminal INPUT, and the input circuit 11 provides a signal of the input power supply terminal VDD0 to the pull-up node PU under the control of the valid level signal of the signal input terminal INPUT; the first pull-down circuit 12 provides a signal of the third power supply terminal VGL1 to the first pull-down node PD1 under the control of the signal of the pull-up node PU; and a first preset signal is provided to the control signal terminal S, so that the first auxiliary node N1 and the first pull-down node PD1 are disconnected.

[0158] In the second stage, a valid level signal is provided to the row reset signal terminal RST, and the row reset circuit 19 provides a signal of the third power supply terminal VGL1 to the pull-up node PU under the control of the valid level signal of the row reset signal terminal RST; the first pull-down control circuit 13 provides a signal of the first power supply terminal VDD1 to the first auxiliary node N1 under the control of the signal of the first power supply terminal VDD1; and a second preset signal is provided to the control signal terminal S, so that the first auxiliary node N1 and the first pull-down node PD1 are turned on.

[0159] The detailed process of the driving method of the shift register can refer to the working principle above, which will not be repeated here.

[0160] It should be noted that the "valid level signal" in this article refers to the valid level signal for the corresponding module circuit or device, and the valid level signals of different module circuits or devices may be the same or different; the "invalid level signal" refers to the invalid level signal for the corresponding module circuit or device, and the invalid level signals of different module circuits or devices may be the same or different. For PMOS, the valid level signal is a low level signal, and the invalid level signal is a high level signal. The valid low level signals of different PMOS may be the same or different; for NMOS, the valid level signal is a high level signal, and the invalid level signal is a low level signal. The valid high level signals of different NMOS may be the same or different.

[0161] An embodiment of the present disclosure further provides a gate driving circuit, and the gate driving circuit includes the shift register in any embodiment of the present disclosure.

[0162] The display panel includes a display area, and the gate driving circuit is located in a frame area outside the display area. Figure 7 FIG. 1 is a schematic diagram of a gate driving circuit in an embodiment of the present disclosure. Figure 7 As shown, the gate driving circuit includes a plurality of cascaded shift registers. Figure 7 Six of the shift registers are shown. Figure 7As shown, the first output terminal Gout of each shift register provides a gate signal to the corresponding row of pixels. The signal input terminal INPUT of the shift register GOA1 is connected to the first initial signal STV1, the first output terminal Gout of the shift register GOA1 provides a gate signal G1 to the first row of pixels, the second output terminal Out_C of the shift register GOA1 is connected to the signal input terminal INPUT of the shift register GOA3, and the row reset signal terminal RST of the shift register GOA1 is connected to the second output terminal Out_C of the shift register GOA3; the first output terminal Gout of the shift register GOA3 provides a gate signal G3 to the third row of pixels, the second output terminal Out_C of the shift register GOA3 is connected to the signal input terminal INPUT of the shift register GOA5, and the row reset signal terminal RST of the shift register GOA3 is connected to the second output terminal Out_C of the shift register GOA5; the first output terminal Gout of the shift register GOA5 provides a gate signal G5 to the fifth row of pixels.

[0163] The signal input terminal INPUT of the shift register GOA2 is connected to the second initial signal STV2, the first output terminal Gout of the shift register GOA2 provides a gate signal G2 to the second row of pixels, the second output terminal Out_C of the shift register GOA2 is connected to the signal input terminal INPUT of the shift register GOA4, and the row reset signal terminal RST of the shift register GOA2 is connected to the second output terminal Out_C of the shift register GOA4; the first output terminal Gout of the shift register GOA4 provides a gate signal G4 to the fourth row of pixels, the second output terminal Out_C of the shift register GOA4 is connected to the signal input terminal INPUT of the shift register GOA6, and the row reset signal terminal RST of the shift register GOA4 is connected to the second output terminal Out_C of the shift register GOA6; the first output terminal Gout of the shift register GOA6 provides a gate signal G6 to the sixth row of pixels.

[0164] Figure 8 FIG. 1 is a schematic diagram of a gate driving circuit in a display panel according to an embodiment of the present disclosure. In another embodiment, Figure 8 As shown, the display panel may include a first frame area and a second frame area located on both sides of the display area, the gate driving circuit located in the first frame area is used to provide gate signals to odd-numbered rows of pixels, and the gate driving circuit located in the second frame area is used to provide gate signals to even-numbered rows of pixels. The gate driving circuit located in the first frame area includes shift registers GOA1, GOA3, GOA5, GOA7, ...; the gate driving circuit located in the second frame area includes shift registers GOA2, GOA4, GOA6, GOA8, ...

[0165] Among them, the signal input terminal INPUT of the shift register GOA1 is connected to the first initial signal STV1, and the clock signal terminal CLK of the shift register GOA1 is connected to the first clock signal GCLK1; the signal input terminal INPUT of the shift register GOA2 is connected to the second initial signal STV2, and the clock signal terminal CLK of the shift register GOA2 is connected to the second clock signal GCLK2; the signal input terminal INPUT of the shift register GOA3 is connected to the third initial signal STV3, and the clock signal terminal CLK of the shift register GOA3 is connected to the third clock signal GCLK3; the signal input terminal INPUT of the shift register GOA4 is connected to the fourth initial signal STV4, and the clock signal terminal CLK of the shift register GOA4 is connected to the fourth clock signal GCLK4. The timing diagram of the four initial signals and the four clock signals can be referred to Fig. 9 , Fig. 9 for Figure 8 A timing diagram of the middle gate drive circuit, Fig. 9 The timing diagram of four initial signals and four clock signals is shown. Fig. 9 It can be seen that the timings of the first initial signal STV1, the second initial signal STV2, the third initial signal STV3 and the fourth initial signal STV4 are arranged in sequence, so that the shift registers GOA1, GOA2, GOA3, GOA4 output gate signals G1, G2, G3, G4 in sequence.

[0166] Based on the inventive concept of the aforementioned embodiment, the embodiment of the present disclosure further provides a display device, the display device includes the shift register in any embodiment of the present disclosure or includes the gate drive circuit in any embodiment of the present disclosure. Exemplarily, the display device may include a display panel, and the shift register or the gate drive circuit may be arranged in a border area outside the display area of ​​the display panel.

[0167] The display device can be: electronic paper, mobile phone, tablet computer, television, monitor, notebook computer, digital photo frame, navigator, wearable display device, or any other product or component with display function.

[0168] In the description of this specification, it should be understood that the terms "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present disclosure.

[0169] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present disclosure, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0170] In the present disclosure, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or a communication; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present disclosure can be understood according to specific circumstances.

[0171] In the present disclosure, unless otherwise clearly specified and limited, a first feature being “above” or “below” a second feature may include that the first and second features are in direct contact, or may include that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, a first feature being “above”, “above”, and “above” a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. A first feature being “below”, “below”, and “below” a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is lower in level than the second feature.

[0172] The disclosure above provides many different embodiments or examples to implement different structures of the present disclosure. In order to simplify the present disclosure, the components and settings of specific examples are described above. Of course, they are only examples, and the purpose is not to limit the present disclosure. In addition, the present disclosure can repeat reference numbers and / or reference letters in different examples, and this repetition is for the purpose of simplification and clarity, which itself does not indicate the relationship between the various embodiments and / or settings discussed.

[0173] The above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of various changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A shift register, characterized in that: include: An input circuit, coupled to the signal input terminal, the input power terminal and the pull-up node respectively, and configured to provide the signal of the input power terminal to the pull-up node under the control of the signal of the signal input terminal; A first pull-down circuit is coupled to the pull-up node, the third power supply terminal and the first pull-down node respectively, and is configured to provide the signal of the third power supply terminal to the first pull-down node under the control of the signal of the pull-up node; A first pull-down control circuit is coupled to the first power supply terminal and the first auxiliary node respectively, and is configured to provide the signal of the first power supply terminal to the first auxiliary node under the control of the signal of the first power supply terminal; an inhibition circuit, coupled to the control signal terminal, the first auxiliary node and the first pull-down node respectively, and configured to disconnect the first auxiliary node and the first pull-down node based on the signal of the control signal terminal when the signal of the pull-up node is an on signal; A first output circuit is coupled to the pull-up node, the clock signal terminal and the first output terminal respectively, and is configured to provide the signal of the clock signal terminal to the first output terminal under the control of the start signal of the pull-up node; The first output pull-down circuit is coupled to the first pull-down node, the fourth power supply terminal and the first output terminal respectively, and is configured to provide the signal of the fourth power supply terminal to the first output terminal under the control of the first pull-down node.

2. The shift register according to claim 1, characterized in that: The suppression circuit is further configured to, when the signal of the pull-up node is a shutdown signal, enable the first auxiliary node and the first pull-down node to be conductive based on the signal of the control signal terminal.

3. The shift register according to claim 1, characterized in that: The suppression circuit includes a nineteenth transistor, a gate of the nineteenth transistor is coupled to a control node, the control node is coupled to the control signal terminal, and a first electrode and a second electrode of the nineteenth transistor are coupled to the first auxiliary node and the first pull-down node respectively.

4. The shift register according to claim 3, characterized in that: The suppression circuit further includes a state control subcircuit, wherein the state control subcircuit is coupled to the control signal terminal, the first voltage signal, the second voltage signal and the control node respectively; The state control subcircuit is configured to provide the first voltage signal to the control node based on the signal of the control signal terminal when the signal of the pull-up node is an on signal, so that the first electrode and the second electrode of the nineteenth transistor are disconnected; and / or, The state control subcircuit is configured to provide the second voltage signal to the control node based on the signal of the control signal terminal when the signal of the pull-up node is a shutdown signal, so as to turn on the first electrode and the second electrode of the nineteenth transistor.

5. The shift register according to claim 4, characterized in that: The state control subcircuit satisfies at least one of the following: The state control subcircuit comprises a first control transistor, a gate of the first control transistor is coupled to the control signal terminal, a first electrode and a second electrode of the first control transistor are coupled to the first voltage signal and the control node respectively, and when the signal of the pull-up node is an on signal, the signal of the control signal terminal controls the first control transistor to be turned on; The state control subcircuit includes a second control transistor, a gate of the second control transistor is coupled to the control signal terminal, a first electrode and a second electrode of the second control transistor are coupled to the second voltage signal and the control node respectively, and when the signal of the pull-up node is a closed signal, the signal of the control signal terminal controls the second control transistor to turn on.

6. The shift register according to claim 5, characterized in that: The first control transistor includes an NMOS, and the second control transistor includes a PMOS.

7. The shift register according to claim 1, characterized in that: The level state of the control signal terminal is the same as that of the pull-up node; The signal at the control signal end includes the first preset signal and the second preset signal, and the level states of the first preset signal and the second preset signal are opposite.

8. The shift register according to claim 7, characterized in that: The control signal terminal is coupled to the pull-up node.

9. The shift register according to any one of claims 1 to 8, characterized in that: Also includes: A second pull-down circuit is coupled to the pull-up node, the third power supply terminal and the second pull-down node respectively, and is configured to provide the signal of the third power supply terminal to the second pull-down node under the control of the signal of the pull-up node; A second pull-down control circuit is coupled to the second power supply terminal and the second auxiliary node respectively, and is configured to provide the signal of the second power supply terminal to the second auxiliary node under the control of the signal of the second power supply terminal; A second output pull-down circuit is coupled to the second pull-down node, the fourth power supply terminal and the first output terminal respectively, and is configured to provide a signal of the fourth power supply terminal to the first output terminal under the control of the second pull-down node; The inhibition circuit is also coupled to the second auxiliary node and the second pull-down node, and is further configured to disconnect the second auxiliary node and the second pull-down node based on the signal at the control signal end when the signal at the pull-up node is an on signal; and / or, the inhibition circuit is further configured to turn on the second auxiliary node and the second pull-down node based on the signal at the control signal end when the signal at the pull-up node is a off signal.

10. The shift register according to claim 9, characterized in that: The suppression circuit includes a twenty-ninth transistor, a gate of the twenty-ninth transistor is coupled to a control node, the control node is connected to the control signal terminal, and a first electrode and a second electrode of the twenty-ninth transistor are coupled to the second auxiliary node and the second pull-down node respectively.

11. The shift register according to claim 9, characterized in that: Also includes at least one of the following: a first auxiliary pull-down circuit, coupled to the signal input terminal, the third power terminal and the first pull-down node respectively, and configured to provide the signal of the third power terminal to the first pull-down node under the control of the signal of the signal input terminal; A first noise reduction circuit is coupled to the first pull-down node, the third power supply terminal and the pull-up node respectively, and is configured to provide a signal of the third power supply terminal to the pull-up node under the control of a signal of the first pull-down node; A second auxiliary pull-down circuit is coupled to the signal input terminal, the third power supply terminal and the second pull-down node respectively, and is configured to provide the signal of the third power supply terminal to the second pull-down node under the control of the signal of the signal input terminal; A second noise reduction circuit is coupled to the second pull-down node, the third power supply terminal and the pull-up node respectively, and is configured to provide the signal of the third power supply terminal to the pull-up node under the control of the signal of the second pull-down node; A row reset circuit, coupled to the row reset signal terminal, the third power supply terminal and the pull-up node respectively, and configured to provide the signal of the third power supply terminal to the pull-up node under the control of the signal of the row reset signal terminal; A frame reset circuit is coupled to the frame reset signal terminal, the third power supply terminal and the pull-up node respectively, and is configured to provide the signal of the third power supply terminal to the pull-up node under the control of the signal of the frame reset signal terminal; The output reset circuit is coupled to the row reset signal terminal, the fourth power supply terminal and the first output terminal respectively, and is configured to provide the signal of the fourth power supply terminal to the first output terminal under the control of the signal of the row reset signal terminal.

12. The shift register according to claim 9, characterized in that: The level states of the first power supply terminal and the second power supply terminal are opposite.

13. The shift register according to claim 11, characterized in that: Satisfy at least one of the following: The input circuit comprises a first transistor, a gate of the first transistor is coupled to the signal input terminal, and a first electrode and a second electrode of the first transistor are respectively coupled to the input power supply terminal and the pull-up node; The first pull-down circuit includes a sixteenth transistor, a gate of the sixteenth transistor is coupled to the pull-up node, and a first electrode and a second electrode of the sixteenth transistor are respectively coupled to the third power supply terminal and the first pull-down node; The first pull-down control circuit includes a fifteenth transistor, a gate and a first electrode of the fifteenth transistor are coupled to the first power supply terminal, and a second electrode of the fifteenth transistor is coupled to the first auxiliary node; The first auxiliary pull-down circuit includes a seventeenth transistor, a gate of the seventeenth transistor is coupled to the signal input terminal, and a first electrode and a second electrode of the seventeenth transistor are respectively coupled to the third power supply terminal and the first pull-down node; The first noise reduction circuit includes an eighteenth transistor, a gate of the eighteenth transistor is coupled to the first pull-down node, and a first electrode and a second electrode of the eighteenth transistor are respectively coupled to the third power supply terminal and the pull-up node; The second pull-down circuit comprises a twenty-sixth transistor, a gate of the second sixteenth transistor is coupled to the pull-up node, and a first electrode and a second electrode of the second sixteenth transistor are respectively coupled to the third power supply terminal and the second pull-down node; The second pull-down control circuit includes a twenty-fifth transistor, a gate and a first electrode of the twenty-fifth transistor are both coupled to the second power supply terminal, and a second electrode of the twenty-fifth transistor is coupled to the second auxiliary node; The second auxiliary pull-down circuit comprises a twenty-seventh transistor, a gate of the twenty-seventh transistor is coupled to the signal input terminal, and a first electrode and a second electrode of the twenty-seventh transistor are respectively coupled to the third power supply terminal and the second pull-down node; The second noise reduction circuit includes a twenty-eighth transistor, a gate of the twenty-eighth transistor is coupled to the second pull-down node, and a first electrode and a second electrode of the twenty-eighth transistor are respectively coupled to the third power supply terminal and the pull-up node; The first output circuit comprises a third transistor, a gate of the third transistor is coupled to the pull-up node, and a first electrode and a second electrode of the third transistor are respectively coupled to the clock signal terminal and the first output terminal; The first output pull-down module comprises an eleventh transistor, a gate of the eleventh transistor is coupled to the first pull-down node, and a first electrode and a second electrode of the eleventh transistor are respectively coupled to the fourth power supply terminal and the first output terminal; The second output pull-down module includes a twenty-first transistor, a gate of the twenty-first transistor is coupled to the second pull-down node, and a first electrode and a second electrode of the twenty-first transistor are respectively coupled to the fourth power supply terminal and the first output terminal; The row reset circuit comprises a second transistor, a gate of the second transistor is coupled to the row reset signal terminal, and a first electrode and a second electrode of the second transistor are respectively coupled to the third power supply terminal and the pull-up node; The frame reset circuit comprises a seventh transistor, a gate of the seventh transistor is coupled to the frame reset signal terminal, and a first electrode and a second electrode of the seventh transistor are respectively coupled to the third power supply terminal and the pull-up node; The output reset circuit includes a fourth transistor, a gate of the fourth transistor is coupled to the row reset signal terminal, and a first electrode and a second electrode of the fourth transistor are coupled to the fourth power supply terminal and the first output terminal respectively.

14. A shift register driving method, characterized in that: Applied to the shift register according to any one of claims 1 to 13, the method comprising: In the first stage, a valid level signal is provided to the signal input terminal, and the input circuit provides a signal from the input power terminal to the pull-up node under the control of the valid level signal of the signal input terminal; the first pull-down circuit provides a signal from the third power terminal to the first pull-down node under the control of the signal of the pull-up node; and a first preset signal is provided to the control signal terminal, so that the first auxiliary node and the first pull-down node are disconnected; In the second stage, a valid level signal is provided to the row reset signal terminal, and the row reset circuit provides the signal of the third power supply terminal to the pull-up node under the control of the valid level signal of the row reset signal terminal; the first pull-down control circuit provides the signal of the first power supply terminal to the first auxiliary node under the control of the signal of the first power supply terminal; and a second preset signal is provided to the control signal terminal, so that the first auxiliary node and the first pull-down node are turned on.

15. A gate driving circuit, characterized in that: The invention comprises the shift register according to any one of claims 1 to 13.

16. A display device, characterized in that: A shift register comprising any one of claims 1 to 13 or a gate drive circuit comprising claim 15.

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