Memory system, operating method of memory controller, and memory device

Abstract

Disclosed is a memory system including: a memory device including a memory cell array and a notification circuit; and a memory controller that transmits a refresh management (RFM) command to the memory device based on the occurrence number of bank activations of the banks included in the memory cell array reaching a threshold value. The memory controller controls a transmission frequency of the RFM command based on the notification obtained by the notification circuit. The notification includes at least one of a row hammer risk included in a row in the memory bank, or temperature information including a temperature range of the memory device.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the priority of Korean Patent Application No. 10-2023-0176034 filed in the Korean Intellectual Property Office on December 6, 2023, and Korean Patent Application No. 10-2024-0069559 filed in the Korean Intellectual Property Office on May 28, 2024, the disclosures of which are incorporated herein by reference in their entirety. Technical Field

[0002] Embodiments of the present disclosure described herein relate to a memory system, an operating method of a memory controller, and a memory device. Background Art

[0003] Row hammer refers to a phenomenon in which, when a row of a dynamic random access memory (DRAM) (e.g., an attack row) is frequently accessed, data in rows physically adjacent to the corresponding row (e.g., a victim row) changes. Summary of the invention

[0004] Embodiments of the present disclosure provide a memory system, an operating method of a memory controller, and a memory device capable of variably controlling a transmission frequency of an RFM command according to a condition of a memory device.

[0005] The row hammer problem can be solved by performing a row hammer refresh operation on the at-risk rows at the appropriate time. Nowadays, the row hammer problem has become very serious because DRAM is manufactured using nanometer-level manufacturing processes. Accordingly, a refresh management (RFM) interface is being introduced to provide additional row hammer refresh opportunities for DRAM. When the number of activations of each memory bank of the DRAM reaches a fixed specific threshold, the memory controller issues an RFM command, and the DRAM can perform a row hammer refresh operation based on the received RFM command.

[0006] In this case, uniformly issuing RFM commands according to a fixed standard may cause unnecessary transmission of RFM commands, thereby causing loss of bandwidth efficiency of the memory system or degradation of memory system performance. The present disclosure relates to a technology for more appropriately issuing RFM commands in consideration of the situation of DRAM.

[0007] According to an embodiment, a memory system may include: a memory device including a memory cell array and a notification circuit; and a memory controller configured to send a refresh management (RFM) command to the memory device based on the number of occurrences of memory cell activation of a memory cell included in the memory cell array reaching a threshold value. The memory controller is configured to control the frequency of sending the RFM command based on a notification obtained through the notification circuit. The notification includes at least one of the following information: a row hammer risk of a row included in the memory cell, or information including a current temperature of the memory device.

[0008] In addition, the storage body may include: a plurality of rows arranged along a row direction; and a plurality of counting units configured to store counting data associated with the number of occurrences of activation of each of the plurality of rows, and risk information associated with the row hammer risk indicates that the counting data reaches a reference count.

[0009] In addition, the notification circuit may include at least one of an alarm pin or a first register. In response to the count data stored in at least one of the plurality of counting units reaching the reference count, the alarm pin may send a risk signal to indicate a risk condition. In response to the count data stored in at least one of the plurality of counting units reaching the reference count, the first register may store flag data to indicate a risk condition.

[0010] Furthermore, the memory controller may obtain the row hammer risk based on the flag data stored in the first register or the risk signal transmitted by the alarm pin.

[0011] In addition, the memory controller can operate in one of a first mode or a second mode based on the row hammer risk. In the first mode, the memory controller can maintain operation without sending an RFM command regardless of the number of occurrences of memory bank activation, and in the second mode, the memory controller can send an RFM command based on the number of occurrences of memory bank activation reaching a threshold.

[0012] Furthermore, based on the flag data including the first data indicating the risk situation, the memory controller may operate in the second mode, otherwise, the memory controller may operate in the first mode.

[0013] Additionally, the memory controller may perform a read operation on the first register to obtain a row hammer risk based on a number of occurrences of bank activation reaching a threshold.

[0014] In addition, in the first mode, based on the number of occurrences of storage body activation reaching a threshold, the memory controller can perform a read operation on the first register, and switch the operation mode from the first mode to the second mode based on obtaining flag data indicating a risk situation, and switch the operation mode from the second mode back to the first mode in response to sending a set number of RFM commands to perform a read operation on the first register.

[0015] Furthermore, when an alert signal is applied through the alert pin, the memory controller may operate in the second mode, and when the obtained flag data does not indicate a risk condition, the memory controller may operate in the first mode.

[0016] Furthermore, based on applying the risk signal through the alert pin while operating in the first mode, the memory controller may operate in the second mode until the RFM command is sent no more than a predetermined number of times before performing a read operation on the first register.

[0017] In addition, the memory controller may set the operation mode to one of a third mode or a fourth mode based on the row hammer risk. In the third mode, the memory controller may send an RFM command based on the number of occurrences of the memory bank activation reaching a first threshold, and in the fourth mode, the memory controller may send an RFM command based on the number of occurrences of the memory bank activation reaching a second threshold. The value of the second threshold may be less than the value of the first threshold.

[0018] Furthermore, the memory controller may set the operation mode to the fourth mode based on applying a risk signal through the alarm pin or obtaining flag data indicating a risk situation by performing a read operation on the first register when operating in the third mode.

[0019] Furthermore, when operating in the fourth mode, the memory controller may perform a read operation on the first register based on the RFM command being sent no more than a predetermined number of times, otherwise, the memory controller may operate in the third mode.

[0020] Furthermore, the notification circuit may include a second register storing temperature information of the memory device, and the memory controller may obtain the temperature information based on a read operation of the second register, and may adjust the threshold value based on the obtained temperature information.

[0021] In addition, the memory device may operate at a first refresh interval within a first temperature range, and may have a second refresh interval shorter than the first refresh interval within a second temperature range. The memory controller may send an RFM command based on the number of occurrences of memory bank activation reaching a third threshold within the first temperature range, and may send an RFM command based on the number of occurrences of memory bank activation reaching a fourth threshold within the second temperature range. The value of the third threshold may be less than the value of the fourth threshold.

[0022] In addition, the memory controller can count the number of occurrences of storage body activation in response to an activation command being sent to the storage body, and can sum the storage body activation time of the storage body based on the activation command sent, and can send an RFM command based on the number of occurrences of storage body activation reaching a threshold or based on the summed storage body activation time reaching a time threshold.

[0023] In addition, based on the storage body activation time being equal to or less than the reference time, the memory controller may increase the number of occurrences of the storage body activation by a first value, and based on the storage body activation time exceeding the reference time, the memory controller may increase the number of occurrences of the storage body activation by a second value greater than the first value.

[0024] According to an embodiment, a method of operating a memory controller that controls a memory device may include: sending a refresh management (RFM) command to a memory device based on a number of occurrences of memory bank activation of a memory bank of the memory device reaching a threshold; obtaining a notification that includes at least one of the following information: information related to a row hammer risk of each row included in a memory bank of the memory device, or temperature information including a temperature range of the memory device; and controlling a sending frequency of the RFM command based on the notification.

[0025] Additionally, controlling the frequency of sending the RFM command may include selectively sending the RFM command based on the notification, or adjusting a threshold based on the notification.

[0026] According to an embodiment, a memory device may include: a memory cell array including a memory bank; a row hammer management circuit; and a notification circuit including at least one of an alarm pin or a register. The memory bank may include: a plurality of rows arranged in a row direction; and a plurality of counting units storing count data associated with the number of occurrences of activation of each of the plurality of rows. The row hammer management circuit may manage the count data of each of the plurality of rows, and may store flag data indicating a risk situation in a register based on the count data stored in at least one of the plurality of counting units reaching a reference count, and apply a risk signal indicating the risk situation to the alarm pin. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The above and other objects and features of the present disclosure will become apparent by describing in detail embodiments of the present disclosure with reference to the attached drawings.

[0028] Figure 1 is a block diagram of a memory system according to an embodiment of the present disclosure.

[0029] Figure 2A is a block diagram of a memory device according to an embodiment of the present disclosure.

[0030] Figure 2B is a block diagram of a memory device according to an embodiment of the present disclosure.

[0031] Figure 3A is a diagram of an example of a memory bank according to an embodiment of the present disclosure.

[0032] Figure 3Bis a diagram showing an example of a bank in which a count unit is included in a count unit region.

[0033] Figure 3C is a diagram showing an example of a memory bank in which a count unit and a parity unit are included in a count unit region.

[0034] Figure 4 is a block diagram illustrating a memory device according to an embodiment of the present disclosure in detail.

[0035] Figure 5A is a block diagram of a memory controller according to an embodiment of the present disclosure.

[0036] Figure 5B is a flowchart illustrating an operating method of a memory controller according to an embodiment of the present disclosure.

[0037] Figure 6 is a block diagram showing a configuration of an RFM control logic according to an embodiment of the present disclosure.

[0038] Figure 7 is a flowchart illustrating an operating method of a memory controller according to an embodiment of the present disclosure.

[0039] Figure 8 is a flowchart illustrating an operating method of a memory controller according to an embodiment of the present disclosure.

[0040] Fig. 9 is a flowchart illustrating an operating method of a memory controller according to an embodiment of the present disclosure.

[0041] Fig.10 is a diagram for describing an operation of selectively transmitting an RFM command according to an embodiment of the present disclosure.

[0042] Fig.11 is a flowchart illustrating an operating method of a memory controller according to an embodiment of the present disclosure.

[0043] Fig.12 is a flowchart illustrating an operating method of a memory controller according to an embodiment of the present disclosure.

[0044] Fig.13 is a flowchart illustrating an operating method of a memory controller according to an embodiment of the present disclosure.

[0045] Fig.14 is a diagram for describing an operation of adjusting a BAT value according to an embodiment of the present disclosure.

[0046] Fig.15 is a block diagram of a memory device according to an embodiment of the present disclosure.

[0047] Fig.16 is a block diagram illustrating RFM control logic according to an embodiment of the present disclosure.

[0048] Fig.17 is a diagram for describing an example of a BAT value for each temperature range according to an embodiment of the present disclosure.

[0049] Fig.18 is a diagram for describing an operation of adjusting a BAT value according to an embodiment of the present disclosure.

[0050] Fig.19 is a block diagram of RFM control logic according to an embodiment of the present disclosure.

[0051] Fig. 20 is a diagram for describing a memory bank activation time according to an embodiment of the present disclosure.

[0052] Fig.21 is a flowchart illustrating an operating method of a memory controller according to an embodiment of the present disclosure.

[0053] Fig.22A is a flowchart illustrating an operating method of a memory controller according to an embodiment of the present disclosure.

[0054] Fig. 22B is a flowchart illustrating an operating method of a memory controller according to an embodiment of the present disclosure.

[0055] Fig.23 is a diagram for describing an operation of transmitting an RFM command in consideration of a bank activation time according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0056] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings so that those skilled in the art to which the present disclosure pertains can easily implement the present disclosure.

[0057] Figure 1 is a block diagram of a memory system according to an embodiment of the present disclosure.

[0058] According to an embodiment of the present disclosure, the memory device 200 may include a notification circuit 700 for notifying the memory controller 100 of a notification associated with a situation of the memory device 200. In an embodiment, the notification may include at least one of the following information: information related to a row hammer risk of a row included in each memory bank of the memory cell array 310, or temperature information indicating a current temperature range including a current temperature of the memory device 200.

[0059] The memory controller 100 may send a refresh management (RFM) command to the memory device 200 based on whether the number of activation times of the storage bodies included in the memory device 200 reaches a threshold value. In an embodiment, the memory controller 100 may variably control the frequency of sending the RFM command based on information associated with the situation of the memory device 200. For example, based on a notification obtained through the notification circuit 700, the memory controller 100 may selectively control whether to send the RFM command, or may adjust a threshold value associated with the sending of the RFM command. In addition, the memory controller 100 may further send the RFM command in consideration of the activation time of the storage bodies included in the memory device 200. Accordingly, the bandwidth efficiency of the memory system 10 and the performance of the memory system 10 may be improved.

[0060] Will refer to Figure 1 Describe it in detail. Figure 1 , the memory system 10 may include a memory controller 100 and a memory device 200 .

[0061] The memory device 200 may receive data from the memory controller 100 and may store the received data. The memory device 200 may read the stored data in response to a request of the memory controller 100 and may transmit the read data to the memory controller 100.

[0062] In an embodiment, the memory device 200 may be a memory device including a volatile memory cell. For example, the memory device 200 may include various dynamic random access memory devices (DRAM), such as double data rate synchronous DRAM (DDRSDRAM), DDR2 SDRAM, DDR3 SDRAM, DDR4 SDRAM, DDR5 SDRAM, DDR6 SDRAM, low power double data rate (LPDDR) SDRAM, LPDDR2 SDRAM, LPDDR3 SDRAM, LPDDR4 SDRAM, LPDDR4X SDRAM, LPDDR5SDRAM, graphic double data rate synchronous graphic random access memory (GDDR SGRAM), GDDR2 SGRAM, GDDR3 SGRAM, GDDR4 SGRAM, GDDR5 SGRAM, and GDDR6 SGRAM.

[0063] Furthermore, in an implementation, the memory device 200 may be a stacked memory device (in which DRAM dies are stacked), such as a high bandwidth memory (HBM), HBM2, or HBM3.

[0064] In addition, in an embodiment, the memory device 200 may be a memory module, such as a dual in-line memory module (DIMM). For example, the memory device 200 may be a registered DIMM (RDIMM), a load-reduced DIMM (LRDIMM), an unbuffered DIMM (UDIMM), a fully buffered DIMM (FB-DIMM), or a small outline DIMM (SO-DIMM). However, this is provided only as an example, and the memory device 200 may be any other memory module, such as a single in-line memory module (SIMM).

[0065] Furthermore, in an implementation, the memory device 200 may be an SRAM device, a NAND flash memory device, a NOR flash memory device, an RRAM device, a FRAM device, a PRAM device, a TRAM device, an MRAM device, or the like.

[0066] The memory device 200 may include a memory cell array 310 and a notification circuit 700 .

[0067] The memory cell array 310 may include a plurality of memory banks. Each of the plurality of memory banks may include a memory cell for storing data. For ease of description, in the specification, it is assumed that each memory bank includes a DRAM cell. However, this is provided only as an example, and each of the plurality of memory banks may be implemented to include any other volatile memory cell other than a DRAM cell. In addition, according to an embodiment, the plurality of memory banks may be implemented to include the same type of memory cells, or may be implemented to include different types of memory cells.

[0068] Each of the plurality of memory banks may include a plurality of rows. Here, a row may refer to a wire that is arranged to extend in a row direction and is electrically connected to a memory cell. For example, a row may refer to a word line that is arranged to extend in a row direction. However, this is provided only as an example. According to an embodiment, a row may refer to a plurality of word lines that are arranged to extend in a row direction.

[0069] The notification circuit 700 may notify the memory controller 100 of a notification associated with a situation of the memory device 200. For example, the memory device 200 may notify the memory circuit of a row hammer risk of a row included in a memory bank of the memory cell array 310 through the notification circuit 700. In an embodiment, the row hammer risk may indicate whether count data associated with the number of activations of each row in the memory bank reaches a reference count. In addition, the memory device 200 may notify temperature information related to a temperature range to which the current temperature of the memory device 200 belongs through the notification circuit 700.

[0070] Meanwhile, when the memory device 200 has a row hammer refresh opportunity, the memory device 200 may perform a row hammer refresh operation. In an embodiment, the row hammer refresh opportunity may include a case where a refresh (REF) command is applied from the memory controller 100 or a case where an RFM command is applied from the memory controller 100.

[0071] The memory controller 100 may control the memory device 200. For example, the memory controller 100 may control the memory device 200 according to a request of a processor supporting various applications such as server applications, personal computer (PC) applications, and mobile applications. For example, the memory controller 100 may be included in a host device including a processor, and may control the memory device 200 according to a request of the processor.

[0072] In order to control the memory device 200, the memory controller 100 may transmit a command and / or an address to the memory device 200. In addition, the memory controller 100 may transmit data to the memory device 200 or may receive data from the memory device 200.

[0073] The memory controller 100 may count the number of bank activations. For example, when the memory controller 100 sends an activate (ACT) command to a specific bank of the memory device 200, the memory controller 100 may increase the number of bank activations by "1". However, the present disclosure is not limited thereto. In addition, the memory controller 100 may send an RFM command to the memory device 200 based on whether the number of bank activations has reached a threshold. In an embodiment, the threshold may be a bank activation threshold (BAT). Below, for convenience, the threshold of the number of bank activations used as a standard for sending the RFM command will be referred to as "BAT" for explanation.

[0074] In an implementation, the memory controller 100 may control the transmission frequency of the RFM command based on the notification obtained through the notification circuit 700 .

[0075] According to an embodiment, the memory controller 100 may selectively send an RFM command based on a row hammer risk. For example, the memory controller 100 may operate in a first mode or a second mode based on the row hammer risk. In the first mode, the memory controller 100 may not send an RFM command even if the number of storage body activations reaches BAT; in the second mode, the memory controller 100 may send an RFM command when the number of storage body activations reaches BAT. Specifically, the memory controller 100 may identify whether the memory device 200 is in a risk situation associated with a row hammer based on the row hammer risk obtained by the notification circuit 700. Accordingly, in an embodiment, the memory controller 100 may operate in a first mode when the current situation is not a risk situation, and the memory controller 100 may operate in a second mode when the current situation is a risk situation. Since the memory controller 100 operates in a first mode or a second mode according to the current situation, the sending frequency of the RFM command may be variably controlled.

[0076] Alternatively, according to an embodiment, the memory controller 100 may adjust the BAT based on the row hammer risk. For example, the memory controller 100 may operate in the third mode or the fourth mode based on the row hammer risk. In the third mode, when the number of storage body activations reaches a first threshold value (hereinafter referred to as "BAT1"), the memory controller 100 may send an RFM command; in the fourth mode, when the number of storage body activations reaches a second threshold value (hereinafter referred to as "BAT2"), the memory controller 100 may send an RFM command. In an embodiment, the value of BAT2 may be less than the value of BAT1. Specifically, the memory controller 100 may identify whether the memory device 200 is in a risk situation associated with a row hammer based on the row hammer risk obtained by the notification circuit 700. Accordingly, in the above example, since the memory controller 100 operates in the third mode when the current situation is not a risk situation, and the memory controller 100 operates in the fourth mode when the current situation is a risk situation, the memory controller 100 may variably control the frequency of sending the RFM command.

[0077] Alternatively, according to an embodiment, the memory controller 100 may adjust the BAT based on temperature information including a temperature range of the memory device 200. The memory device 200 may have different refresh intervals (tREFI) according to the temperature range. In an embodiment, the refresh interval refers to a time period during which a REF command is sent from the memory controller 100 to the memory device 200. For example, the memory device 200 may have a first refresh interval in a first temperature range, and may have a second refresh interval shorter than the first refresh interval in a second temperature range higher than the first temperature range. In this case, since the sending cycle of the REF command is relatively long in the low temperature range, the row hammer refresh opportunity based on the REF command in the low temperature range may also be reduced. That is, since the degree of loss of the row hammer refresh opportunity based on the REF command varies with the temperature range, the number of RFM commands required to compensate for the loss of the row hammer refresh opportunity may also vary with the temperature range.

[0078] In an embodiment, when the number of storage body activations reaches a third threshold value (hereinafter referred to as "BAT3") under the condition that the temperature range of the memory device 200 is the first temperature range, the memory controller 100 may send an RFM command; when the number of storage body activations reaches a fourth threshold value (hereinafter referred to as "BAT4") under the condition that the temperature range of the memory device 200 is the second temperature range, the memory controller 100 may send an RFM command. In an embodiment, the value of BAT3 may be less than the value of BAT4. That is, the memory controller 100 may variably control the sending frequency of the RFM command based on the temperature information including the temperature range of the memory device 200. In this case, the sending frequency of the RFM command may be relatively high within the first temperature range and may be relatively low within the second temperature range. Accordingly, the loss of the row hammer refresh opportunity based on the REF command may be appropriately compensated according to the temperature range. Specifically, the burden of the memory controller 100 for sending the RFM command may be reduced within a relatively high temperature range.

[0079] Meanwhile, the memory controller 100 may further transmit the RFM command in consideration of the bank activation time of the memory bank included in the memory cell array 310. In this case, the transmission frequency of the RFM command may be variably controlled based on the bank activation time.

[0080] According to an embodiment, in response to whether the memory controller 100 sends an ACT command for a specific memory bank of the memory device 200, the memory controller 100 may count the number of memory bank activations of the corresponding memory bank, and may sum the memory bank activation time of the corresponding memory bank based on the sent ACT command. In an embodiment, the memory bank activation time may refer to the time from the time point when the ACT command is sent to the time point when the precharge (PRE) command after the ACT command is sent, but the present disclosure is not limited thereto. Accordingly, when the number of memory bank activations reaches BAT or the summed memory bank activation time reaches a threshold, the memory controller 100 may send an RFM command to the memory device 200. Below, for convenience, the description of the threshold associated with the memory bank activation time is referred to as "memory bank activation time threshold (BATT)". In this case, even if the number of memory bank activations does not reach BAT, the RFM command may be sent when the memory bank activation time reaches BATT.

[0081] Alternatively, according to an embodiment, when the bank activation time is equal to or less than the reference time, the memory controller 100 may increase the bank activation count by a first value (e.g., "1"); when the bank activation time exceeds the reference time, the memory controller 100 may increase the bank activation count by a second value (e.g., "2") greater than the first value. Accordingly, when the bank activation count reaches BAT, the memory controller 100 may send an RFM command to the memory device 200. In this case, as more commands with bank activation times exceeding the reference time are sent, the faster the bank activation count may increase. This may mean that the RFM command is sent more frequently.

[0082] According to the above-described embodiment further considering the bank activation time, it is possible to cope with a problem caused by a pass gate effect (PGE) phenomenon, that is, a problem in which the probability of data loss of a victim row increases as the activation time of a target row increases.

[0083] At the same time, refer to Figure 1 The described embodiments may be independently implemented in the memory system 10 , but the present disclosure is not limited thereto. For example, at least one embodiment may be implemented together in the memory system 10 .

[0084] According to the above-described embodiment, the transmission frequency of the RFM command can be variably controlled in consideration of various conditions of the memory device 200, such as row hammer risk, refresh interval time according to temperature range, and PGE phenomenon of the memory cell. Accordingly, the bandwidth efficiency of the memory system or the performance of the memory system can be improved.

[0085] Meanwhile, in the specification, the case where the number of storage body activations reaches the threshold value BAT, BAT1, BAT2, BAT3 or BAT4 may include the case where the number of storage body activations increased is greater than the threshold value BAT, BAT1, BAT2, BAT3 or BAT4, in addition to the case where the number of storage body activations increased is consistent with the threshold value BAT, BAT1, BAT2, BAT3 or BAT4. That is, the case where the number of storage body activations increased is greater than the threshold value BAT, BAT1, BAT2, BAT3 or BAT4 due to abnormal operation or design change may also correspond to the case where the number of storage body activations reaches the threshold value BAT, BAT1, BAT2, BAT3 or BAT4.

[0086] For example, due to abnormal operation of the memory controller 100, the number of storage body activations increased by "1" may skip the threshold value BAT, BAT1, BAT2, BAT3, or BAT4, and may exceed the threshold value BAT, BAT1, BAT2, BAT3, or BAT4. This situation may also be included in the case where the number of storage body activations reaches the threshold value BAT, BAT1, BAT2, BAT3, or BAT4. In addition, for example, the threshold value BAT, BAT1, BAT2, BAT3, or BAT4 may be set to 65, but when the memory controller 100 is designed to increase the number of storage body activations by "2", the number of storage body activations increased by "2" may directly increase from 64 to 66 without reaching "65". This situation may also be included in the case where the number of storage body activations reaches the threshold value BAT, BAT1, BAT2, BAT3, or BAT4.

[0087] At the same time, the above content can also be applied to the case where the storage body activation time reaches the threshold value (BATT). That is, in the specification, the case where the summed storage body activation time reaches the threshold value BATT, in addition to the case where the summed storage body activation time is consistent with the threshold value BATT, can also include the case where the summed storage body activation time exceeds the threshold value BATT.

[0088] Next, we will refer to Figures 2A to 4 Memory devices according to various embodiments of the present disclosure are described. Figure 2A is a block diagram of a memory device according to an embodiment of the present disclosure. Figure 2A The memory device 200A may be Figure 1 The present disclosure is not limited thereto. Figure 2A In the present invention, the description given above in connection with components similar to those described above will be omitted or simplified.

[0089] Reference Figure 2A , the memory device 200A may include a memory cell array 310, a row hammer management circuit 500, and a risk notification circuit 700A.

[0090] The memory cell array 310 may include a plurality of memory banks 310_1 to 310_n, each memory bank including a memory cell for storing data. Each of the plurality of memory banks 310_1 to 310_n may include a plurality of rows. In addition, each of the plurality of memory banks 310_1 to 310_n may include a counting cell area CCA. The counting cell area CCA may include a plurality of counting cells, and each of the plurality of counting cells may store the number of activations of the corresponding row as counting data. The counting data stored in the counting cell may be referred to as "per row activation count data" or "PRAC data".

[0091] For example, when a target row is accessed based on an ACT command applied from the memory controller 100, count data may be read from a count unit corresponding to the target row in an activated state. Thereafter, the read count data may be modified, and the modified count data may be written again to the count unit corresponding to the target row. The number of activations of each of the plurality of rows may be stored in a corresponding count unit through a read-modify-write (RMW) operation.

[0092] According to an embodiment, some storage cells connected to one row may be used as counting cells. In this case, the counting cell area CCA may include counting cells associated with each of the multiple rows. Alternatively, according to an embodiment, some storage cells connected to one row may be used as counting cells, and other storage cells may be used as parity check cells. The parity check cell may store parity check data for performing an error correction operation on the counting data. In this case, the counting cell area CCA may include counting cells corresponding to the multiple rows, respectively, and a parity check cell for each of the multiple rows.

[0093] At the same time, Figure 2A In the embodiment, each of the multiple memory banks 310_1 to 310_n shows an embodiment including a counting unit area CCA. However, this is provided only as an example. According to an embodiment, some of the multiple memory banks 310_1 to 310_n may not include a counting unit area CCA. According to an embodiment, different memory banks may share the same counting unit area CCA. For example, when different memory banks share the same word line, only any one of the different memory banks may include a counting unit area CCA, and the remaining memory banks may share and use the corresponding counting unit area CCA.

[0094] The row hammer management circuit 500 may manage count data associated with each of the plurality of rows based on a command received from the memory controller 100. For example, when a word line is activated according to an ACT command received from the memory controller 100, the row hammer management circuit 500 may count the number of activations of a target row corresponding to the activated word line. Thereafter, the row hammer management circuit 500 may store the count data as the number of activations in a counting unit associated with the corresponding target row. However, this is provided only as an example, and the row hammer management circuit 500 may count the number of activations of the target row based on a precharge (PRE) command.

[0095] According to an embodiment, the row hammer management circuit 500 may perform an RMW operation to manage count data of each of the plurality of rows. In addition, according to an embodiment, the row hammer management circuit 500 may further consider an activation time of a target row to manage count data of each of the plurality of rows. In this case, when the activation time of the target row exceeds a reference time, the row hammer management circuit 500 may further additionally increase the count data.

[0096] At the same time, the row hammer management circuit 500 may notify the memory controller 100 of the row hammer risk based on the count data. In an embodiment, the row hammer risk may indicate whether the count data reaches a reference count. At the same time, the reference count may be appropriately set by the designer within the process strength of the memory cell. Here, the process strength may refer to a threshold value of the number of activations of the attack row, within which the data of the victim row will not change, but the present disclosure is not limited thereto.

[0097] Specifically, the memory device 200A may include a risk notification circuit 700A, which includes at least one of an alarm pin 711 or a mode register 712. The alarm pin 711 may be electrically connected to the memory controller 100 through an alarm signal line. A signal associated with a row hammer risk may be applied to the alarm pin 711. Accordingly, the memory controller 100 may identify the row hammer risk of the memory device 200A based on the signal applied to the alarm pin 711. In addition, the mode register 712 may store flag data associated with the row hammer risk. Accordingly, the memory controller 100 may obtain the flag data stored in the mode register 712 through a mode register read operation, and may identify the row hammer risk of the memory device 200A based on the obtained flag data.

[0098] For example, when the count data stored in at least one of the plurality of count units reaches the reference count, the row hammer management circuit 500 may apply a risk signal indicating a risk situation to the alarm pin 711. Accordingly, when the risk signal is applied to the alarm pin 711, the memory controller 100 may recognize that the row hammer risk of the memory device 200A reaches a risk level. In addition, when the count data stored in at least one of the plurality of count units reaches the reference count, the row hammer management circuit 500 may store flag data indicating a risk situation in the mode register 712. Accordingly, when the flag data indicating a risk situation is read from the mode register 712, the memory device 200A may recognize that the row hammer risk of the memory device 200A reaches a risk level. In this case, according to an embodiment, the case where the count data reaches the reference count may include, in addition to the case where the count data is consistent with the reference count, a case where the count data exceeds the reference count. Meanwhile, when no risk signal is received through the alarm pin 711 and the flag data read from the mode register 712 does not indicate a risk condition, the memory controller 100 may recognize that the row hammer risk of the memory device 200A is low.

[0099] The memory controller 100 may variably control the transmission frequency of the RFM command based on a signal applied to the alarm pin 711 or flag data stored in the mode register 712, as shown in FIG. Figure 1 described.

[0100] According to an embodiment, the memory device 200A may perform a row hammer refresh operation at various opportunities. For example, the memory device 200A may perform a row hammer refresh operation in response to an RFM command received from the memory controller 100. In addition, the memory device 200A may perform a normal refresh operation and a row hammer refresh operation in response to a REF command received from the memory controller 100. In addition, the memory device 200A may perform a row hammer refresh operation in an idle state or while performing a background operation. In this case, the memory device 200A may perform a row hammer refresh operation based on count data stored in a plurality of count units.

[0101] Figure 2B is a block diagram of a memory device according to an embodiment of the present disclosure. Figure 2B The memory device 200B may be Figure 1 and Figure 2A The present disclosure is not limited thereto. Figure 2B In the present invention, descriptions given in conjunction with components similar to those described above will be omitted or simplified.

[0102] Reference Figure 2B, the memory device 200B may include a memory cell array 310, a register group 600, a row hammer management circuit 500, and a risk notification circuit 700A.

[0103] According to an embodiment of the present disclosure, the counting data stored in the plurality of counting units may be managed by registers. To this end, the memory device 200B may include a register group 600. The register group 600 may include a plurality of registers 600_1 to 600_m. In this case, one register may correspond to one memory bank. Alternatively, one register may correspond to a plurality of memory banks.

[0104] Each of the plurality of registers 600_1 to 600_m may store information related to some of the plurality of rows included in the corresponding memory bank. For example, each of the plurality of registers 600_1 to 600_m may store addresses and count data associated with rows having relatively large count data among the plurality of rows included in the corresponding memory bank.

[0105] To this end, the row hammer management circuit 500 may update the register group 600 by using the modified count data of the target row generated by the RMW operation. For example, the row hammer management circuit 500 may select a register corresponding to the memory bank to which the target row belongs from among the registers of the register group 600. Thereafter, the row hammer management circuit 500 may compare the address and count data of the row managed in the selected register with the address and the modified count data of the target row. Based on the comparison result, the row hammer management circuit 500 may manage the address and count data of the row having relatively large count data among the multiple rows of the memory bank in the register.

[0106] In reference Figure 2A At various opportunities described, the memory device 200B may perform a row hammer refresh operation based on information of rows managed in registers of the register group 600 .

[0107] Meanwhile, according to an embodiment, the row hammer management circuit 500 may notify the memory controller 100 of the row hammer risk based on the count data stored in the registers of the register group 600. For example, when at least one of the count data managed in the registers of the register group 600 reaches the reference count, the row hammer management circuit 500 may apply a risk signal indicating a risk situation to the alarm pin 711. In addition, when at least one of the count data managed in the registers of the register group 600 reaches the reference count, the row hammer management circuit 500 may store flag data indicating a risk situation in the mode register 712. The memory controller 100 may variably control the transmission frequency of the RFM command based on the signal applied to the alarm pin 711 or the flag data stored in the mode register 712, as shown in FIG. Figure 1 described.

[0108] Figure 3A is a diagram of an example of a memory bank according to an embodiment of the present disclosure. Figure 3A The memory bank 310_1 may correspond to Figure 2A and Figure 2B The first memory bank 310_1 is a memory bank 310_2, but the present disclosure is not limited thereto. Figure 3A , the first memory bank 310_1 may include a first memory bank array 311_1 , a row decoder 260_1 , and a column decoder 270_1 .

[0109] The first memory cell array 311_1 may include a plurality of memory cells. The first memory cell array 311_1 may include a normal area NA and a counting cell area CCA. The normal area NA may refer to an area in the first memory cell array 311_1 that is allocated for storing user data. Alternatively, the normal area NA may refer to the remaining area in the first memory cell array 311_1 except for the area allocated to the counting cell area CCA. The counting cell area CCA may refer to an area in the first memory cell array 311_1 that is allocated for storing count data of each of the plurality of rows ROW1 to ROWj.

[0110] The row decoder 260_1 may activate one of the plurality of rows ROW1 to ROWj in response to the row address RA. For example, each of the plurality of rows ROW1 to ROWj may correspond to a word line.

[0111] The column decoder 270_1 may activate one of the plurality of columns COL1 to COLi in response to the column address CA. For example, each of the plurality of columns COL1 to COLi may correspond to a column selection line (CSL). However, this is provided only as an example. According to an embodiment, each of the plurality of columns COL1 to COLi may correspond to a bit line.

[0112] According to an embodiment, the counting cell area CCA may include a counting cell for storing counting data of a plurality of rows ROW1 to ROWj. Alternatively, according to an embodiment, the counting cell area CCA may include a counting cell for storing counting data of a plurality of rows ROW1 to ROWj, and a parity check unit for performing an error correction operation on the counting data.

[0113] Figure 3B is a diagram showing an example of a bank in which a counting cell is included in a counting cell area CCA. Figure 3C is a diagram showing an example of a bank in which a counting unit and a parity unit are included in a counting unit area CCA. Figure 3B and Figure 3C The memory bank 310_1 may correspond to Figure 2A , Figure 2B and Figure 3A The first memory bank 310_1 may be a memory bank 310_2, but the present disclosure is not limited thereto.

[0114] Reference Figure 3B and Figure 3C , the first memory bank 310_1 may include a first memory bank array 311_1 , a row decoder 260_1 , and a column decoder 270_1 .

[0115] The first memory bank array 311_1 may include a plurality of memory cells electrically connected to a plurality of word lines WL1 to WLj and a plurality of column selection lines CSL1 to CSLi. The plurality of word lines WL1 to WLj may be defined as a plurality of rows ROW1 to ROWj, and the plurality of column selection lines CSL1 to CSLi may be defined as a plurality of columns COL1 to COLi.

[0116] A portion of the first memory array 311_1 may be allocated to the normal area NA, and the rest of the first memory array 311_1 may be allocated to the counting unit area CCA.

[0117] In this case, according to the implementation mode, Figure 3B As shown, a memory cell corresponding to one of the plurality of columns COL1 to COLi may be allocated to the counting cell area CCA. Accordingly, each memory cell of the plurality of memory cells CC1 to CCj allocated to the counting cell area CCA may store the counting data of the corresponding row. The memory cells CC1 to CCj storing the counting data may be referred to as "counting cells". For example, the first counting cell CC1 may store the counting data of the first row ROW1, the second counting cell CC2 may store the counting data of the second row ROW2, and the jth counting cell CCj may store the counting data of the jth row ROWj.

[0118] Alternatively, according to the implementation mode, Figure 3CAs shown, the memory cells corresponding to at least two columns of the plurality of columns COL1 to COLi may be allocated to the counting cell area CCA. In this case, each memory cell corresponding to the i-th column COLi of the plurality of memory cells CC1 to CCj may store the counting data of the corresponding row. In addition, each memory cell corresponding to the (i-1)-th column COLi-1 of the plurality of memory cells PC1 to PCj may store the parity data of the corresponding counting data. The memory cells PC1 to PCj storing the parity data may be referred to as "parity cells". For example, the first parity cell PC1 may store the parity data of the counting data stored in the first counting cell CC1, the second parity cell PC2 may store the parity data of the counting data stored in the second counting cell CC2, and the j-th parity cell PCj may store the parity data of the counting data stored in the j-th counting cell CCj.

[0119] Count data and / or parity data of each of the plurality of rows ROW1 to ROWj may be managed in the counting unit area CCA of the first memory bank 310_1 by the above-described method.

[0120] At the same time, Figure 3B and Figure 3C , a description is given of a memory cell corresponding to one of the plurality of columns COL1 to COLi being allocated to a counting unit or a parity check unit. However, this is provided only as an example. According to an embodiment, memory cells corresponding to at least two of the plurality of columns COL1 to COLi may be allocated to a counting unit, and memory cells corresponding to at least two of the remaining columns among the plurality of columns COL1 to COLi may be allocated to a parity check unit.

[0121] Figure 4 is a block diagram illustrating a memory device according to an embodiment of the present disclosure in detail. Figure 4 The memory device 200C may be Figure 1 , Figure 2A and Figure 2B The present disclosure is not limited thereto but is an embodiment of the memory devices 200, 200A, and 200B.

[0122] Reference Figure 4, the memory device 200C may include a control logic circuit 210, an address register 220, a memory body control logic circuit 230, a refresh control circuit 400, a row address multiplexer 240, a column address latch 250, a row decoder 260, a column decoder 270, a memory body array group 311, a sense amplifier unit 285, an input / output gating circuit 290, an ECC engine 350, a data input / output buffer 320, a row hammer management circuit 500, a register group 600 and a risk notification circuit 700A.

[0123] The bank array group 311 may include a plurality of bank arrays 311_1 to 311_n. Each of the plurality of bank arrays 311_1 to 311_n may include a plurality of memory cells. For example, each of the plurality of memory cells may be formed at an intersection of a corresponding word line and a corresponding bit line.

[0124] The row decoder 260 may include a plurality of sub-row decoders 260_1 to 260_n. Each of the plurality of sub-row decoders 260_1 to 260_n may be connected to a corresponding memory bank array among the plurality of memory bank arrays 311_1 to 311_n.

[0125] The sense amplifier unit 285 may include a plurality of sense amplifiers 285_1 to 285 — n. Each of the plurality of sense amplifiers 285_1 to 285 — n may be connected to a corresponding bank array among the plurality of bank arrays 311_1 to 311 — n.

[0126] The column decoder 270 may include a plurality of sub-column decoders 270_1 to 270_n. Each of the plurality of sub-column decoders 270_1 to 270_n may be connected to a corresponding bank array among the plurality of bank arrays 311_1 to 311_n through a corresponding sense amplifier.

[0127] A plurality of bank arrays 311_1 to 311_n, a plurality of sense amplifiers 285_1 to 285_n, a plurality of sub-column decoders 270_1 to 270_n, and a plurality of sub-row decoders 260_1 to 260_n may constitute a plurality of banks. For example, a first bank array 311_1, a first sense amplifier 285_1, a first sub-column decoder 270_1, and a first sub-row decoder 260_1 may constitute a first bank.

[0128] The address register 220 may receive an address ADDR including a bank address BANK_ADDR, a row address ROW_ADDR, and a column address COL_ADDR from the memory controller 100. The address register 220 may provide the received bank address BANK_ADDR to the bank control logic circuit 230, may provide the received row address ROW_ADDR to the row address multiplexer 240, and may provide the received column address COL_ADDR to the column address latch 250. In addition, the address register 220 may provide the bank address BANK_ADDR and the row address ROW_ADDR to the row hammer management circuit 500.

[0129] The bank control logic circuit 230 may generate a bank control signal in response to the bank address BANK_ADDR. For example, a sub-row decoder corresponding to the bank address BANK_ADDR among the plurality of sub-row decoders 260_1 to 260_n may be activated in response to the bank control signal. In addition, a sub-column decoder corresponding to the bank address BANK_ADDR among the plurality of sub-column decoders 270_1 to 270_n may be activated in response to the bank control signal.

[0130] The row address multiplexer 240 may receive a row address ROW_ADDR from the address register 220 and may receive a refresh row address REF_ADDR from the refresh control circuit 400. The row address multiplexer 240 may selectively output the row address ROW_ADDR or the refresh row address REF_ADDR as the row address RA. The row address RA output from the row address multiplexer 240 may be applied to each of the plurality of sub-row decoders 260_1 to 260_n.

[0131] The refresh control circuit 400 may operate in a normal refresh mode or a row hammer refresh mode. According to an embodiment, the refresh control circuit 400 may sequentially increase or decrease the refresh row address REF_ADDR in the normal refresh mode. In addition, according to an embodiment, the refresh control circuit 400 may receive a hammer address HADDR in the row hammer refresh mode. Accordingly, the refresh control circuit 400 may output the address of the victim row adjacent to the attack row as the refresh row address REF_ADDR based on the hammer address HADDR.

[0132] A sub row decoder selected from among the plurality of sub row decoders 260_1 to 260_n by the bank control logic circuit 230 may activate a word line corresponding to a row address RA output from the row address multiplexer 240. For example, the selected sub row decoder may apply a word line driving voltage to a word line corresponding to the row address.

[0133] The column address latch 250 may receive the column address COL_ADDR from the address register 220 and may temporarily store the received column address COL_ADDR. In addition, for example, in a burst mode, the column address latch 250 may sequentially increase the received column address COL_ADDR. The column address latch 250 may apply the temporarily stored column address COL_ADDR' or the sequentially increased column address COL_ADDR' to each of the plurality of sub-column decoders 270_1 to 270_n.

[0134] A sub-column decoder activated by the bank control logic circuit 230 among the plurality of sub-column decoders 270_1 to 270 — n may activate a sense amplifier corresponding to a bank address BANK_ADDR and a column address COL_ADDR through an input / output gating circuit 290 .

[0135] The input / output gating circuit 290 may include a circuit for gating input / output data. In addition, the input / output gating circuit 290 may include a data latch for storing codewords output from the plurality of memory bank arrays 311_1 to 311_n, and a write driver for writing data into the plurality of memory bank arrays 311_1 to 311_n.

[0136] In a read operation, a codeword CW read from a memory bank array selected from the plurality of memory bank arrays 311_1 to 311_n may be sensed by a sense amplifier corresponding to the selected memory bank array and may be stored in a data latch of the input / output gating circuit 290. In addition, the ECC engine 350 may perform ECC decoding on the codeword CW stored in the data latch to provide it as data DTA to the data input / output buffer 320. The data input / output buffer 320 may generate a data signal DQ based on the data DTA and may provide the data signal DQ to the memory controller 100 together with the selection signal DQS.

[0137] In a write operation, data DTA to be written into a memory bank array selected from among the plurality of memory bank arrays 311_1 to 311_n may be received by the data input / output buffer 320 as a data signal DQ. The data input / output buffer 320 may convert the data signal DQ into data DTA so as to provide it to the ECC engine 350. The ECC engine 350 may generate parity bits (or parity data) based on the data DTA, and may provide a codeword CW including the data DTA and the parity bits to the input / output gating circuit 290. The input / output gating circuit 290 may write the codeword CW into the selected memory bank array.

[0138] In a write operation, the data input / output buffer 320 may convert the data signal DQ into data DTA to be provided to the ECC engine 350. In a read operation, the data input / output buffer 320 may convert the data DTA provided from the ECC engine 350 into the data signal DQ.

[0139] In a write operation, the ECC engine 350 may perform ECC encoding on the data DTA. In a read operation, the ECC engine 350 may perform ECC decoding on the codeword CW. In addition, the ECC engine 350 may perform ECC encoding and ECC decoding on the count data CNTD provided from the row hammer management circuit 500.

[0140] The control logic circuit 210 may control the operation of the memory device 200C. For example, the control logic circuit 210 may generate a control signal so that the memory device 200C performs a write operation, a read operation, a normal refresh operation, and a row hammer refresh operation. The control logic circuit 210 may include a command decoder 211 that decodes a command CMD received from the memory controller 100, and a mode register (MRS) 212 for setting an operation mode of the memory device 200C.

[0141] The command decoder 211 may decode the command CMD to generate internal command signals such as an internal activation signal IACT, an internal precharge signal IPRE, an internal read signal IRD, and an internal write signal IWR. In addition, the command decoder 211 may generate a control signal corresponding to the command CMD by decoding a chip select signal, a command / address signal, etc. Meanwhile, according to an embodiment, the mode register group 212 may include a mode register 712, in which flag data associated with a row hammer risk is stored, and a mode register (e.g., MR4), in which information related to a temperature range of the memory device 200C is stored.

[0142] The row hammer management circuit 500 may perform various types of operations to manage the row hammer phenomenon occurring in the memory device 200C.

[0143] For example, the row hammer management circuit 500 may manage count data for each of the plurality of rows.

[0144] According to an embodiment, the row hammer management circuit 500 may receive the count data CNTD from the ECC engine 350. The row hammer management circuit 500 may modify the count data CNTD, and may provide the modified count data UCNTD to the ECC engine 350 again.

[0145] In an embodiment, when an ACT command for a target row is applied, count data CNTD stored in a count unit of the target row and parity data stored in a parity unit of the target row may be provided to the ECC engine 350. The ECC engine 350 may perform an ECC decoding operation on the count data CNTD by using the parity data, and may transmit the count data CNTD to the row hammer management circuit 500. The row hammer management circuit 500 may generate modified count data UCNTD by increasing the count data CNTD by "1" or increasing the count data CNTD by "k" (k is a natural number of 2 or more) in consideration of the activation time of the target row. The row hammer management circuit 500 may provide the modified count data UCNTD to the ECC engine 350, and the ECC engine 350 may generate parity data by performing an ECC encoding operation on the modified count data UCNTD. The modified count data UCNTD and parity data associated with the modified count data UCNTD may be stored in the count unit and the parity unit of the target row.

[0146] According to an embodiment, the row hammer management circuit 500 may send the target row address TR_ADDR and the modified count data UCNTD to the register group 600. The row hammer management circuit 500 may selectively update the register group 600 by using the target row address TR_ADDR and the modified count data UCNTD.

[0147] In an embodiment, the row hammer management circuit 500 may select a register corresponding to the storage body to which the target row belongs from among the registers of the register group 600. The row hammer management circuit 500 may compare the address and / or count data managed in the selected register with the address TR_ADDR and / or the modified count data UCNTD of the target row, and may update the register based on the comparison result. For example, when at least one count data in the entry of the register is less than the modified count data UCNTD of the target row, the row hammer management circuit 500 may replace the entry of the register corresponding to the minimum count data with the address TR_ADDR and the modified count data UCNTD of the target row. Since the memory device 200C manages the address and count data associated with a row having relatively large count data among a plurality of rows through the register group 600, the memory device 200C may manage the risk of the occurrence of the row hammer phenomenon for each row to be equal to or lower than an appropriate level, and may effectively prevent the row hammer phenomenon.

[0148] Meanwhile, the row hammer management circuit 500 may inform the memory controller 100 of the row hammer risk based on the count data.

[0149] According to an embodiment, the hammer management circuit 500 may monitor whether at least one of the count data stored in the plurality of count units reaches a reference count. When the count data stored in at least one of the plurality of count units reaches the reference count, the hammer management circuit 500 may apply a risk signal indicating a risk situation to the alarm pin 711, or may store flag data indicating a risk situation in the mode register 712.

[0150] Alternatively, according to an embodiment, the row hammer management circuit 500 may monitor whether at least one of the count data stored in the plurality of count units reaches a reference count by using the count data managed in the register of the register group 600. In this case, when at least one of the count data managed in the register of the register group 600 reaches the reference count, the row hammer management circuit 500 may apply a risk signal indicating a risk situation to the alarm pin 711, or may store flag data indicating a risk situation in the mode register 712.

[0151] At the same time, Figure 4 , a description is given of the memory device 200C including the ECC engine 350. However, this is provided only as an example. According to an embodiment, the memory device 200C may not include the ECC engine. In this case, the row hammer management circuit 500 may read the count data of the count unit of the target row through the input / output gating circuit 290, may increase the read count data to generate the modified count data, and may write the modified count data into the count unit of the target row through the input / output gating circuit 290 again.

[0152] Figure 5A is a block diagram of a memory controller according to an embodiment of the present disclosure. Figure 5A The memory controller 100 may be Figure 1 The memory controller 100 of the embodiment of the present invention is not limited thereto. Figure 5A , the memory controller 100 may include a processor 110 , an RFM control logic 120 , a refresh logic 130 , a scheduler 140 , and a memory interface 150 interconnected by a bus.

[0153] The processor 110 may control all operations of the memory controller 100. For example, the processor 110 may individually control the RFM control logic 120, the refresh logic 130, the scheduler 140, and the memory interface 150. The processor 110 may be implemented with a general-purpose processor including one or more processor cores, a dedicated processor, and / or an application processor, but the present disclosure is not limited thereto.

[0154] The refresh logic 130 may generate a refresh (REF) command for a normal refresh operation, and may send the generated REF command to the memory device 200. For example, the memory controller 100 may obtain information related to the refresh interval time tREFI from the memory device 200. Accordingly, the refresh logic 130 may generate a REF command in each cycle corresponding to the refresh interval time tREFI, and may send the REF command to the memory device 200. However, the present disclosure is not limited thereto. According to an embodiment, the memory device 200 may perform a normal refresh operation based on the received REF command. In addition, according to an embodiment, the memory device 200 may perform a normal refresh operation and a row hammer refresh operation based on the received REF command.

[0155] The scheduler 140 may schedule a command sequence generated in the memory controller 100 and may manage transmission of commands. The memory interface 150 may perform interfacing with the memory device 200 .

[0156] The RFM control logic 120 may generate a refresh management (RFM) command for a row hammer refresh operation and may transmit the generated RFM command to the memory device 200 .

[0157] Specifically, the RFM control logic 120 may perform various operations of the memory controller 100 associated with the sending of the above-mentioned RFM command. For example, the RFM control logic 120 may count the number of bank activations of the banks included in the memory device 200, and may send an RFM command to the memory device 200 based on whether the counted number of bank activations reaches the BAT.

[0158] In an embodiment, the RFM control logic 120 may variably control the frequency of transmission of the RFM command according to information associated with the situation of the memory device 200. For example, based on the row hammer risk of the memory device 200 obtained by the notification circuit 700 or temperature information including the temperature range of the memory device 200, the RFM control logic 120 may selectively control whether to transmit the RFM command, or may adjust the BAT. In addition, the RFM control logic 120 may further transmit the RFM command in consideration of the activation time of the memory bank included in the memory device 200.

[0159] According to the above-described embodiment, the transmission frequency of the RFM command can be variably controlled in consideration of various conditions of the memory device 200, such as row hammer risk, refresh interval time according to temperature range, and PGE phenomenon of the memory cell. Accordingly, the bandwidth efficiency of the memory system or the performance of the memory system can be improved.

[0160] Figure 5Bis a flowchart illustrating an operating method of a memory controller according to an embodiment of the present disclosure.

[0161] Reference Figure 5B In operation S510, the memory controller 100 may send an RFM command to the memory device 200 based on the number of bank activations of the memory banks included in the memory device 200 reaching BAT. For example, the memory controller 100 may count the number of bank activations whenever an ACT command is sent to the memory device 200, and may send an RFM command to the memory device 200 when the counted number of bank activations reaches BAT.

[0162] In operation S520, the memory controller 100 may obtain a notification through the notification circuit 700 of the memory device 200. In an embodiment, the notification may include at least one of information related to row hammer risk of rows included in a bank of the memory device 200 or temperature information including a temperature range of the memory device 200.

[0163] Specifically, the notification circuit 700 may include a risk notification circuit 700A and / or a temperature notification circuit 700B (see Fig.15 ).

[0164] The risk notification circuit 700A may include at least one of an alarm pin 711 or a mode register 712. A signal associated with the row hammer risk may be applied to the alarm pin 711, and the mode register 712 may store flag data associated with the row hammer risk. Accordingly, the memory controller 100 may receive the signal applied to the alarm pin 711, and may obtain the row hammer risk of the memory device 200. In addition, the memory controller 100 may obtain the row hammer risk of the memory device 200 by reading the flag data stored in the mode register 712 through a mode register read operation.

[0165] The temperature notification circuit 700B may notify the memory controller 100 of information related to the temperature of the memory device 200. For example, the temperature notification circuit 700B may be implemented with a mode register storing temperature information including a temperature range of the memory device 200, but the present disclosure is not limited thereto. When the temperature notification circuit 700B is implemented with a mode register, the memory controller 100 may obtain the temperature information of the memory device 200 through a mode register read operation on the corresponding register.

[0166] In operation S530, the memory controller 100 may variably control the transmission frequency of the RFM command based on the obtained notification. Specifically, based on the notification, the memory controller 100 may selectively transmit the RFM command, or may adjust the BAT.

[0167] According to an embodiment, the memory controller 100 may selectively send an RFM command based on the row hammer risk obtained through the risk notification circuit 700A. As described above, when the count data stored in at least one of the plurality of count units of the memory device 200 reaches the reference count, a risk signal may be applied to the alarm pin 711, and the flag data may be stored in the mode register 712. Accordingly, before receiving the risk signal through the alarm pin 711 or reading the flag data from the mode register 712, the memory controller 100 may determine that the row hammer risk of the memory device 200 is low. In this case, the memory controller 100 may not send the RFM command even if the number of bank activations reaches BAT. On the contrary, when a risk signal is received through the alarm pin 711 or the flag data indicating the risk situation is read from the mode register 712, it may be determined that the row hammer risk of the memory device 200 reaches the risk level. In this case, the memory controller 100 may send the RFM command to the memory device 200 whenever the number of bank activations reaches BAT.

[0168] According to an embodiment, the memory controller 100 may adjust the BAT based on the row hammer risk obtained through the risk notification circuit 700A. For example, in the case where the row hammer risk is low, the memory controller 100 may send an RFM command to the memory device 200 each time the number of memory bank activations reaches BAT1. On the contrary, in the case where the row hammer risk reaches a risk level (e.g., a high risk), the memory controller 100 may send an RFM command to the memory device 200 each time the number of memory bank activations reaches BAT2. As described above, since the value of BAT2 is lower than the value of BAT1, the frequency of sending the RFM command corresponding to the case where the operation is performed based on BAT1 may be relatively low compared to the frequency of sending the RFM command corresponding to the case where the operation is performed based on BAT2.

[0169] According to an embodiment, the memory controller 100 may adjust the BAT based on the temperature information of the memory device 200 obtained through the temperature notification circuit 700B. For example, in the case where the temperature range of the memory device 200 is a relatively low first temperature range, the memory controller 100 may send an RFM command to the memory device 200 whenever the number of bank activations reaches BAT3. On the contrary, in the case where the temperature range of the memory device 200 is a relatively high second temperature range, the memory controller 100 may send an RFM command to the memory device 200 whenever the number of bank activations reaches BAT4. As described above, since the value of BAT3 is lower than the value of BAT4, the frequency of transmission of the RFM command corresponding to the case where the operation is performed based on BAT4 may be relatively low compared to the frequency of transmission of the RFM command corresponding to the case where the operation is performed based on BAT3.

[0170] Meanwhile, the memory controller 100 may transmit the RFM command in further consideration of an activation time of a memory bank included in the memory device 200 .

[0171] According to an embodiment, when any one of a threshold condition associated with the number of bank activations (i.e., BAT) and a threshold condition associated with the bank activation time (i.e., BATT) is satisfied, the memory controller 100 may send an RFM command to the memory device 200. In this case, even if the number of bank activations does not reach the BAT, the RFM command may be sent when the bank activation time reaches the BATT.

[0172] According to an embodiment, the memory controller 100 may count the number of memory bank activations in consideration of the memory bank activation time. In an embodiment, when the memory bank activation time is equal to or less than the reference time, the memory controller 100 may increase the number of memory bank activations by "1". In addition, when the memory bank activation time exceeds the reference time, the memory controller 100 may increase the number of memory bank activations by "2".

[0173] According to the above-described embodiment, the transmission frequency of the RFM command can be variably controlled in consideration of various conditions of the memory device 200, such as row hammer risk, refresh interval time according to temperature range, and PGE phenomenon of the memory cell. Accordingly, the bandwidth efficiency of the memory system or the performance of the memory system can be improved.

[0174] Figure 6 is a block diagram showing the configuration of the RFM control logic according to an embodiment of the present disclosure. Figure 6 The RFM control logic 120 may include a counter 121 , an RFM command generator 123 , and a hammer risk obtainer 125 .

[0175] The counter 121 may count the number of storage body activations. According to an embodiment, the counter 121 may count the number of storage body activations based on an ACT command sent to the storage device 200. For example, each time an ACT command is sent to the storage device 200, the counter 121 may increase the number of storage body activations by "1". Below, for convenience, a description will be given of counting the number of storage body activations based on the ACT command, but the embodiment is not limited thereto. For example, the counter 121 may count the number of storage body activations to "1" based on a PRE command sent to the storage device 200.

[0176] Meanwhile, according to an embodiment, a counter 121 may be provided to each bank of the memory device 200. The counter 121 corresponding to each bank may count the number of bank activations of the corresponding bank.

[0177] The hammer risk obtainer 125 may obtain the hammer risk of the memory device 200 through the risk notification circuit 700A. For example, the hammer risk obtainer 125 may receive a signal applied to the alarm pin 711 and may obtain the hammer risk of the memory device 200. In addition, the hammer risk obtainer 125 may obtain the hammer risk of the memory device 200 by reading flag data stored in the mode register 712 through a mode register read operation.

[0178] The RFM command generator 123 may generate an RFM command based on the number of bank activations counted by the counter 121 and the row hammer risk of the memory device 200 obtained by the row hammer risk obtainer 125 , and may transmit the generated RFM command to the memory device 200 .

[0179] According to an embodiment, the RFM command generator 123 may operate in a first mode or a second mode based on the row hammer risk. In the first mode, the RFM command generator 123 may not send an RFM command even if the number of bank activations reaches BAT; in the second mode, the RFM command generator 123 may send an RFM command when the number of bank activations reaches BAT. In other words, when the number of bank activations reaches BAT, the RFM command may be selectively sent based on the row hammer risk.

[0180] In addition, according to an embodiment, the RFM command generator 123 may operate in a third mode or a fourth mode based on the row hammer risk. In the third mode, when the number of bank activations reaches BAT1, the RFM command generator 123 may send an RFM command; in the fourth mode, when the number of bank activations reaches BAT2, the RFM command generator 123 may send an RFM command. Accordingly, the BAT value may be appropriately adjusted based on the row hammer risk.

[0181] The following will refer to Figures 7 to 10 Various embodiments are described for selectively sending RFM commands based on risk of a hammer.

[0182] Figure 7 is a flowchart showing an operating method of a memory controller according to an embodiment of the present disclosure. Figure 7 In operation S710, the memory controller 100 may determine whether the memory device 200 is in a risk situation associated with row hammer. For example, the memory controller 100 may determine whether the memory device 200 is in a risk situation based on the row hammer risk of the memory device 200 obtained through the risk notification circuit 700A.

[0183] Specifically, the row hammer risk may indicate whether the count data stored in at least one of the plurality of count units corresponding to the plurality of rows included in the memory bank of the memory device 200 respectively reaches the reference count. When the count data reaches the reference count, the memory device 200 may apply a risk signal indicating the risk situation to the alarm pin 711, or may store flag data indicating the risk situation in the mode register 712. In this case, according to an embodiment, the case where the count data reaches the reference count may include a case where the count data exceeds the reference count in addition to the case where the count data is consistent with the reference count.

[0184] Accordingly, when a risk signal is received through the alarm pin 711 or flag data indicating a risk situation is read from the mode register 712, the memory controller 100 can determine that the memory device 200 is in a risk situation associated with a row hammer. In addition, when no risk signal is received through the alarm pin 711 and the flag data read from the mode register 712 does not indicate a risk situation, the memory controller 100 can determine that the memory device 200 is not in a risk situation associated with a row hammer.

[0185] When the memory device 200 is not in a risk situation associated with a row hammer ("No" in operation S710), the memory controller 100 may perform operation S720. In operation S720, the memory controller 100 may operate in a first mode. In the first mode, even if the number of bank activations reaches BAT, the memory controller 100 does not send an RFM command to the memory device 200.

[0186] Meanwhile, when the memory device 200 is in a risk situation associated with a row hammer ("Yes" in operation S710), the memory controller 100 may perform operation S730. In operation S730, the memory controller 100 may operate in the second mode. In the second mode, when the number of bank activations reaches BAT, the memory controller 100 may send an RFM command to the memory device 200.

[0187] Figure 8 is a flowchart illustrating an operating method of a memory controller according to an embodiment of the present disclosure.

[0188] Reference Figure 8 In operation S810, the memory controller 100 may count the number of bank activation times. For example, each time an ACT command for a specific bank of the memory device 200 is sent, the memory controller 100 may increase the number of bank activation times by "1".

[0189] In operation S820, the memory controller 100 may determine whether the counted number of storage body activations (expressed as CNT) reaches BAT. In this case, as described above, the case where the counted number of storage body activations (expressed as CNT) reaches BAT may include a case where the value of the counted number of storage body activations (expressed as CNT) is greater than BAT in addition to the case where the counted number of storage body activations (expressed as CNT) is consistent with BAT.

[0190] Accordingly, according to an embodiment, the memory controller 100 may determine whether the counted bank activation number CNT (denoted as CNT) reaches BAT by determining whether the counted bank activation number (denoted as CNT) is equal to or greater than BAT.

[0191] When the counted number of memory cell activations (expressed as CNT) is less than BAT, that is, when the counted number of memory cell activations (expressed as CNT) does not reach BAT ("No" in operation S820), the memory controller 100 may perform operation S810 again. When the counted number of memory cell activations (expressed as CNT) is equal to or greater than BAT, that is, when the counted number of memory cell activations (expressed as CNT) reaches BAT ("Yes" in operation S820), the memory controller 100 may perform operation S830.

[0192] In operation S830, the memory controller 100 may determine whether the memory device 200 is in a risk situation associated with a row hammer. For example, the memory controller 100 may determine whether the memory device 200 is in a risk situation based on the row hammer risk obtained by the risk notification circuit 700A. According to an embodiment, the memory controller 100 may determine whether the memory device 200 is in a risk situation by performing a mode register read operation on the mode register 712.

[0193] For example, when the flag data read from the mode register 712 is a risk flag, the memory controller 100 may determine that the memory device 200 is in a risk situation. In addition, when the flag data read from the mode register 712 is not a risk flag, the memory controller 100 may determine that the memory device 200 is not in a risk situation.

[0194] When the memory device 200 is not in a risk situation ("No" in operation S830), the memory controller 100 may perform operation S840. In operation S840, the memory controller 100 may reset the bank activation count (expressed as CNT). Accordingly, the memory controller 100 may perform operation S810 again.

[0195] Meanwhile, when the memory device 200 is in a risk situation ("Yes" in operation S830), the memory controller 100 may perform operation S850. In operation S850, the memory controller 100 may send an RFM command to the memory device 200. In this case, the memory controller 100 may reset the number of bank activation times (expressed as CNT). Accordingly, the memory controller 100 may perform operation S810 again.

[0196] That is, refer again to Figure 8 , when operating in the first mode, the memory controller 100 may operate in the order of operation S810, operation S820, operation S830, and operation S840. In addition, when operating in the second mode, the memory controller 100 may operate in the order of operation S810, operation S820, operation S830, and operation S850. In this case, whenever the number of storage body activation times (expressed as CNT) reaches BAT ("Yes" in operation S820), the memory controller 100 may perform a mode register read operation, and may operate in the first mode or the second mode depending on whether the flag data read from the mode register 712 is a risk flag.

[0197] Meanwhile, according to an embodiment, when operating in the first mode, whenever the number of bank activations (expressed as CNT) reaches BAT ("Yes" in operation S820), the memory controller 100 may perform a mode register read operation. However, when obtaining flag data from the mode register 712 ("Yes" in operation S830) when operating in the first mode, the memory controller 100 may perform a mode register read operation. Figure 8 Unlike the example shown, the memory controller 100 may operate in the second mode without performing a mode register read operation until the RFM command is sent a given number of times. In this case, the memory controller 100 may perform a mode register read operation after the RFM command is sent a given number of times.

[0198] The reason is that, as the memory device 200 escapes from the risk situation, a case where the memory controller 100 operating in the second mode changes the mode to the first mode is not a case where the memory controller 100 should change the mode urgently.

[0199] Accordingly, the memory controller 100 can quickly detect a situation where a risk situation associated with a row hammer occurs while operating in the first mode, and can immediately operate in the second mode. In addition, when the memory controller 100 enters the second mode, the memory controller 100 may not perform a mode register read operation until the RFM command is sent a given number of times. Accordingly, resource consumption required for the mode register read operation can be reduced.

[0200] The following will refer to Fig. 9 An embodiment is described in which the memory controller 100 operates in the second mode until a mode register read operation is performed on the mode register 712 after the RFM command is issued a given number of times.

[0201] Fig. 9 is a flowchart illustrating an operating method of a memory controller according to an embodiment of the present disclosure.

[0202] Reference Fig. 9 , in operation S910, the memory controller 100 may count the number of bank activation times.

[0203] In operation S920 , the memory controller 100 may determine whether the counted number of bank activations (denoted as CNT) reaches BAT.

[0204] When the counted number of memory cell activations (expressed as CNT) is less than BAT, that is, when the counted number of memory cell activations (expressed as CNT) does not reach BAT ("No" in operation S920), the memory controller 100 may perform operation S910 again. When the counted number of memory cell activations (expressed as CNT) is equal to or greater than BAT, that is, when the counted number of memory cell activations (expressed as CNT) reaches BAT ("Yes" in operation S920), the memory controller 100 may perform operation S930.

[0205] In operation S930, the memory controller 100 may transmit an RFM command to the memory device 200. In this case, the memory controller 100 may reset a bank activation count (expressed as CNT).

[0206] In operation S940, the memory controller 100 may determine whether the RFM command is transmitted a given number of times “N.” According to an embodiment, the given number of times “N” may be set to one of positive integers.

[0207] When the RFM command is not sent a given number of "N" times ("No" in operation S940), the memory controller 100 may perform operation S910 again. When the RFM command is sent a given number of "N" times ("Yes" in operation S940), the memory controller 100 may perform operation S950.

[0208] Referring to the above-described operations S910 to S940 , the memory controller 100 may operate in the second mode without performing a mode register read operation on the mode register 712 until the RFM command is transmitted a given number of times “N”.

[0209] In operation S950, the memory controller 100 may determine whether the memory device 200 is in a risk situation associated with a row hammer. For example, the memory controller 100 may determine whether the memory device 200 is in a risk situation based on the row hammer risk obtained by the risk notification circuit 700A. According to an embodiment, the memory controller 100 may determine whether the memory device 200 is in a risk situation by performing a mode register read operation on the mode register 712.

[0210] When the memory device 200 is not in a risk situation (“No” in operation S950 ), the memory controller 100 may perform Figure 8 Operation S810.

[0211] When the memory device 200 is in a risk situation ("Yes" in operation S950), the memory controller 100 may perform operation S910. In this case, the memory controller 100 may operate in the second mode without performing a mode register read operation until the RFM command is sent a given number "N".

[0212] Meanwhile, the above description is made by taking as an example the case where the memory controller 100 performs the mode register read operation on the mode register 712 in both operation S930 and operation S950 to determine whether the memory device 200 is in a risk situation. In this case, for example, when flag data indicating a risk situation is read from the mode register 712 ("Yes" in operation S830), the memory controller 100 operating in the first mode may operate in the second mode. According to an embodiment, in this case, as shown in reference to Fig. 9 As described above, the memory controller 100 may operate in the second mode until the RFM command is sent a given number of times "N", and then a mode register read operation may be performed on the mode register 712. Accordingly, when the flag data is read and no risk situation is indicated ("No" in operation S950), the memory controller 100 may operate in the first mode again.

[0213] However, the embodiments are not limited thereto. For example, in operation S830, the memory controller 100 may determine whether a risk situation of the memory device 200 has occurred based on a signal received through the alarm pin 711; in operation S950, the memory controller 100 may determine whether a risk situation of the memory device 200 has occurred based on a mode register read operation of the mode register 712. In this case, for example, when a risk signal is applied to the alarm pin 711 ("Yes" in operation S830), the memory controller 100 operating in the first mode may operate in the second mode. According to the embodiments, in this case, as shown in reference Fig. 9As described above, the memory controller 100 may operate in the second mode until the RFM command is sent a given number of times "N", and then a mode register read operation may be performed on the mode register 712. When the flag data obtained through the mode register read operation does not indicate a risk situation ("No" in operation S950), the memory controller 100 may operate in the first mode again.

[0214] Fig.10 is a diagram for describing an operation of selectively transmitting an RFM command according to an embodiment of the present disclosure. Fig.10 The figure above shows an example of sending an RFM command without considering the risk of hammering, and Fig.10 The following diagram shows an example of selectively sending RFM commands based on row hammer risk.

[0215] exist Fig.10 In the following figure, the row hammer flag data RH RISK FLAG may refer to a signal indicating the row hammer risk of the memory device 200. For example, the row hammer flag data RH RISK FLAG may refer to a flag data signal of the row hammer risk read from the mode register 712 (or a signal of the row hammer risk applied to the alarm pin 711). Reference numeral 21 may refer to a flag data signal indicating a risk situation read from the mode register 712 (or a risk signal applied to the alarm pin 711).

[0216] Reference Fig.10 As shown in the above figure, whenever the number of bank activations (expressed as CNT) reaches BAT, the memory controller 100 may send an RFM command.

[0217] Reference Fig.10 As shown in the lower figure, even if the bank activation count (expressed as CNT) reaches BAT, the memory controller 100 may selectively send the RFM command based on the row hammer flag data RH RISK FLAG.

[0218] According to an embodiment, when the memory device 200 is not in a risk situation associated with a row hammer risk, the memory controller 100 may operate in the first mode. For example, even if the number of bank activations (expressed as CNT) reaches BAT, the memory controller 100 may not send an RFM command until the flag data signal (or risk signal) 21 is obtained.

[0219] Meanwhile, when the flag data signal (or risk signal) 21 is obtained, the memory controller 100 operating in the first mode may operate in the second mode. Fig.10In the lower figure, the portion of the drawing after applying the flag data signal (or risk signal) 21 shows the operation in the second mode, in which the RFM command is sent every time the number of storage body activations (expressed as CNT) reaches BAT.

[0220] In this case, according to an embodiment, the memory controller 100 may operate in the second mode until the RFM command is sent a given number of times. In an embodiment, the memory controller 100 may not perform a mode register read operation on the mode register 712 until the RFM command is sent a given number of times.

[0221] When the RFM command is sent a given number of times while operating in the second mode, the memory controller 100 may perform a mode register read operation on the mode register 712. When the flag data read from the mode register 712 is not flag data indicating a risk situation, the memory controller 100 may operate in the first mode. When the read flag is flag data indicating a risk situation, the memory controller 100 may operate in the second mode again until the RFM command is sent a given number of times.

[0222] Alternatively, according to an embodiment, when the RFM command is sent a given number of times while operating in the second mode, the memory controller 100 may check the signal applied to the alert pin 711, and may determine whether to operate in the first mode based on the checked signal. For example, when it is checked that the signal applied to the alert pin 711 is not a risk signal at a time point when the RFM command is completely sent a given number of times, the memory controller 100 may operate in the first mode. When it is checked that the signal applied to the alert pin 711 is a risk signal at a time point when the RFM command is completely sent a given number of times, the memory controller 100 may operate in the second mode until the RFM command is sent a given number of times.

[0223] The following will refer to Figures 11 to 14 Various implementations of changing the BAT value based on the risk of a hammer are described. Figures 11 to 14 , the description given above will be omitted or simplified.

[0224] Fig.11 is a flowchart showing an operating method of a memory controller according to an embodiment of the present disclosure. Fig.11 , in operation S1110 , the memory controller 100 may determine whether the memory device 200 is in a risk situation associated with row hammer.

[0225] When the memory device 200 is not in a risk situation associated with a row hammer ("No" in operation S1110), the memory controller 100 may perform operation S1120. In operation S1120, the memory controller 100 may operate in the third mode. In the third mode, when the number of bank activations reaches BAT1, the memory controller 100 may send an RFM command to the memory device 200.

[0226] Meanwhile, when the memory device 200 is in a risk situation associated with a row hammer ("Yes" in operation S1110), the memory controller 100 may perform operation S1130. In operation S1130, the memory controller 100 may operate in the fourth mode. In the fourth mode, when the number of bank activations reaches BAT2, the memory controller 100 may send an RFM command to the memory device 200. According to an embodiment, the value of BAT2 may be less than the value of BAT1. That is, the sending frequency of the RFM command in the fourth mode may be higher than the sending frequency of the RFM command in the third mode.

[0227] Fig.12 is a flowchart illustrating an operating method of a memory controller according to an embodiment of the present disclosure.

[0228] Reference Fig.12 , in operation S1210, the memory controller 100 may count the number of bank activation times.

[0229] In operation S1220, the memory controller 100 may determine whether the counted number of storage body activations (expressed as CNT) reaches BAT1. In an embodiment, the case where the counted number of storage body activations (expressed as CNT) reaches BAT1 includes, in addition to the case where the counted number of storage body activations (expressed as CNT) is consistent with BAT1, the case where the value of the counted number of storage body activations (expressed as CNT) is greater than BAT1.

[0230] According to an embodiment, therefore, the memory controller 100 may determine whether the counted number of bank activations (expressed as CNT) reaches BAT1 by determining whether the counted number of bank activations (expressed as CNT) is equal to or greater than BAT1.

[0231] When the counted number of memory cell activations (expressed as CNT) is less than BAT1, that is, when the counted number of memory cell activations (expressed as CNT) does not reach BAT1 ("No" in operation S1220), the memory controller 100 may perform operation S1210 again. When the counted number of memory cell activations (expressed as CNT) is equal to or greater than BAT1, that is, when the counted number of memory cell activations CNT reaches BAT1 ("Yes" in operation S1220), the memory controller 100 may perform operation S1230.

[0232] In operation S1230, the memory controller 100 may transmit an RFM command to the memory device 200. In this case, the memory controller 100 may reset a bank activation count (expressed as CNT).

[0233] In operation S1240, the memory controller 100 may determine whether the memory device 200 is in a risk situation associated with a row hammer. For example, when the flag read from the mode register 712 indicates a risk situation, the memory controller 100 may determine that the memory device 200 is in a risk situation. In addition, when the flag read from the mode register 712 does not indicate a risk situation, the memory controller 100 may determine that the memory device 200 is not in a risk situation.

[0234] When the memory device 200 is not in the risk situation (“No” in operation S1240 ), the memory controller 100 may perform operation S1210 again.

[0235] Meanwhile, when the memory device 200 is in a risk situation ("Yes" in operation S1240), the memory controller 100 may perform operation S1250. In operation S1250, the memory controller 100 may count the number of bank activation times.

[0236] In operation S1260, the memory controller 100 may determine whether the counted number of memory cell activations (expressed as CNT) reaches BAT2. In an embodiment, the value of BAT2 may be less than the value of BAT1. Meanwhile, as described above, the case where the counted number of memory cell activations (expressed as CNT) reaches BAT2 includes, in addition to the case where the counted number of memory cell activations (expressed as CNT) is consistent with BAT2, the case where the value of the counted number of memory cell activations (expressed as CNT) is greater than BAT2.

[0237] According to an embodiment, therefore, the memory controller 100 may determine whether the counted number of bank activations (expressed as CNT) reaches BAT2 by determining whether the counted number of bank activations (expressed as CNT) is equal to or greater than BAT2.

[0238] When the counted number of memory cell activations (expressed as CNT) is less than BAT2, that is, when the counted number of memory cell activations (expressed as CNT) does not reach BAT2 ("No" in operation S1260), the memory controller 100 may perform operation S1250 again. When the counted number of memory cell activations (expressed as CNT) is equal to or greater than BAT2, that is, when the counted number of memory cell activations (expressed as CNT) reaches BAT2 ("Yes" in operation S1260), the memory controller 100 may perform operation S1270.

[0239] In operation S1230, the memory controller 100 may send an RFM command to the memory device 200. In this case, the memory controller 100 may reset the bank activation count (expressed as CNT). Accordingly, the memory controller 100 may perform operation S1240 again.

[0240] That is, refer again to Fig.12 , when operating in the third mode, the memory controller 100 may operate in the order of operation S1210, operation S1220, operation S1230, and operation S1240. In addition, when operating in the fourth mode, the memory controller 100 may operate in the order of operation S1250, operation S1260, operation S1270, and operation S1240. In this case, whenever an RFM command is sent in response to the number of memory bank activations (expressed as CNT) reaching BAT1 or BAT2 (S1230 or S1270), the memory controller 100 may perform a mode register read operation and may operate in the third mode or the fourth mode depending on whether the flag read from the mode register 712 is a risk flag.

[0241] Meanwhile, according to an embodiment, when operating in the third mode, whenever the number of bank activations (expressed as CNT) reaches BAT1 ("Yes" in operation S1220), the memory controller 100 may perform a mode register read operation. However, when flag data indicating a risk situation is obtained from the mode register 712 when operating in the third mode ("Yes" in operation S1240), the memory controller 100 may perform a mode register read operation. Fig.12 Unlike the example shown, the memory controller 100 may operate in the fourth mode without performing a mode register read operation until the RFM command is sent a given number of times. In this case, the memory controller 100 may perform a mode register read operation after the RFM command is sent a given number of times.

[0242] The reason is that, as the memory device 200 escapes from the risk situation, the case where the memory controller 100 operating in the fourth mode changes the mode to the third mode is not a case where the memory controller 100 should change the mode urgently.

[0243] Accordingly, the memory controller 100 can quickly detect a situation where a risk situation associated with a row hammer occurs while operating in the third mode, and can immediately operate in the fourth mode. In addition, when the memory controller 100 enters the fourth mode, the memory controller 100 may not perform a mode register read operation until the RFM command is sent a given number of times. Accordingly, resource consumption required for the mode register read operation can be reduced.

[0244] The following will refer to Fig.13 An embodiment is described in which the memory controller 100 operates in the fourth mode until the RFM command is sent a given number of times and performs a mode register read operation on the mode register 712. According to the embodiment, Fig.13 The operation in the fourth mode shown may correspond to Fig.12 The operations in the fourth mode are shown, and operation S1310, operation S1320, operation S1330, and operation S1350 may correspond to operation S1250, operation S1260, operation S1270, and operation S1240, respectively.

[0245] Fig.13 is a flowchart illustrating an operating method of a memory controller according to an embodiment of the present disclosure.

[0246] Reference Fig.13 , in operation S1310, the memory controller 100 may count the number of bank activation times.

[0247] In operation S1320 , the memory controller 100 may determine whether the counted number of bank activations (denoted as CNT) reaches BAT2 .

[0248] When the counted number of memory cell activations (expressed as CNT) is less than BAT2, that is, when the counted number of memory cell activations (expressed as CNT) does not reach BAT2 ("No" in operation S1320), the memory controller 100 may perform operation S1310 again. When the counted number of memory cell activations (expressed as CNT) is equal to or greater than BAT2, that is, when the counted number of memory cell activations (expressed as CNT) reaches BAT2 ("Yes" in operation S1320), the memory controller 100 may perform operation S1330.

[0249] In operation S1330, the memory controller 100 may transmit an RFM command to the memory device 200. In this case, the memory controller 100 may reset a bank activation count (expressed as CNT).

[0250] In operation S1340, the memory controller 100 may determine whether the RFM command is transmitted a given number of times “N.” According to an embodiment, the given number of times “N” may be set to one of positive integers.

[0251] When the RFM command is not sent a given number of "N" times ("No" in operation S1340), the memory controller 100 may perform operation S1310 again. When the RFM command is sent a given number of "N" times ("Yes" in operation S1340), the memory controller 100 may perform operation S1350.

[0252] Referring to the above-described operations S1310 to S1340 , the memory controller 100 may operate in the fourth mode without performing a mode register read operation on the mode register 712 until the RFM command is transmitted a given number of times “N”.

[0253] In operation S1350 , the memory controller 100 may determine whether the memory device 200 is in a risk situation associated with row hammer. According to an embodiment, the memory controller 100 may determine whether the memory device 200 is in a risk situation through a mode register read operation on the mode register 712 .

[0254] When the memory device 200 is not in a risk situation (“No” in operation S1350 ), the memory controller 100 may perform Fig.12 Operation S1210.

[0255] When the memory device 200 is in a risk situation (Yes in operation S1350), the memory controller 100 may perform operation S1310. In this case, the memory controller 100 may operate in the fourth mode without performing a mode register read operation until the RFM command is sent a given number "N".

[0256] Meanwhile, the above description is made by taking as an example the case where the memory controller 100 performs the mode register read operation on the mode register 712 in both operation S1240 and operation S1350 to determine whether the memory device 200 is in a risk situation. In this case, for example, when the flag data read from the mode register 712 indicates a risk situation ("Yes" in operation S1240), the memory controller 100 operating in the third mode may operate in the fourth mode. According to an embodiment, in this case, as shown in reference to Fig.13As described above, the memory controller 100 may operate in the fourth mode until the RFM command is sent a given number of times "N", and then a mode register read operation may be performed on the mode register 712. Accordingly, when the flag data does not indicate a risk situation ("No" in operation S1350), the memory controller 100 may operate in the third mode again.

[0257] However, the embodiments are not limited thereto. For example, in operation S1240, the memory controller 100 may determine whether a risk situation of the memory device 200 has occurred based on a signal received through the alarm pin 711; in operation S1350, the memory controller 100 may determine whether a risk situation of the memory device 200 has occurred based on a mode register read operation of the mode register 712. In this case, for example, when a risk signal is applied to the alarm pin 711 ("Yes" in operation S1240), the memory controller 100 operating in the third mode may operate in the fourth mode. According to the embodiments, in this case, as shown in reference Fig.13 As described above, the memory controller 100 may operate in the fourth mode until the RFM command is sent a given number of times "N", and then a mode register read operation may be performed on the mode register 712. When the flag data obtained through the mode register read operation does not indicate a risk situation ("No" in operation S1350), the memory controller 100 may operate in the first mode again.

[0258] Fig.14 is a diagram for describing an operation of adjusting a BAT value according to an embodiment of the present disclosure. Fig.14 The above figure shows an example of sending the RFM command in a state where the BAT value is fixed, and Fig.10 The following figure shows an example of sending an RFM command in a state where the BAT value is controlled according to the row hammer risk.

[0259] exist Fig.14 In the following figure, the row hammer flag data RH RISK FLAG may refer to a signal indicating the row hammer risk of the memory device 200. For example, the row hammer flag data RH RISK FLAG may refer to a flag data signal of the row hammer risk read from the mode register 712 (or a signal of the row hammer risk applied to the alarm pin 711). Reference numeral 21 may refer to a flag data signal indicating a risk situation read from the mode register 712 (or a risk signal applied to the alarm pin 711).

[0260] Reference Fig.14As shown in the figure above, whenever the number of bank activations (expressed as CNT) reaches BAT, the memory controller 100 may send an RFM command. In this case, BAT may have a fixed value regardless of the row hammer risk. Fig.14 As can be understood from the above figure, RFM commands are sent at regular intervals (or periodically).

[0261] Reference Fig.14 As shown in the figure below, the memory controller 100 may change the BAT value according to the row hammer flag data RHRISK FLAG of the memory device 200 .

[0262] According to an embodiment, when the memory device 200 is not in a risk situation associated with a row hammer risk, the memory controller 100 may operate in the third mode. For example, when the number of bank activations (expressed as CNT) reaches BAT1, the memory controller 100 may send an RFM command until a flag data signal (or risk signal) 21 is obtained.

[0263] Meanwhile, when the flag data signal (or risk signal) 21 is obtained, the memory controller 100 operating in the third mode may operate in the fourth mode. Fig.14 In the following figure, the portion of the drawing after applying the flag data signal (or risk signal) 21 shows the operation in the fourth mode, in which the RFM command is sent every time the number of storage body activations (expressed as CNT) reaches BAT2. As described above, since the value of BAT2 is less than the value of BAT1, it can be confirmed that the sending frequency of the RFM command corresponding to the case of operation in the fourth mode is higher than the sending frequency of the RFM command corresponding to the case of operation in the third mode.

[0264] According to an embodiment, in this case, the memory controller 100 may operate in the fourth mode until the RFM command is sent a given number of times. In this case, the memory controller 100 may not perform a mode register read operation on the mode register 712 until the number of times the RFM command is sent reaches a given number of times.

[0265] When the RFM command is sent a given number of times while operating in the fourth mode, the memory controller 100 may perform a mode register read operation on the mode register 712. When the flag data read from the mode register 712 by the mode register read operation does not indicate a risk situation, the memory controller 100 may operate in the third mode. When the read flag data indicates a risk situation, the memory controller 100 may operate in the fourth mode again until the RFM command is sent a given number of times.

[0266] Alternatively, according to an embodiment, when the RFM command is sent a given number of times while operating in the fourth mode, the memory controller 100 may check the signal applied to the alert pin 711, and may determine whether to operate in the third mode based on the checked signal. For example, when it is checked that the signal applied to the alert pin 711 is not a risk signal at a time point when the RFM command is completely sent a given number of times, the memory controller 100 may operate in the third mode. When it is checked that the signal applied to the alert pin 711 is a risk signal at a time point when the RFM command is completely sent a given number of times, the memory controller 100 may operate in the fourth mode again until the RFM command is sent a given number of times.

[0267] The following will refer to Figures 15 to 18 Various embodiments of changing the BAT value based on temperature information of the memory device 200 are described.

[0268] Fig.15 is a block diagram of a memory device according to an embodiment of the present disclosure. Fig.15 The memory device 200D may be Figure 1 , Figure 2A , Figure 2B and Figure 4 The present disclosure is not limited thereto but is an embodiment of the memory devices 200, 200A, 200B, and 200C.

[0269] Reference Fig.15 , the memory device 200D may include a memory cell array 310 and a temperature notification circuit 700B. Figures 1 to 3C The memory cell array 310 is described in detail, and thus, additional description will be omitted to avoid redundancy.

[0270] The temperature notification circuit 700B may notify the memory controller 100 of information related to the temperature of the memory device 200D. For example, the temperature notification circuit 700B may store the temperature information of the memory device 200D. In an embodiment, the format of the temperature information is not limited as long as the information indicates the temperature range to which the temperature of the memory device 200D belongs.

[0271] According to an embodiment, the temperature notification circuit 700B may be a mode register (e.g., MR4) associated with refresh settings among mode registers compliant with the Joint Electronic Device Engineering Council (JEDEC) DDR5 specification. Information related to refresh settings according to temperature ranges may be stored in MR4. Accordingly, information related to the temperature range of the memory device 200D may be obtained based on the information stored in MR4.

[0272] However, the temperature notification circuit 700B is not limited to MR4. The temperature notification circuit 700B may include various memories such as registers, cache memories, and RAMs capable of storing information for identifying the temperature range of the memory device 200D (such as information stored in MR4).

[0273] Fig.16 is a block diagram illustrating RFM control logic according to an embodiment of the present disclosure. Fig.16 The RFM control logic 120B (as a component included in the memory controller 100) may be Figure 5A and Figure 6 The RFM control logic 120 and 120A are described below, but the present disclosure is not limited thereto.

[0274] Reference Fig.16 The RFM control logic 120B may include a counter 121 , an RFM command generator 123 , and a temperature information obtainer 127 .

[0275] Reference Figure 6 The counter 121 is described in detail, and thus, an additional description will be omitted to avoid redundancy.

[0276] The temperature information obtainer 127 may read the information stored in the temperature notification circuit 700B to obtain the temperature information of the memory device 200. For example, when the temperature notification circuit 700B is implemented with MR4, the temperature information obtainer 127 may obtain the temperature information of the memory device 200 by performing a mode register read operation on MR4. However, the present disclosure is not limited thereto.

[0277] The RFM command generator 123 may generate an RFM command based on the number of bank activations counted by the counter 121 or information related to the temperature of the memory device 200 obtained by the temperature information obtainer 127 , and may transmit the generated RFM command to the memory device 200 .

[0278] According to an embodiment, the RFM command generator 123 may adjust the BAT based on the temperature information. For example, when the number of bank activations reaches BAT3 when the temperature of the memory device 200 is within the first temperature range, the RFM command generator 123 may send an RFM command. In an embodiment, the case where the number of bank activations (expressed as CNT) reaches BAT3 includes, in addition to the case where the number of bank activations (expressed as CNT) is consistent with BAT3, a case where the value of the number of bank activations (expressed as CNT) is greater than BAT3. In addition, when the number of bank activations reaches BAT4 when the temperature of the memory device 200 is within a second temperature range higher than the first temperature range, the RFM command generator 123 may send an RFM command. In an embodiment, the case where the number of bank activations (expressed as CNT) reaches BAT4 includes, in addition to the case where the counted number of bank activations (expressed as CNT) is consistent with BAT4, a case where the value of the number of bank activations (expressed as CNT) is greater than BAT4. At the same time, according to an embodiment, the value of BAT3 may be set to be less than the value of BAT4.

[0279] Specifically, in the case of DDR4 products, as the temperature range becomes lower, the refresh interval time tREFI can become longer. Accordingly, as the temperature range becomes lower, the row hammer refresh opportunity based on the REF command can become lower. The reduction in the mitigation opportunity of the row hammer can be compensated by making the BAT value lower as the temperature range decreases. That is, in the above example, since the value of BAT3 is less than the value of BAT4, the sending frequency of the RFM command in the first temperature range can be higher than the sending frequency of the RFM command in the second temperature range. Accordingly, the mitigation opportunity that is reduced according to the temperature range can be appropriately compensated.

[0280] Fig.17 is a diagram for describing an example of a BAT value for each temperature range according to an embodiment of the present disclosure. Fig.17 Three temperature ranges stored in MR4 and BAT values ​​corresponding to the three temperature ranges are shown. For example, the first temperature range may indicate the lowest temperature range among the three temperature ranges, the third temperature range may indicate the highest temperature range, and the second temperature range may be a temperature range between the first temperature range and the third temperature range.

[0281] As described above, since the mitigation opportunity of the row hammer based on the REF command decreases as the temperature decreases, the BAT values ​​corresponding to the first temperature range to the third temperature range, respectively, may increase in the order of K, L, and M. That is, according to an embodiment, the value of "L" may be equal to or greater than the value of "K", and the value of "M" may be equal to or greater than the value of "L".

[0282] The memory controller 100 may obtain temperature information of the memory device 200 through a mode register read operation on MR4 , and may generate and transmit an RFM command by using a BAT value corresponding to the obtained temperature range of the memory device 200 .

[0283] Fig.18 is a diagram for describing an operation of adjusting a BAT value according to an embodiment of the present disclosure. Fig.18 Shown with Fig.17 The first temperature range to the third temperature range correspond to the RFM command sending operation.

[0284] Reference Fig.18 , when the number of storage body activations reaches "K" when the temperature range of the storage device 200 is the first temperature range, the memory controller 100 may send an RFM command. In addition, when the number of storage body activations reaches "L" when the temperature range of the storage device 200 is the second temperature range, the memory controller 100 may send an RFM command. In addition, when the number of storage body activations reaches "M" when the temperature range of the storage device 200 is the third temperature range, the memory controller 100 may send an RFM command. In an embodiment, the case where the number of storage body activations (expressed as CNT) reaches a specific number (i.e., K, L, or M), in addition to the case where the number of storage body activations (expressed as CNT) is consistent with the corresponding number (i.e., K, L, or M), may also include the case where the value of the storage body activation number (expressed as CNT) is greater than the corresponding number (i.e., K, L, or M).

[0285] In this case, since the BAT values ​​of the temperature ranges increase in the order of K, L, and M, the memory controller 100 may send the RFM command at a relatively higher frequency (or at shorter intervals / more frequently) as the temperature range moves toward a relatively lower temperature range.

[0286] Next, we will refer to Figures 19 to 23 Various embodiments of sending RFM commands taking into account memory bank activation time are described.

[0287] Fig.19 is a block diagram of RFM control logic according to an embodiment of the present disclosure, and Fig. 20 is a diagram for describing a memory bank activation time according to an embodiment of the present disclosure. Fig.19 The RFM control logic 120C (as a component included in the memory controller 100) may be Figure 5A , Figure 6 and Fig.16 The present disclosure is not limited to the implementation of the RFM control logic 120, 120A and 120B.

[0288] Reference Fig.19 , the RFM control logic 120C may include a counter 121 , an RFM command generator 123 , and a bank activation time manager 129 .

[0289] The counter 121 may count the number of memory bank activation times.

[0290] According to an embodiment, regardless of the bank activation time, the counter 121 may count the number of bank activation times by increasing the number of bank activation times by “1” whenever an ACT command is sent to the memory device 200 .

[0291] Meanwhile, according to an embodiment, the counter 121 may count the number of storage body activation times in consideration of the storage body activation time. For example, the counter 121 may convert the storage body activation time into the number of storage body activation times to count the number of storage body activation times. In this case, when the counter 121 counts the number of storage body activation times, the counter 121 may increase the value in different ways according to the storage body activation time based on the corresponding ACT command. In an embodiment, information related to the storage body activation time based on the ACT command may be obtained through the storage body activation time manager 129, but the present disclosure is not limited thereto.

[0292] In an embodiment, when the storage body activation time based on the first ACT command is equal to or less than the reference time, the counter 121 may increase the number of activations by a first value (e.g., "1") according to the transmission of the first ACT command. In addition, when the storage body activation time based on the second ACT command exceeds the reference time, the counter 121 may increase the number of activations by a second value (e.g., "2") according to the transmission of the second ACT command.

[0293] In this case, according to an embodiment, when the counter 121 counts the number of storage body activation times, the counter 121 may increase the value corresponding to the storage body activation time at one time. For example, when the storage body activation time based on the ACT command exceeds the reference time, the counter 121 may increase the number of activation times by "2" at one time.

[0294] Alternatively, according to an embodiment, when the counter 121 counts the number of bank activation times, the counter 121 may gradually increase the value corresponding to the bank activation time. For example, when the ACT command is sent, the counter 121 may increase the number of bank activation times by "1". Thereafter, the counter 121 may check the bank activation time; when the bank activation time exceeds the reference time, the counter 121 may additionally increase the number of bank activation times by "1".

[0295] Meanwhile, for ease of description, the above describes an example of dividing the storage body activation time into two segments based on one reference time. However, of course, the implementation is not limited thereto. According to the implementation, the storage body activation time may be divided into three or more segments. For example, the storage body activation time may be divided into three segments based on a first reference time and a second reference time. In an implementation, the second reference time may be longer than the first reference time.

[0296] In this case, when the storage body activation time based on the first ACT command is equal to or less than the first reference time, the counter 121 may increase the number of activations by a first value (e.g., "1") according to the transmission of the first ACT command. In addition, when the storage body activation time based on the second ACT command exceeds the first reference time and is equal to or less than the second reference time, the counter 121 may increase the number of activations by a second value (e.g., "2") according to the transmission of the second ACT command. In addition, when the storage body activation time based on the third ACT command exceeds the second reference time, the counter 121 may increase the number of activations by a third value (e.g., "3") according to the transmission of the third ACT command.

[0297] The bank activation time manager 129 may manage a bank activation time associated with an ACT command transmitted by the memory controller 100 .

[0298] According to an embodiment, the bank activation time manager 129 may obtain the bank activation time. Fig. 20 As shown, the time length T1 from the first time point t1 of sending the ACT command to the second time point t2 of sending the PRE command can be the storage body activation time based on the ACT command. When the ACT command is sent, the storage body activation time manager 129 can calculate (or measure) the time length between the time point of sending the ACT command and the time point of sending the PRE command after the ACT command, and can obtain the storage body activation time based on the corresponding ACT command.

[0299] Meanwhile, according to an embodiment, the bank activation time manager 129 may sum the bank activation time. For example, whenever an ACT command is sent, the bank activation time manager 129 may obtain the bank activation time based on each ACT command and may accumulate the obtained bank activation time.

[0300] The RFM command generator 123 may generate an RFM command based on the number of bank activation times counted by the counter 121 and the bank activation time managed by the bank activation time manager 129 , and may transmit the generated RFM command to the memory device 200 .

[0301] According to an embodiment, when the number of bank activations reaches BAT, the RFM command generator 123 may send an RFM command to the memory device 200. In this case, the RFM command generator 123 may determine whether the number of bank activations reaches BAT by using the number of bank activations counted in consideration of the bank activation time. In this case, as more ACT commands with bank activation times exceeding the reference time are sent, the number of bank activations may increase faster. This may mean that the RFM command is sent more frequently.

[0302] Meanwhile, according to an embodiment, when the number of bank activations reaches BAT or the summed bank activation time reaches BATT, the RFM command generator 123 may send an RFM command to the memory device 200. In this case, the RFM command generator 123 may determine whether the number of bank activations reaches BAT by using the number of bank activations counted without considering the bank activation time. In this case, even if the number of bank activations does not reach BAT, the RFM command may be sent when the bank activation time reaches BATT.

[0303] Fig.21 is a flowchart illustrating an operating method of a memory controller according to an embodiment of the present disclosure. Fig.21 An embodiment of sending an RFM command based on a threshold value BAT associated with the number of memory bank activations and a threshold value BATT associated with the memory bank activation time is shown. Fig.21 , the description given above will be omitted.

[0304] Reference Fig.21 In operation S2110, the memory controller 100 may count the number of bank activation times. For example, when an ACT command is sent, the memory controller 100 may increase the number of bank activation times (expressed as CNT) by "1".

[0305] In operation S2120, the memory controller 100 may sum the bank activation time. For example, the memory controller 100 may obtain the bank activation time based on the ACT command, and may accumulate the obtained bank activation time.

[0306] In operation S2130, the memory controller 100 may determine whether the counted number of memory cell activations (expressed as CNT) reaches BAT. In this case, the case where the counted number of memory cell activations (expressed as CNT) reaches BAT may include a case where the value of the counted number of memory cell activations (expressed as CNT) is greater than BAT, in addition to the case where the counted number of memory cell activations (expressed as CNT) is consistent with BAT.

[0307] Accordingly, according to an embodiment, the memory controller 100 may determine whether the counted bank activation number CNT (denoted as CNT) reaches BAT by determining whether the counted bank activation number (denoted as CNT) is equal to or greater than BAT.

[0308] When the counted number of bank activations (denoted as CNT) is equal to or greater than BAT, that is, when the counted number of bank activations (denoted as CNT) reaches BAT (“Yes” in operation S2130), the memory controller 100 may perform operation S2150. In operation S2150, the memory controller 100 may send an RFM command to the memory device 200.

[0309] When the number of memory cell activations (expressed as CNT) is less than BAT, that is, when the number of memory cell activations (expressed as CNT) does not reach BAT ("No" in operation S2130), the memory controller 100 may perform operation S2140. In operation S2140, the memory controller 100 may determine whether the summed number of memory cell activations CNT has reached BATT so far. In an embodiment, the case where the summed number of memory cell activations reaches BATT may include a case where the summed number of memory cell activations is greater than BATT in addition to the case where the summed number of memory cell activations is consistent with BATT.

[0310] Accordingly, according to an embodiment, the memory controller 100 may determine whether the summed number of bank activations reaches BATT by determining whether the summed number of bank activations is equal to or greater than BATT.

[0311] When the summed bank activation count is equal to or greater than BATT, that is, when the summed bank activation count reaches BATT ("Yes" in operation S2140), the memory controller 100 may perform operation S2150. In operation S2150, the memory controller 100 may send an RFM command to the memory device 200. In this case, the memory controller 100 may reset the bank activation count (expressed as CNT).

[0312] When the summed bank activation count is less than the BATT, that is, when the summed bank activation count does not reach the BATT (“No” in operation S2140 ), the memory controller 100 may perform operation S2110 .

[0313] at the same time, Fig.21, the case where operation S2120 is performed after operation S2110 is performed and operation S2140 is performed after operation S2130 is performed is shown as an example, but the present disclosure is not limited thereto. According to an embodiment, operation S2120 may be performed before operation S2110. In addition, operation S2140 may be performed before operation S2130. In the case where operation S2140 is performed before operation S2130, when the summed number of storage body activations does not reach BATT, operation S2130 may be performed, and when the summed number of storage body activations does not reach BATT, operation S2110 may be performed again.

[0314] Fig.22A and Fig. 22B is a flowchart illustrating an operating method of a memory controller according to an embodiment of the present disclosure. Fig.22A and Fig. 22B An embodiment of counting the number of memory bank activation times taking into account the memory bank activation time is shown. Fig.22A and Fig. 22B , the description given above will be omitted or simplified.

[0315] Reference Fig.22A , in operation S2210 , the memory controller 100 may send an ACT command to the memory device 200 .

[0316] In operation S2215 , the memory controller 100 may determine whether a bank activation time based on the ACT command exceeds a reference time.

[0317] When the bank activation time is equal to or less than the reference time ("No" in operation S2215), the memory controller 100 may perform operation S2220. In addition, when the bank activation time exceeds the reference time ("Yes" in operation S2215), the memory controller 100 may perform operation S2225.

[0318] In operation S2220, the memory controller 100 may increase the number of bank activation times (denoted as CNT) by a first value. In an embodiment, the first value may be "1", but the present disclosure is not limited thereto.

[0319] In operation S2225, the memory controller 100 may increase the number of bank activation times (denoted as CNT) by a second value. In an embodiment, the second value may be greater than the first value. For example, when the first value is "1", the second value may be "2". However, the present disclosure is not limited thereto.

[0320] In operation S2230, the memory controller 100 may determine whether the counted number of memory cell activations (expressed as CNT) reaches BAT. In this case, according to an embodiment, the memory controller 100 may determine whether the counted number of memory cell activations (expressed as CNT) reaches BAT by determining whether the counted number of memory cell activations (expressed as CNT) is equal to or greater than BAT.

[0321] When the counted number of bank activations (expressed as CNT) is equal to or greater than BAT, that is, when the counted number of bank activations (expressed as CNT) reaches BAT ("Yes" in operation S2230), the memory controller 100 may perform operation S2235. In operation S2235, the memory controller 100 may send an RFM command to the memory device 200. In this case, the memory controller 100 may reset the number of bank activations (expressed as CNT).

[0322] Meanwhile, when the bank activation number (denoted as CNT) is less than BAT, that is, when the bank activation number (denoted as CNT) does not reach BAT (“No” in operation S2230 ), the memory controller 100 may perform operation S2210 again.

[0323] according to Fig.22A , when the memory controller 100 counts the number of bank activation times, the memory controller 100 may increase a value corresponding to the bank activation time at one time.

[0324] At the same time, refer to Fig. 22B , in operation S2250 , the memory controller 100 may send an ACT command to the memory device 200 .

[0325] In operation S2255, the memory controller 100 may increase the bank activation count (denoted as CNT) by a first value based on the ACT command. In an embodiment, the first value may be "1", but the present disclosure is not limited thereto.

[0326] In operation S2260 , the memory controller 100 may determine whether a bank activation time based on the ACT command exceeds a reference time.

[0327] When the bank activation time is equal to or less than the reference time ("No" in operation S2260), the memory controller 100 may perform operation S2265. In addition, when the bank activation time exceeds the reference time ("Yes" in operation S2260), the memory controller 100 may perform operation S2270.

[0328] In operation S2270 , the memory controller 100 may additionally increase the number of bank activation times (denoted as CNT) by a first value, and may then perform operation S2265 .

[0329] In operation S2265, the memory controller 100 may determine whether the counted number of memory cell activations (expressed as CNT) reaches BAT. In this case, according to an embodiment, the memory controller 100 may determine whether the counted number of memory cell activations (expressed as CNT) reaches BAT by determining whether the counted number of memory cell activations (expressed as CNT) is equal to or greater than BAT.

[0330] When the counted number of bank activations (expressed as CNT) is equal to or greater than BAT, that is, when the counted number of bank activations (expressed as CNT) reaches BAT ("Yes" in operation S2265), the memory controller 100 may perform operation S2275. In operation S2275, the memory controller 100 may send an RFM command to the memory device 200. In this case, the memory controller 100 may reset the number of bank activations (expressed as CNT).

[0331] Meanwhile, when the bank activation number (denoted as CNT) is less than BAT, that is, when the bank activation number (denoted as CNT) does not reach BAT (“No” in operation S2265 ), the memory controller 100 may perform operation S2250 again.

[0332] Reference Fig. 22B , when the memory controller 100 counts the number of bank activation times, the memory controller 100 may gradually increase a value corresponding to the bank activation time.

[0333] Fig.23 is a diagram for describing an operation of transmitting an RFM command in consideration of a bank activation time according to an embodiment of the present disclosure.

[0334] Fig.23 The above figure shows an example of sending an RFM command without considering the bank activation time, and Fig.23 The following figure shows an example of sending an RFM command in consideration of the bank activation time. In an embodiment, the two examples are provided under the assumption that an ACT command having a bank activation time exceeding a reference time is sent the same number of times.

[0335] Reference Fig.23, the memory controller 100 may increase the number of bank activations (denoted as CNT) by “1” whenever an ACT command is sent, and may send an RFM command to the memory device 200 when the counted number of bank activations (denoted as CNT) reaches BAT.

[0336] Reference Fig.23 As shown in the figure below, the memory controller 100 can convert the storage body activation time into the number of storage body activation times so as to be added to the number of storage body activation times. For example, when an ACT command with a storage body activation time exceeding a reference time is sent to the memory device 200, the memory controller 100 can increase the number of storage body activations by "2" according to the corresponding ACT command. In this case, as ACT commands with storage body activation times exceeding the reference time are sent more frequently, the number of storage body activations can increase faster. This may mean that RFM commands are sent more frequently. Accordingly, it is possible to cope with problems caused by the PGE phenomenon.

[0337] Meanwhile, according to an embodiment, the memory controller 100 may determine whether to send an RFM command by considering both a threshold value BAT associated with the number of bank activations and a threshold value BATT associated with the bank activation time. In this case, even if the number of bank activations does not reach BAT, an RFM command may be sent when the bank activation time reaches BATT. Accordingly, it is possible to cope with problems caused by the PGE phenomenon.

[0338] According to the above embodiments of the present disclosure, the sending frequency of the RFM command can be variably controlled according to the situation of the memory device, and accordingly, the bandwidth efficiency of the memory system or the performance of the memory system can be improved.

[0339] Although this specification contains many specific implementation details, these details should not be interpreted as limitations on the scope of what may be claimed or on the scope of any invention, but rather as descriptions of features that may be specific to a particular embodiment of a particular invention. In a single embodiment, certain features described in this specification in the context of separate embodiments may also be implemented in combination. Conversely, various features described in the context of a single embodiment may also be implemented separately in multiple embodiments, or in appropriate sub-combinations. In addition, although the above-mentioned features may be described above as working in certain combinations, in some cases, one or more features in a combination may be deleted from the combination, and the combination may be directed to a sub-combination or a variation of a sub-combination.

[0340] While the present disclosure has been described with reference to the embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications can be made thereto without departing from the spirit and scope of the present disclosure as set forth in the appended claims.

Claims

1. A memory system, comprising: A memory device including a memory cell array and a notification circuit; as well as a memory controller configured to: send a refresh management RFM command to the memory device based on the number of occurrences of memory bank activation of the memory bank included in the memory cell array reaching a threshold value, The memory controller is configured to: control the sending frequency of the RFM command based on the notification obtained by the notification circuit, and The notification includes at least one of the following information: risk information related to a row hammer risk of a row included in the memory bank, or temperature information of the memory device, wherein the temperature information includes a current temperature of the memory device.

2. The memory system according to claim 1, wherein: The storage body comprises: a plurality of rows arranged along a row direction; and a plurality of counting units configured to store counting data associated with a number of occurrences of activation of each of the plurality of rows, and The risk information related to the hammer risk indicates that the count data reaches a reference count.

3. The memory system according to claim 2, wherein: The notification circuit includes at least one of the following: an alarm pin configured to: in response to the count data stored in at least one of the plurality of counting units reaching the reference count, send a risk signal to indicate a risk situation, or The first mode register is configured to: in response to the count data stored in at least one of the plurality of count units reaching the reference count, store flag data to indicate the risk condition.

4. The memory system according to claim 3, wherein: The memory controller is configured to: The hammer risk is obtained based on the flag data stored in the first register or the risk signal sent by the alarm pin.

5. The memory system according to claim 4, wherein: The memory controller is configured to: Based on the hammer risk, setting the operation mode to one of a first mode or a second mode, Wherein, in the first mode, the memory controller is configured to: maintain operation without sending the RFM command regardless of the number of occurrences of the memory bank activation, and Wherein, in the second mode, the memory controller is configured to: send the RFM command based on the number of occurrences of the storage body activation reaching the threshold.

6. The memory system according to claim 5, wherein: The memory controller is configured to: setting the operating mode to the second mode based on the flag data including first data indicative of the risk situation; as well as Otherwise, the operation mode is set to the first mode.

7. The memory system according to claim 6, wherein: The memory controller is configured to: A read operation is performed on the first register to obtain the row hammer risk based on the number of occurrences of the memory bank activation reaching the threshold.

8. The memory system according to claim 6, wherein: The memory controller is configured to: In the first mode, a read operation is performed on the first register to obtain the row hammer risk based on the number of occurrences of the memory bank activation reaching the threshold value, switching the operating mode from the first mode to the second mode based on obtaining the flag data indicative of the risk condition, and In response to sending a set number of RFM commands to perform a read operation on the first register, the operation mode is switched from the second mode back to the first mode.

9. The memory system according to claim 5, wherein: The memory controller is configured to: setting the operating mode to the second mode based on applying the risk signal via the alarm pin; as well as Otherwise, the operation mode is set to the first mode.

10. The memory system according to claim 9, wherein: The memory controller is configured to: Based on the risk signal applied through the alert pin when the memory controller operates in the first mode, operating in the second mode until the RFM command is sent no more than a predetermined number of times, a read operation is performed on the first register.

11. The memory system according to claim 4, wherein: The memory controller is configured to: Based on the hammer risk, setting the operation mode to one of the third mode or the fourth mode, Wherein, in the third mode, the memory controller is configured to: send the RFM command based on the number of occurrences of the memory bank activation reaching a first threshold, Wherein, in the fourth mode, the memory controller is configured to: send the RFM command based on the number of occurrences of the memory bank activation reaching a second threshold, and The value of the second threshold is smaller than the value of the first threshold.

12. The memory system according to claim 11, wherein: The memory controller is configured to: When the memory controller operates in the third mode, the operation mode is set to the fourth mode based on applying the risk signal through the alarm pin or based on obtaining the flag data indicating the risk situation by performing a read operation on the first register.

13. The memory system according to claim 12, wherein: The memory controller is configured to: When the memory controller operates in the fourth mode, based on the RFM command being sent no more than a predetermined number of times, performing a read operation on the first register; as well as Otherwise, operate in the third mode.

14. The memory system according to claim 1, wherein: The notification circuit comprises: a second register configured to store temperature information of the storage device, and Wherein, the memory controller is configured as: obtaining the temperature information based on a read operation of the second register; and The threshold is adjusted based on the obtained temperature information.

15. The memory system of claim 14, wherein: The memory device is configured to operate at a first refresh interval within a first temperature range, and the memory device is configured to operate at a second refresh interval shorter than the first refresh interval within a second temperature range, Wherein, the memory controller is configured as: Based on the number of occurrences of the memory bank activation within the first temperature range reaching a third threshold, sending the RFM command; and Based on the number of occurrences of the memory bank activation within the second temperature range reaching a fourth threshold, sending the RFM command, and The value of the third threshold is smaller than the value of the fourth threshold.

16. The memory system according to claim 1, wherein: The memory controller is configured to: In response to an activation command being sent to the memory bank, counting a number of occurrences of activation of the memory bank; summing a bank activation time of the bank based on the activation command sent to the bank; as well as The RFM command is sent based on the number of occurrences of the storage body activation reaching the threshold or based on the summed storage body activation time reaching a time threshold.

17. The memory system according to claim 1, wherein: The memory controller is configured to: Based on the memory bank activation time being equal to or less than a reference time, increasing the number of occurrences of the memory bank activation by a first value; and Based on the bank activation time exceeding the reference time, the number of occurrences of the bank activation is increased by a second value greater than the first value.

18. A method of operating a memory controller, the memory controller controlling a memory device, the method comprising: Sending a refresh management RFM command to the memory device based on whether the number of occurrences of memory bank activation of the memory bank of the memory device reaches a threshold; Obtaining a notification, the notification including at least one of the following information: information related to a row hammer risk of each row included in the memory bank of the memory device, or temperature information related to the memory device, wherein the temperature information includes a temperature range of the memory device; as well as A frequency of sending the RFM command is controlled based on the notification.

19. The method according to claim 18, wherein: Controlling the sending frequency of the RFM command includes: The RFM command is selectively sent based on the notification, or the threshold is adjusted based on the notification.

20. A memory device comprising: A memory cell array including a memory bank; Hammer management circuit; as well as a notification circuit comprising at least one of an alert pin or a register, Wherein, the storage body includes: a plurality of rows arranged along a row direction; and a plurality of counting units configured to store counting data associated with a number of occurrences of activation of each of the plurality of rows, and Wherein, the hammer management circuit is configured as follows: managing count data for each of the plurality of rows; and Based on the count data stored in at least one of the plurality of count units reaching a reference count, flag data indicating a risk situation is stored in the register, and a risk signal indicating the risk situation is applied to the alarm pin.

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