Semiconductor device, memory circuit and operation method of memory

Abstract

The invention discloses a semiconductor device, a memory device and an operation method of a memory. In one aspect, the semiconductor device comprises a memory array, and the memory array comprises a first memory unit and a second memory unit. The second memory unit has an operating characteristic different from that of the first memory unit. The semiconductor device includes a first write circuit for writing first data to the first memory cell. The semiconductor device includes a second write circuit configured to write second data to the second memory cell, wherein the second write circuit is selectively configured to compensate for the operating characteristic of the second memory cell.

Description

Technical Field

[0001] The disclosed embodiments relate to a memory circuit, and more particularly to a memory circuit with write assist. Background Art

[0002] The semiconductor industry has experienced rapid growth due to the continued increase in the integration density of various electronic components, such as transistors, diodes, resistors, capacitors, etc. In most cases, this increase in integration density is due to repeated reductions in minimum feature size, which allows more components to be integrated into a given area. Summary of the invention

[0003] In some embodiments, a semiconductor device is provided. The semiconductor device includes a memory array, a first write circuit, and a second write circuit. The memory array includes a first memory cell and a second memory cell. The second memory cell has an operating characteristic different from the operating characteristic of the first memory cell. The first write circuit is used to write first data into the first memory cell. The second write circuit writes second data into the second memory cell, wherein the second write circuit is selectively used to compensate for the operating characteristic of the second memory cell.

[0004] In some embodiments, a memory circuit is provided, comprising: a write driver device that writes input data to one of a first column or a second column of a memory array; a write assist circuit that enables the write driver device to selectively operate at one of a first voltage or a second voltage; and a write assist enabling circuit that activates the write assist circuit based on an indication that the first column or the second column includes a memory cell with a defect.

[0005] In some embodiments, a method of operating a memory is provided, comprising the steps of providing an indication that a memory cell of a memory array has predetermined operating characteristics; detecting a write operation of a row or column of the memory array including memory cells having the predetermined operating characteristics; and selectively activating a write assist circuit during the write operation to compensate for the predetermined operating characteristics of the memory cell. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The various aspects of the disclosed embodiments can be best understood when the following detailed description is read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1 A schematic block diagram illustrating a memory array implementing a write assist circuit for selective activation based on memory test results according to some embodiments;

[0008] Figure 2 A schematic block diagram illustrating another memory array implementing a write assist circuit that is selectively activated based on a specified column address according to some embodiments;

[0009] Figure 3 A schematic block diagram illustrating another memory array implementing a write assist circuit that is selectively activated based on a specified row address according to some embodiments;

[0010] Figure 4 A schematic block diagram illustrating another memory array implementing a write assist circuit that is selectively activated based on a specified row address and a specified column address according to some embodiments;

[0011] Figure 5 A flow chart illustrating an example method of operating a disclosed memory array including the selectively activated write assist circuits described herein, in accordance with some embodiments of the present disclosure.

[0012]

Explanation of symbols

[0013] 100, 200, 300, 400: memory circuit

[0014] 101, 101A~101N, 201, 201A~201N, 301, 301A~301N, 401, 401A~401N

[0015] :Memory Block

[0016] 102, 102A~102N, 202, 202A~202N, 302, 302A~302N, 402, 402A~402N

[0017] :Write assist enable circuit

[0018] 104, 104A~104N, 204, 204A~204N, 304, 304A~304N, 404, 404A~404N

[0019] :Write Driver Circuit

[0020] 106, 106A~106N, 206, 206A~206N, 306, 306A~306N, 406, 406A~406N

[0021] :Write auxiliary circuit

[0022] 108, 108A~108N, 208, 208A~208N, 308, 308A~308N, 408, 408A~408N

[0023] :Multiplexer Circuit

[0024] 110, 210, 310, 410: memory unit

[0025] 112, 212, 312, 412: weak memory cells

[0026] 120, 220, 320, 420: Write auxiliary configuration circuit

[0027] 214, 416: second output terminal

[0028] 314, 414: address matching circuit

[0029] 500:Method

[0030] 502, 504, 506: Operation

[0031] BL0, BLC, !BLC, !BL0, BLM, !BLM: bit line

[0032] C: Identifier

[0033] Col ADDR: column address

[0034] Data 0, Data N: Input data

[0035] Row 0ADDR~Row R ADDR: row address

[0036] Write: Write enable signal DETAILED DESCRIPTION

[0037] The following disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. The specific examples of components and configurations described below are for simplifying the disclosed embodiments. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include an embodiment in which the first feature and the second feature are directly contacted, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be directly contacted. In addition, the disclosed embodiments may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0038] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," "top," "bottom," and the like may be used herein to describe the relationship of one element or feature to another element or feature as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

[0039] Design specifications provide constraints on various operating characteristics for operating memory circuits, including word line pulse widths and memory write voltages, among others. As design specifications begin to use higher sigma values, such as six sigma values, for smaller and denser memory circuits, these design constraints begin to affect the aggregate write performance of the memory. Even when such design constraints are implemented, defects in memory cells are still possible. One such defect includes a "weak" memory cell, which is a memory cell that has difficulty holding or maintaining a desired state during a write operation due to various factors, such as process variations, degradation over time, or other environmental conditions.

[0040] These design constraints require activation of the write assist circuitry of the entire memory array, even when only a small number of memory cells are identified as weak memory cells. Various test methods can be used to identify defects in manufactured memory devices, including built-in self-test (BIST) circuits or external test circuits. However, this approach has significant disadvantages for memory device design and manufacturing. The use of high sigma values ​​means that the resulting design is extremely conservative in terms of power consumption and performance, resulting in a waste of active power (e.g., writing much wider word line pulse widths to compensate for potentially defective cells) and an increase in cycle time, which can be significant for some memory operations. In addition, write assist circuits are added for each access, even when these write assist circuits may not actually be needed for non-defective memory cells, which further increases the overall power consumption of the device.

[0041] To address these and other issues, the devices, circuits, and methods described herein provide techniques for selectively activating write assist circuits only when needed to compensate for defective memory cells. Advantages of such techniques include lower effective power, reduced cycle time, higher performance memory cells, and more efficient use of available space on a wafer to manufacture memory chips. Selectively activating write assist circuits can be implemented in various configurations, including activating write assist upon detection of a write operation to a specified memory block, a specified memory column, a specified memory row, or a combination thereof. Various test methods can be used to identify defective memory bits (and any block, column, or row address thereof), including BIST techniques or external test techniques, among others.

[0042] These techniques can improve overall device performance and power consumption by reducing the number of write assist circuits that are activated during normal operation. Active power can be reduced by disabling certain portions of the circuit when they are not needed, thereby reducing average device power consumption. Reducing this constant active power consumption by allowing the write assist circuitry to be selectively activated enables looser design constraints (e.g., 5.5σ), resulting in timing improvements and active power reductions.

[0043] Figure 1 Schematic block diagram illustrating a memory circuit 100 that implements selective activation of write assist circuits 106A-106N based on memory test results according to some embodiments. As shown, the memory circuit 100 includes an array of memory cells 110 (sometimes referred to herein as "bit cells") that can store digital data. Each of the components shown in the memory circuit 100 can receive power from one or more voltage sources. The memory circuit 100 can include one or more logic gates and subcircuits, each of which can be composed of one or more logic gates. A logic gate is an electronic device that performs a logical operation on one or more input signals to produce a single output signal.

[0044] Various embodiments of the circuits and logic gates implementing the memory circuit 100 may include various transistors. The transistors described herein may be of a particular type (n-type or p-type), but the embodiments are not limited thereto. The transistors may be any suitable type of transistor, including but not limited to metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductors (CMOSs), P-channel metal oxide semiconductors (PMOSs), N-channel metal oxide semiconductors (NMOSs), bipolar junction transistors (BJTs), high voltage transistors, high frequency transistors, P-channel and / or N-channel field effect transistors (PFETs / N-channel field effect transistors, NFETs), FinFETs, planar MOS transistors with raised source / drains, nanosheet FETs, nanowire FETs, or the like.

[0045] As shown, the memory circuit 100 includes a plurality of memory blocks 101A-101N (sometimes generally referred to as memory blocks 101), each of which includes various memory cells 110. The memory cell 110 may be any type of memory device capable of storing at least one bit of memory data, including but not limited to a static random access memory (SRAM) cell or a dynamic random access memory (DRAM) cell, etc. The memory cell 110 may be manufactured to have one or more defects due to the nature of the manufacturing process used to create the memory cell. Such defects may cause the memory cell to become a "weak memory" cell, which has difficulty maintaining or maintaining a desired (e.g., write) state during a write operation due to various factors (such as process variations, degradation over time, or other environmental conditions). Memory cells 110 having such defects may be referred to herein as weak memory cells 112.

[0046] As shown, each memory block 101 may include one or more columns of memory cells 110 arranged in corresponding rows. Each column of the memory block 101 may include one or more weak memory cells 112. In this example, each memory block 101 is shown as including two columns of memory cells 110 (or weak memory cells 112). However, it should be understood that each block may include any number of columns, which are specified in this example by an identifier C (e.g., the total number of columns in the block). Each column in the memory block 101 may be addressed by a corresponding set of bit lines (such as bit line BL0 and its corresponding logically inverted bit line). If multiple columns are included in the memory block 101, the memory block 101 may include corresponding multiplexer circuits.

[0047] In this example, memory block 101A includes two memory columns, and thus includes a 1:2 multiplexer circuit 108A (sometimes generally referred to as multiplexer circuit 108) that switches between bit line BL0 and bit line BLC based on an input column address (shown as Col ADDR) signal received from a memory control circuit. In this example, each memory block 101 includes two columns of memory cells 110, and thus multiplexer circuits 108 (e.g., multiplexer circuits 108A-108N) are each 1:2 multiplexer circuits. Multiplexer circuits 108 receive corresponding bit line signals from write driver circuits 104 (e.g., one of write driver circuits 104A-104N) of a corresponding memory block 101 and provide respective output bit line signals to a selected column. Multiplexer circuits 108 can select between each column based on a column address (shown here as Col ADDR) that can be received from a memory control circuit.

[0048] As shown, the memory cells 110 (and weak memory cells 112) are arranged in one or more rows, each of which can be selected using a corresponding row address (shown here as Row ADDR, ranging from 0 to R rows, i.e., Row 0ADDR to RowR ADDR). Each row address can be provided by a memory control circuit of a memory block 101 of the memory, which can select a corresponding row and column of column address and row address signals. The memory control circuit can include any type of control circuit that provides signals for coordinating read or write operations through the circuit system of the memory circuit 100. For example, the memory control circuit can provide a write enable signal (shown here as "Write") that activates various components of a write enable driver. For example, the write enable signal can activate the corresponding write driver circuit 104, the write assist circuit 106 and / or the write assist enable circuit 102 of the memory block 101.

[0049] As shown, each memory block 101 is shown to include one of write driver circuits 104A-104N (sometimes generally referred to as write driver circuits 104). Each write driver circuit 104 can generate one or more signals to write input data (here shown as "Data 0" of the first memory block 101A and "Data N" of the Nth memory block 101N) to the selected memory cell 110. To this end, the write driver circuit 104 can drive the bit line corresponding to the selected memory cell 110 (e.g., bit line BLC and bit line !BLC, where the ! designator indicates the logical inversion of the corresponding signal) to perform a write operation to store the input data (e.g., Data 0) in the addressed memory cell 110 (or weak memory cell 112). In some embodiments, the write driver 104 includes a level shifter circuit that can adjust the voltage levels of the output signals to align them with the voltage requirements of the memory cell 110 to be written. The write driver circuit 104 may include write enable logic that causes the write driver circuit 104 to remain deactivated until a write enable signal (shown here as the “Write” signal) is received.

[0050] As shown, write driver circuits 104A-104N are integrated with corresponding write assist circuits 106A-106N (sometimes generally referred to as "write assist circuits 106"). Write assist circuits 106 may be used to compensate for defective weak memory cells 112, which may include different operating characteristics than memory cells 110. For example, weak memory cells 112 may require a higher voltage on their corresponding storage elements than memory cells 110 to effectively write data to the weak memory cells 112. Therefore, when write assist circuits 106 are activated, each write assist circuit 106 may selectively increase the voltage provided by its corresponding write driver circuit 104. Write assist circuits 106 may apply negative voltage write assist and positive voltage write assist to increase the voltage difference across weak memory cells 112 when selected for a write operation.

[0051] The negative voltage write assist operation involves applying a temporary negative voltage to at least one of the bit lines during a write operation (e.g., reducing a voltage that was originally intended to be a ground voltage), thereby effectively increasing the total voltage potential across the weak memory cell 112 to compensate for its operating characteristics. The positive voltage write assist operation includes boosting a positive voltage to at least one bit line during a write operation, thereby increasing the voltage potential across the weak memory cell 112. To implement these operations, the write assist circuit 106 may include one or more boost circuits, charge pump circuits, or other circuits to increase or decrease the voltage of one or more bit lines (e.g., bit line BLC, bit line !BLC, etc.).

[0052] Each of the memory blocks 101A-101N is shown as including a corresponding write assist enabling circuit 102A-102N (sometimes generally referred to as a write assist enabling circuit 102). The write assist enabling circuit 102 may include logic (e.g., transistors, logic gates, latches, flip-flops, registers, etc.) that enables the write assist circuit 106 to be selectively activated or deactivated based on an input signal from the write assist configuration circuit 120. For example, when the write assist enabling circuit 102 receives a programming signal from the write assist configuration circuit 120 indicating that the memory block 101 includes a defective memory cell (here shown as the weak memory cell 112 in the second column), the write assist enabling circuit 102 may generate a signal that selectively activates the write assist circuit 106 of the corresponding memory block 101.

[0053] In some embodiments, the write assist enabling circuit 102 may be part of a shift register (e.g., a flip-flop chain). For example, the write assist enabling circuit 102 of each memory block may provide an output to the next write assist enabling circuit 102 of the next memory block 101 in the memory array. The circuit may be configured by repeatedly shifting configuration data through each of the write assist enabling circuits 102 in the memory circuit 100. The configuration data may indicate which write assist enabling circuits 102 will enable corresponding write assist circuits 106 of the memory circuit 100 during a write operation and which write assist circuits 106 will remain deactivated during a write operation. In this example, write assist enable circuit 102A may be used to activate write assist circuit 106A via configuration data because memory block 101A includes weak memory cell 112, and write assist enable circuit 102N may be received to deactivate write assist circuit 106N because memory block 101N is shown as not including any defective memory cells.

[0054] The configuration data of the write assist enabling circuit 102 may be stored in the write assist configuration circuit 120, which may include any suitable programmable storage device for configuring the memory circuit 100. In some embodiments, the configuration data stored in the write assist configuration circuit 120 may be provided to each of the write assist enabling circuits 102 (e.g., the configuration data is shifted through each of the write assist enabling circuits 102) after a reset, power-on, or another predetermined event. For example, upon receiving a resent signal, the write assist enabling circuits 102 of the memory circuit 100 may be repeatedly shifted through the configuration data until all of the write assist enabling circuits 102 are configured.

[0055] The write assist configuration circuit 120 may include any type of storage device suitable for storing configuration data for each of the write assist enabling circuits 102. In this example, the configuration data indicates whether the write assist circuit 106 of a particular memory block 101 is to be activated when a write operation is performed on the memory cells 110 included in the memory block 101. Figure 2 , Figure 3 and Figure 4 Additional embodiments of configuration data that may be stored in the write assist configuration circuit 120 are described. The write assist configuration circuit 120 may include any suitable type of programmable memory, including electrical fuse memory, flash memory, or the like. The write assist configuration circuit 120 may include logic for configuring each of the write assist enabling circuits 102, such as by repeatedly shifting data through each of the write assist enabling circuits 102 until all of the write assist enabling circuits 102 are configured.

[0056] The write assist configuration circuit 120 may include or may communicate with one or more test circuits such as a BIST circuit or a built-in self-test and repair (BISTR) circuit that operates to test the operating characteristics of the memory circuit 100. In some embodiments, the write assist configuration circuit 120 may communicate with an external test circuit that performs similar operations as the BIST or BISTR circuit. The results from such test circuits may be stored in a programmable memory of the write assist configuration circuit 120 as configuration data for the write assist enabling circuit 102. The test circuit may include a test pattern generator, a response analyzer, and control logic that enables the test circuit to execute a series of memory arrays to identify any defective memory cells (e.g., weak memory cells 112).

[0057] A testing process may be performed as part of the manufacturing process to identify weak memory cells 112. Corresponding configuration data may then be generated that identifies which memory cells are defective or have normal operating characteristics. Figure 2 , Figure 3 and Figure 4 As described in further detail, the configuration data may include row addresses and / or column addresses of identified weak memory cells 112 in the memory circuit 100. In some embodiments, an indication is provided as to whether each memory block 101 includes at least one weak memory cell 112. Figure 1 In the example shown in , such an indication may be provided to configure each write assist enabling circuit 102 to selectively enable the write assist circuit 106 to write to any identified weak memory cells 112 .

[0058] In some embodiments, the write assist configuration circuit 120 may dynamically update the configuration data stored in its programmable memory. For example, the write assist configuration circuit 120 may utilize a BIST or BISTR circuit to periodically test the memory cells 110 of the memory circuit 100 to determine whether any of the memory cells 110 have become weak memory cells 112. Once any additional weak memory cells 112 are identified, the write assist configuration circuit 120 may update the configuration data with the identifier, column address, and / or row address of the memory block 101 of the weak memory cell 112, which configuration data may be used to configure the write assist enabling circuit 102 as described herein. The write assist configuration circuit 120 provides the configuration signal to the write assist enabling circuit 102 as a "WA shift" signal, which may be propagated through each of the write assist enabling circuits 102 via at least one shift register included in the write assist enabling circuit 102. Each storage flip-flop in the shift register may be included in a respective write assist enable circuit 102 and may include an indication identifying whether the corresponding memory block 101 includes at least one weak memory cell 112. Figure 2 , Figure 3 and Figure 4 Additional embodiments for selectively activating write assist circuitry are described.

[0059] refer to Figure 2 , illustrates a schematic block diagram of a memory circuit 200 that implements selective activation of a write assist circuit (e.g., write assist circuits 206A-206N, sometimes generally referred to as write assist circuit 206) according to some embodiments. As shown, the memory circuit 200 includes an array of memory cells 210 that can store digital data and can include Figure 1 The memory circuit 200 may include any structure and functionality of the memory cell 110. Each of the components shown in the memory circuit 200 may receive power from one or more voltage sources. The memory circuit 200 may include one or more logic gates and subcircuits, each of which may be composed of one or more logic gates. A logic gate is an electronic device that performs a logical operation on one or more input signals to produce a single output signal.

[0060] Various embodiments of the circuits and logic gates implementing the memory circuit 200 may include various transistors. The transistors described herein may be of a particular type (n-type or p-type), but the embodiments are not limited thereto. The transistors may be any suitable type of transistor, including but not limited to MOSFETs, CMOS transistors, PMOS, NMOS, BJTs, high voltage transistors, high frequency transistors, PFETs / NFETs, FinFETs, planar MOS transistors with raised source / drain, nanosheet FETs, nanowire FETs, or the like.

[0061] As shown, the memory circuit 200 includes memory blocks 201A-201N (sometimes generally referred to as memory blocks 201), each of which includes a memory cell 210. Each of the memory blocks 201 and the memory cells 210 may be similar to the combination of Figure 1 The memory block 101 and the memory unit 110 described herein each include a combination of Figure 1 Any structure and functionality of the memory block 101 and memory cell 110 described herein. As described herein, the memory cell 210 may be manufactured with one or more defects due to the nature of the manufacturing process used to create the memory cell. Such defects may cause the memory cell to become a "weak memory cell" that has difficulty maintaining or maintaining a desired (e.g., writing) state during a write operation due to various factors (such as process variations, degradation over time, or other environmental conditions). Memory cells 210 with such defects may be referred to herein as weak memory cells 212.

[0062] As described herein, if multiple columns of memory cells 210 (or weak memory cells 212) are included in memory block 201, memory block 201 may include corresponding multiplexer circuits. In this example, memory blocks 201A-201N each include two memory columns, and memory blocks 201A-201N include 1:2 multiplexer circuits 208A-208N (sometimes generally referred to as multiplexer circuits 208). Multiplexer circuits 208 may be similar to Figure 1 The multiplexer circuit 108 includes Figure 1 Multiplexer circuit 208 may select between each column in memory block 201 based on a column address (shown here as Col ADDR) that may be received from memory control circuitry.

[0063] As shown, the memory cells 210 (and weak memory cells 212) are arranged in one or more rows, each of which can be selected using a corresponding row address (shown here as Row ADDR, ranging from 0 to R rows, i.e., Row 0ADDR to RowR ADDR). Each row address can be provided by a memory control circuit of a memory block 201 of the memory, which can select a corresponding row and column of column address and row address signals. The memory control circuit can include any type of control circuit that provides signals for coordinating read or write operations through the circuit system of the memory circuit 200. For example, the memory control circuit can provide a write enable signal (shown here as "Write") that activates various components of a write enable driver. For example, the write enable signal can activate the corresponding write driver circuit 204, the write assist circuit 206 and / or the write assist enable circuit 202 of the memory block 201.

[0064] Each memory block 201 is shown as including one of write driver circuits 204A-204N (sometimes referred to generally as write driver circuits 204). Write driver circuits 204 may be similar to Figure 1 The write driver circuit 104 includes Figure 1 Any structure and functionality of the write driver circuit 104 of the present invention. For example, as described herein, the write driver circuit 204 can drive the bit lines (e.g., bit lines BLC and !BLC) corresponding to the addressed memory cell 210 to perform a write operation to store input data (e.g., Data 0) in the addressed memory cell 210 (or weak memory cell 212). As shown, the write driver circuits 204A-204N are integrated with corresponding write assist circuits 206A-206N (sometimes generally referred to as "write assist circuits 206"), and the write assist circuits 206A-206N may include Figure 1 For example, the write assist circuit 206 can perform negative voltage write assist and positive voltage write assist operations to increase the voltage on the selected weak memory cell 212.

[0065] Each of the memory blocks 201A-201N is shown as including a corresponding write assist enabling circuit 202A-202N (sometimes generally referred to as a write assist enabling circuit 202). The write assist enabling circuit 202 may include logic (e.g., transistors, logic gates, latches, flip-flops, registers, etc.) that enables the write assist circuit 206 to be selectively activated or deactivated based on an input signal from the write assist configuration circuit 220.

[0066] exist Figure 2In the example shown in , the write assist enabling circuit 202 may perform a matching operation between one or more stored column addresses and an input column address (e.g., Col ADDR) of a write operation. The stored column address with which the input column address is compared may be a column of the corresponding memory block 201 that has been determined to include at least one defective memory cell 212. The comparison may be performed via one or more logic gates or comparison circuits corresponding to the write assist enabling circuit 202. Upon detecting a match between the input column address and the column address of the column including the weak memory cell 212, the write assist enabling circuit 202 may selectively activate the write assist circuit 206 to compensate for the operating characteristics of the weak memory cell 212. In this example, the right-hand column of the memory block 201A includes the weak memory cell 212.

[0067] When a write operation addresses the rightmost column of the memory block 201A for a write operation, the write assist enabling circuit 206A detects a match between the input column address and the address of the rightmost column and generates a signal to activate the write assist circuit 206A. The write assist circuit 206A can then generate an increased voltage potential (e.g., relative to a normal write operation) across the bit lines BLC and !BLC. The increased voltage potential is provided via the second output terminal 214 of the multiplexer circuit 208A. The increased voltage enables a successful write operation at the weak memory cell 212. In this example, the write assist enabling circuit 202 selectively activates the write assist circuit 206 only when the corresponding column of the memory block 201 containing the weak memory cell is written. When the column of the same memory block 201 that does not contain the weak memory cell 212 is written, the write assist circuit 206 is disabled and the normal voltage is applied.

[0068] As described herein, the configuration data of the write assist enabling circuit 202 may be stored in the write assist configuration circuit 220. The write assist configuration circuit 220 may be similar to Figure 1 The write assist configuration circuit 120 includes Figure 1 In this example, the configuration data provided to one or more registers of the write assist enabling circuits 202A-202N (e.g., via shifting thereof) may include the column address of each of any columns in the memory blocks 201A-201N that are determined (e.g., via the testing process described herein) to include at least one weak memory cell 212. The configuration data may be provided to the write assist enabling circuit 202 in response to a reset, power-on, or configuration signal. In combination Figure 3 and Figure 4 Additional implementations are described for selectively activating a write assist circuit based on a row address (eg, row addresses Row 0ADDR to Row RADDR).

[0069] refer to Figure 3 , illustrates a schematic block diagram of a memory circuit 300 that implements selective activation of write assist circuits (e.g., write assist circuits 306A-306N) according to a specified row address (e.g., row addresses Row 0 ADDR to Row R ADDR) according to some embodiments. The memory circuit 300 may be similar to Figure 2 The memory circuit 200 or Figure 1 The memory circuit 100 includes Figure 2 The memory circuit 200 or Figure 1 As shown, the memory circuit 300 includes an array of memory cells 310 that can store digital data and can include Figure 1 1. The memory circuit 300 may include any structure and functionality of the memory cell 110. Each of the components shown in the memory circuit 300 may receive power from one or more voltage sources. The memory circuit 300 may include one or more logic gates and subcircuits, each of which may be composed of one or more logic gates. A logic gate is an electronic device that performs a logical operation on one or more input signals to produce a single output signal.

[0070] Various embodiments of the circuits and logic gates implementing the memory circuit 300 may include various transistors. The transistors described herein may be of a particular type (n-type or p-type), but the embodiments are not limited thereto. The transistors may be any suitable type of transistor, including but not limited to MOSFETs, CMOS transistors, PMOS, NMOS, BJTs, high voltage transistors, high frequency transistors, PFETs / NFETs, FinFETs, planar MOS transistors with raised source / drain, nanosheet FETs, nanowire FETs, or the like.

[0071] As shown, the memory circuit 300 includes memory blocks 301A-301N (sometimes generally referred to as memory blocks 301), each of which includes a memory cell 310. Each of the memory blocks 301 and the memory cells 310 may be similar to the combination of Figure 1 The memory block 101 and the memory unit 110 described herein each include a combination of Figure 1Any structure and functionality of the memory block 101 and memory cell 110 described herein. As described herein, the memory cell 310 may be manufactured with one or more defects due to the nature of the manufacturing process used to create the memory cell. Such defects may cause the memory cell to become a "weak memory cell" that has difficulty maintaining or maintaining a desired (e.g., writing) state during a write operation due to various factors (such as process variations, degradation over time, or other environmental conditions). A memory cell 310 with such defects may be referred to herein as a weak memory cell 312.

[0072] As described herein, if multiple columns of memory cells 310 (or weak memory cells 312) are included in memory block 301, memory block 301 may include corresponding multiplexer circuits. In this example, memory blocks 301A-301N each include two memory columns, and memory blocks 301A-301N include 1:2 multiplexer circuits 308A-308N (sometimes generally referred to as multiplexer circuits 308). Multiplexer circuits 308 may be similar to Figure 1 The multiplexer circuit 108 includes Figure 1 Multiplexer circuit 308 may select between each column in memory block 301 based on a column address (shown here as Col ADDR) that may be received from memory control circuitry.

[0073] As shown, the memory cells 310 (and weak memory cells 312) are arranged in one or more rows, each of which can be selected using a corresponding row address (shown here as Row ADDR, ranging from 0 to R rows, i.e., Row 0ADDR to RowR ADDR). Each row address can be provided by a memory control circuit of a memory block 301 of the memory, which can select a corresponding row and column of column address and row address signals. The memory control circuit can include any type of control circuit that provides signals for coordinating read or write operations through the circuit system of the memory circuit 300. For example, the memory control circuit can provide a write enable signal (shown here as "Write") that activates various components of a write enable driver. For example, the write enable signal can activate the corresponding write driver circuit 304, the write assist circuit 306 and / or the write assist enable circuit 302 of the memory block 301.

[0074] Each memory block 301 is shown as including one of write driver circuits 304A-304N (sometimes referred to generally as write driver circuits 304). Write driver circuits 304 may be similar to Figure 1 The write driver circuit 104 includes Figure 1Any structure and functionality of the write driver circuit 104 of the present invention. For example, as described herein, the write driver circuit 304 can drive the bit lines (e.g., bit lines BLC and !BLC) corresponding to the addressed memory cell 310 to perform a write operation to store input data (e.g., Data 0) in the addressed memory cell 310 (or weak memory cell 312). As shown, the write driver circuits 304A-304N are integrated with corresponding write assist circuits 306A-306N (sometimes generally referred to as "write assist circuits 306"), and the write assist circuits 306A-306N may include Figure 1 For example, the write assist circuit 306 can perform negative voltage write assist and positive voltage write assist operations to increase the voltage on the selected weak memory cell 312.

[0075] Each of the memory blocks 301A-301N is shown as including a corresponding write assist enabling circuit 302A-302N (sometimes generally referred to as a write assist enabling circuit 302). The write assist enabling circuit 302 may include Figure 1 The write assist enabling circuit 302 may include logic (e.g., transistors, logic gates, latches, flip-flops, registers, etc.) that enables the write assist circuit 306 to be selectively activated or deactivated based on an input signal from the write assist configuration circuit 320.

[0076] exist Figure 3 In the example shown in FIG. 3 , the write assist enabling circuit 302 can enable the corresponding write assist circuit 306 in response to the signal from the address matching circuit 314. For example, in combination with Figure 1 As described herein, each write assist enabling circuit 302 may include a register or other storage device that stores an indication of whether the corresponding memory block 301 includes at least one weak memory cell 312. As described herein, the write assist configuration circuit 320 (which may be similar to Figure 1 The write assist configuration circuit 120 includes Figure 1 The configuration data may be provided to the write assist enabling circuit 302 as a “WA shift” signal, which may be propagated through each of the write assist enabling circuits 302 via at least one shift register included in the write assist enabling circuit 302. Each storage flip-flop in the shift register may be included in a respective write assist enabling circuit 302 and may include an indication identifying whether the corresponding memory block 301 includes at least one weak memory cell 312.

[0077] Additionally, the write assist configuration circuit 320 may provide data to the row address matching circuit 314. The row address matching circuit 314 may provide an activation signal to the write assist enabling circuit 302 in response to detecting a match between an input row address of the memory circuit 300 and a stored row address identified as including a weak memory cell 312. For example, in addition to providing an indication of whether each memory block 301 includes at least one weak memory cell 312, the write assist configuration circuit 320 may additionally provide the address of the row in which the weak memory cell 312 has been detected. In some embodiments, the row address may be determined based on the testing techniques described herein. The write assist configuration circuit 320 may provide the detected row address to the row address matching circuit 314, for example, in response to a reset, power-on, or in response to a configuration signal. The write assist configuration circuit 320 may therefore provide configuration data to both the address matching circuit and the write assist enabling circuit 302.

[0078] The row address matching circuit 314 may include logic gates, transistors, or any other device or circuit that can compare an input row address for a write operation with a stored row address provided by the write assist configuration circuit 320. In some implementations, the row address matching circuit 314 may include one or more storage devices, registers, or memory devices that store the row address provided by the write assist configuration circuit 320. The comparison performed by the row address matching circuit 314 may generate a signal indicating whether the input row address matches the stored (or provided) row address (e.g., Row 1 ADDR in this example) of the row that includes the weak memory cell 312.

[0079] If the row address matching circuit 314 detects a match, the row address matching circuit 314 may provide an activation signal to the write assist enabling circuit 302. If during a write operation, the write assist enabling circuit 302 has also received an indication (e.g., via a WA Shift signal) that its corresponding memory block 301 includes at least one weak memory cell 312, the write assist enabling circuit 302 may activate the write assist circuit 306 integrated with the corresponding write driver circuit 304 to compensate for the operating characteristics of the weak memory cell 312. In this example, as shown, if a write operation occurs to write Row 1 (e.g., as specified by the write address) and memory block 301A, the write enable assist circuit 302A may provide a signal to activate the write assist circuit 306A integrated with the write driver circuit 304A. This method selectively activates the write assist circuit 306 only when the row and memory block 301 to be written to include at least one weak memory cell 312. For example, since the memory block 301N is not shown as including any weak memory cells, the write assist enabling circuit 302 will not activate the write assist circuit 306, thereby saving power when performing a write operation on the memory block 301N. Figure 4 Additional embodiments are described in which both row addresses and column addresses are used to selectively activate write assist circuitry.

[0080] refer to Figure 4 , illustrates a schematic block diagram of a memory circuit 400 that implements selective activation of write assist circuits 406A-406N (sometimes generally referred to as write assist circuits 406) according to some embodiments based on a specified row address (e.g., one of row addresses Row 0 ADDR to Row R ADDR) and a specified column address (e.g., Col ADDR). The memory circuit 400 may be similar to Figure 3 The memory circuit 300, Figure 2 The memory circuit 200 or Figure 1 The memory circuit 100 includes Figure 3 The memory circuit 300, Figure 2 The memory circuit 200 or Figure 1 As shown, the memory circuit 400 includes an array of memory cells 410 that can store digital data and can include Figure 1 1. The memory circuit 400 may include any structure and functionality of the memory cell 110. Each of the components shown in the memory circuit 400 may receive power from one or more voltage sources. The memory circuit 400 may include one or more logic gates and subcircuits, each of which may be composed of one or more logic gates. A logic gate is an electronic device that performs a logical operation on one or more input signals to produce a single output signal.

[0081] Various embodiments of the circuits and logic gates implementing memory circuit 400 may include various transistors. The transistors described herein may be of a particular type (n-type or p-type), but embodiments are not limited thereto. The transistors may be any suitable type of transistor, including but not limited to MOSFETs, CMOS transistors, PMOS, NMOS, BJTs, high voltage transistors, high frequency transistors, PFETs / NFETs, FinFETs, planar MOS transistors with raised source / drain, nanosheet FETs, nanowire FETs, or the like.

[0082] As shown, the memory circuit 400 includes memory blocks 401A-401N (sometimes generally referred to as memory blocks 401), each of which includes a memory cell 410. Each of the memory blocks 401 and the memory cells 410 may be similar to the combination of Figure 1 The memory block 101 and the memory unit 110 described herein each include a combination of Figure 1 Any structure and functionality of the memory block 101 and memory cell 110 described herein. As described herein, the memory cell 410 may be manufactured with one or more defects due to the nature of the manufacturing process used to create the memory cell. Such defects may cause the memory cell to become a "weak memory cell" that has difficulty maintaining or maintaining a desired (e.g., writing) state during a write operation due to various factors (such as process variations, degradation over time, or other environmental conditions). A memory cell 410 having such defects may be referred to herein as a weak memory cell 412.

[0083] As described herein, if multiple columns of memory cells 410 (or weak memory cells 412) are included in memory block 401, memory block 401 may include corresponding multiplexer circuits. In this example, memory blocks 401A-401N each include two memory columns, and memory blocks 401A-401N include 1:2 multiplexer circuits 408A-408N (sometimes generally referred to as multiplexer circuits 408). Multiplexer circuits 408 may be similar to Figure 1 The multiplexer circuit 108 includes Figure 1 Multiplexer circuit 408 may select between each column in memory block 401 based on a column address (shown here as Col ADDR) that may be received from memory control circuitry.

[0084] As shown, the memory cells 410 (and weak memory cells 412) are arranged in one or more rows, each of which can be selected using a corresponding row address (shown here as Row ADDR, ranging from 0 to R rows, i.e., Row 0ADDR to RowR ADDR). Each row address can be provided by a memory control circuit of a memory block 401 of the memory, which can select a corresponding row and column of column address and row address signals. The memory control circuit can include any type of control circuit that provides signals for coordinating read or write operations through the circuit system of the memory circuit 400. For example, the memory control circuit can provide a write enable signal (shown here as "Write") that activates various components of the write enable driver 404. For example, the write enable signal can activate the corresponding write driver circuit 404, the write assist circuit 406 and / or the write assist enable circuit 402 of the memory block 401.

[0085] As combined Figures 1 to 3 As described, each memory block 401 is shown as including one of write driver circuits 404A-404N (sometimes generally referred to as write driver circuits 404). Write driver circuits 404 may be similar to Figure 1 The write driver circuit 104 includes Figure 1 Any structure and functionality of the write driver circuit 104 of the present invention. For example, as described herein, the write driver circuit 404 can drive the bit lines (e.g., bit lines BLC and !BLC) corresponding to the addressed memory cell 410 to perform a write operation to store input data (e.g., Data 0) in the addressed memory cell 410 (or weak memory cell 412). As shown, the write driver circuits 404A-404N are integrated with corresponding write assist circuits 406A-406N (sometimes generally referred to as "write assist circuits 406"), and the write assist circuits 406A-406N may include Figure 1 For example, as described herein, the write assist circuit 406 can perform negative voltage write assist and positive voltage write assist operations to increase the voltage on the selected weak memory cell 412.

[0086] Each of the memory blocks 401A-401N is shown as including a corresponding write assist enabling circuit 402A-402N (sometimes generally referred to as a write assist enabling circuit 402). The write assist enabling circuit 402 may include Figure 1The write assist enabling circuit 402 may include logic (e.g., transistors, logic gates, latches, flip-flops, registers, etc.) that enables the write assist circuit 406 to be selectively activated or deactivated based on an input signal from the write assist configuration circuit 420.

[0087] exist Figure 4 In the example shown in , the write assist enabling circuit 402 can enable the corresponding write assist circuit 406 in response to a signal from the address matching circuit 414 indicating a match between an input row address and an address of a row including at least one weak memory cell 412. In addition, the write assist enabling circuit 402 regulates activation of the corresponding write assist circuit 406 when matching an input column address (e.g., Col ADDR) with an identifier of at least one column in the memory block 401 including at least one weak memory cell 412. Thus, the write assist enabling circuit 402 can regulate activation of the write assist circuit 406 when writing to both the row and the column including the weak memory cell 412 based on the techniques described herein.

[0088] The write assist enable circuit 402 may include logic for performing a comparison operation between one or more stored column addresses and an input column address (e.g., Col ADDR) for a write operation. The stored column address with which the input column address is compared may be a column of the corresponding memory block 401 that has been determined to include at least one defective memory cell 412. The comparison may be performed via one or more logic gates or comparison circuits corresponding to the write assist enable circuit 402.

[0089] As combined Figures 1 to 3 As described above, the stored column address may be provided as part of the configuration data of the write assist enabling circuit 402. The configuration data of the write assist enabling circuit 402 may be stored in the write assist configuration circuit 420, which may be similar to Figure 2 The write assist configuration circuit 220 includes Figure 2 In this example, the configuration data provided to one or more registers of the write assist enabling circuits 402A-402N (e.g., via shifting thereof) may include the column address of each of any columns in the memory blocks 401A-401N that are determined (e.g., via the testing process described herein) to include at least one weak memory cell 412. The configuration data may be provided to the write assist enabling circuit 402 in response to a reset, power-on, or configuration signal.

[0090] Additionally, the write assist enabling circuit 402 may further adjust the activation of the write assist circuit 406 based on a signal from the address matching circuit 414. For example, the write assist configuration circuit 420 may provide data to the row address matching circuit 414. The row address matching circuit 414 may include logic gates, transistors, or any other device or circuit that can compare an input row address of a write operation with a stored row address provided by the write assist configuration circuit 420. The row address matching circuit 414 may include Figure 3 Any structure of the row address matching circuit 314 and realize Figure 3 any functionality of the row address matching circuit 314.

[0091] The row address matching circuit 414 may provide an activation signal to the write assist enabling circuit 402 in response to detecting a match between an input row address of the memory circuit 400 and a stored row address identified as including a weak memory cell 412. The write assist configuration circuit 420 may provide an address of a row determined to include at least one weak memory cell 412 (e.g., Row 1 ADDR as shown) to the row address matching circuit 414, for example, in response to a reset, power-up, or in response to a configuration signal. The write assist configuration circuit 420 may thus provide configuration data to both the address matching circuit and the write assist enabling circuit 402. When the write assist enabling circuit 402 selectively activates the write assist circuit 406, the increased voltage generated by the write assist circuit 406 may be provided via an output terminal of the multiplexer 404, which corresponds to a respective Col ADDR for a write operation. For example, as shown, if a write operation occurs on Row 1 ADDR and the second row of memory block 401A, write assist enable circuit 402A activates write assist circuit 406A, which provides a corresponding output via second output terminal 416 of multiplexer 404A.

[0092] Figure 5 Description of some embodiments of the present disclosure for respectively operating Figures 1 to 4 1. A flow chart of an example method 500 for the disclosed memory circuits 100, 200, 300, and 400. The method 500 may be used to operate a memory circuit or device (e.g., the memory circuit 100, the memory circuit 200, the memory circuit 300, the memory circuit 400, etc.) to selectively activate a write assist circuit. For example, at least some of the operations described in the method 500 may be performed using Figures 1 to 4 It should be noted that method 500 is merely an example and is not intended to limit the disclosed embodiments. Therefore, it should be understood that the method 500 may be used in Figure 5 Additional operations are provided before, during, and after method 500, and some other operations may only be briefly described herein.

[0093] Briefly, method 500 begins at operation 502 by providing an indication (e.g., via a WA Shift signal) that a memory cell (e.g., a weak memory cell 112) of a memory array has a predetermined operating characteristic (e.g., as opposed to a normally operating memory cell, as a weak memory cell). Method 500 proceeds to operation 504 by detecting a write operation (e.g., via a "Write" signal) of a row or column (e.g., identified by Row ADDR or Col ADDR as described herein) of the memory array that includes the memory cell having the predetermined operating characteristic. Method 500 ends at operation 506 by selectively activating a write assist circuit during a write operation to compensate for the predetermined operating characteristic of the memory cell.

[0094] Referring to operation 502, an indication is provided (e.g., via a WAShift signal) that a memory cell of a memory array (e.g., a weak memory cell 112) has a predetermined operating characteristic (e.g., as opposed to a normally operating memory cell, as a weak memory cell). The indication may be generated by one or more test circuits, which may be included in one or more write assist configuration circuits (e.g., write assist configuration circuits 120, 220, 320, or 420, etc.). The indication may include the row and / or column address of any memory cell identified as a weak memory cell. The indication may include an indication of each memory block of a memory array that includes at least one weak memory cell. The indication may be stored in one or more storage devices, such as a programmable memory (e.g., flash memory, electric fuse memory, etc.). A test circuit, such as a BIST or BISTR circuit, or an external test circuit may be used to identify the weak memory cell.

[0095] Referring to operation 504, a write operation is detected (e.g., via a "Write" signal) to a row or column (e.g., identified by Row ADDR or Col ADDR as described herein) of a memory array that includes memory cells having predetermined operating characteristics. The write operation may be detected as corresponding to a memory block, column, and / or row that includes at least one weak memory cell. For example, a row address matching circuit (e.g., row address matching circuit 314, row address matching circuit 414) may detect a write operation to a row that includes at least one weak memory cell. A write assist enabling circuit may detect a write operation to a memory block and / or column that includes at least one weak memory cell.

[0096] Referring to operation 506, write assist circuits (e.g., write assist circuit 106, write assist circuit 206, write assist circuit 306, and write assist circuit 406, etc.) are selectively activated during a write operation to compensate for predetermined operating characteristics of the memory cells. For example, activation of the write assist circuits of a memory block may be conditioned upon detection of a write operation to a memory block, row, and / or column that includes at least one weak memory cell. The write assist circuits may generate an increased voltage across the weak memory cell during a write operation to compensate for its operating characteristics (e.g., a manufacturing defect that affects its ability to maintain its state during a write operation).

[0097] In one aspect of the disclosed embodiment, a semiconductor device is disclosed. The semiconductor device includes a memory array, the memory array includes a first memory cell and a second memory cell, the second memory cell having an operating characteristic different from the operating characteristic of the first memory cell. The semiconductor device includes a first write circuit for writing first data into the first memory cell. The semiconductor device includes a second write circuit for writing second data into the second memory cell. The second write circuit is selectively used to compensate for the operating characteristic of the second memory cell.

[0098] In some embodiments, the first memory unit and the second memory unit each comprise a respective bit cell in a memory array.

[0099] In some embodiments, the first write circuit operates at a first voltage to write first data to the first memory cell, and the second write circuit operates at a second voltage to write second data to the second memory cell.

[0100] In some embodiments, the semiconductor device further includes: a write assist enabling circuit for enabling the second write circuit to selectively operate using a second voltage.

[0101] In some embodiments, the write assist enabling circuit includes a latch that selectively enables the second write circuit to operate using the second voltage.

[0102] In some embodiments, the latch causes the second write circuit to operate using a second voltage based on a column address of the second memory cell.

[0103] In some embodiments, the semiconductor device further includes a register storing control data, the control data indicating that the first write circuit is to operate at a first voltage and the second write circuit is to operate at a second voltage.

[0104] In some embodiments, the semiconductor device further comprises: an address matching circuit for generating a write assist enable signal when receiving a write address corresponding to the second memory cell, wherein the second write circuit is for compensating for an operating characteristic of the second memory cell based on the write assist enable signal.

[0105] In some embodiments, the semiconductor device further includes a multiplexer circuit configured to receive a write signal from the second write circuit and provide the write signal to one of the first column or the second column, wherein the first column includes the second memory cell.

[0106] In another aspect of the disclosed embodiment, a memory circuit is disclosed. The memory circuit includes a write driver device for writing input data to one of a first column or a second column of a memory array. The memory circuit includes a write assist circuit for causing the write driver device to selectively operate at one of a first voltage or a second voltage. The memory circuit includes a write assist enabling circuit for activating the write assist circuit based on an indication that the first column or the second column includes a memory cell with a defect.

[0107] In some embodiments, the memory circuit further includes a multiplexer device for receiving a write signal from the write driver device and providing the write signal to one of a first column or a second column of the memory array, the first column or the second column being selected based on a column address signal.

[0108] In some embodiments, the write assist enabling circuit further activates the write assist circuit based on the column address signal matching the column address of the memory cell having the defect.

[0109] In some embodiments, wherein the defective memory cell is defined within a first row of a memory array, the memory circuit further includes a row address matching circuit that generates a row enable signal upon detecting a match between an input row address and an address of the first row, and the write assist enable circuit is used to further activate the write assist circuit based on the row enable signal.

[0110] In some embodiments, the memory circuit further includes a multiplexer device that receives the write signal from the write driver device and provides the write signal to one of a first column or a second column of the memory array, the first column or the second column being selected based on a column address signal.

[0111] In some embodiments, the write assist enabling circuit further activates the write assist circuit based on the column address signal matching the column address of the memory cell having the defect.

[0112] In some embodiments, the write assist circuit is further configured to enable the write driver to generate a boosted write voltage for writing into the defective memory cell.

[0113] In some embodiments, the write assist circuit further enables the write driver to lower a ground voltage for writing to the memory cell having the defect.

[0114] Another aspect of the disclosed embodiments is directed to a method. The method includes providing an indication that a memory cell of a memory array has a predetermined operating characteristic. The method includes detecting a write operation of a row or column of the memory array including the memory cell having the predetermined operating characteristic. The method includes selectively activating a write assist circuit during the write operation to compensate for the predetermined operating characteristic of the memory cell.

[0115] In some embodiments, the step of detecting a write operation includes the step of comparing an input column address of the write operation with a column address of the memory cell having the predetermined operating characteristic.

[0116] In some embodiments, the step of detecting a write operation includes the step of comparing an input row address of the write operation with row addresses of memory cells having predetermined operating characteristics.

[0117] As used herein, the terms "about" and "approximately" generally mean plus or minus 10% of the specified value. For example, about 0.5 would include 0.45 and 0.55, about 10 would include 9 to 11, and about 1000 would include 900 to 1100.

[0118] The foregoing summarizes the features of several embodiments so that those skilled in the art may better understand the various aspects of the disclosed embodiments. Those skilled in the art will appreciate that they may readily use the disclosed embodiments as a basis for designing or modifying other processes and structures for achieving the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art will also appreciate that such equivalent constructions do not depart from the spirit and scope of the disclosed embodiments, and that various changes, substitutions, and modifications may be made herein without departing from the spirit and scope of the disclosed embodiments.

Claims

1. A semiconductor device, characterized in that: include: A memory array includes a first memory cell and a second memory cell, the second memory cell having an operating characteristic different from an operating characteristic of the first memory cell; a first writing circuit, used for writing first data into the first memory unit; and A second write circuit is used to write second data into the second memory cell, wherein the second write circuit is selectively used to compensate for the operating characteristic of the second memory cell.

2. The semiconductor device according to claim 1, wherein The first write circuit is used to operate at a first voltage to write the first data into the first memory cell, and the second write circuit is used to operate at a second voltage to write the second data into the second memory cell.

3. The semiconductor device according to claim 2, wherein: Further including: a write assist enabling circuit, for enabling the second write circuit to selectively operate using the second voltage, The write assist enabling circuit includes a latch, and the latch is used to selectively enable the second write circuit to operate using the second voltage. The latch enables the second write circuit to operate using the second voltage based on a column address of the second memory cell.

4. The semiconductor device according to claim 2, wherein: Further included is a register storing control data indicating that the first write circuit is to operate at the first voltage and the second write circuit is to operate at the second voltage.

5. The semiconductor device according to claim 1, wherein Further including: An address matching circuit is used to generate a write assist enable signal when receiving a write address corresponding to the second memory unit, wherein the second write circuit is used to compensate the operating characteristic of the second memory unit based on the write assist enable signal.

6. A memory circuit, characterized in that: include: a write driver device for writing input data into one of a first column or a second column of a memory array; a write assist circuit for causing the write driver device to selectively operate at one of a first voltage or a second voltage; and A write assist enabling circuit is configured to activate the write assist circuit based on an indication that the first row or the second row includes a memory cell having a defect.

7. The memory circuit according to claim 6, wherein: Further including: a multiplexer device for receiving a write signal from the write driver device and providing the write signal to one of the first column or the second column of the memory array, the first column or the second column being selected based on a column address signal, The write assist enabling circuit is used to activate the write assist circuit based on the column address signal matching a column address of the memory cell having the defect.

8. The memory circuit according to claim 6, wherein: The memory cell having the defect is defined in a first row of the memory array, and the memory circuit further comprises: a row address matching circuit for generating a row enable signal when a match between an input row address and an address of the first row is detected, and the write assist enable circuit for further activating the write assist circuit based on the row enable signal; and a multiplexer device for receiving a write signal from the write driver device and providing the write signal to one of the first column or the second column of the memory array, the first column or the second column being selected based on a column address signal, The write assist enabling circuit is used to activate the write assist circuit based on the column address signal matching a column address of the memory cell having the defect.

9. A method for operating a memory, characterized in that: The following steps are involved: providing an indication that a memory cell of a memory array has a predetermined operating characteristic; detecting a write operation of a row or column of the memory array including the memory cells having the predetermined operating characteristic; and A write assist circuit is selectively activated during the write operation to compensate for the predetermined operating characteristic of the memory cell.

10. The method according to claim 9, characterized in that The step of detecting the write operation includes the following steps: comparing an input column address of the write operation with a column address of the memory cell having the predetermined operation characteristic.

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