Double-node flip self-recovery SRAM (Static Random Access Memory) unit based on multi-input inverter and integrated circuit

Abstract

The invention discloses a double-node flip self-recovery SRAM (Static Random Access Memory) unit based on multiple input inverters, which comprises five transmission tubes and a storage module with a symmetrical structure, and the storage module consists of nine multiple input inverters. Comprising a first multi-input phase inverter INV1, a second multi-input phase inverter INV2, a third multi-input phase inverter INV3, a fourth multi-input phase inverter INV4, a fifth multi-input phase inverter INV5, a sixth multi-input phase inverter INV6, a seventh multi-input phase inverter INV7, an eighth multi-input phase inverter INV8 and a ninth multi-input phase inverter INV9. And the five transmission tubes comprise a first transmission tube N13, a second transmission tube N14, a third transmission tube N15, a fourth transmission tube N16 and a fifth transmission tube N17. According to the SRAM unit, the original storage value can be recovered from any single-node overturning and any pair of double-node overturning, and meanwhile, more access tubes can enable the SRAM unit to have higher read-write access speed.

Description

Technical Field

[0001] The present invention relates to the technical field of nano integrated circuit anti-soft error reinforcement lock, and in particular to a dual-node flip self-recovery SRAM unit based on a multi-input inverter and an integrated circuit. Background Art

[0002] With the continuous advancement of semiconductor technology, the size of integrated circuits has gradually decreased. As an important storage component, static random access memory (SRAM) has become increasingly sensitive to radiation environments. The most common manifestations of the impact of high-energy particles such as protons, neutrons, and heavy ions on SRAM cells in radiation environments are single event upsets (SEU) and double-node upsets (DNU). Single event upsets refer to when high-energy particles hit the sensitive area of ​​the SRAM cell, the ionization effect produced will cause an instantaneous change in the node voltage, thereby causing the flip of the storage value. With the continuous reduction of CMOS technology, the distance between nodes is reduced, and the charge sharing effect becomes more significant, which makes the impact of a single particle likely to affect multiple nodes at the same time, resulting in the occurrence of DNU. This will cause the storage value of one or two storage nodes inside the memory to flip, thereby causing potential reliability problems for integrated circuits and systems. Therefore, it is imperative to study the radiation hardening design for SEU and DNU. Under the above research background, the present invention further studies the structure of the storage unit.

[0003] In order to improve the reliability of SRAM cells in radiation environments, researchers have proposed a variety of radiation hardening technologies, mainly including: System-level reinforcement: Methods such as error correction coding (ECC) improve the system's fault tolerance through complex encoding and decoding mechanisms. However, these methods often bring large area and power consumption overhead.

[0004] Layout-level hardening: By optimizing the circuit layout, increasing the physical distance between nodes, and reducing the possibility of charge sharing, this approach is effective but may increase complexity in the design and manufacturing process.

[0005] Circuit-level reinforcement: Redundancy design and feedback mechanism are used for storage circuits to enhance the fault tolerance of SRAM cells. For example, some designs increase the tolerance to SEU and DNU by adding redundant nodes and cross-coupling structures.

[0006] In recent years, many new radiation-resistant SRAM cells have been proposed. These designs usually sacrifice some performance indicators, such as read / write speed and power consumption, while improving radiation resistance. For example, patent number: CN118262760A discloses a single-particle double flip-resistant SRAM cell based on six-column input split inverters. Although it is fully self-recoverable from any single node flip, only some double node pairs can recover from DNU. Summary of the invention

[0007] The present invention aims to solve one of the technical problems in the related art at least to a certain extent. To this end, one object of the present invention is to propose a dual-node flip self-recovery SRAM cell based on a multi-input inverter, with five transmission tubes and a symmetrical storage structure design. The SRAM cell can recover its original storage value from any single-node flip and any pair of dual-node flips, and at the same time, more access tubes can make it have a faster read and write access speed.

[0008] In the first aspect, the present invention proposes a dual-node flip self-recovery SRAM unit based on a multi-input inverter, comprising five transmission tubes and a storage module with a symmetrical structure, wherein the storage module comprises a first multi-input inverter INV1, a second multi-input inverter INV2, a third multi-input inverter INV3, a fourth multi-input inverter INV4, a fifth multi-input inverter INV5, a sixth multi-input inverter INV6, a seventh multi-input inverter INV7, an eighth multi-input inverter INV8, and a ninth multi-input inverter INV9, and each group of multi-input inverter storage nodes corresponds to: node I1, node I2, node I3, node I4, node I5, node I6, node I7, node I8 and node I9 respectively. The five transmission tubes include a first transmission tube N13, a second transmission tube N14, a third transmission tube N15, a fourth transmission tube N16, and a fifth transmission tube N17. The gates of the first transmission tube N13, the second transmission tube N14, the third transmission tube N15, the fourth transmission tube N16, and the fifth transmission tube N17 are all used as switches for reading and writing data of the SRAM unit, and the drains are connected to the bit lines to control the reading and writing of data. The source of the first transmission tube N13, the source of the second transmission tube N14, the source of the third transmission tube N15, the source of the fourth transmission tube N16, and the source of the fifth transmission tube N17 are respectively connected to the node I1, the node I2, the node I3, the node I4, and the node I9; The storage module internally forms a small loop. When the SRAM stores 0, the signal flows as follows: node I1→node I2→node I3→node I2→node I1; node I4→node I5→node I6→node I5→node I4; node I7→node I8→node I9→node I8→node I7; When the SRAM stores 1, the signal flow is: node I1→node I6→node I7→node I6→node I1; node I2→node I5→node I8→node I5→node I2; node I3→node I4→node I9→node I4→node I3.

[0009] Preferably, the signal output terminal of the first multi-input inverter INV1 is connected to the input terminal N2 of the second multi-input inverter INV2 and the input terminal P8 of the sixth multi-input inverter INV6 respectively; The signal output terminal of the second multi-input inverter INV2 is respectively connected to the input terminal P1 of the first multi-input inverter INV1, the input terminal P3 of the third multi-input inverter INV3 and the input terminal N6 of the fifth multi-input inverter INV5; The signal output terminal of the third multi-input inverter INV3 is connected to the input terminal N3 of the second multi-input inverter INV2 and the input terminal P4 of the fourth multi-input inverter INV4 respectively; The signal output terminal of the fourth multi-input inverter INV4 is respectively connected to the input terminal N4 of the third multi-input inverter INV3, the input terminal P6 of the fifth multi-input inverter INV5 and the input terminal N12 of the ninth multi-input inverter INV9; The signal output terminal of the fifth multi-input inverter INV5 is respectively connected to the input terminal P2 of the second multi-input inverter INV2, the input terminal N5 of the fourth multi-input inverter INV4, the input terminal N8 of the sixth multi-input inverter INV6 and the input terminal P11 of the eighth multi-input inverter INV8; The signal output terminal of the sixth multi-input inverter INV6 is respectively connected to the input terminal N1 of the first multi-input inverter INV1, the input terminal P7 of the fifth multi-input inverter INV5 and the input terminal N9 of the seventh multi-input inverter; The signal output terminal of the seventh multi-input inverter INV7 is connected to the input terminal P9 of the sixth multi-input inverter INV6 and the input terminal N10 of the eighth multi-input inverter INV8 respectively; The signal output terminal of the eighth multi-input inverter INV8 is respectively connected to the input terminal N7 of the fifth multi-input inverter INV5, the input terminal P10 of the seventh multi-input inverter INV7 and the input terminal P12 of the ninth multi-input inverter INV9; The signal output terminal of the ninth multi-input inverter INV9 is connected to the input terminal P5 of the fourth multi-input inverter INV4 and the input terminal N11 of the eighth multi-input inverter INV8 respectively.

[0010] Preferably, the storage module is bilaterally symmetrical with the storage node I5 of the fifth multi-input inverter INV5 as a symmetry axis.

[0011] Preferably, the first multi-input inverter INV1, the third multi-input inverter INV3, the seventh multi-input inverter INV7 and the ninth multi-input inverter INV9 have the same structure; The second multi-input inverter INV2 and the eighth multi-input inverter INV8 have the same structure; The fourth multi-input inverter INV4 and the sixth multi-input inverter INV6 have the same structure.

[0012] Preferably, the first multi-input inverter INV1, the third multi-input inverter INV3, the seventh multi-input inverter INV7 and the ninth multi-input inverter INV9 are all two-input inverters consisting of one NMOS tube and one PMOS tube; The second multi-input inverter INV2 and the eighth multi-input inverter INV8 are both three-input inverters consisting of two NMOS tubes and one PMOS tube; The fourth multi-input inverter INV4 and the sixth multi-input inverter INV6 are both three-input inverters consisting of two PMOS tubes and one NMOS tube; The fifth multi-input inverter INV5 is a four-input inverter composed of two NMOS tubes and two PMOS tubes.

[0013] Preferably, the first multi-input inverter INV1 includes a PMOS tube MP1 and an NMOS tube MN1, the drain of the PMOS tube MP1 is connected to the drain of the NMOS tube MN1, the connection point is the signal output end of the first multi-input inverter INV1, the source of the PMOS tube MP1 and the substrate of the PMOS tube MP1 are both connected to the power supply VDD; the substrate of the NMOS tube MN1 and the source of the NMOS tube MN1 are both grounded; The second multi-input inverter INV2 includes a PMOS transistor MP2, an NMOS transistor MN2 and an NMOS transistor MN3. The drain of the PMOS transistor MP2 is connected to the drains of the NMOS transistors MN2 and MN3 respectively, and the connection point is the signal output terminal of the second multi-input inverter INV2; the source of the PMOS transistor MP2 and the substrate of the PMOS transistor MP2 are both connected to the power supply VDD; the substrates of the NMOS transistors MN2 and MN3 and the sources of the NMOS transistors MN2 and MN3 are all grounded; The fourth multi-input inverter INV4 includes a PMOS tube MP4, a PMOS tube MP5 and an NMOS tube MN5. The drains of the PMOS tubes MP4 and MP5 are connected to the drain of the NMOS tube MN5, and the connection point is the signal output end of the fourth multi-input inverter INV4; the sources of the PMOS tubes MP4 and MP5 and the substrates of the PMOS tubes MP4 and MP5 are connected to the power supply VDD; the substrate of the NMOS tube MN5 and the source of the NMOS tube MN5 are grounded; The fifth multi-input inverter INV5 includes a PMOS tube MP6, a PMOS tube MP7, an NMOS tube MN6 and an NMOS tube MN7. The drains of the PMOS tube MP6 and the PMOS tube MP7 are connected to the drains of the NMOS tube MN6 and the NMOS tube MN7, and the connection point is the signal output end of the fifth multi-input inverter INV5; the sources of the PMOS tube MP6 and the PMOS tube MP7 and the substrates of the PMOS tube MP6 and the PMOS tube MP7 are connected to the power supply VDD; the substrates of the NMOS tube MN6 and the NMOS tube MN7 and the sources of the NMOS tube MN6 and the NMOS tube MN7 are grounded.

[0014] Preferably, the gate of the first transmission tube N13, the gate of the second transmission tube N14, the gate of the third transmission tube N15, the gate of the fourth transmission tube N16 and the gate of the fifth transmission tube N17 are respectively connected to the word line WL; The drain of the first transmission tube N13, the drain of the third transmission tube N15 and the drain of the fifth transmission tube N17 are respectively connected to the bit line BLN; The drain of the second transmission transistor N14 and the drain of the fourth transmission transistor N16 are respectively connected to the bit line BL.

[0015] Preferably, when the word line WL = 0, the SRAM cell enters a latch mode, and the value of the cell is stored through positive feedback of the circuit; when the word line WL = 1, the SRAM cell enters a read-write mode; when the bit line BL = 1 and BLN = 0, a value 1 is written to the SRAM cell; when the bit line BL = 0 and BLN = 1, a value 0 is written to the SRAM cell; when the bit lines BL and BLN are precharged to 1, the value stored in the SRAM cell is determined by the difference between BL and BLN after discharge.

[0016] In a second aspect, the present invention provides an integrated circuit comprising any one of the above-mentioned solutions of the dual-node flip self-recovery SRAM unit based on multi-input inverters.

[0017] The beneficial effects of the present invention are: A more reasonable layout and wiring method is adopted to greatly improve reliability, so that any single node and any pair of double nodes can tolerate flipping and restore to the original stored value; Five NMOS transistors are used as transmission tubes, which have low latency. In transparent mode, the voltage of the bit line BL / BLN changes faster, so the reading and writing speeds are also faster, so the transmission delay is low; The symmetrical structure uses a cross-coupled feedback mechanism to enable storage nodes to recover quickly when they are hit by SEU or DNU; The symmetrical structure reduces the complexity of the signal propagation path, thereby reducing read and write delays; The symmetric structure reduces the number of redundant nodes, thereby reducing static power consumption; Symmetry enables storage nodes to better maintain balance when facing noise interference, reducing the impact of noise from a single node on the overall storage state. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 The present invention provides a circuit schematic diagram of a dual-node flip self-recovery SRAM unit based on a multi-input inverter.

[0019] Figure 2 This is a circuit schematic diagram of a two-input inverter proposed by the present invention.

[0020] Figure 3 A circuit schematic diagram comparing two three-input inverters proposed in the present invention.

[0021] Figure 4 This is a circuit schematic diagram of a four-input inverter proposed in the present invention. DETAILED DESCRIPTION

[0022] Reference Figure 1 , a dual-node flip self-recovery SRAM cell based on a multi-input inverter, comprising five transmission tubes and a storage module with a symmetrical structure, the storage module comprising a first multi-input inverter INV1, a second multi-input inverter INV2, a third multi-input inverter INV3, a fourth multi-input inverter INV4, a fifth multi-input inverter INV5, a sixth multi-input inverter INV6, a seventh multi-input inverter INV7, an eighth multi-input inverter INV8, and a ninth multi-input inverter INV9; The storage node of the first multi-input inverter INV1 is I1, the storage node of the second multi-input inverter INV2 is I2, the storage node of the third multi-input inverter INV3 is I3, the storage node of the fourth multi-input inverter INV4 is I4, the storage node of the fifth multi-input inverter INV5 is I5, the storage node of the sixth multi-input inverter INV6 is I6, the storage node of the seventh multi-input inverter INV7 is I7, the storage node of the eighth multi-input inverter INV8 is I8, and the storage node of the ninth multi-input inverter INV9 is I9; The five transmission tubes include a first transmission tube N13, a second transmission tube N14, a third transmission tube N15, a fourth transmission tube N16, and a fifth transmission tube N17. The gates of the first transmission tube N13, the second transmission tube N14, the third transmission tube N15, the fourth transmission tube N16, and the fifth transmission tube N17 are all used as switches for reading and writing data of the SRAM unit, and the drains are connected to the bit lines to control the reading and writing of data. The sources of the first transmission tube N13, the second transmission tube N14, the third transmission tube N15, the fourth transmission tube N16, and the fifth transmission tube N17 are respectively connected to the node I1, the node I2, the node I3, the node I4, and the node I9.

[0023] A small loop is formed inside the storage module. When the SRAM stores 0, the signal flows as follows: node I1→node I2→node I3→node I2→node I1; node I4→node I5→node I6→node I5→node I4; node I7→node I8→node I9→node I8→node I7; When the SRAM stores 1, the signal flow is: node I1→node I6→node I7→node I6→node I1; node I2→node I5→node I8→node I5→node I2; node I3→node I4→node I9→node I4→node I3.

[0024] Obviously, based on the above, for a storage module with a loop structure, the value of the previous node can positively feedback the value of the next node, thereby maintaining the value of the entire unit.

[0025] In this embodiment, refer to Figure 1 , the signal output terminal of the first multi-input inverter INV1 is connected to the input terminal N2 of the second multi-input inverter INV2 and the input terminal P8 of the sixth multi-input inverter INV6 respectively; The signal output terminal of the second multi-input inverter INV2 is respectively connected to the input terminal P1 of the first multi-input inverter INV1, the input terminal P3 of the third multi-input inverter INV3 and the input terminal N6 of the fifth multi-input inverter INV5; The signal output terminal of the third multi-input inverter INV3 is connected to the input terminal N3 of the second multi-input inverter INV2 and the input terminal P4 of the fourth multi-input inverter INV4 respectively; The signal output terminal of the fourth multi-input inverter INV4 is respectively connected to the input terminal N4 of the third multi-input inverter INV3, the input terminal P6 of the fifth multi-input inverter INV5 and the input terminal N12 of the ninth multi-input inverter INV9; The signal output terminal of the fifth multi-input inverter INV5 is respectively connected to the input terminal P2 of the second multi-input inverter INV2, the input terminal N5 of the fourth multi-input inverter INV4, the input terminal N8 of the sixth multi-input inverter INV6 and the input terminal P11 of the eighth multi-input inverter INV8; The signal output terminal of the sixth multi-input inverter INV6 is respectively connected to the input terminal N1 of the first multi-input inverter INV1, the input terminal P7 of the fifth multi-input inverter INV5 and the input terminal N9 of the seventh multi-input inverter; The signal output terminal of the seventh multi-input inverter INV7 is connected to the input terminal P9 of the sixth multi-input inverter INV6 and the input terminal N10 of the eighth multi-input inverter INV8 respectively; The signal output terminal of the eighth multi-input inverter INV8 is respectively connected to the input terminal N7 of the fifth multi-input inverter INV5, the input terminal P10 of the seventh multi-input inverter INV7, and the input terminal P12 of the ninth multi-input inverter INV9; The signal output terminal of the ninth multi-input inverter INV9 is connected to the input terminal P5 of the fourth multi-input inverter INV4 and the input terminal N11 of the eighth multi-input inverter INV8, respectively.

[0026] In this embodiment, refer to Figure 1 The storage module is bilaterally symmetrical with the storage node I5 of the fifth multi-input inverter INV5 as the symmetry axis.

[0027] In this embodiment, refer to Figure 1 , the first multi-input inverter INV1, the third multi-input inverter INV3, the seventh multi-input inverter INV7 and the ninth multi-input inverter INV9 have the same structure; The second multi-input inverter INV2 and the eighth multi-input inverter INV8 have the same structure; The fourth multi-input inverter INV4 and the sixth multi-input inverter INV6 have the same structure.

[0028] In this embodiment, refer to Figure 1 , the first multi-input inverter INV1, the third multi-input inverter INV3, the seventh multi-input inverter INV7 and the ninth multi-input inverter INV9 are all two-input inverters consisting of an NMOS tube and a PMOS tube; The second multi-input inverter INV2 and the eighth multi-input inverter INV8 are both three-input inverters consisting of two NMOS tubes and one PMOS tube; The fourth multi-input inverter INV4 and the sixth multi-input inverter INV6 are both three-input inverters consisting of two PMOS tubes and one NMOS tube; The fifth multi-input inverter INV5 is a four-input inverter composed of two NMOS tubes and two PMOS tubes.

[0029] In this embodiment, refer to Figure 2 and Figure 3 The first multi-input inverter INV1 includes a PMOS tube MP1 and an NMOS tube MN1. The drain of the PMOS tube MP1 is connected to the drain of the NMOS tube MN1, and the connection point is the signal output end of the first multi-input inverter INV1. The source of the PMOS tube MP1 and the substrate of the PMOS tube MP1 are both connected to the power supply VDD; the substrate of the NMOS tube MN1 and the source of the NMOS tube MN1 are both grounded; The second multi-input inverter INV2 includes a PMOS transistor MP2, an NMOS transistor MN2 and an NMOS transistor MN3. The drain of the PMOS transistor MP2 is connected to the drains of the NMOS transistors MN2 and MN3 respectively, and the connection point is the signal output terminal of the second multi-input inverter INV2; the source of the PMOS transistor MP2 and the substrate of the PMOS transistor MP2 are both connected to the power supply VDD; the substrates of the NMOS transistors MN2 and MN3 and the sources of the NMOS transistors MN2 and MN3 are all grounded; The fourth multi-input inverter INV4 includes a PMOS tube MP4, a PMOS tube MP5 and an NMOS tube MN5. The drains of the PMOS tubes MP4 and MP5 are connected to the drain of the NMOS tube MN5, and the connection point is the signal output terminal of the fourth multi-input inverter INV4; the sources of the PMOS tubes MP4 and MP5 and the substrates of the PMOS tubes MP4 and MP5 are connected to the power supply VDD; the substrate of the NMOS tube MN5 and the source of the NMOS tube MN5 are grounded; The fifth multi-input inverter INV5 includes a PMOS tube MP6, a PMOS tube MP7, an NMOS tube MN6 and an NMOS tube MN7. The drains of the PMOS tube MP6 and the PMOS tube MP7 are connected to the drains of the NMOS tube MN6 and the NMOS tube MN7, and the connection point is the signal output end of the fifth multi-input inverter INV5; the sources of the PMOS tube MP6 and the PMOS tube MP7 and the substrates of the PMOS tube MP6 and the PMOS tube MP7 are connected to the power supply VDD; the substrates of the NMOS tube MN6 and the NMOS tube MN7 and the sources of the NMOS tube MN6 and the NMOS tube MN7 are grounded.

[0030] In this embodiment, refer to Figure 1 , the gate of the first transmission tube N13, the gate of the second transmission tube N14, the gate of the third transmission tube N15, the gate of the fourth transmission tube N16 and the gate of the fifth transmission tube N17 are respectively connected to the word line WL; The drain of the first transmission tube N13, the drain of the third transmission tube N15 and the drain of the fifth transmission tube N17 are respectively connected to the bit line BLN; The drain of the second transmission transistor N14 and the drain of the fourth transmission transistor N16 are respectively connected to the bit line BL.

[0031] When the word line WL = 0, the SRAM cell enters the latch mode, and the value of the cell is stored through the positive feedback of the circuit. When the word line WL = 1, the SRAM cell enters the read-write mode. When the bit line BL = 1 and BLN = 0, the value 1 is written to the SRAM cell; when the bit line BL = 0 and BLN = 1, the value 0 is written to the SRAM cell; when the bit lines BL and BLN are precharged to 1, the value stored in the SRAM cell is determined by the difference between BL and BLN after discharge.

[0032] As another embodiment of the present application, this embodiment proposes an integrated circuit, including any one of the above-mentioned solutions of the dual-node flip self-recovery SRAM unit based on multi-input inverters.

[0033] In order to more clearly illustrate the scheme and effect of this implementation, examples are given in conjunction with the accompanying drawings: Reference Figure 1-4 , when WL = 1, the unit works in transparent mode. When BL = 1, BLN = 0, the first transmission tube N13, the second transmission tube N14, the third transmission tube N15, the fourth transmission tube N16, and the fifth transmission tube N17 are turned on, and the nodes I2 and I4 are initialized to the value of BL, and the nodes I1, I3, and I9 are initialized to the value of BLN, that is, the write 1 operation is completed. When BL = 0, BLN = 1, the first transmission tube N13, the second transmission tube N14, the third transmission tube N15, the fourth transmission tube N16, and the fifth transmission tube N17 are turned on, and the nodes I2 and I4 are initialized to the value of BL, and the nodes I1, I3, and I9 are initialized to the value of BLN, that is, the write 0 operation is completed. When both BL and BLN are precharged to 1, if the value stored in the structure is 1, BLN is discharged through nodes I1, I3, and I9, and the read 1 operation is completed by reading the difference between bit lines BL and BLN; if the value stored in the structure is 0, BL is discharged through nodes I2 and I4, and the read 0 operation is completed by reading the difference between bit lines BL and BLN.

[0034] When WL = 0, the SRAM unit works in latch mode, and the first transmission tube N13, the second transmission tube N14, the third transmission tube N15, the fourth transmission tube N16, and the fifth transmission tube N17 are turned off. Therefore, the storage value of the dual-node flip self-recovery SRAM unit based on the multi-input inverter is saved in the storage module loop (node ​​I1→node I2→node I3→I2→node I1, node I4→node I5→node I6→node I5→node I4, node I7→node I8→node I9→node I8→node I7). For the loop structure storage module, the value of the previous node can positively feedback the value of the next node to maintain the value of the entire unit. In summary, the SRAM unit can work normally.

[0035] The fault-tolerant working principle of the SRAM cell proposed in the present invention is described below. First, the case of single node upset (SNU) of the SRAM cell is discussed. All nodes of the SRAM cell can be hardened by single node upset. According to the symmetry and loop feedback rules of the SRAM, only the following five SNU cases need to be considered: (1) node I1, (2) node I2, (3) node I3, (4) node I4, (5) node I5; the following analysis is performed when the SRAM cell stores 0.

[0036] For the situation (1), when SNU occurs at the node I1, when the node I1 changes from 1 to 0, the input terminal N2 of the second multi-input inverter INV2 is OFF, the input terminal P8 of the sixth multi-input inverter INV6 is ON, and the values ​​of the nodes I3, I4, I5, I7, I8, and I9 do not change immediately. Therefore, due to the temporary opening of the input terminal P8 of the sixth multi-input inverter INV6, the input terminal N8 of the sixth multi-input inverter INV6 remains ON, and the weak 1 of the node I6 is neutralized by the strong 0 of the node I6, so that the node I6 maintains a value of 0. Since the input terminal P2 of the second multi-input inverter INV2 remains OFF and the input terminal N3 of the second multi-input inverter INV2 remains ON, the node I2 remains 0 even if the input terminal N2 of the second multi-input inverter INV2 is temporarily turned off. When node I6 is 0, input terminal N1 of the first multi-input inverter INV1 is OFF, and when node I2 is 0, input terminal P1 of the first multi-input inverter INV1 is ON, and node I1 is restored to 1. Therefore, node I1 can be reinforced when SNU flips, and the principle of SNU reinforcement of node I9 is ​​similar.

[0037] For the case (2), when SNU occurs at the node I2, when the node I2 changes from 0 to 1, the input terminal P1 of the first multi-input inverter INV1 is OFF, the input terminal P3 of the third multi-input inverter INV3 is OFF, and the input terminal N6 of the fifth multi-input inverter INV5 is ON. However, the values ​​of the nodes I4, I6, I7, I8, and I9 do not change immediately. Because the input terminal P1 of the first multi-input inverter INV1 and the input terminal P3 of the third multi-input inverter INV3 are temporarily turned OFF, the input terminal N1 of the first multi-input inverter INV1 and the input terminal N4 of the third multi-input inverter INV3 remain OFF, and thus the stored values ​​of the nodes I1 and I3 remain unchanged. Because the input terminals P6 and P7 of the fifth multi-input inverter INV5 remain ON, the input terminal N7 of the fifth multi-input inverter INV5 remains OFF, and the input terminal N6 of the fifth multi-input inverter INV5 is temporarily opened, the strong 1 of the node I5 neutralizes the weak 0, so the node I5 remains 1. In summary, the input terminal P2 of the second multi-input inverter INV2 remains OFF, the input terminal N2 of the second multi-input inverter INV2 and the input terminal N3 of the second multi-input inverter INV2 remain ON, so the node I2 is restored to the correct value 0. Therefore, the node I2 can be reinforced when the SNU flips, and the principle of SNU reinforcement of the node I8 is similar to this.

[0038] For the case (3), when SNU occurs at the node I3, when the value of the node I3 changes from 1 to 0, the input terminal N3 of the second multi-input inverter INV2 is OFF, the input terminal P4 of the fourth multi-input inverter INV4 is ON, and the values ​​of the nodes I1, I5, I6, I7, I8, and I9 do not change immediately. Therefore, when the input terminal N5 of the fourth multi-input inverter INV4 is in the ON state and the input terminal P5 of the fourth multi-input inverter INV4 is in the OFF state, since the input terminal P4 of the fourth multi-input inverter INV4 is temporarily turned on, the weak 1 of the node I4 is neutralized by the strong 0 of the node I4, and the node I4 maintains the original value. Because the input terminal P2 of the second multi-input inverter INV2 remains OFF and the input terminal N2 of the second multi-input inverter INV2 remains ON, even if the input terminal N3 of the second multi-input inverter INV2 is temporarily turned off, the node I2 remains 0. Then the input terminal P3 of the third multi-input inverter INV3 is opened, the input terminal N4 of the third multi-input inverter INV3 is closed, and the node I3 is restored to the correct value 1. Therefore, the node I3 can provide SNU flip reinforcement, and the principle of the reinforcement of the node I7 is similar to this.

[0039] For the case (4), when SNU occurs at the node I4, when the value of the node I4 changes from 0 to 1, the input terminal N4 of the third multi-input inverter INV3 and the input terminal N12 of the ninth multi-input inverter INV9 are ON, the input terminal P6 of the fifth multi-input inverter INV5 is OFF, and the values ​​of the nodes I1, I2, I6, I7, and I8 do not change immediately. Because the input terminals N6 and N7 of the fifth multi-input inverter INV5 remain OFF, and the input terminal P7 of the fifth multi-input inverter INV5 remains ON, the node I5 remains 1 even if the input terminal P6 of the fifth multi-input inverter INV5 is temporarily turned off. Because the input terminal P3 of the third multi-input inverter INV3 and the input terminal P12 of the ninth multi-input inverter INV9 remain ON, the input terminal N4 of the third multi-input inverter INV3 and the input terminal N12 of the ninth multi-input inverter INV9 are temporarily opened, and the strong 1 of the node I3 and the node I9 neutralize the weak 0, so the node I3 and the node I9 remain 1. Therefore, the input terminal P4 of the fourth multi-input inverter INV4 and the input terminal P5 of the fourth multi-input inverter INV4 remain OFF, the input terminal N5 of the fourth multi-input inverter INV4 remains ON, and the node I4 is restored to the correct value 0. Therefore, the node I4 can provide SNU flip reinforcement, and the principle of the reinforcement of the node I6 is similar.

[0040] For the situation (5), when SNU occurs at the node I5, when the value of the node I5 changes from 1 to 0, the input terminal P2 of the second multi-input inverter INV2 and the input terminal P11 of the eighth multi-input inverter INV8 are ON, the input terminal N5 of the fourth multi-input inverter INV4 and the input terminal N8 of the sixth multi-input inverter INV6 are OFF, and the values ​​of the nodes I1, I3, I7 and I9 do not change immediately. Because the input terminals P4 and P5 of the fourth multi-input inverter INV4 and the input terminals P8 and P9 of the sixth multi-input inverter INV6 remain OFF, the input terminals N5 of the fourth multi-input inverter INV4 and N8 of the sixth multi-input inverter INV6 are temporarily turned off, so the values ​​of the nodes I4 and I6 remain unchanged. Because the input terminals N2 and N3 of the second multi-input inverter INV2, the input terminals N10 and N11 of the eighth multi-input inverter INV8 remain ON, the input terminals P2 and P11 of the second multi-input inverter INV2 and the eighth multi-input inverter INV8 are temporarily opened, so the strong 0 of the nodes I2 and I8 neutralizes the weak 1, so the nodes I2 and I8 remain 0. Therefore, the input terminals P6 and P7 of the fifth multi-input inverter INV5 remain ON, the input terminals N6 and N7 of the fifth multi-input inverter INV5 remain OFF, and the node I5 is restored to the correct value 1. Therefore, the node I5 can provide SNU flip reinforcement.

[0041] Next, we discuss the double node upset (DNU) case of the SRAM cell. There are 36 pairs of nodes in the SRAM cell that can be hardened against double node upsets. Here, we analyze three DNU cases: (1) <node I1, node I2> (2) <node I2, node I3> (3) <node I3, node I4>; other cases can also be verified using the same analysis method. The following analysis is performed when the SRAM cell stores 0.

[0042] For the situation (1), before DNU occurs at <node I1, node I2>, the value of node I1 is 1, and the value of node I2 is 0. After DNU occurs, the value of node I1 becomes 0, and the value of node I2 becomes 1, causing the input terminal N2 of the second multi-input inverter INV2, the input terminal P1 of the first multi-input inverter INV1, and the input terminal P3 of the third multi-input inverter INV3 to be closed, and the input terminal P8 of the sixth multi-input inverter INV6 and the input terminal N6 of the fifth multi-input inverter INV5 to be opened. The values ​​of node I4, node I7, node I8, and node I9 do not change immediately. The input terminal N4 of the third multi-input inverter INV3 is OFF, and the input terminal P3 of the third multi-input inverter INV3 is temporarily turned off, so the value of node I3 remains unchanged. The input terminal P6 of the fifth multi-input inverter INV5 remains ON, the input terminal N7 of the fifth multi-input inverter INV5 remains OFF, the input terminal N6 of the fifth multi-input inverter INV5 is temporarily opened, the strong 1 of the node I5 neutralizes the weak 0, so the node I5 remains 1. Therefore, the input terminal N8 of the sixth multi-input inverter INV6 remains ON, the input terminal P9 of the sixth multi-input inverter INV6 remains OFF, the input terminal P8 of the sixth multi-input inverter INV6 is temporarily opened, the strong 0 of the node I6 neutralizes the weak 1, so the node I6 remains 0. Therefore, the input terminal P2 of the second multi-input inverter INV2 remains OFF, the input terminal N3 of the second multi-input inverter INV2 remains ON, the input terminal N2 of the second multi-input inverter INV2 is temporarily turned off, and the node I2 returns to its original value 0. The input terminal P1 of the first multi-input inverter INV1 is restored to ON, the input terminal N1 of the first multi-input inverter INV1 is OFF, and the node I1 is restored to the original value 1. Therefore, when the storage unit stores a value of 0, the node pair <node I1, node I2> can be restored from DNU. Due to symmetry, <node I8, node I9> has the same DNU recovery principle.

[0043] For the situation (2), before DNU occurs at <node I2, node I3>, the value of node I2 is 0, and the value of node I3 is 1. After DNU occurs, the value of node I2 becomes 1, and the value of node I3 becomes 0, causing the input terminal P1 of the first multi-input inverter INV1, the input terminal P3 of the third multi-input inverter INV3, and the input terminal N3 of the second multi-input inverter INV2 to be closed, and the input terminal P4 of the fourth multi-input inverter INV4 and the input terminal N6 of the fifth multi-input inverter INV5 to be opened. The values ​​of nodes I6, I7, I8, and I9 do not change immediately. Because the input terminal N1 of the first multi-input inverter INV1 is OFF, the input terminal P1 of the first multi-input inverter INV1 is temporarily turned off, so the value of node I1 remains 1. Because the input terminal N7 of the fifth multi-input inverter INV5 remains OFF, the input terminal P7 of the fifth multi-input inverter INV5 remains ON, the input terminal N6 of the fifth multi-input inverter INV5 is temporarily turned on, the strong 1 of the node I5 neutralizes the weak 0, and thus the node I5 remains 1. Therefore, the input terminal N5 of the fourth multi-input inverter INV4 remains ON, the input terminal P5 of the fourth multi-input inverter INV4 remains OFF, the input terminal P4 of the fourth multi-input inverter INV4 is temporarily turned on, the strong 0 of the node I4 neutralizes the weak 1, and thus the node I4 remains 0. Therefore, the input terminal P2 of the second multi-input inverter INV2 remains OFF, the input terminal N2 of the second multi-input inverter INV2 remains ON, the input terminal N3 of the second multi-input inverter INV2 is temporarily turned off, and the node I2 returns to its original value 0. Therefore, the input terminal P3 of the third multi-input inverter INV3 is restored to ON, the input terminal N4 of the third multi-input inverter INV3 is OFF, and I3 finally recovers to the original value 1. Therefore, when the storage unit stores a value of 0, the node pair <node I2, node I3> can recover from DNU. Due to symmetry, <node I7, node I8> has the same DNU recovery principle.

[0044] For the case of (3), before DNU occurs at <node I3, node I4>, the value of node I3 is 1, and the value of node I4 is 0. After DNU occurs, the value of node I3 becomes 0, and the value of node I4 becomes 1, causing the input terminal P6 of the fifth multi-input inverter INV5 and the input terminal N3 of the second multi-input inverter INV2 to be closed, and the input terminal P4 of the fourth multi-input inverter INV4, the input terminal N4 of the third multi-input inverter INV3, and the input terminal N12 of the ninth multi-input inverter INV9 to be opened. The values ​​of nodes I1, I6, I7, and I8 do not change immediately. Because the input terminal P12 of the ninth multi-input inverter INV9 remains ON, the input terminal N12 of the ninth multi-input inverter INV9 is temporarily opened, and the strong 1 of node I9 neutralizes the weak 0, so node I9 remains 1. Because the input terminal P7 of the fifth multi-input inverter INV5 remains ON, and the input terminal N7 of the fifth multi-input inverter INV5 remains OFF, the node I5 remains 1. Therefore, the input terminal P2 of the second multi-input inverter INV2 is OFF, the input terminal N2 of the second multi-input inverter INV2 is ON, the input terminal N3 of the second multi-input inverter INV2 is temporarily turned off, and the node I2 remains 0. Therefore, the input terminal P3 of the third multi-input inverter INV3 remains ON, the input terminal N4 of the third multi-input inverter INV3 is temporarily turned on, and the strong 1 of the node I3 neutralizes the weak 0, so the node I3 eventually returns to the original value 1. Therefore, the input terminal P4 of the fourth multi-input inverter INV4 returns to OFF, the input terminal P5 of the fourth multi-input inverter INV4 remains OFF, and the input terminal N5 of the fourth multi-input inverter INV4 remains ON, and the node I4 eventually returns to the original value 0. Therefore, when the storage unit stores a value of 0, the node pair <node I3, node I4> can recover from DNU. Due to symmetry, <node I6, node I7> has the same DNU recovery principle.

[0045] From the above analysis, it can be seen that the SRAM cell of the present invention is fully hardened against flipping of any single node and any double node.

[0046] In summary, the present invention improves the reliability of the SRAM cell circuit. Compared with the existing SRAM cell, the present invention reduces the delay but increases the power consumption, and improves the tolerance of the SRAM cell, with more superior stability. The present invention proposes a high reliability solution for high-stability integrated circuits and system designs operating under high-intensity radiation conditions, which can be applied to application scenarios such as aerospace that have strict standards for the reliability of SRAM cells.

Claims

1. A dual-node flip self-recovery SRAM cell based on a multi-input inverter, characterized in that: It includes five transmission tubes and a storage module with a symmetrical structure, wherein the storage module includes a first multi-input inverter INV1, a second multi-input inverter INV2, a third multi-input inverter INV3, a fourth multi-input inverter INV4, a fifth multi-input inverter INV5, a sixth multi-input inverter INV6, a seventh multi-input inverter INV7, an eighth multi-input inverter INV8, and a ninth multi-input inverter INV9, and each group of multi-input inverter storage nodes respectively corresponds to: node I1, node I2, node I3, node I4, node I5, node I6, node I7, node I8 and node I9; The five transmission tubes include a first transmission tube N13, a second transmission tube N14, a third transmission tube N15, a fourth transmission tube N16, and a fifth transmission tube N17. The gates of the first transmission tube N13, the second transmission tube N14, the third transmission tube N15, the fourth transmission tube N16, and the fifth transmission tube N17 are all used as switches for reading and writing data of the SRAM unit, and the drains are connected to the bit lines to control the reading and writing of data. The source of the first transmission tube N13, the source of the second transmission tube N14, the source of the third transmission tube N15, the source of the fourth transmission tube N16, and the source of the fifth transmission tube N17 are respectively connected to the node I1, the node I2, the node I3, the node I4, and the node I9; When the SRAM stores 0, the signal flow is: node I1→node I2→node I3→node I2→node I1; node I4→node I5→node I6→node I5→node I4; node I7→node I8→node I9→node I8→node I7; When the SRAM stores 1, the signal flow is: node I1→node I6→node I7→node I6→node I1; node I2→node I5→node I8→node I5→node I2; node I3→node I4→node I9→node I4→node I3.

2. A dual-node flip self-recovery SRAM cell based on a multi-input inverter according to claim 1, characterized in that: The signal output terminal of the first multi-input inverter INV1 is connected to the input terminal N2 of the second multi-input inverter INV2 and the input terminal P8 of the sixth multi-input inverter INV6 respectively; The signal output terminal of the second multi-input inverter INV2 is respectively connected to the input terminal P1 of the first multi-input inverter INV1, the input terminal P3 of the third multi-input inverter INV3 and the input terminal N6 of the fifth multi-input inverter INV5; The signal output terminal of the third multi-input inverter INV3 is connected to the input terminal N3 of the second multi-input inverter INV2 and the input terminal P4 of the fourth multi-input inverter INV4 respectively; The signal output terminal of the fourth multi-input inverter INV4 is respectively connected to the input terminal N4 of the third multi-input inverter INV3, the input terminal P6 of the fifth multi-input inverter INV5 and the input terminal N12 of the ninth multi-input inverter INV9; The signal output terminal of the fifth multi-input inverter INV5 is respectively connected to the input terminal P2 of the second multi-input inverter INV2, the input terminal N5 of the fourth multi-input inverter INV4, the input terminal N8 of the sixth multi-input inverter INV6 and the input terminal P11 of the eighth multi-input inverter INV8; The signal output terminal of the sixth multi-input inverter INV6 is respectively connected to the input terminal N1 of the first multi-input inverter INV1, the input terminal P7 of the fifth multi-input inverter INV5 and the input terminal N9 of the seventh multi-input inverter; The signal output terminal of the seventh multi-input inverter INV7 is connected to the input terminal P9 of the sixth multi-input inverter INV6 and the input terminal N10 of the eighth multi-input inverter INV8 respectively; The signal output terminal of the eighth multi-input inverter INV8 is respectively connected to the input terminal N7 of the fifth multi-input inverter INV5, the input terminal P10 of the seventh multi-input inverter INV7 and the input terminal P12 of the ninth multi-input inverter INV9; The signal output terminal of the ninth multi-input inverter INV9 is connected to the input terminal P5 of the fourth multi-input inverter INV4 and the input terminal N11 of the eighth multi-input inverter INV8 respectively.

3. A dual-node flip self-recovery SRAM cell based on a multi-input inverter according to claim 1, characterized in that: The storage module is bilaterally symmetrical with the storage node I5 of the fifth multi-input inverter INV5 as a symmetry axis.

4. A dual-node flip self-recovery SRAM cell based on a multi-input inverter according to claim 3, characterized in that: The first multi-input inverter INV1, the third multi-input inverter INV3, the seventh multi-input inverter INV7 and the ninth multi-input inverter INV9 have the same structure; The second multi-input inverter INV2 and the eighth multi-input inverter INV8 have the same structure; The fourth multi-input inverter INV4 and the sixth multi-input inverter INV6 have the same structure.

5. A dual-node flip self-recovery SRAM cell based on a multi-input inverter according to claim 4, characterized in that: The first multi-input inverter INV1, the third multi-input inverter INV3, the seventh multi-input inverter INV7 and the ninth multi-input inverter INV9 are all two-input inverters consisting of an NMOS tube and a PMOS tube; The second multi-input inverter INV2 and the eighth multi-input inverter INV8 are both three-input inverters consisting of two NMOS tubes and one PMOS tube; The fourth multi-input inverter INV4 and the sixth multi-input inverter INV6 are both three-input inverters consisting of two PMOS tubes and one NMOS tube; The fifth multi-input inverter INV5 is a four-input inverter composed of two NMOS tubes and two PMOS tubes.

6. A dual-node flip self-recovery SRAM cell based on a multi-input inverter according to claim 4, characterized in that: The first multi-input inverter INV1 includes a PMOS tube MP1 and an NMOS tube MN1, the drain of the PMOS tube MP1 is connected to the drain of the NMOS tube MN1, the connection point is the signal output end of the first multi-input inverter INV1, the source of the PMOS tube MP1 and the substrate of the PMOS tube MP1 are both connected to the power supply VDD; the substrate of the NMOS tube MN1 and the source of the NMOS tube MN1 are both grounded; The second multi-input inverter INV2 includes a PMOS transistor MP2, an NMOS transistor MN2 and an NMOS transistor MN3. The drain of the PMOS transistor MP2 is connected to the drains of the NMOS transistors MN2 and MN3 respectively, and the connection point is the signal output terminal of the second multi-input inverter INV2; the source of the PMOS transistor MP2 and the substrate of the PMOS transistor MP2 are both connected to the power supply VDD; the substrates of the NMOS transistors MN2 and MN3 and the sources of the NMOS transistors MN2 and MN3 are all grounded; The fourth multi-input inverter INV4 includes a PMOS tube MP4, a PMOS tube MP5 and an NMOS tube MN5. The drains of the PMOS tubes MP4 and MP5 are connected to the drain of the NMOS tube MN5, and the connection point is the signal output end of the fourth multi-input inverter INV4; the sources of the PMOS tubes MP4 and MP5 and the substrates of the PMOS tubes MP4 and MP5 are connected to the power supply VDD; the substrate of the NMOS tube MN5 and the source of the NMOS tube MN5 are grounded; The fifth multi-input inverter INV5 includes a PMOS tube MP6, a PMOS tube MP7, an NMOS tube MN6 and an NMOS tube MN7. The drains of the PMOS tube MP6 and the PMOS tube MP7 are connected to the drains of the NMOS tube MN6 and the NMOS tube MN7, and the connection point is the signal output end of the fifth multi-input inverter INV5; the sources of the PMOS tube MP6 and the PMOS tube MP7 and the substrates of the PMOS tube MP6 and the PMOS tube MP7 are connected to the power supply VDD; the substrates of the NMOS tube MN6 and the NMOS tube MN7 and the sources of the NMOS tube MN6 and the NMOS tube MN7 are grounded.

7. The dual-node flip self-recovery SRAM cell based on a multi-input inverter according to claim 1, characterized in that: The gate of the first transmission tube N13, the gate of the second transmission tube N14, the gate of the third transmission tube N15, the gate of the fourth transmission tube N16 and the gate of the fifth transmission tube N17 are respectively connected to the word line WL; The drain of the first transmission tube N13, the drain of the third transmission tube N15 and the drain of the fifth transmission tube N17 are respectively connected to the bit line BLN; The drain of the second transmission transistor N14 and the drain of the fourth transmission transistor N16 are respectively connected to the bit line BL.

8. The dual-node flip self-recovery SRAM cell based on a multi-input inverter according to claim 7, characterized in that: When the word line WL = 0, the SRAM cell enters the latch mode, and the value of the cell is stored through the positive feedback of the circuit. When the word line WL = 1, the SRAM cell enters the read-write mode. When the bit line BL = 1 and BLN = 0, the value 1 is written to the SRAM cell. When the bit line BL = 0, BLN = 1, the value 0 is written to the SRAM cell; when the bit lines BL and BLN are precharged to 1, the value stored in the SRAM cell is determined by the difference between BL and BLN after discharge.

9. An integrated circuit, characterized in that: A dual-node flip self-recovery SRAM unit based on a multi-input inverter is included as described in any one of claims 1 to 8.

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