Shift register and driving method thereof, gate driving circuit and display device

Abstract

The invention discloses a shift register and a driving method thereof, a gate driving circuit and a display device. The shift register comprises an input sub-circuit; the first control sub-circuit is configured to transmit a signal of a first clock signal end to a second node in response to the control of the first node; transmitting a first level signal of a first level end to a second node in response to the control of a first clock signal end; the second control sub-circuit is configured to transmit a second level signal to the first node in response to control of a second node and a second clock signal end; the first output sub-circuit is configured to transmit a first level signal of a first level end to an output end in response to the control of the first node; the second output sub-circuit is configured to respond to the control of the first node, the second node and a second clock signal end, and conduct a second level end and the output end; and the first leakage-proof electronic circuit is configured to provide the first level signal for the second node at least when the input end provides the first level signal.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a shift register and a driving method thereof, a gate driving circuit and a display device. Background Art

[0002] With the continuous development of display technology, the development of displays in recent years has gradually shown a trend of high integration and low cost. One of the most important technologies is the mass production of Gate Driver on Array (GOA) technology.

[0003] The GOA technology is used to integrate a shift register circuit composed of a thin film transistor (TFT) on an array substrate of a display substrate to form a scanning drive for the display substrate. Summary of the invention

[0004] In a first aspect, the present disclosure provides a shift register, comprising:

[0005] an input subcircuit configured to transmit an input signal at the input terminal to the first node in response to control of the first clock signal terminal;

[0006] A first control subcircuit is configured to transmit the signal of the first clock signal terminal to the second node in response to the control of the first node; and transmit the first level signal of the first level terminal to the second node in response to the control of the first clock signal terminal;

[0007] a second control subcircuit configured to transmit the second level signal of the second level terminal to the first node in response to control of the second node and the second clock signal terminal;

[0008] a first output sub-circuit configured to transmit the first level signal at the first level end to the output end of the shift register in response to control of the first node;

[0009] A second output sub-circuit, configured to connect the second level terminal to the output terminal in response to control of the first node, the second node and the second clock signal terminal;

[0010] a first leakage-proof electronic circuit configured to provide the first level signal to the second node at least when the first level signal is provided at the input terminal;

[0011] The first node is a connection node between the input sub-circuit, the first control sub-circuit and the second control sub-circuit, and the second node is a connection node between the first control sub-circuit and the second control sub-circuit.

[0012] In some embodiments, the first leakage-proof electronic circuit comprises:

[0013] A twelfth transistor, wherein the control electrode and the first electrode of the twelfth transistor are both electrically connected to the first level end, and the second electrode of the twelfth transistor is electrically connected to the second node.

[0014] In some embodiments, the first leakage-proof electronic circuit comprises:

[0015] an eleventh transistor, a control electrode of the eleventh transistor being electrically connected to the input terminal, and a first electrode of the eleventh transistor being electrically connected to the first level terminal;

[0016] A twelfth transistor, wherein a control electrode of the twelfth transistor is electrically connected to the second electrode of the eleventh transistor, a first electrode of the twelfth transistor is electrically connected to the first level end, and a second electrode of the twelfth transistor is electrically connected to the second node.

[0017] In some embodiments, the second control subcircuit comprises:

[0018] a fourteenth transistor, wherein a control electrode of the fourteenth transistor is electrically connected to the second node, and a first electrode of the fourteenth transistor is electrically connected to the second level end;

[0019] a seventh transistor, wherein a control electrode of the seventh transistor is electrically connected to the second node, and a first electrode of the seventh transistor and a second electrode of the fourteenth transistor are connected to a sixth node;

[0020] a second transistor, wherein a control electrode of the second transistor is electrically connected to the second clock signal terminal, a first electrode of the second transistor is electrically connected to the second electrode of the seventh transistor, and a second electrode of the second transistor is electrically connected to the first node;

[0021] The shift register further includes a second leakage prevention electronic circuit configured to transmit the first level signal to the sixth node in response to at least control of the first node.

[0022] In some embodiments, the second leakage-proof electronic circuit comprises:

[0023] A fifteenth transistor, wherein the control electrode of the fifteenth transistor is electrically connected to the first node, the first electrode is electrically connected to the first level end, and the second electrode is electrically connected to the sixth node.

[0024] In some embodiments, the first leakage prevention electronic circuit and the second leakage prevention electronic circuit are connected to a seventh node, and the first leakage prevention electronic circuit is further configured to transmit the first level signal to the seventh node in response to the input signal;

[0025] The second leakage-proof electronic circuit comprises:

[0026] a thirteenth transistor, a control electrode of which is electrically connected to the seventh node, a first electrode of which is electrically connected to the second level end, and a second electrode of which is directly electrically connected to the sixth node or electrically connected to the sixth node through a fourth capacitor;

[0027] A fifteenth transistor has a control electrode electrically connected to the first node, a first electrode electrically connected to the first level end, and a second electrode electrically connected to the sixth node.

[0028] In some embodiments, the input subcircuit includes a first transistor, a control electrode of the first transistor is electrically connected to the first clock signal terminal, a first electrode is electrically connected to the input terminal, and a second electrode is electrically connected to the first node.

[0029] In some embodiments, the first control subcircuit comprises:

[0030] a fifth transistor, wherein a control electrode of the fifth transistor is electrically connected to the first node, a first electrode of the fifth transistor is electrically connected to the first clock signal terminal, and a second electrode of the fifth transistor is electrically connected to the second node;

[0031] A sixth transistor, wherein a control electrode of the sixth transistor is electrically connected to the first clock signal end, a first electrode is electrically connected to the first level end, and a second electrode is electrically connected to the second node.

[0032] In some embodiments, the first output subcircuit comprises:

[0033] a third transistor, wherein a control electrode of the third transistor is electrically connected to the first node, a first electrode of the third transistor is electrically connected to the first level end, and a second electrode of the third transistor is electrically connected to the output end;

[0034] A third capacitor, wherein two ends of the third capacitor are electrically connected to the first node and the second clock signal end respectively.

[0035] In some embodiments, the second output subcircuit includes: a first output control unit, a second output control unit and an output unit; the first output control unit and the second output control unit are connected to a fourth node, and the second output control unit and the output unit are connected to a fifth node;

[0036] The first output control unit is configured to transmit the signal of the second clock signal terminal to the fourth node in response to the control of the second node;

[0037] The second output control unit is configured to transmit the signal of the fourth node to the fifth node in response to the control of the second clock signal terminal; and transmit the second level signal to the fifth node in response to the control of the first node;

[0038] The output unit is configured to transmit the first level signal to the output terminal in response to control of the fifth node.

[0039] In some embodiments, the first output control unit includes:

[0040] an eighth transistor, wherein a control electrode of the eighth transistor is electrically connected to the second node, a first electrode is electrically connected to the second clock signal terminal, and a second electrode is electrically connected to the fourth node;

[0041] A second capacitor, wherein two ends of the second capacitor are electrically connected to the second node and the fourth node respectively.

[0042] In some embodiments, the second output control unit comprises:

[0043] a ninth transistor, wherein a control electrode of the ninth transistor is electrically connected to the second clock signal terminal, a first electrode of the ninth transistor is electrically connected to the fourth node, and a second electrode of the ninth transistor is electrically connected to the fifth node;

[0044] A tenth transistor, wherein a control electrode of the tenth transistor is electrically connected to the first node, a first electrode is electrically connected to the second level end, and a second electrode is electrically connected to the fifth node.

[0045] In some embodiments, the output unit includes:

[0046] a first capacitor, wherein two ends of the first capacitor are electrically connected to the second level end and the fifth node respectively;

[0047] A fourth transistor, wherein a control electrode of the fourth transistor is electrically connected to the fifth node, a first electrode is electrically connected to the second level end, and a second electrode is electrically connected to the output end.

[0048] In a second aspect, the present disclosure further provides a driving method of the shift register as described above, comprising:

[0049] In the first stage, the input terminal and the first clock signal terminal both provide a first level signal, the second clock signal terminal provides a second level signal, the input subcircuit transmits the signal of the input terminal to the first node, and the first output subcircuit disconnects the output terminal from the first level terminal; the first control subcircuit and the first anti-leakage electronic circuit provide a first level signal to the second node, and the second output subcircuit maintains a disconnected state between the second level terminal and the output terminal; the output terminal keeps outputting the first level signal of the previous stage;

[0050] In the second stage, the input terminal and the first clock signal terminal both provide a second level signal, the second clock signal terminal provides a first level signal, the second control subcircuit transmits the second level signal of the second level terminal to the first node, and the second output subcircuit transmits the second level signal of the second signal terminal to the output terminal;

[0051] In the third stage, the input terminal and the second clock signal terminal both provide a second level signal, the first clock signal terminal provides a first level signal, the first control subcircuit transmits the first level signal of the first level terminal to the second node, and the second output subcircuit maintains a conductive state between the second level terminal and the output terminal;

[0052] In the fourth stage, the input terminal and the second clock signal terminal both provide a first level signal, the first clock signal terminal provides a second level signal, the second control subcircuit transmits the second level signal of the second level terminal to the first node, and the first anti-leakage electronic circuit provides the first level signal for the second node; the second output subcircuit transmits the second level signal of the second signal terminal to the output terminal;

[0053] In the fifth stage, the input end and the first clock signal end both provide a first level signal, the second clock signal end provides a second level signal, the input sub-circuit transmits the first level signal of the input end to the first node, the first leakage prevention electronic circuit provides the first level signal to the second node, the second output sub-circuit disconnects the output end from the second level end; the first output sub-circuit transmits the first level signal of the first level signal end to the output end.

[0054] In a third aspect, the present disclosure further provides a gate driving circuit, which comprises a plurality of cascaded shift registers as described above.

[0055] In a fourth aspect, the present disclosure further provides a display device, comprising the above-mentioned gate driving circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] The accompanying drawings are used to provide a further understanding of the present disclosure and constitute a part of the specification. Together with the following specific embodiments, they are used to explain the present disclosure but do not constitute a limitation of the present disclosure. In the accompanying drawings:

[0057] Figure 1 is a schematic diagram of a shift register provided in some embodiments.

[0058] Figure 2 for Figure 1 The driving timing diagram of the shift register under normal state is shown.

[0059] Figure 3 A schematic diagram of the structure of a shift register provided in some embodiments of the present disclosure.

[0060] Figure 4 Schematic diagram of a shift register provided in some other embodiments of the present disclosure.

[0061] Figure 5 Schematic diagram of a shift register provided in some other embodiments of the present disclosure.

[0062] Figure 6 for Figure 5 The working timing diagram of the shift register is shown.

[0063] Figure 7 Schematic diagram of a shift register provided in some other embodiments of the present disclosure.

[0064] Figure 8 Schematic diagram of a shift register provided in some other embodiments of the present disclosure.

[0065] Fig. 9 A schematic diagram of a driving method for a shift register provided in some embodiments of the present disclosure. DETAILED DESCRIPTION

[0066] The specific implementation of the present disclosure is described in detail below in conjunction with the accompanying drawings. It should be understood that the specific implementation described herein is only used to illustrate and explain the present disclosure, and is not used to limit the present disclosure.

[0067] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0068] Unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not represent any order, quantity or importance, but are only used to distinguish different components. Similarly, "including" or "comprising" and similar words mean that the elements or objects appearing in front of the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0069] It should be noted that the transistors used in the embodiments of the present disclosure may be thin film transistors or field effect transistors or other devices with the same characteristics. Since the source and drain of the transistors used are symmetrical, there is no difference between the source and drain. In the embodiments of the present disclosure, in order to distinguish the source and drain of the transistor, one of the electrodes is called the first electrode, the other electrode is called the second electrode, and the gate is called the control electrode. In addition, transistors can be divided into N-type and P-type according to the characteristics of the transistor. The following embodiments are described with N-type transistors. When N-type transistors are used, the first electrode is the source of the N-type transistor, the second electrode is the drain of the N-type transistor, and when the gate inputs a high level, the source and drain are turned on, and the P-type is the opposite. It can be imagined that the use of P-type transistors is something that a person skilled in the art can easily think of without creative labor, so it is also within the scope of protection of the embodiments of the present disclosure. In addition, according to the material of the active layer in the transistor, the transistor can be divided into oxide thin film transistors, low temperature polysilicon thin film transistors and other types. Generally, oxide thin film transistors are N-type transistors, and low temperature polysilicon thin film transistors are P-type transistors.

[0070] Among them, in the present disclosure, "first level signal" / "first level potential" refers to a signal / potential that can control the conduction of the transistor after being input to the control electrode of the transistor, and "second level signal" refers to a signal / potential that can control the cutoff of the transistor after being input to the control electrode of the transistor. In some embodiments, the first level signal can be a high level signal, and the first level potential is a high level potential; the second level signal can be a low level signal, and the second level potential is a low level potential; in other embodiments, the first level signal is a low level signal, and the first level potential is a low level potential; the second level signal is a high level signal, and the second level potential is a high level potential. Among them, for N-type transistors, the first level signal is a high level signal, and the first level potential is a high level potential; the second level signal is a low level signal, and the second level potential is a low level potential. For P-type transistors, the first level signal is a low level signal, and the first level potential is a low level potential; the second level signal is a high level signal, and the second level potential is a high level potential.

[0071] In the display substrate, a plurality of gate lines and a plurality of data lines intersect in the display area to define a plurality of pixels, and a pixel circuit and a light-emitting device are provided in each pixel. The working phase of the pixel circuit includes a data writing phase and a light-emitting phase. In the data writing phase, the pixel circuit responds to the scanning signal on the gate line to write the data voltage and the threshold voltage into the storage capacitor, thereby performing threshold compensation; in the light-emitting phase, the pixel circuit responds to the light-emitting control signal on the light-emitting control line to provide a driving current for the light-emitting device. Among them, the structure of the above-mentioned light-emitting device includes multiple types, which can be selected and set according to actual needs. For example, the above-mentioned light-emitting device can be an OLED (Organic Light-Emitting Diode), a quantum dot light-emitting diode (Quantum Dot Light Emitting Diodes, referred to as QLED) or a micro light-emitting diode (Micro Light Emitting Diodes, referred to as Micro LED), etc.

[0072] The peripheral area of ​​the display substrate is provided with a plurality of gate drive circuits, and the gate drive circuits include a plurality of cascaded shift registers. For example, the peripheral area is provided with a first gate drive circuit and a second gate drive circuit, and the first gate drive circuit includes a plurality of cascaded first shift registers, the first shift register is connected to the gate line, and the plurality of first shift registers sequentially provide scanning signals for the plurality of gate lines. The second gate drive circuit includes a plurality of cascaded second shift registers, the second shift register is connected to the light-emitting control line, and the plurality of second shift registers sequentially provide light-emitting control signals for the plurality of light-emitting control lines.

[0073] Figure 1 is a schematic diagram of a shift register provided in some embodiments, such as Figure 1 As shown, the shift register includes: an input subcircuit 10 , a first control subcircuit 20 , a second control subcircuit 30 , a first output subcircuit 40 and a second output subcircuit 50 .

[0074] The input subcircuit 10 is electrically connected to the input terminal EIN, the first node n1, and the first clock signal terminal CLK of the shift register, and is configured to transmit the input signal of the input terminal EIN to the first node n1 in response to the control of the first clock signal terminal CLK. The first control subcircuit 20 is electrically connected to the first node n1, the second node n2, the first clock signal terminal CLK, and the first level terminal V1, and is configured to transmit the signal of the first clock signal terminal CLK to the second node n2 in response to the control of the first node n1; and transmit the first level signal of the first level terminal V1 to the second node n2 in response to the control of the first clock signal terminal CLK. The second control subcircuit 30 is connected to the second node n2, the second clock signal terminal CKB, and the second level terminal V2, and is configured to transmit the second level signal of the second level terminal V2 to the first node n1 in response to the control of the second node n2 and the second clock signal terminal CKB. The first output sub-circuit 40 is electrically connected to the first level terminal V1, the first node n1 and the output terminal EOUT of the shift register, and is configured to transmit the first level signal of the first level terminal V1 to the output terminal EOUT of the shift register in response to the control of the first node n1. The second output sub-circuit 50 is electrically connected to the first node n1, the second node n2, the second clock signal terminal CKB, the second level terminal V2 and the output terminal EOUT, and is configured to conduct the second level terminal V2 with the output terminal EOUT in response to the control of the first node n1, the second node n2 and the second clock signal terminal CKB. Optionally, the second output sub-circuit 50 connects the second level terminal V2 with the output terminal EOUT in response to the second level signal of the first node n1, the first level signal of the second node n2 and the first level signal of the second clock signal terminal CKB; and, in response to the second level signal of the first node n1, the first level signal of the second node n2 and the second level signal of the second clock signal terminal CKB, maintains the on-off state of the second level terminal V2 and the output terminal EOUT; and, in response to the first level signal of the first node n1 and the second level signal of the second node n2, disconnects the second level terminal V2 from the output terminal EOUT.

[0075] In an example, the first control subcircuit 20 may specifically include a fifth transistor M5 and a sixth transistor M6, wherein the control electrode of the fifth transistor M5 is electrically connected to the first node n1, the first electrode is electrically connected to the first clock signal terminal CLK, and the second electrode is electrically connected to the second node n2. The control electrode of the sixth transistor M6 is electrically connected to the first clock signal terminal CLK, the first electrode is electrically connected to the first level terminal V1, and the second electrode is electrically connected to the second node n2. The second control subcircuit 30 may specifically include a seventh transistor M7 and a second transistor M2, wherein the control electrode of the seventh transistor M7 is electrically connected to the second node n2, the first electrode is electrically connected to the second level terminal V2, and the second electrode is connected to the first electrode of the second transistor M2 at the third node n3; the control electrode of the second transistor M2 is electrically connected to the second clock signal terminal CKB, and the second electrode is electrically connected to the first node n1.

[0076] Figure 2 for Figure 1 The driving timing diagram of the shift register in a normal state is shown in FIG. 1 . In this embodiment, each transistor is an N-type transistor, the first level signal is a high level signal, and the second level signal is a low level signal. Figure 2 As shown, in the first stage t1, the input terminal EIN and the second clock signal terminal CKB both provide a second level signal, and the first clock signal terminal CLK provides a first level signal. At this time, the sixth transistor M6 is turned on, thereby transmitting the first level signal of the first level terminal V1 to the second node n2. In addition, the first transistor M1 is turned on, thereby transmitting the second level signal of the input terminal EIN to the first node n1, thereby controlling the third transistor M3 to be turned off. The second output subcircuit 50 maintains the disconnection state between the second level terminal V2 and the output terminal EOUT. The output terminal EOUT keeps outputting the first level signal of the previous stage.

[0077] In the second stage t2, the input terminal EIN and the first clock signal terminal CLK both provide a second level signal, and the second clock signal terminal CKB provides a first level signal. At this time, the second control subcircuit 30 transmits the second level signal of the second level terminal V2 to the first node n1, so that the first output subcircuit 40 disconnects the first level terminal V1 from the output terminal EOUT. The fifth transistor M5 and the sixth transistor M6 in the first control subcircuit 20 are both turned off, and the second node n2 is still at the first level potential. The second output subcircuit 50 connects the second level terminal V2 to the output terminal EOUT, and the output terminal EOUT outputs the second level signal.

[0078] In the third stage t3, the input terminal EIN and the second clock signal terminal CKB both provide a second level signal, and the first clock signal terminal CLK provides a first level signal. At this time, the input sub-circuit 10 transmits the second level signal of the input terminal EIN to the first node n1, so that the first output sub-circuit 40 disconnects the first level terminal V1 from the output terminal EOUT. The sixth transistor M6 of the first control sub-circuit 20 is turned on, so that the first level signal of the first level terminal V1 is transmitted to the second node n2; the second output sub-circuit 50 maintains the conduction state between the second level terminal V2 and the output terminal EOUT in response to the second level signal of the first node n1, the first level signal of the second node n2, and the second level signal of the second clock signal terminal CKB.

[0079] In the fourth stage t4, the input terminal EIN and the second clock signal terminal CKB both provide a first level signal, and the first clock signal terminal CLK provides a second level signal. The working process of this stage is the same as that of the second stage.

[0080] In the fifth stage t5, the input terminal EIN and the first clock signal terminal CLK both provide a first level signal, and the second clock signal terminal CKB provides a second level signal. The input subcircuit 10 transmits the first level signal of the input terminal EIN to the first node n1, so that the first output subcircuit 40 connects the first level terminal V1 with the output terminal EOUT, and the output terminal EOUT outputs the first level signal. In addition, the fifth transistor M5 and the sixth transistor M6 of the first control subcircuit 20 are turned on, so that the first level terminal V1 and the first level signal of the first clock signal terminal CLK are transmitted to the second node n2. The second output subcircuit 50 disconnects the second level terminal V2 from the output terminal EOUT in response to the first level signal of the first node n1.

[0081] In the sixth stage t6, both the input terminal EIN and the second clock signal terminal CKB provide a first level signal, and the second clock signal terminal CKB provides a first level signal. At this time, the input sub-circuit 10 disconnects the first node n1 from the input terminal EIN, and the first node n1 maintains the first level potential of the previous stage, and the first output sub-circuit 40 keeps the output terminal EOUT and the first level terminal V1 connected. In addition, the fifth transistor M5 is turned on, thereby transmitting the second level signal of the first clock signal terminal CLK to the second node n2; the second output sub-circuit 50 disconnects the second level terminal V2 from the output terminal EOUT in response to the first level signal of the first node n1.

[0082] Optionally, the working process of the shift register also includes between the third stage t3 and the fourth stage t4: a first holding stage t31 and a second holding stage t32, wherein the signal timing of the shift register in the first holding stage t31 is the same as that in the second stage t2, and the signal timing of the second holding stage t32 is the same as that in the third stage t3, which will not be repeated here.

[0083] During the operation of the shift register, when the transistors do not leak, the shift register can operate normally. However, when the transistor leaks, the normal output of the shift register cannot be guaranteed. For example, if the threshold voltage Vth of the fifth transistor M5 is greater than 0, when the signals of the first node n1 and the first clock signal terminal CLK are both second-level signals, the fifth transistor M5 is turned off because the voltage difference Vgs between the control electrode and the first electrode of the fifth transistor M5 is less than the threshold voltage. If the threshold voltage of the fifth transistor M5 shifts to less than 0, when the signals of the first node n1 and the first clock signal terminal CLK are both second-level signals, the fifth transistor M5 cannot be turned off, resulting in leakage of the second node n2; when the second node n2 drops to the second-level potential, the output terminal EOUT always outputs the first-level signal. Similarly, when the threshold voltage of the transistors in the input sub-circuit 10 and the second control sub-circuit 30 shifts to less than 0, leakage will occur at the third node n3. In this case, the second level signal output by the output terminal EOUT is normal, but when the signal of the first clock signal terminal CLK changes, the signal of the output terminal EOUT will also fluctuate.

[0084] Figure 3 is a schematic diagram of the structure of a shift register provided in some embodiments of the present disclosure, such as Figure 3 As shown, the shift register includes an input subcircuit 10, a first control subcircuit 20, a second control subcircuit 30, a first output subcircuit 40, a second output subcircuit 50 and a first anti-leakage electronic circuit 60. The input subcircuit 10, the first control subcircuit 20 and the second control subcircuit 30 are connected to a first node n1; the first control subcircuit 20, the second control subcircuit 30 and the first anti-leakage electronic circuit 60 are connected to a second node n2.

[0085] The input subcircuit 10 is configured to transmit the input signal of the input terminal EIN to the first node n1 in response to the control of the first clock signal terminal CLK. The first control subcircuit 20 is configured to transmit the signal of the first clock signal terminal CLK to the second node n2 in response to the control of the first node n1; and transmit the first level signal of the first level terminal V1 to the second node n2 in response to the control of the first clock signal terminal CLK. The second control subcircuit 30 is configured to transmit the second level signal of the second level terminal V2 to the first node n1 in response to the control of the second node n2 and the second clock signal terminal CKB. The first output subcircuit 40 is configured to transmit the first level signal of the first level terminal V1 to the output terminal EOUT of the shift register in response to the control of the first node n1. The second output subcircuit 50 is configured to connect the second level terminal V2 to the output terminal EOUT in response to the control of the first node n1, the second node n2 and the second clock signal terminal CKB. The second output subcircuit 50 is configured to, in response to the second level signal of the first node n1, the first level signal of the second node n2 and the first level signal of the second clock signal terminal CKB, conduct the second level terminal V2 and the output terminal EOUT; in response to the second level signal of the first node n1, the first level signal of the second node n2 and the second level signal of the second clock signal terminal CKB, maintain the conduction state of the second level terminal V2 and the output terminal EOUT; and, in response to the first level signal of the first node n1 and the second level signal of the second node n2, disconnect the output terminal EOUT from the second level terminal V2. The first anti-leakage electronic circuit 60 is configured to provide a first level signal to the second node n2 at least when the input terminal EIN provides a first level signal.

[0086] and Figure 1 Compared to the shift register shown in Figure 2 The shift register also includes a first leakage prevention electronic circuit 60, and the first leakage prevention electronic circuit 60 provides a first level signal to the second node n2 at least when the input terminal EIN provides a first level signal, thereby preventing the potential of the second node n2 from decreasing due to leakage of the transistor in the second control subcircuit 30, thereby reducing or preventing output abnormalities caused by the potential of the second node n2.

[0087] Figure 4 Schematic diagram of a shift register provided in some other embodiments of the present disclosure, such as Figure 4As shown, the second control subcircuit 30 of the shift register includes: a fourteenth transistor M14, a seventh transistor M7 and a second transistor M2. The control electrode of the fourteenth transistor M14 is electrically connected to the second node n2, and the first electrode of the fourteenth transistor M14 is electrically connected to the second level terminal V2. The control electrode of the seventh transistor M7 is electrically connected to the second node n2, and the first electrode of the seventh transistor M7 and the second electrode of the fourteenth transistor M14 are connected to the sixth node n6. The control electrode of the second transistor M2 is electrically connected to the second clock signal terminal CKB, the first electrode of the second transistor M2 and the second electrode of the seventh transistor M7 are connected to the third node n3, and the second electrode of the second transistor M2 is electrically connected to the first node n1. When the second node n2 is at the first level potential and the second clock signal terminal CKB provides the first level signal, the fourteenth transistor M14, the seventh transistor M7 and the second transistor M2 are turned on, so as to transmit the second level signal of the second level terminal V2 to the first node n1.

[0088] like Figure 4 As shown, the shift register also includes a second anti-leakage electronic circuit 70, which is electrically connected to the sixth node n6 and the first node n1, and is configured to, at least in response to the control of the first node n1, transmit the first level signal to the sixth node n6 to reduce the voltage between the control electrode and the second electrode of the fourteenth transistor M14 and the voltage between the control electrode and the first electrode of the seventh transistor M7, thereby reducing the leakage of the transistor between the first node n1 and the second level end V2 due to the threshold voltage offset, which is beneficial to maintain the voltage of the third node n3 and reduce the output abnormality of the third node n3 caused by leakage.

[0089] Figure 5 is a schematic diagram of a shift register provided in some other embodiments of the present disclosure, Figure 5 The shift register shown in FIG. Figure 4 A specific implementation of Figure 5 As shown, the input subcircuit 10 includes a first transistor M1, a control electrode of the first transistor M1 is electrically connected to the first clock signal terminal CLK, a first electrode is electrically connected to the input terminal EIN, and a second electrode is electrically connected to the first node n1. When the first clock signal terminal CLK provides a first level signal, the first transistor M1 is turned on, thereby transmitting the signal of the input terminal EIN to the first node n1.

[0090] like Figure 5As shown, the first control subcircuit 20 includes: a fifth transistor M5 and a sixth transistor M6, wherein the control electrode of the fifth transistor M5 is electrically connected to the first node n1, the first electrode is electrically connected to the first clock signal terminal CLK, and the second electrode is electrically connected to the second node n2. The control electrode of the sixth transistor M6 is electrically connected to the first clock signal terminal CLK, the first electrode is electrically connected to the first level terminal V1, and the second electrode is electrically connected to the second node n2. When the first node n1 is at the first level potential, the fifth transistor M5 is turned on, thereby transmitting the signal of the first clock signal terminal CLK to the second node n2; when the first clock signal terminal CLK provides a first level signal, the sixth transistor M6 is turned on, thereby transmitting the signal of the first level terminal V1 to the second node n2.

[0091] The second control subcircuit 30 includes: a fourteenth transistor M14, a seventh transistor M7, and a second transistor M2. The control electrode of the fourteenth transistor M14 is electrically connected to the second node n2, and the first electrode of the fourteenth transistor M14 is electrically connected to the second level terminal V2. The control electrode of the seventh transistor M7 is electrically connected to the second node n2, and the first electrode of the seventh transistor M7 and the second electrode of the fourteenth transistor M14 are connected to the sixth node n6. The control electrode of the second transistor M2 is electrically connected to the second clock signal terminal CKB, the first electrode of the second transistor M2 is electrically connected to the second electrode of the seventh transistor M7, and the second electrode of the second transistor M2 is electrically connected to the first node n1. When the second node n2 is at the first level potential and the second clock signal terminal CKB provides the first level signal, the fourteenth transistor M14, the seventh transistor M7, and the second transistor M2 are turned on, thereby transmitting the second level signal of the second level terminal V2 to the first node n1.

[0092] The first output subcircuit 40 includes: a third transistor M3 and a third capacitor C3, wherein the control electrode of the third transistor M3 is electrically connected to the first node n1, the first electrode is electrically connected to the first level terminal V1, and the second electrode is electrically connected to the output terminal EOUT. The two ends of the third capacitor C3 are electrically connected to the first node n1 and the second clock signal terminal CKB, respectively. When the first node n1 is at the first level potential, the third transistor M3 is turned on, thereby transmitting the first level signal of the first level terminal V1 to the output terminal EOUT; and when the first node n1 is in a floating state, under the voltage stabilization effect of the third capacitor C3, the first node n1 can still maintain the voltage of the previous stage.

[0093] The second output subcircuit 50 includes: a first output control unit 51, a second output control unit 52 and an output unit 53. The first output control unit 51 and the second output control unit 52 are connected to the fourth node n4, and the second output control unit 52 and the output unit 53 are connected to the fifth node n5. The first output control unit 51 is configured to transmit the signal of the second clock signal terminal CKB to the fourth node n4 in response to the control of the second node n2. The second output control unit 52 is configured to transmit the signal of the fourth node n4 to the fifth node n5 in response to the control of the second clock signal terminal CKB; and transmit the second level signal to the fifth node n5 in response to the control of the first node n1. The output unit 53 is configured to transmit the first level signal to the output terminal EOUT in response to the control of the fifth node n5.

[0094] Specifically, the first output control unit 51 can be configured to transmit the signal of the second clock signal terminal CKB to the fourth node n4 in response to the first level signal of the second node n2; and disconnect the second clock signal terminal CKB from the fourth node n4 in response to the second level signal of the second node n2; and keep the voltage between the second node n2 and the fourth node n4 unchanged when the second node n2 is floating. The second output control unit 52 can be configured to connect the fourth node n4 with the fifth node n5 in response to the first level signal of the second clock signal terminal CKB; and connect the fifth node n5 with the second level terminal V2 in response to the first level signal of the first node n1. The output unit 53 can be configured to transmit the second level signal of the second level terminal V2 to the output terminal EOUT in response to the first level signal of the fifth node n5, and keep the voltage between the second level terminal V2 and the fifth node n5 unchanged when the fifth node n5 is floating.

[0095] like Figure 5 As shown, the first output control unit 51 may include: an eighth transistor M8 and a second capacitor C2, wherein the control electrode of the eighth transistor M8 is electrically connected to the second node n2, the first electrode is electrically connected to the second clock signal terminal CKB, and the second electrode is electrically connected to the fourth node n4; the two ends of the second capacitor C2 are electrically connected to the second node n2 and the fourth node n4, respectively. When the second node n2 is at the first level potential, the eighth transistor M8 is turned on, thereby transmitting the signal of the second clock signal terminal CKB to the fourth node n4. When the second node n2 is in a floating state, under the bootstrap effect of the second capacitor C2, the voltage between the second node n2 and the fourth node n4 remains unchanged.

[0096] like Figure 5As shown, the second output control unit 52 includes: a ninth transistor M9 and a tenth transistor M10. The control electrode of the ninth transistor M9 is electrically connected to the second clock signal terminal CKB, the first electrode is electrically connected to the fourth node n4, and the second electrode is electrically connected to the fifth node n5. The control electrode of the tenth transistor M10 is electrically connected to the first node n1, the first electrode is electrically connected to the second level terminal V2, and the second electrode is electrically connected to the fifth node n5. When the second clock signal terminal CKB provides a first level signal, the ninth transistor M9 is turned on, thereby connecting the fourth node n4 to the fifth node n5; when the first node n1 is at the first level potential, the tenth transistor M10 is turned on, thereby connecting the second level terminal V2 to the fifth node n5.

[0097] like Figure 5 As shown, the output unit 53 includes: a first capacitor C1 and a fourth transistor M4. The two ends of the first capacitor C1 are electrically connected to the second level terminal V2 and the fifth node n5, respectively. The control electrode of the fourth transistor M4 is electrically connected to the fifth node n5, the first electrode is electrically connected to the second level terminal V2, and the second electrode is electrically connected to the output terminal EOUT. When the fifth node n5 is at the first level potential, the fourth transistor M4 is turned on, thereby transmitting the second level signal of the second level terminal V2 to the output terminal EOUT; when the fifth node n5 is at the second level potential, the fourth transistor M4 disconnects the second level terminal V2 from the output terminal EOUT; when the fifth node n5 is floating, under the voltage stabilization effect of the first capacitor C1, the fifth node n5 can still maintain the voltage of the previous stage.

[0098] like Figure 5 As shown, the first anti-leakage electronic circuit 60 includes a twelfth transistor M12, the control electrode and the first electrode of the twelfth transistor M12 are both electrically connected to the first level terminal V1, and the second electrode of the twelfth transistor M12 is electrically connected to the second node n2. At this time, the twelfth transistor M12 is in a continuous conduction state, so as to continuously supply power to the second node n2.

[0099] like Figure 5 As shown, the second anti-leakage electronic circuit 70 includes a fifteenth transistor M15, wherein the control electrode of the fifteenth transistor M15 is electrically connected to the first node n1, the first electrode of the fifteenth transistor M15 is electrically connected to the first level terminal V1, and the second electrode of the fifteenth transistor M15 is electrically connected to the sixth node n6. When the first node n1 is at a first level potential, the fifteenth transistor M15 transmits the first level signal of the first level terminal V1 to the sixth node n6; when the first node n1 is at a second level potential, the fifteenth transistor M15 disconnects the first level terminal V1 from the sixth node n6.

[0100] Figure 6 for Figure 5 The working timing diagram of the shift register shown below is combined with Figure 5 to Figure 6 The working process of the shift register in the embodiment of the present disclosure is introduced, wherein each transistor in the shift register is an N-type transistor as an example for explanation, in which the high level signal is used as the first level signal, and the low level signal is used as the second level signal.

[0101] In the first stage t1, the input terminal EIN and the second clock signal terminal CKB both provide low-level signals, and the first clock signal terminal CLK provides a high-level signal. At this time, the first transistor M1 is turned on, so that the low-level signal of the input terminal EIN is transmitted to the first node n1, and then the third transistor M3, the fifth transistor M5 and the fifteenth transistor M15 are controlled to be turned off. In addition, the sixth transistor M6 and the twelfth transistor M12 are turned on, so that the high-level signal of the first level terminal V1 is transmitted to the second node n2. Since the second node n2 receives a high-level signal, the seventh transistor M7, the fourteenth transistor M14 and the eighth transistor M8 are turned on, and the low-level signal of the second clock signal terminal CKB is transmitted to the fourth node n4 through the eighth transistor M8. At the same time, the ninth transistor M9 and the tenth transistor M10 are both turned off, the fifth node n5 maintains the low-level potential of the previous stage, and the fourth transistor M4 maintains the disconnected state of the previous stage. Since there is no discharge path at the output terminal EOUT, the high-level signal of the previous stage is kept output.

[0102] In the second stage t2, the input terminal EIN and the first clock signal terminal CLK both provide low-level signals, and the second clock signal terminal CKB provides a high-level signal. At this time, the first transistor M1 and the sixth transistor M6 are turned off, and under the voltage stabilization of the third capacitor C3, the first node n1 maintains a low-level potential, thereby controlling the third transistor M3, the fifth transistor M5 and the fifteenth transistor M15 to be turned off. The twelfth transistor M12 is turned on, so that the second node n2 is at a high-level potential, thereby controlling the fourteenth transistor M14, the seventh transistor M7 and the eighth transistor M8 to be turned on. In addition, the second transistor M2 is turned on, so that the low-level signal of the second level terminal V2 is transmitted to the first node n1, and the tenth transistor M10 is turned off. The high level signal of the second clock signal terminal CKB is transmitted to the fourth node n4 through the eighth transistor M8, and since the ninth transistor M9 is turned on under the control of the high level signal provided by the second clock signal terminal CKB, the fifth node n5 receives the high level signal of the fourth node n4, thereby controlling the fourth transistor M4 to be turned on, and the low level signal of the second level terminal V2 is transmitted to the output terminal EOUT.

[0103] In the third stage t3, the input terminal EIN and the second clock signal terminal CKB provide a low level signal, and the first clock signal terminal CLK provides a high level signal. At this time, the first transistor M1 is turned on, so that the low level signal of the input terminal EIN is transmitted to the first node n1, thereby controlling the third transistor M3, the fifth transistor M5 and the tenth transistor M10 to remain turned off. At the same time, the sixth transistor M6 and the twelfth transistor M12 are turned on, so that the second node n2 receives a high level signal to control the seventh transistor M7, the fourteenth transistor M14 and the eighth transistor M8 to be turned on. Since the eighth transistor M8 is turned on, the low level signal of the second clock signal terminal CKB is transmitted to the fourth node n4. The second transistor M2 and the ninth transistor M9 are turned off under the control of the low level signal of the second clock signal terminal CKB. The fifth node n5 maintains the high level potential of the previous stage under the energy storage effect of the first capacitor C1, so that the fourth transistor M4 remains in the on state, and the second level signal of the second level terminal V2 is transmitted to the output terminal EOUT.

[0104] In the fourth stage t4, the input terminal EIN and the second clock signal terminal CKB both provide high level signals, and the first clock signal terminal CLK provides a low level signal. At this time, the on-off state of each transistor and the potential of each node are the same as those in the second stage t2, which will not be repeated here.

[0105] In the fifth stage t5, the input terminal EIN and the first clock signal terminal CLK both provide high-level signals, and the second clock signal terminal CKB provides a low-level signal. At this time, the first transistor M1 is turned on, thereby transmitting the high-level signal of the input terminal EIN to the first node n1, thereby controlling the fifteenth transistor M15 and the third transistor M3 to be turned on, and the first-level signal of the first level terminal V1 is transmitted to the output terminal EOUT via the third transistor M3. At the same time, the fifth transistor M5, the sixth transistor M6 and the twelfth transistor M12 are turned on, so that in the fifth stage t5, the second node n2 receives a high-level signal; in the interval stage t5-1 after the fifth stage t5, due to the discharge effect of the fifth transistor M5 on the second node n2, the second node n2 is reduced to a low-level potential. When the second node n2 is at a high level, the seventh transistor M7, the fourteenth transistor M14 and the eighth transistor M8 are turned on, and the low level signal of the second clock signal terminal CKB is transmitted to the fourth node n4 through the eighth transistor M8; the sixth node n6 and the third node n3 are turned on; when the second node n2 is at a low level potential, the seventh transistor M7, the fourteenth transistor M14 and the eighth transistor M8 are turned off, if the threshold voltages of the fourteenth transistor M14 and the fifteenth transistor M15 are equal, then the voltage of the sixth node n6 = (V1-V2) / 2; if the threshold voltages of the fourteenth transistor M14 and the fifteenth transistor M15 are different, then the voltage of the sixth node n6 is close to the voltage of the level end connected to the one with the smaller threshold voltage of the fourteenth transistor M14 and the fifteenth transistor M15.

[0106] In addition, in the fifth stage t5 and the interval stage t5-1, since the second clock signal terminal CKB provides a low level signal, the second transistor M2 and the ninth transistor M9 are turned off. Since the first node n1 receives a high level signal, the tenth transistor M10 is turned on, thereby transmitting the low level signal of the second level terminal V2 to the fifth node n5, thereby keeping the fourth transistor M4 in the off state.

[0107] In the sixth stage t6, the input terminal EIN and the second clock signal terminal CKB provide a high level signal, and the first clock signal terminal CLK provides a low level signal. At this time, the first transistor M1 is turned off, and the first node n1 maintains a high level potential under the energy storage effect of the third capacitor C3, thereby controlling the third transistor M3 to be turned on, and the first level signal of the first level terminal V1 is transmitted to the output terminal EOUT; thereby further increasing the potential of the first node n1. At the same time, the sixth transistor M6 is turned off, and the fifth transistor M5 is turned on, so that the second node n2 can continue to be discharged, so that its potential is reduced, and then the seventh transistor M7, the fourteenth transistor M14 and the eighth transistor M8 are turned off. Since the first node n1 is at a high level potential, the fifteenth transistor M15 is turned on, and the potential of the sixth node n6 is pulled up. In addition, since the second clock signal terminal CKB provides a high level signal, the second transistor M2 and the ninth transistor M9 are turned on. Since the first node n1 is at a high level potential, the tenth transistor M10 is turned on, thereby transmitting the low level signal of the second level end V2 to the fifth node n5, thereby keeping the fourth transistor M4 in the off state.

[0108] There may also be a first holding stage t31 and a second holding stage t32 between the third stage t3 and the fourth stage t4. In the first holding stage t31, the on-off state of each transistor and the potential of each node are the same as those in the second stage t2; in the second holding stage t32, the on-off state of each transistor and the potential of each node are the same as those in the third stage t3.

[0109] Figure 7 is a schematic diagram of a shift register provided in some other embodiments of the present disclosure, Figure 7 for Figure 4 Another specific implementation of the shift register shown in . Figure 7 The shift register shown is Figure 5 Similarly, the difference lies in the specific structures of the first anti-leakage electronic circuit 60 and the second anti-leakage electronic circuit 70. Figure 7In the embodiment, the first anti-leakage electronic circuit 60 and the second anti-leakage electronic circuit 70 are connected to the seventh node n7, and the first anti-leakage electronic circuit 60 is further configured to transmit the first level signal to the seventh node n7 in response to the input signal. The first anti-leakage electronic circuit 60 includes: an eleventh transistor M11 and a twelfth transistor M12. The control electrode of the eleventh transistor M11 is electrically connected to the input terminal EIN, and the first electrode of the eleventh transistor M11 is electrically connected to the first level terminal V1. The control electrode of the twelfth transistor M12 is electrically connected to the second electrode of the eleventh transistor M11, the first electrode of the twelfth transistor M12 is electrically connected to the first level terminal V1, and the second electrode of the twelfth transistor M12 is electrically connected to the second node n2. When the input terminal EIN provides the first level signal, the eleventh transistor M11 and the twelfth transistor M12 are turned on, thereby supplying power to the second node n2.

[0110] like Figure 7 As shown, the second anti-leakage electronic circuit 70 includes: a thirteenth transistor M13 and a fifteenth transistor M15, wherein the control electrode of the thirteenth transistor M13 is electrically connected to the seventh node n7, the first electrode is electrically connected to the second level terminal V2, and the second electrode is electrically connected to the sixth node n6. The control electrode of the fifteenth transistor M15 is electrically connected to the first node n1, the first electrode is electrically connected to the first level terminal V1, and the second electrode is electrically connected to the sixth node n6.

[0111] Figure 7 The shift register operation timing and Figure 6 The same. In the first stage t1, the input terminal EIN and the second clock signal terminal CKB both provide low-level signals, and the first clock signal terminal CLK provides a high-level signal. At this time, the first transistor M1 is turned on, so that the low-level signal of the input terminal EIN is transmitted to the first node n1, and then the third transistor M3, the fifth transistor M5 and the fifteenth transistor M15 are controlled to be turned off. In addition, the sixth transistor M6 is turned on, so that the high-level signal of the first level terminal V1 is transmitted to the second node n2. Since the second node n2 receives a high-level signal, the seventh transistor M7, the fourteenth transistor M14 and the eighth transistor M8 are turned on, and the low-level signal of the second clock signal terminal CKB is transmitted to the fourth node n4 through the eighth transistor M8. At the same time, the ninth transistor M9 and the tenth transistor M10 are both turned off, the fifth node n5 maintains the low-level potential of the previous stage, and the fourth transistor M4 maintains the disconnected state of the previous stage. Since there is no discharge path at the output terminal EOUT, the high-level signal of the previous stage is output.

[0112] In the second stage t2, the input terminal EIN and the first clock signal terminal CLK both provide low-level signals, and the second clock signal terminal CKB provides a high-level signal. At this time, the first transistor M1 and the sixth transistor M6 are turned off, and under the voltage stabilization of the third capacitor C3, the first node n1 maintains a low-level potential, thereby controlling the third transistor M3, the fifth transistor M5 and the fifteenth transistor M15 to be turned off. Under the energy storage effect of the second capacitor C2, the second node n2 maintains a high-level potential, thereby controlling the fourteenth transistor M14, the seventh transistor M7 and the eighth transistor M8 to be turned on. In addition, the second transistor M2 is turned on, thereby transmitting the low-level signal of the second level terminal V2 to the first node n1, and the tenth transistor M10 is turned off. The high level signal of the second clock signal terminal CKB is transmitted to the fourth node n4 through the eighth transistor M8, and since the ninth transistor M9 is turned on under the control of the high level signal provided by the second clock signal terminal CKB, the fifth node n5 receives the high level signal of the fourth node n4, thereby controlling the fourth transistor M4 to be turned on, and the low level signal of the second level terminal V2 is transmitted to the output terminal EOUT.

[0113] In the third stage t3, the input terminal EIN and the second clock signal terminal CKB provide a low level signal, and the first clock signal terminal CLK provides a high level signal. At this time, the eleventh transistor M11, the twelfth transistor M12, the thirteenth transistor M13 and the fifteenth transistor M15 are all turned off, and the conduction state of the remaining transistors is the same as Figure 5 The states of the transistors in the third stage t3 are the same, which will not be described in detail here.

[0114] In the fourth stage t4, the input terminal EIN and the second clock signal terminal CKB both provide high-level signals, and the first clock signal terminal CLK provides a low-level signal. At this time, the first transistor M1 and the sixth transistor M6 are turned off, and under the voltage stabilization of the third capacitor C3, the first node n1 maintains a low-level potential, thereby controlling the third transistor M3, the fifth transistor M5 and the fifteenth transistor M15 to be turned off. At the same time, the eleventh transistor M11 and the twelfth transistor M12 are turned on, thereby transmitting the high-level signal of the first level terminal V1 to the second node n2, thereby controlling the fourteenth transistor M14, the seventh transistor M7 and the eighth transistor M8 to be turned on. In addition, the thirteenth transistor M13 and the second transistor M2 are turned on, thereby transmitting the low-level signal of the second level terminal V2 to the sixth node n6, the third node n3 and the first node n1, and the tenth transistor M10 and the fifteenth transistor M15 are turned off. The high level signal of the second clock signal terminal CKB is transmitted to the fourth node n4 through the eighth transistor M8, and since the ninth transistor M9 is turned on under the control of the high level signal provided by the second clock signal terminal CKB, the fifth node n5 receives the high level signal of the fourth node n4, thereby controlling the fourth transistor M4 to be turned on, and the low level signal of the second level terminal V2 is transmitted to the output terminal EOUT.

[0115] In the fifth stage t5, the input terminal EIN and the first clock signal terminal CLK both provide high level signals, and the second clock signal terminal CKB provides a low level signal. In this stage, the eleventh transistor M11, the twelfth transistor M12, the thirteenth transistor M13 and the fifteenth transistor M15 are all turned on, and the on-off states of the remaining transistors and the voltages of the nodes are all referred to in the Figure 5 The description will not be repeated here.

[0116] In the sixth stage t6, the input terminal EIN and the second clock signal terminal CKB provide a high level signal, and the first clock signal terminal CLK provides a low level signal. At this time, the eleventh transistor M11, the twelfth transistor M12, the thirteenth transistor M13 and the fifteenth transistor M15 are turned on, and the on-off states of the remaining transistors and the voltages of the nodes are all referred to in Figure 5 The description will not be repeated here.

[0117] There may also be a first holding stage t31 and a second holding stage t32 between the third stage t3 and the fourth stage t4. In the first holding stage t31, the on-off state of each transistor and the potential of each node are the same as those in the second stage t2; in the second holding stage t32, the on-off state of each transistor and the potential of each node are the same as those in the third stage t3.

[0118] Figure 8 is a schematic diagram of a shift register provided in some other embodiments of the present disclosure, Figure 8 for Figure 4Another specific implementation of the shift register shown in . Figure 8 The shift register shown is Figure 7 Similar, except that Figure 8 In the embodiment, the thirteenth transistor M13 is electrically connected to the sixth node n6 through the fourth capacitor C4. By providing the fourth capacitor C4 between the sixth node n6 and the thirteenth transistor M13, it is beneficial to maintain the potential of the sixth node n6, so that when the seventh transistor M7 and the fourteenth transistor M14 have a large negative offset, the seventh transistor M7 and the fourteenth transistor M14 can still prevent leakage of the sixth node n6. Figure 8 The shift register and Figure 7 The working process of the shift register is the same and will not be repeated here.

[0119] The present disclosure also provides a shift register driving method. Fig. 9 Schematic diagram of a driving method of a shift register provided in some embodiments of the present disclosure, such as Fig. 9 As shown, the driving method includes:

[0120] In the first stage, the input end and the first clock signal end both provide a first level signal, the second clock signal provides a second level signal, the input subcircuit transmits the signal of the input end to the first node, and the first output subcircuit disconnects the output end from the first level end; the first control subcircuit and the first leakage prevention electronic circuit provide the first level signal to the second node, and the second output subcircuit maintains the disconnection state between the second level end and the output end; the output end keeps outputting the first level signal of the previous stage.

[0121] In the second stage, the input end and the first clock signal end both provide second level signals, the second clock signal end provides a first level signal, the second control subcircuit transmits the second level signal of the second level end to the first node, and the second output subcircuit transmits the second level signal of the second signal end to the output end.

[0122] In the third stage, the input terminal and the second clock signal terminal both provide a second level signal, the first clock signal terminal provides a first level signal, the first control subcircuit transmits the first level signal of the first level terminal to the second node, and the second output subcircuit maintains the conduction state between the second level terminal and the output terminal.

[0123] In the fourth stage, the input terminal and the second clock signal terminal both provide a first level signal, the first clock signal terminal provides a second level signal, the second control subcircuit transmits the second level signal of the second level terminal to the first node, and the first leakage prevention electronic circuit provides the first level signal to the second node; the second output subcircuit transmits the second level signal of the second signal terminal to the output terminal.

[0124] In the fifth stage, the input terminal and the first clock signal terminal both provide a first level signal, the second clock signal terminal provides a second level signal, the input sub-circuit transmits the first level signal of the input terminal to the first node, the first leakage prevention electronic circuit provides the first level signal to the second node, the second output sub-circuit disconnects the output terminal from the second level terminal; the first output sub-circuit transmits the first level signal of the first level signal terminal to the output terminal.

[0125] The working process of the shift register is specifically described above and will not be repeated here.

[0126] The disclosed embodiment also provides a gate drive circuit, which includes a plurality of cascaded shift registers, wherein each shift register is a shift register in the above embodiment. In two adjacent shift registers, the output end of the previous shift register is electrically connected to the input end of the next shift register.

[0127] An embodiment of the present disclosure further provides a display device, which includes the above-mentioned gate driving circuit.

[0128] In some embodiments, the display device is an OLED display device, which includes a display substrate, the display substrate includes a base substrate and a plurality of pixel units arranged on the base substrate, each pixel unit includes a light-emitting device and a pixel circuit electrically connected to the light-emitting device, and the plurality of pixel circuits can be arranged in an array, and each row of pixel circuits is electrically connected to a gate line and a light-emitting control line to receive a scanning signal on the gate line and a light-emitting control signal on the light-emitting control line. The gate drive circuit in the above embodiment can be arranged on the base substrate and provide light-emitting control signals to the plurality of light-emitting control lines in sequence.

[0129] It is to be understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of the present disclosure, but the present disclosure is not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and substance of the present disclosure, and these modifications and improvements are also considered to be within the scope of protection of the present disclosure.

Claims

1. A shift register, include: an input subcircuit configured to transmit an input signal at the input terminal to the first node in response to control of the first clock signal terminal; A first control subcircuit is configured to transmit the signal of the first clock signal terminal to the second node in response to the control of the first node; and transmitting the first level signal of the first level terminal to the second node in response to the control of the first clock signal terminal; a second control subcircuit configured to transmit the second level signal of the second level terminal to the first node in response to control of the second node and the second clock signal terminal; a first output sub-circuit configured to transmit the first level signal at the first level end to the output end of the shift register in response to control of the first node; A second output sub-circuit, configured to connect the second level terminal to the output terminal in response to control of the first node, the second node and the second clock signal terminal; a first leakage-proof electronic circuit configured to provide the first level signal to the second node at least when the first level signal is provided at the input terminal; The first node is a connection node between the input sub-circuit, the first control sub-circuit and the second control sub-circuit, and the second node is a connection node between the first control sub-circuit and the second control sub-circuit.

2. The shift register according to claim 1, in, The first leakage-proof electronic circuit comprises: A twelfth transistor, wherein the control electrode and the first electrode of the twelfth transistor are both electrically connected to the first level end, and the second electrode of the twelfth transistor is electrically connected to the second node.

3. The shift register according to claim 1, in, The first leakage-proof electronic circuit comprises: an eleventh transistor, a control electrode of the eleventh transistor being electrically connected to the input terminal, and a first electrode of the eleventh transistor being electrically connected to the first level terminal; A twelfth transistor, wherein a control electrode of the twelfth transistor is electrically connected to the second electrode of the eleventh transistor, a first electrode of the twelfth transistor is electrically connected to the first level end, and a second electrode of the twelfth transistor is electrically connected to the second node.

4. The shift register according to claim 1, in, The second control subcircuit comprises: a fourteenth transistor, wherein a control electrode of the fourteenth transistor is electrically connected to the second node, and a first electrode of the fourteenth transistor is electrically connected to the second level end; a seventh transistor, wherein a control electrode of the seventh transistor is electrically connected to the second node, and a first electrode of the seventh transistor and a second electrode of the fourteenth transistor are connected to a sixth node; a second transistor, wherein a control electrode of the second transistor is electrically connected to the second clock signal terminal, a first electrode of the second transistor is electrically connected to the second electrode of the seventh transistor, and a second electrode of the second transistor is electrically connected to the first node; The shift register further includes a second leakage prevention electronic circuit configured to transmit the first level signal to the sixth node in response to at least control of the first node.

5. The shift register according to claim 4, in, The second leakage-proof electronic circuit comprises: A fifteenth transistor, wherein the control electrode of the fifteenth transistor is electrically connected to the first node, the first electrode is electrically connected to the first level end, and the second electrode is electrically connected to the sixth node.

6. The shift register according to claim 4, in, The first leakage prevention electronic circuit and the second leakage prevention electronic circuit are connected to a seventh node, and the first leakage prevention electronic circuit is further configured to transmit the first level signal to the seventh node in response to the input signal; The second leakage-proof electronic circuit comprises: a thirteenth transistor, a control electrode of which is electrically connected to the seventh node, a first electrode of which is electrically connected to the second level end, and a second electrode of which is directly electrically connected to the sixth node or electrically connected to the sixth node through a fourth capacitor; A fifteenth transistor has a control electrode electrically connected to the first node, a first electrode electrically connected to the first level end, and a second electrode electrically connected to the sixth node.

7. The shift register according to any one of claims 1 to 6, in, The input subcircuit includes a first transistor, a control electrode of the first transistor is electrically connected to the first clock signal terminal, a first electrode is electrically connected to the input terminal, and a second electrode is electrically connected to the first node.

8. The shift register according to any one of claims 1 to 6, in, The first control subcircuit comprises: a fifth transistor, wherein a control electrode of the fifth transistor is electrically connected to the first node, a first electrode of the fifth transistor is electrically connected to the first clock signal terminal, and a second electrode of the fifth transistor is electrically connected to the second node; A sixth transistor, wherein a control electrode of the sixth transistor is electrically connected to the first clock signal end, a first electrode is electrically connected to the first level end, and a second electrode is electrically connected to the second node.

9. The shift register according to any one of claims 1 to 6, in, The first output sub-circuit comprises: a third transistor, wherein a control electrode of the third transistor is electrically connected to the first node, a first electrode of the third transistor is electrically connected to the first level end, and a second electrode of the third transistor is electrically connected to the output end; A third capacitor, wherein two ends of the third capacitor are electrically connected to the first node and the second clock signal end respectively.

10. The shift register according to any one of claims 1 to 6, in, The second output subcircuit comprises: a first output control unit, a second output control unit and an output unit; the first output control unit and the second output control unit are connected to a fourth node, and the second output control unit and the output unit are connected to a fifth node; The first output control unit is configured to transmit the signal of the second clock signal terminal to the fourth node in response to the control of the second node; The second output control unit is configured to transmit the signal of the fourth node to the fifth node in response to the control of the second clock signal terminal; and transmit the second level signal to the fifth node in response to the control of the first node; The output unit is configured to transmit the first level signal to the output terminal in response to control of the fifth node.

11. The shift register according to claim 10, in, The first output control unit comprises: an eighth transistor, wherein a control electrode of the eighth transistor is electrically connected to the second node, a first electrode is electrically connected to the second clock signal terminal, and a second electrode is electrically connected to the fourth node; A second capacitor, wherein two ends of the second capacitor are electrically connected to the second node and the fourth node respectively.

12. The shift register according to claim 10, in, The second output control unit comprises: a ninth transistor, wherein a control electrode of the ninth transistor is electrically connected to the second clock signal terminal, a first electrode of the ninth transistor is electrically connected to the fourth node, and a second electrode of the ninth transistor is electrically connected to the fifth node; A tenth transistor, wherein a control electrode of the tenth transistor is electrically connected to the first node, a first electrode is electrically connected to the second level end, and a second electrode is electrically connected to the fifth node.

13. The shift register according to claim 10, in, The output unit comprises: a first capacitor, wherein two ends of the first capacitor are electrically connected to the second level end and the fifth node respectively; A fourth transistor, wherein a control electrode of the fourth transistor is electrically connected to the fifth node, a first electrode is electrically connected to the second level end, and a second electrode is electrically connected to the output end.

14. A method for driving a shift register according to any one of claims 1 to 13, include: In the first stage, the input terminal and the first clock signal terminal both provide a first level signal, the second clock signal terminal provides a second level signal, the input subcircuit transmits the signal of the input terminal to the first node, and the first output subcircuit disconnects the output terminal from the first level terminal; The first control subcircuit and the first anti-leakage electronic circuit provide a first level signal for the second node, and the second output subcircuit maintains a disconnection state between the second level terminal and the output terminal; The output end keeps outputting the first level signal of the previous stage; In the second stage, the input terminal and the first clock signal terminal both provide a second level signal, the second clock signal terminal provides a first level signal, the second control subcircuit transmits the second level signal of the second level terminal to the first node, and the second output subcircuit transmits the second level signal of the second signal terminal to the output terminal; In the third stage, the input terminal and the second clock signal terminal both provide a second level signal, the first clock signal terminal provides a first level signal, the first control subcircuit transmits the first level signal of the first level terminal to the second node, and the second output subcircuit maintains a conductive state between the second level terminal and the output terminal; In the fourth stage, the input terminal and the second clock signal terminal both provide a first level signal, the first clock signal terminal provides a second level signal, the second control subcircuit transmits the second level signal of the second level terminal to the first node, and the first anti-leakage electronic circuit provides the first level signal to the second node; The second output subcircuit transmits the second level signal of the second signal terminal to the output terminal; In the fifth stage, the input terminal and the first clock signal terminal both provide a first level signal, the second clock signal terminal provides a second level signal, the input subcircuit transmits the first level signal of the input terminal to the first node, the first anti-leakage electronic circuit provides the first level signal for the second node, and the second output subcircuit disconnects the output terminal from the second level terminal; The first output sub-circuit transmits the first level signal of the first level signal terminal to the output terminal.

15. A gate driving circuit comprising a plurality of cascaded shift registers according to any one of claims 1 to 13.

16. A display device comprising the gate driving circuit according to claim 15.

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