T-type three-level circuit fault wave sealing recovery processing method

Abstract

The invention discloses a T-type three-level circuit fault wave sealing recovery processing method, which comprises the following steps of: increasing driving signal response time and / or wave sealing recovery signal response time of a vertical tube relative to a transverse tube, so that the vertical tube is conducted with the transverse tube after wave sealing recovery. Or only the vertical pipe is subjected to hardware wave sealing treatment, and the transverse pipe is always in a conducting state; when wave sealing recovery is carried out, the vertical pipe is conducted with the transverse pipe based on the hardware wave sealing structure. Compared with a traditional mode, the device has the advantages that it can be guaranteed that the normally-closed transverse pipe is conducted earlier than the high-frequency vertical pipe in the wave sealing recovery process of the system, the overvoltage risk of the high-frequency transverse pipe is avoided, and the stability of the system is improved.

Description

Technical Field

[0001] The present application relates to the technical field of renewable energy power generation, and in particular to a method for processing a fault-enclosing wave of a T-type three-level circuit. Background Art

[0002] The T-type three-level circuit is a circuit structure widely used in the field of power electronics, especially in inverter design. Its basic structure consists of four switching tubes and related diodes, capacitors and other components. These switching tubes are arranged in a specific way to form a shape similar to the letter "T".

[0003] When a fault occurs in a T-type three-level circuit, the switch tube will be controlled to enter the wave blocking mode based on its own fault protection measures. After the fault is eliminated, the switch tube can be restored to wave. However, when the conventional T-type three-level circuit fault wave blocking is restored, there is no specific restriction on the recovery timing of the switch tube, which only depends on the timing corresponding to the conventional modulation. Therefore, when the fault wave blocking is restored, the high-frequency vertical tube corresponding to the positive and negative cycles of the current may be restored to conduction before the normally closed horizontal tube, causing the high-frequency horizontal tube to be subject to the risk of overvoltage, resulting in system failure. Summary of the invention

[0004] One of the objectives of the present application is to provide a T-type three-level circuit fault envelope recovery processing method that can solve at least one defect in the above-mentioned background technology.

[0005] In order to achieve at least one of the above-mentioned purposes, the technical solution adopted in the present application is: a T-type three-level circuit fault wave recovery processing method, comprising the following steps: increasing the drive signal response time and / or the wave recovery signal response time of the vertical tube relative to the horizontal tube, so that when the vertical tube is performing wave recovery, the vertical tube is turned on after the horizontal tube.

[0006] Preferably, the vertical tube responds to the driving signal through the vertical tube driving circuit, and the horizontal tube responds to the driving signal through the horizontal tube driving circuit; by increasing the response time of the vertical tube driving circuit to the driving signal and / or shortening the response time of the horizontal tube driving circuit to the driving signal, the vertical tube is turned on after the horizontal tube when the vertical tube performs wave recovery.

[0007] Preferably, the vertical tube driving circuit and the horizontal tube driving circuit both include a driving chip, an on-resistance and a gate capacitor; the driving chip is connected in series with the on-resistance, and the gate capacitor is connected in parallel with the on-resistance to form an RC control circuit; the response time of the driving signal is controlled by adjusting the resistance of the on-resistance and / or the capacitance of the gate capacitor.

[0008] Preferably, the wave sealing recovery signal is generated by a wave sealing system, which includes a wave sealing signal generating module, a latch module, a horizontal pipe wave sealing unit and a vertical pipe wave sealing unit; the wave sealing signal generating module is suitable for outputting a wave sealing recovery signal, the input end of the vertical pipe wave sealing unit is signal-connected with the wave sealing signal generating module through the latch module, the output end of the vertical pipe wave sealing unit is suitable for sending a conduction signal to the vertical pipe, and the latch module is suitable for delaying the wave sealing recovery signal sent by the wave sealing signal generating module; the input end of the horizontal pipe wave sealing unit is signal-connected with the wave sealing signal generating module, and the output end of the horizontal pipe wave sealing unit is suitable for sending a conduction signal to the horizontal pipe.

[0009] Preferably, the latch module includes a latch unit and a delay unit; the output of the horizontal pipe wave sealing unit serves as the input of the delay unit, and the output of the delay unit and the output of the wave sealing signal generating module both serve as the input of the latch unit, and then the latch unit sends the delayed wave sealing recovery signal to the vertical pipe wave sealing unit.

[0010] Preferably, the delay unit adopts an RC circuit structure.

[0011] Preferably, the latch module includes a comparison unit and a latch unit; the midpoint voltage of the horizontal pipe and a preset reference voltage serve as inputs of the comparison unit, and the output of the comparison unit and the output of the wave-sealing signal generating module serve as inputs of the latch unit, and then the latch unit sends the delayed wave-sealing recovery signal to the vertical pipe wave-sealing unit.

[0012] Preferably, when the wave recovery is in the positive half cycle of the current, the preset reference voltage V ref ≤[(V BUS / 2)+ΔV] / N; when the wave is restored to the negative half cycle of the current, the preset reference voltage V ref ≤ΔV / N; where V BUS represents the bus voltage, ΔV represents the voltage margin, and N represents the midpoint voltage sampling divider ratio of the cross tube.

[0013] Preferably, the latch unit is an AND gate unit.

[0014] A T-type three-level circuit fault wave sealing recovery processing method comprises the following steps: only the vertical pipe is subjected to hardware wave sealing processing, and the horizontal pipe is always in a conducting state; and then when performing wave sealing recovery, the vertical pipe is conducted after the horizontal pipe based on the hardware wave sealing structure.

[0015] Compared with the prior art, the beneficial effects of this application are: Compared with the traditional method, the present application can ensure that the normally closed cross pipe is turned on before the high-frequency vertical pipe during the system's wave blocking recovery process, thereby avoiding the risk of overpressure of the high-frequency cross pipe and improving the stability of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 The figure is a schematic diagram of the circuit structure of an existing T-type three-level three-phase inverter.

[0017] Figure 2 for Figure 1 Current schematic diagram of the middle a-phase bridge arm when it works normally in the negative half cycle of current.

[0018] Figure 3 for Figure 1 Current schematic diagram of the middle a-phase bridge arm when the wave blocking protection is triggered during the negative half cycle of the current.

[0019] Figure 4 for Figure 1 Schematic diagram of the current of the left tube Qa3 when the middle a-phase bridge arm triggers the wave blocking protection in the negative half cycle of the current.

[0020] Figure 5 for Figure 1 Schematic diagram of the current in which the upper tube Qa1 is turned on first when the blocking wave of the negative half cycle of the current is restored in the middle a-phase bridge arm.

[0021] Figure 6 for Figure 1 Schematic diagram of the current in which the lower tube Qa2 is turned on first when the blocking wave of the negative half cycle of the current is restored in the middle a-phase bridge arm.

[0022] Figure 7 for Figure 1 Voltage stress waveform of the right tube Qa4 when the blocking wave of the middle a-phase bridge arm is restored in the negative half cycle of current.

[0023] Figure 8 for Figure 1 Schematic diagram of the current in which the left tube Qa3 is turned on first when the blocking wave of the negative half cycle of the current is restored in the middle a-phase bridge arm.

[0024] Fig. 9 for Figure 1 Schematic diagram of the current in which the right tube Qa4 is turned on first when the blocking wave of the negative half cycle of the current is restored in the middle a-phase bridge arm.

[0025] Fig.10 for Figure 1 Current schematic diagram of the middle a-phase bridge arm when it works normally in the positive half cycle of current.

[0026] Fig.11 for Figure 1 Schematic diagram of the current of the right tube Qa3 when the middle a-phase bridge arm triggers the wave blocking protection in the positive half cycle of current.

[0027] Fig.12 for Figure 1 Schematic diagram of the current in the middle a-phase bridge arm when the upper tube Qa1 is turned on first when the wave of the current positive half cycle is restored.

[0028] Fig.13 for Figure 1 Schematic diagram of the current in which the lower tube Qa2 is turned on first when the blocking wave of the middle a-phase bridge arm is restored in the positive half cycle of the current.

[0029] Fig.14 for Figure 1 Schematic diagram of the current in which the left tube Qa3 is turned on first when the wave of the middle a-phase bridge arm is restored in the positive half cycle of the current.

[0030] Fig.15 for Figure 1 Schematic diagram of the current in which the right tube Qa4 is turned on first when the wave of the middle a-phase bridge arm is restored in the positive half-cycle of the current.

[0031] Fig.16 The following is a schematic diagram of the workflow of this application.

[0032] Fig.17 This is a schematic diagram of the layout of the drive circuit of the a-phase bridge arm in this application.

[0033] Fig.18 for Fig.17 Specific circuit topology diagram of the driving circuit in FIG.

[0034] Fig.19 It is a structural schematic diagram of an existing wave-enclosing system.

[0035] Fig. 20 This is a schematic diagram of the structure of the wave blocking system after adding a latch module in this application.

[0036] Fig.21 This is a schematic diagram of the structure of one example of the latch module in this application.

[0037] Fig. 22 FIG. 4 is a schematic diagram of the structure of another example of the latch module in the present application.

[0038] Fig.23 This is a schematic diagram of the structure of the wave sealing system for independently sealing the vertical pipe in this application.

[0039] In the figure: a wave-sealing signal generating module 100 , a vertical pipe wave-sealing unit 210 , a horizontal pipe wave-sealing unit 220 , a vertical pipe driving circuit 310 , a horizontal pipe driving circuit 320 , a latch module 400 , a latch unit 401 , a delay unit 402 , and a comparison unit 403 . DETAILED DESCRIPTION

[0040] Below, the present application is further described in conjunction with specific implementation methods. It should be noted that in the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms should not be understood as necessarily being directed to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification.

[0041] In the description of the present application, it should be noted that directional words, such as the terms "center", "lateral", "longitudinal", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", etc., indicating directions and positional relationships are based on the directions or positional relationships shown in the accompanying drawings, and are only for the convenience of narrating the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and cannot be understood as limiting the specific scope of protection of the present application.

[0042] It should be noted that the terms "first", "second", etc. in the description and claims of the present application are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0043] In this application, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be connected, detachably connected, or integrated; it can be mechanically connected or electrically connected; it can be directly connected or indirectly connected through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0044] In the present application, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may include that the first and second features are in direct contact, or may include that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, a first feature being "above", "above" and "above" a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. A first feature being "below", "below" and "below" a second feature includes that the first feature is directly below and obliquely below the second feature, or simply indicates that the first feature is lower in level than the second feature.

[0045] The terms "including" and "having" and any variations thereof in the specification and claims of the present application are intended to cover non-exclusive inclusions. For example, a process, method, system, product or apparatus comprising a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to these processes, methods, products or apparatuses.

[0046] In order to facilitate the understanding of the technical solution of the present application, a circuit analysis of the fault wave recovery of the T-type three-level circuit may be first performed below.

[0047] like Figure 1 As shown in FIG. 1 , it is a schematic diagram of the circuit architecture of a traditional T-type three-level three-phase inverter, which mainly includes three groups of bridge arms, namely, the a-phase bridge arm, the b-phase bridge arm and the c-phase bridge arm. Each group of bridge arms includes four switch tubes. Taking the a-phase bridge arm as an example, the four switch tubes can be the upper tube Qa1, the lower tube Qa2, the left tube Qa3 and the right tube Qa4 respectively; according to the arrangement direction of the switch tubes, the upper tube Qa1 and the lower tube Qa2 can be defined as vertical tubes, and the left tube Qa3 and the right tube Qa4 can be defined as horizontal tubes.

[0048] It should be noted that there are many specific types of switching tubes, which may be MOSFET devices, IGBT devices, or their series-parallel forms; for the convenience of describing subsequent contents, this application will take the switching tube using MOSFET devices as an example for explanation.

[0049] The c-pole of the upper tube Qa1 is connected to the positive bus BUS+, and the e-pole is connected to the c-pole of the lower tube Qa2; the e-pole of the lower tube Qa2 is connected to the negative bus BUS-. The c-pole of the left tube Qa3 is connected to the c-pole of the right tube Qa4, and the e-pole is connected to the bus midpoint BUSN. The e-pole of the right tube Qa4 is connected to the e-pole of the upper tube Qa1 (the c-pole of the lower tube Qa2).

[0050] The two risers need to withstand the full bus voltage V when working. BUS, that is, the voltage difference between the positive bus BUS+ and the negative bus BUS-, and the two cross tubes only need to withstand half the bus voltage V BUS / 2, that is, the voltage difference between the positive bus BUS+ and the bus midpoint BUSN or the negative bus BUS- and the bus midpoint BUSN. For the convenience of explanation, the subsequent content takes the bus midpoint BUSN as the 0 potential reference point, and the potential of the positive bus BUS+ is V BUS / 2, the potential of the negative bus BUS- is -V BUS / 2.

[0051] When an inverter fails, the blocking protection may be triggered. In some fault situations, the inverter may actively try to restore normal operation and re-transmit the switch tube within a short period of time after the fault occurs, such as wave-by-wave current limiting protection. In the scenario where the inverter re-transmits the wave and resumes normal operation within a short period of time after blocking, the T-type three-level circuit has certain requirements for the conduction timing of each switch tube. Based on the different current cycles in which the blocking recovery is located, the conduction states of the horizontal tube and the vertical tube may be different. The following analysis will be based on the scenario where the a-phase bridge arm is in the negative half-cycle and the positive half-cycle of the current during the blocking recovery.

[0052] 1. The wave recovery is in the negative half cycle of the current.

[0053] like Figure 2 As shown, before the wave is sealed, the upper tube Qa1 is normally open, the left tube Qa3 is normally closed, and the lower tube Qa2 and the right tube Qa4 are alternately turned on. Note that the current direction of the inductor La is assumed to be as follows: Figure 2 As shown, it flows from the right end to the left end. After the wave blocking protection is triggered, the switch tubes Qa1-Qa4 are all turned off. Due to the effect of the inductor La, the body diode of the upper tube Qa1 can form the following Figure 3 The freewheeling path shown. At this time, the e-pole potential of the right tube Qa4 is clamped to V BUS / 2+V F1 , V F1 is the conduction voltage drop of the body diode in the vertical tube.

[0054] like Figure 4 As shown, the inductor La charges the parasitic capacitor C3 of the left tube Qa3 through the body diode of the right tube Qa4. At this time, the voltage drop borne by the left tube Qa3 is about half the bus voltage V BUS / 2, the voltage drop on the right tube Qa4 is the body diode conduction voltage drop V F2 .

[0055] Scenario 1: The upper tube Qa1 resumes conduction first.

[0056] like Figure 5 As shown in the figure, if the upper tube Qa1 is turned on first when the blocking wave is restored, the inductor current i LFlows to the positive busbar BUS+ through the main channel of the upper tube Qa1. At this time, the e-pole potential of the right tube Qa4 is clamped to V BUS / 2+V on1 , where V on1 is the conduction voltage drop of the vertical tube, and the voltage drop borne by the left tube Qa3 is about half the bus voltage V BUS / 2, the pressure drop on the right tube Qa4 is about 0, so there is no overpressure risk for the left tube Qa3 and the right tube Qa4.

[0057] Scenario 2: The lower tube Qa2 resumes conduction first.

[0058] like Figure 6 As shown in the figure, if the lower tube Qa2 is turned on first when the wave is restored, the cathode potential of the body diode of the right tube Qa4 is higher than the anode potential, and the body diode of the right tube Qa4 will enter the reverse recovery state. The parasitic capacitor C3 of the left tube Qa3 discharges the lower tube Qa2 through the body diode of the right tube Qa4, and the discharge amount Q is equal to the reverse recovery charge of the diode. At this time, the c-pole potential V C =V BUS / 2-Q / C 3 , C 3 represents the capacitance value of parasitic capacitor C3; the voltage drop on the left tube Qa3 is V C -V BUS / 2, the pressure drop on the right tube Qa4 is V C +V BUS / 2. The withstand voltage of the left tube Qa3 and the right tube Qa4 is half the bus voltage V BUS / 2 has a certain margin design. Therefore, under certain working conditions, such as when the bus voltage is high and the reverse recovery charge of the body diode of the right tube Qa4 is small, there is a risk of overvoltage on the right tube Qa4.

[0059] Specifically, Figure 7 As shown in the figure, it is the voltage stress waveform of the right tube Qa4. 1 The time to seal the wave, t 2 Re-send the wave at any time. 1 Before the moment, the voltage stress on the right tube Qa4 is half the bus voltage V BUS / 2,t 1 After the moment of blocking, the e-pole potential of the right tube Qa4 is clamped to the bus voltage V BUS , the body diode of the right tube Qa4 is turned on. At this time, the voltage stress on the right tube Qa4 is the body diode conduction voltage drop V F2 .

[0060] In t 2 At this moment, the lower tube Qa2 is turned on, and the e-pole potential of the right tube Qa4 is clamped to the negative bus voltage V BUS-, the body diode of the right tube Qa4 reverses and the parasitic capacitor C3 of the left tube Qa3 discharges through the body diode of the right tube Qa4. At this time, the voltage stress V C =V BUS -Q / C 3 If the reverse recovery charge of the body diode of the right tube Qa4 is small, it may cause Figure 6 V C Greater than half bus voltage V BUS / 2, which causes voltage stress risk on the right tube Qa4.

[0061] Scenario 3: The left tube Qa3 resumes conduction first.

[0062] like Figure 8 As shown, if the left tube Qa3 is turned on first when the wave is restored, the inductor current i L The current flows to the busbar midpoint BUSN through the body diode of the right tube Qa4 and the main channel of the left tube Qa3. Then the voltage drop borne by the left tube Qa3 is the horizontal tube conduction voltage drop V on2 , where V on2 is the conduction voltage drop of the horizontal tube, and the voltage drop of the right tube Qa4 is the conduction voltage drop of the body diode of the horizontal tube V F2 Therefore, there is no overpressure risk for the left tube Qa3 and the right tube Qa4.

[0063] Scenario 4: The right tube Qa4 resumes conduction first.

[0064] like Fig. 9 As shown, if the right tube Qa4 is turned on first when the wave is restored, the inductor current i L The voltage drops to the negative bus BUS+ through the body diode of the upper tube Qa1. The voltage drop to the left tube Qa3 is about half the bus voltage V BUS / 2, the voltage drop on the right tube Qa4 is the horizontal tube conduction voltage drop V on2 Therefore, there is no overpressure risk for the left tube Qa3 and the right tube Qa4.

[0065] 2. The wave recovery is in the positive half cycle of current.

[0066] like Fig.10 As shown in the figure, before the wave blocking, the lower tube Qa2 is normally open, the right tube Qa4 is normally closed, and the upper tube Qa1 and the left tube Qa3 are alternately turned on. At this time, the current direction of the inductor La flows from the left end to the right end. After the wave blocking protection is triggered, the switch tubes Qa1-Qa4 are all turned off. Due to the effect of the inductor La, the body diode of the lower tube Qa2 forms the following Figure 3 The freewheeling path shown. At this time, the e-pole potential of the right tube Qa4 is clamped to -V BUS / 2-V F1 .

[0067] like Fig.11As shown, the bus midpoint BUSN charges the parasitic capacitance of the right tube Qa4 through the body diode of the left tube Qa3. At this time, the voltage drop borne by the right tube Qa4 is about half the bus voltage V BUS / 2, the voltage drop on the left tube Qa3 is the body diode conduction voltage drop V F2 .

[0068] Scenario 5: The upper tube Qa1 resumes conduction first.

[0069] like Fig.12 As shown in the figure, if the upper tube Qa1 is turned on first when the wave is restored, the cathode potential of the body diode of the left tube Qa3 is higher than the anode potential, and the body diode of the left tube Qa3 enters the reverse recovery state. The parasitic capacitor C4 of the right tube Qa4 discharges the upper tube Qa1 through the body diode of the left tube Qa3, and the discharge amount Q is equal to the reverse recovery charge of the diode. At this time, the c-pole potential V C =V BUS / 2-Q / C 4 , C 4 represents the capacitance value of parasitic capacitor C4; the voltage drop on the right tube Qa4 is V BUS / 2-V C , the pressure drop on the left tube Qa3 is V C +V BUS / 2. Therefore, under certain operating conditions, such as when the bus voltage is high and the reverse recovery charge of the body diode of the right tube Qa4 is small, there is an overvoltage risk for the left tube Qa3.

[0070] Scenario 6: The lower tube Qa2 resumes conduction first.

[0071] like Fig.13 As shown in the figure, if the lower tube Qa2 is turned on first when the blocking wave is restored, the inductor current i L The current flows from the negative bus BUS- to the inductor through the lower tube Qa2. At this time, the e-pole potential of the right tube Qa4 is clamped to -V BUS / 2-V on1 , then the voltage drop on the left tube Qa3 is about 0, and the voltage drop on the right tube Qa4 is about half the bus voltage V BUS / 2, so there is no overpressure risk for the left tube Qa3 and the right tube Qa4.

[0072] Scene 7: The left tube Qa3 resumes conduction first.

[0073] like Fig.14 As shown, if the left tube Qa3 is turned on first when the wave is restored, the inductor current i L The current flows from the negative bus BUS- to the inductor through the body diode of the lower tube Qa2. Then the e-pole potential of the right tube Qa4 is clamped to -V BUS / 2-V F1, the voltage drop on the left tube Qa3 is the horizontal tube conduction voltage drop V on2 The voltage drop on the right tube Qa4 is about half the bus voltage V BUS / 2, so there is no overpressure risk for the left tube Qa3 and the right tube Qa4.

[0074] Scenario 8: The right tube Qa4 resumes conduction first.

[0075] like Fig.15 As shown, if the right tube Qa4 is turned on first when the wave is restored, the inductor current i L The current flows from the busbar midpoint BUSN to the inductor through the body diode of the left tube Qa3 and the right tube Qa4. At this time, the voltage drop borne by the left tube Qa3 is the body diode conduction voltage drop V F2 , the voltage drop on the right tube Qa4 is the horizontal tube conduction voltage drop V on2 Therefore, there is no overpressure risk for the left tube Qa3 and the right tube Qa4.

[0076] For ease of understanding, the pipe pressures of the horizontal pipes in the above eight scenarios can be summarized in a table; among them, the conduction voltage drop V on1 and the conduction voltage drop of the horizontal tube V on2 Since the value is small, it can be regarded as 0, so the specific summary table is as follows:

[0077] It can be seen from the above table that when the wave blocking is restored, only when the horizontal pipe is connected before the vertical pipe can it be ensured that there is no overpressure danger in the horizontal pipe and the vertical pipe. Therefore, the core idea of ​​this application is how to control the vertical pipe to be connected after the horizontal pipe when the wave blocking is restored. There are many specific implementation methods that can achieve the above requirements. For the convenience of understanding, three specific embodiments will be described in detail below.

[0078] Embodiment 1: like Fig.16 As shown, a T-type three-level circuit fault wave sealing recovery processing method includes the following steps: increasing the drive signal response time of the vertical tube relative to the horizontal tube, so that the vertical tube is turned on later than the horizontal tube when the vertical tube performs wave sealing recovery.

[0079] For ease of understanding, we can first briefly describe the wave recovery architecture of the T-type three-level circuit. Fig.16 and Fig.17As shown, the wave-encapsulation recovery architecture of the T-type three-level circuit mainly includes a wave-encapsulation system, a vertical pipe driving circuit 310, and a horizontal pipe driving circuit 320. When performing wave-encapsulation recovery, the wave-encapsulation system can output a wave-encapsulation recovery signal to the vertical pipe driving circuit 310 and the horizontal pipe driving circuit 320 respectively, and then the vertical pipe driving circuit 310 and the horizontal pipe driving circuit 320 can process the wave-encapsulation recovery signal after receiving it and generate a driving signal for controlling the vertical pipe and the horizontal pipe to conduct respectively.

[0080] Based on the basic working process of the wave-sealing recovery architecture of the T-type three-level circuit, this embodiment adjusts the response time of the driving signal when the vertical tube driving circuit 310 and the horizontal tube driving circuit 320 respectively generate driving signals to the vertical tube and the horizontal tube, so that the vertical tube receives the driving signal after the horizontal tube, thereby ensuring that the vertical tube is turned on later than the horizontal tube, thereby avoiding the risk of overvoltage of the horizontal tube.

[0081] It should be known that, for a single-phase bridge arm, the number of the horizontal tubes and the number of the vertical tubes are both two, so the number of the horizontal tube driving circuit 320 and the number of the vertical tube driving circuit 310 are both two; each driving circuit is independently controlled and connected to the corresponding switch tube.

[0082] In this embodiment, Fig.16 As shown, based on the arrangement architecture of the driving circuit, there are three main specific implementation methods for increasing the response time of the vertical tube to the driving signal of the horizontal tube. The first is to increase the response time of the vertical tube driving circuit 310 to the driving signal, that is, to delay the output of the driving signal; the second is to shorten the response time of the horizontal tube driving circuit 320 to the driving signal, that is, to advance the output of the driving signal; the third is a combination of the first and the second, that is, to increase the response time of the vertical tube driving circuit 310 to the driving signal, and shorten the response time of the horizontal tube driving circuit 320 to the driving signal. The above three methods can all meet the actual needs of this application, and those skilled in the art can choose according to their actual needs.

[0083] It is understandable that there are various specific structures of the driving circuit that can delay and advance the driving signal. For ease of understanding, a detailed description will be given below through specific examples.

[0084] Specifically, Fig.18As shown, the vertical tube driving circuit 310 and the horizontal tube driving circuit 320 both include a driving chip, an on-resistance Ron, a diode D1, a gate capacitor Cge and a voltage-stabilizing diode D2. The on-resistance Ron is connected in parallel with the diode D1 to form a protection branch, the input end of the driving chip is connected to the wave-sealing system, the output end of the driving chip is connected to the first end of the protection branch, and the second end of the protection branch is connected to the corresponding switch tube. The gate capacitor Cge and the voltage-stabilizing diode D2 are both connected in parallel between the second end of the protection branch and the bridge arm circuit, so that the gate capacitor Cge and the on-resistance Ron are connected in parallel to form an RC control circuit.

[0085] When the response time of the horizontal tube driving circuit 320 to the driving signal needs to be shortened, the resistance value of the on-resistance Ron and the capacitance value of the gate-source capacitor Cge in the horizontal tube driving circuit 320 can be reduced at the same time. When the response time of the vertical tube driving circuit 310 to the driving signal needs to be increased, the resistance value of the on-resistance Ron and the capacitance value of the gate-source capacitor Cge in the vertical tube driving circuit 310 can be increased at the same time.

[0086] It should be noted that, whether reducing the delay of the RC control circuit in the horizontal tube driving circuit 320 or increasing the delay of the RC control circuit in the vertical tube driving circuit 310, it is necessary to reasonably set the values ​​of the turn-on resistance Ron and the gate-source capacitance Cge according to the device performance of the vertical tube and the horizontal tube and the actual circuit difference. If the value is too small, the driving signal may have voltage spikes or oscillations; if the value is too large, the switch tube may conduct slowly, thereby affecting normal control. Generally speaking, the difference in conduction time between the horizontal tube and the vertical tube is much smaller than the switching cycle of the T-type three-level circuit, so reasonably adjusting the delay of the driving circuit will not affect the control process of the entire system.

[0087] Embodiment 2: like Fig.16 As shown, a T-type three-level circuit fault wave recovery processing method includes the following steps: increasing the wave recovery signal response time of the vertical pipe relative to the horizontal pipe, so that the vertical pipe is turned on later than the horizontal pipe when performing wave recovery.

[0088] For ease of understanding, the traditional method of fault wave recovery in a T-type three-level circuit can be explained first. Fig.19 , which is a schematic diagram of the circuit architecture of an existing conventional wave-enclosing system, wherein the conventional wave-enclosing system mainly includes a wave-enclosing signal generating module 100, a horizontal pipe wave-enclosing unit 220, and a vertical pipe wave-enclosing unit 210. The output end of the wave-enclosing signal generating module 100 is connected to the input ends of the horizontal pipe wave-enclosing unit 220 and the vertical pipe wave-enclosing unit 210, respectively, and the output ends of the horizontal pipe wave-enclosing unit 220 and the vertical pipe wave-enclosing unit 210 are connected to the input ends of the horizontal pipe driving circuit 320 and the vertical pipe driving circuit 310, respectively.

[0089] Taking the a-phase bridge arm as an example, the number of the horizontal tube wave-sealing unit 220 and the vertical tube wave-sealing unit 210 are both two, so as to respectively connect the signals with the driving circuits of the corresponding switch tubes. Fig.19 As shown, the wave-sealing signal generating module 100 can output a signal LOCK. When the signal LOCK is at a low level, it is a fault wave-sealing signal. When the signal LOCK is at a high level, it is a wave-sealing recovery signal. Qa1 The control signal of the upper tube Qa1 output by the main control; PWM Qa2 The control signal of the lower tube Qa2 output by the main control; PWM Qa3 The control signal of the left tube Qa3 of the main control output; PWM Qa4 It is the control signal of the right tube Qa4 of the main control output. CTL Qa1 CTL is the input signal of the driving circuit corresponding to the upper tube Qa1; Qa2 is the input signal of the driving circuit corresponding to the lower tube Qa2; CTL Qa3 It is the input signal of the driving circuit corresponding to the left tube Qa3; CTL Qa4 is the input signal of the driving circuit corresponding to the right tube Qa4. There are many specific types of the horizontal tube wave-sealing unit 220 and the vertical tube wave-sealing unit 210. For the sake of easy understanding, this embodiment is described by taking the AND gate unit as an example.

[0090] When the system operates normally, the signal LOCK output by the wave-enclosing signal generating module 100 is at a high level, and the wave-enclosing unit corresponding to each switch tube will output the corresponding control signal PWM output by the master control.

[0091] When a system failure occurs and blocking is required, the blocking signal generating module 100 outputs a low level signal LOCK, which is sent to each blocking unit and each blocking unit outputs a low level, so that each switch tube is in a driving blocking state.

[0092] When the wave-enclosing recovery is required, the wave-enclosing signal generating module 100 outputs the signal LOCK at a high level. Qa1 or PWM Qa2 ) and the normally closed cross-tube control signal (PWM Qa3 or PWM Qa4 ) are both high level. Due to the difference in the opening time of the vertical pipe and the parameters of the driving circuit, the high-frequency vertical pipe may be turned on before the normally closed horizontal pipe, causing the high-frequency horizontal pipe to be exposed to overvoltage risk. However, this embodiment delays the response time of the wave sealing recovery signal output by the wave sealing signal generating module 100 to the vertical pipe wave sealing unit 210, so as to ensure that the vertical pipe is turned on after the horizontal pipe when the wave sealing is restored.

[0093] In order to achieve the above functions, this embodiment improves the traditional wave-enclosing system. There are many specific ways of improvement. For the sake of easy understanding, a specific example will be used for detailed description below. Fig. 20 As shown, the wave-encapsulation system includes a wave-encapsulation signal generating module 100, a latching module 400, a horizontal pipe wave-encapsulation unit 220, and a vertical pipe wave-encapsulation unit 210. The wave-encapsulation signal generating module 100 can output a wave-encapsulation recovery signal, the input end of the vertical pipe wave-encapsulation unit 210 is connected to the wave-encapsulation signal generating module 100 by signal through the latching module 400, the output end of the vertical pipe wave-encapsulation unit 210 can send a conduction signal to the vertical pipe, and the latching module 400 can delay the wave-encapsulation recovery signal sent by the wave-encapsulation signal generating module 100. The input end of the horizontal pipe wave-encapsulation unit 220 is connected to the wave-encapsulation signal generating module 100 by signal, and the output end of the horizontal pipe wave-encapsulation unit 220 can send a conduction signal to the horizontal pipe.

[0094] It is understandable that the conduction signal sent by the vertical tube wave sealing unit 210 to the vertical tube is the input signal corresponding to the vertical tube driving circuit 310, and the conduction signal sent by the horizontal tube wave sealing unit 220 to the horizontal tube is the input signal corresponding to the horizontal tube driving circuit 320. The function of the latch module 400 is to control the vertical tube to maintain the wave sealing state until the normally closed horizontal tube is opened or the high-frequency horizontal tube has no overvoltage risk, and then release the wave sealing state when the wave sealing recovery is performed. There are many specific structures of the latch module 400 that can realize the above functions. For the sake of easy understanding, two specific examples will be used for detailed description below.

[0095] Example 1: Fig.21 As shown, the latch module 400 includes a latch unit 401 and a delay unit 402. For a single-phase bridge arm, the number of latch units 401 and delay units 402 are both two, so as to form two latch delay circuits respectively connected to the corresponding vertical pipe driving circuit 310. The output of the horizontal pipe wave-sealing unit 220 is used as the input of the delay unit 402, and the output of the delay unit 402 and the output of the wave-sealing signal generating module 100 are both used as the input of the latch unit 401, and then the latch unit 401 sends the delayed wave-sealing recovery signal to the vertical pipe wave-sealing unit 210.

[0096] It is understandable that there are many specific structural types of the latch unit 401 and the delay unit 402. In this example, the latch unit 401 preferably adopts an AND gate unit, and the delay unit 402 preferably adopts an RC circuit structure. For ease of understanding, the specific working process of Example 1 will be described in detail below, taking the a-phase bridge arm as an example.

[0097] Specifically, Fig.21 As shown, the driver chip input signal CTL of the right tube Qa4 Qa4The delay unit 402 corresponding to the upper tube Qa1 is connected to one input end of the latch unit 401 corresponding to the upper tube Qa1. The other input end of the latch unit 401 corresponding to the upper tube Qa1 is connected to the output of the envelope signal generating module 100. The driver chip input signal CTL of the left tube Qa3 Qa3 The delay unit 402 corresponding to the lower tube Qa2 is connected to one input end of the latch unit 401 corresponding to the lower tube Qa2. The other input end of the latch unit 401 corresponding to the lower tube Qa2 is connected to the output of the wave envelope signal generating module 100.

[0098] When the system performs wave blocking recovery, the wave blocking signal generating module 100 outputs the signal LOCK as high level, and the horizontal pipe wave blocking unit 220 is immediately controlled by the main control. The two outputs of the latch module 400 are controlled by the driver chip input signal CTL of the left pipe Qa3. Qa3 The right tube Qa4 driver chip input signal CTL Qa4 control.

[0099] When the a-phase bridge arm is in the positive half cycle of the current, the right tube Qa4 is normally closed, and the signal CTL output by the horizontal tube wave sealing unit 220 corresponding to the right tube Qa4 is restored at the first time. Qa4 The control signal PWM output by the master Qa4 At this time, the signal CTL output by the horizontal tube wave-sealing unit 220 corresponding to the right tube Qa4 is Qa4 The capacitor C is charged by the current limiting resistor R in the delay unit 402 corresponding to the upper tube Qa1. When the voltage of the capacitor C rises to the input threshold voltage of the latch unit 401 corresponding to the upper tube Qa1, the latch unit 401 corresponding to the upper tube Qa1 outputs a high level. At this time, the signal CTL output by the vertical tube sealing unit 210 corresponding to the upper tube Qa1 is Qa1 The control signal PWM output by the master Qa1 Since the left tube Qa3 is a high-frequency switch and the lower tube Qa2 is normally closed, the output of the latch unit 401 corresponding to the lower tube Qa2 does not affect the output of the vertical tube wave-sealing unit 210 corresponding to the lower tube Qa2.

[0100] When the a-phase bridge arm is in the negative half cycle of the current, the left tube Qa3 is normally closed, and the signal CTL output by the horizontal tube wave-sealing unit 220 corresponding to the left tube Qa3 is restored at the first time. Qa3 The control signal PWM output by the master Qa3 At this time, the signal CTL output by the horizontal pipe wave-sealing unit 220 corresponding to the left pipe Qa3 is Qa3The capacitor C is charged by the current limiting resistor R in the delay unit 402 corresponding to the lower tube Qa2. When the voltage of the capacitor C rises to the input threshold voltage of the latch unit 401 corresponding to the lower tube Qa2, the latch unit 401 corresponding to the lower tube Qa2 outputs a high level. At this time, the signal CTL output by the vertical tube sealing unit 210 corresponding to the lower tube Qa2 is Qa2 The control signal PWM output by the master Qa2 Since the right tube Qa4 is a high-frequency switch and the upper tube Qa1 is normally closed, the output of the latch unit 401 corresponding to the upper tube Qa1 does not affect the output of the vertical tube wave-sealing unit 210 corresponding to the upper tube Qa1.

[0101] Example 2: Fig. 22 As shown, the latch module 400 includes a comparison unit 403 and a latch unit 401. For a single-phase bridge arm, the number of latch units 401 and comparison units 403 are both two, so as to form two latch delay circuits respectively connected to the corresponding vertical tube driving circuit 310. 1 And the preset reference voltage V ref As the input of the comparison unit 403 , the output of the comparison unit 403 and the output of the wave envelope signal generating module 100 are used as the input of the latch unit 401 , and then the latch unit 401 sends the delayed wave envelope recovery signal to the riser wave envelope unit 210 .

[0102] It is understandable that the specific structures and working principles of the latch unit 401 and the comparison unit 403 are well known to those skilled in the art, so they will not be elaborated in detail here. In this example, the latch unit 401 is preferably an AND gate unit, and the comparison unit 403 is preferably a comparator. For ease of understanding, the specific working process of Example 2 will be described in detail below, taking the a-phase bridge arm as an example.

[0103] Specifically, from the above analysis process, it can be known that the upper tube Qa1 and the lower tube Qa2 have overvoltage risks in the positive half cycle and the negative half cycle of the current respectively. Therefore, the input terminal reference voltage V ref1 is the reference voltage of the positive half cycle of the current, and the reference voltage V ref2 It is the reference voltage for the negative half cycle of current.

[0104] In the positive half cycle of the current, Fig. 20 and Fig. 22As shown, the output of the comparison unit 403 corresponding to the upper tube Qa1 is connected to an input end of the corresponding latch unit 401, and the other input end of the latch unit 401 is connected to the output end of the wave-sealing signal generating module 100. The output of the latch unit 401 is connected to an input end of the vertical tube wave-sealing unit 210 corresponding to the upper tube Qa1. The other input end of the vertical tube wave-sealing unit 210 corresponding to the upper tube Qa1 is connected to the control signal PWM output by the main control. Qa1 .

[0105] In the negative half cycle of the current, the output of the comparison unit 403 corresponding to the lower tube Qa2 is connected to an input end of the corresponding latch unit 401, and the other input end of the latch unit 401 is connected to the output end of the wave-encapsulation signal generating module 100. The output of the latch unit 401 is connected to an input end of the vertical tube wave-encapsulation unit 210 corresponding to the lower tube Qa2. The other input end of the vertical tube wave-encapsulation unit 210 corresponding to the lower tube Qa2 is connected to the control signal PWM output by the main control. Qa2 .

[0106] When the sealing wave is restored in the positive half cycle of the current, it can be seen from the above analysis process that if the upper tube Qa1 is turned on before the right tube Qa4, the left tube Qa3 may be subject to overvoltage risk. At this time, the e-pole potential of the left tube Qa3 is the potential of the busbar midpoint BUSN, that is, 0 potential; the c-pole potential is the midpoint potential V 1 Therefore, in the positive half cycle of the current, the positive input terminal reference voltage V ref1 Need to meet: V ref1 ≤[(V BUS / 2)+ΔV] / N.

[0107] When the sealing wave is restored in the negative half cycle of the current, it can be seen from the above analysis process that if the lower tube Qa2 is turned on before the left tube Qa3, the right tube Qa4 may be subject to overvoltage risk. At this time, the e-pole potential of the right tube Qa4 is the potential of the negative half bus BUS-, that is, -V BUS / 2 potential; the c-pole potential is the midpoint potential of the transverse tube V 1 Therefore, in the negative half cycle of the current, the positive input terminal reference voltage V ref2 Need to meet: V ref2 ≤ΔV / N.

[0108] Among them, V BUS represents bus voltage, ΔV represents voltage margin, and N represents cross-tube midpoint voltage V 1 The sampling voltage divider ratio; the voltage margin ΔV and the cross-tube midpoint voltage V 1 The sampling voltage divider ratio N should be set reasonably according to the actual working conditions.

[0109] It can be understood that the above-mentioned embodiment 1 and embodiment 2 can be used separately or in combination, and the specific selection can be made according to the actual needs of those skilled in the art.

[0110] Embodiment three: like Fig.23 As shown, a T-type three-level circuit fault wave sealing recovery processing method includes the following steps: only the vertical pipe is subjected to hardware wave sealing processing, and the horizontal pipe is always in a conducting state; and then when performing wave sealing recovery, the vertical pipe is conducted after the horizontal pipe based on the hardware wave sealing structure.

[0111] For ease of understanding, the specific working process of this embodiment will be described in detail below by taking the a-phase bridge arm as an example.

[0112] like Fig.23 As shown, only the upper tube Qa1 and the lower tube Qa2 are blocked by hardware. The control signal PWM output by the master Qa3 Directly connected to the drive input signal CTL of the left tube Qa3 Qa3 ; The control signal PWM output by the master Qa4 Directly connected to the drive input signal CTL of the right tube Qa4 Qa4 .

[0113] When the system is blocking the wave, the blocking signal generating module 100 outputs the signal LOCK as a low level, and the vertical tube blocking unit 210 outputs a low level, so that the upper tube Qa1 and the lower tube Qa2 are both blocking the wave. At this time, the horizontal tube is in normal wave release, and the inductor current can be continued through the main channel or body diode of the right tube Qa4 and the main channel of the left tube Qa3. The specific flow direction of the inductor current can be referred to Figure 8 Therefore, only performing hardware blocking on the vertical pipe can achieve the purpose of performing hardware blocking on both the horizontal pipe and the vertical pipe, that is, disconnecting the DC bus from the output, and at the same time avoiding the overcurrent risk of the high-frequency horizontal pipe when the blocking is restored.

[0114] The above describes the basic principles, main features and advantages of the present application. Those skilled in the art should understand that the present application is not limited by the above embodiments, and the above embodiments and the specification only describe the principles of the present application. The present application may have various changes and improvements without departing from the spirit and scope of the present application, and these changes and improvements fall within the scope of the present application for which protection is sought. The scope of protection claimed by the present application is defined by the attached claims and their equivalents.

Claims

1. A T-type three-level circuit fault wave recovery processing method, characterized in that: The method comprises the following steps: increasing the driving signal response time and / or the wave envelope recovery signal response time of the vertical pipe relative to the horizontal pipe, so that when the vertical pipe performs wave envelope recovery, the vertical pipe is turned on later than the horizontal pipe.

2. The T-type three-level circuit fault envelope recovery processing method according to claim 1, characterized in that: The vertical pipe responds to the driving signal through the vertical pipe driving circuit, and the horizontal pipe responds to the driving signal through the horizontal pipe driving circuit; By increasing the response time of the vertical tube driving circuit to the driving signal and / or shortening the response time of the horizontal tube driving circuit to the driving signal, the vertical tube is turned on after the horizontal tube when the vertical tube performs wave envelope recovery.

3. The T-type three-level circuit fault wave recovery processing method according to claim 2, characterized in that: The vertical tube driving circuit and the horizontal tube driving circuit both include a driving chip, an on-resistance resistor and a gate capacitor; the driving chip is connected in series with the on-resistance resistor, and the gate capacitor is connected in parallel with the on-resistance resistor to form an RC control circuit; The response time of the driving signal is controlled by adjusting the resistance of the on-resistance and / or the capacitance of the gate capacitor.

4. The T-type three-level circuit fault encapsulation recovery processing method according to claim 1, characterized in that: The wave sealing recovery signal is generated by a wave sealing system, and the wave sealing system includes a wave sealing signal generating module, a latch module, a horizontal pipe wave sealing unit and a vertical pipe wave sealing unit; The wave-enclosing signal generating module is suitable for outputting a wave-enclosing recovery signal, the input end of the vertical pipe wave-enclosing unit is connected to the wave-enclosing signal generating module through the latch module, the output end of the vertical pipe wave-enclosing unit is suitable for sending a conduction signal to the vertical pipe, and the latch module is suitable for delaying the wave-enclosing recovery signal sent by the wave-enclosing signal generating module; The input end of the cross-pipe wave-sealing unit is signal-connected to the wave-sealing signal generating module, and the output end of the cross-pipe wave-sealing unit is suitable for sending a conduction signal to the cross-pipe.

5. The T-type three-level circuit fault wave recovery processing method according to claim 4, characterized in that: The latch module includes a latch unit and a delay unit; the output of the horizontal pipe wave sealing unit is used as the input of the delay unit, and the output of the delay unit and the output of the wave sealing signal generating module are both used as the input of the latch unit, and then the latch unit sends the delayed wave sealing recovery signal to the vertical pipe wave sealing unit.

6. The T-type three-level circuit fault encapsulation recovery processing method according to claim 5, characterized in that: The delay unit adopts an RC circuit structure.

7. The T-type three-level circuit fault envelope recovery processing method according to claim 4, characterized in that: The latch module includes a comparison unit and a latch unit; the midpoint voltage of the horizontal pipe and a preset reference voltage are used as inputs of the comparison unit, and the output of the comparison unit and the output of the wave-sealing signal generating module are used as inputs of the latch unit, and then the latch unit sends the delayed wave-sealing recovery signal to the vertical pipe wave-sealing unit.

8. The T-type three-level circuit fault encapsulation recovery processing method according to claim 7, characterized in that: When the wave is restored to the positive half cycle of the current, the preset reference voltage V ref ≤[(V BUS / 2)+ΔV] / N; When the wave recovery is in the negative half cycle of the current, the preset reference voltage V ref ≤ΔV / N; Among them, V BUS represents the bus voltage, ΔV represents the voltage margin, and N represents the midpoint voltage sampling divider ratio of the cross tube.

9. The T-type three-level circuit fault encapsulation recovery processing method according to claim 5 or 7, characterized in that: The latch unit is an AND gate unit.

10. A method for recovering a fault wave of a T-type three-level circuit, characterized in that: The method comprises the following steps: only performing hardware wave sealing processing on the vertical pipe, and the horizontal pipe is always in a conducting state; and then when performing wave sealing recovery, the vertical pipe is conducted after the horizontal pipe based on the hardware wave sealing structure.

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